US20040246039A1 - Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit - Google Patents

Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit Download PDF

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US20040246039A1
US20040246039A1 US10/250,082 US25008203A US2004246039A1 US 20040246039 A1 US20040246039 A1 US 20040246039A1 US 25008203 A US25008203 A US 25008203A US 2004246039 A1 US2004246039 A1 US 2004246039A1
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United States
Prior art keywords
switch element
node
capacitor circuit
switched capacitor
switch
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US10/250,082
Inventor
Chi-Ming Hsiao
Guang-Kaai Dehng
Ming-Horng Tsai
Ling-Wei Ke
En-Hsiang Yeh
Chi-Kun Chiu
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MediaTek Inc
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MediaTek Inc
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Priority to US10/250,082 priority Critical patent/US20040246039A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIU, CHI-KUN, DEHNG, GUANG-KAAI, HSIAO, CHI-MING, KE, LING-WEI, TSAI, MING-HORNG, YEH, EN-HSIANG
Priority to US10/605,095 priority patent/US6815996B1/en
Priority to US10/709,461 priority patent/US20040246040A1/en
Priority to TW093115671A priority patent/TWI240479B/en
Priority to PCT/CN2004/000599 priority patent/WO2004107558A1/en
Priority to CN200480006928.5A priority patent/CN100468953C/en
Publication of US20040246039A1 publication Critical patent/US20040246039A1/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/124Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/1262Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements
    • H03B5/1265Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements switched capacitors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/003Circuit elements of oscillators
    • H03B2200/005Circuit elements of oscillators including measures to switch a capacitor
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J2200/00Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
    • H03J2200/10Tuning of a resonator by means of digitally controlled capacitor bank

Definitions

  • the present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit used in a voltage controlled oscillator (VCO) that can minimize the clock feedthrough effect thereby preventing the VCO frequency drift phenomenon during calibration and the synthesizer phase locking period.
  • VCO voltage controlled oscillator
  • VCO voltage controlled oscillator
  • Each discretely variable capacitor in the plurality of discretely variable capacitors 16 is made up of a switched capacitor circuit 20 and each switched capacitor circuit is controlled by an independent control signal 22 .
  • the switched capacitor circuit 20 can selectively connect or disconnect a capacitor 24 to the resonator of the VCO 10 .
  • Different on/off combinations of switched capacitor arrays results in a wider capacitance range of the LC type resonator and hence a wider VCO 10 oscillation frequency coverage.
  • FIG. 2 shows a switched capacitor circuit 20 a according to the prior art.
  • a capacitor 30 is connected between the first oscillator node OSC_P and a node A.
  • a switch element 32 selectively connects node A to ground, and the switch element 32 is controlled by a control signal SW.
  • the switch element 32 is turned on, the capacitance associated with the capacitor 30 is added to the overall capacitance in the VCO 10 resonator.
  • the switch element 32 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor 30 and the off state capacitance associated with the switch element 32 .
  • FIG. 3 shows a differential type switched capacitor circuit 20 b according to the prior art. Differential implementations have much greater common-mode noise rejection and are widely used in high-speed integrated circuit environments.
  • a positive side capacitor 40 is connected between the first oscillator node OSC_P and a node A.
  • a positive side switch element 42 selectively connects node A to ground.
  • a negative side capacitor 44 is connected between the second oscillator node OSC_N and a node B.
  • a negative side switch element 46 selectively connects node B to ground.
  • All three switch elements 42 , 46 , 48 are controlled by the same control signal SW.
  • the switch elements 42 , 46 , 48 are turned on, the capacitance associated with the series combination of the positive and negative side capacitors 40 , 44 is added to the overall capacitance in the VCO 10 .
  • the switch elements 42 , 46 , 48 are turned off, the differential input capacitance is the series combination of the positive and negative side capacitors 40 , 44 and other switch parasitic capacitance.
  • the overall input capacitance when all switch elements 42 , 46 , 48 are turned off is lower than that when all switch elements 42 , 46 , 48 are turned on. Without the center switch element 48 , the switched capacitor circuit 20 b is itself another embodiment of the differential type switch capacitor circuit according to the prior art.
  • the differential switched capacitor circuit 20 b shown in FIG. 3 switches off, it suffers from the same clock feedthrough effect problem at node A and at node B.
  • the positive side node A has an undesired voltage step change caused by the clock feedthrough effect of both the positive side switch element 42 and the clock feedthrough effect of the center switch element 48 .
  • the negative side node B has an undesired voltage step caused by the clock feedthrough effect of both the negative side switch element 46 and the clock feedthrough effect of the center switch element 48 .
  • the voltage step change and recovery at node A and node B changes the capacitance of the VCO 10 resonator and causes an undesired momentary drift in the VCO 10 frequency.
  • a switched capacitor circuit capable of minimizing clock feedthrough effect.
  • the switched capacitor circuit comprising a switch element having a first terminal connected to a capacitor, a second terminal connected to ground, and a control terminal; and a low-pass filter having an input terminal connected to a control signal and an output terminal connected to the control terminal of the switch element, wherein the low-pass filter is for making the switch element gradually switch off.
  • a method for minimizing clock feedthrough effect when switching a switched capacitor circuit comprises providing a plurality of differently sized switch elements that selectively connect a capacitor to a node depending upon a control signal applied to a control terminal of each of the switch elements.
  • sequencing the control signals such that the switch elements are switched off in decreasing order based on size, whereby the largest switch element is switched off first and the smallest switch element is switched off last.
  • the method further comprising when switching the switched capacitor circuit to an off state, providing a means for making the smallest switch element gradually switch off.
  • the switched capacitor circuit is gradually switched off to minimize the clock feedthrough effect and prevent an undesired drift in the VCO 10 frequency.
  • the switched capacitor circuit is instantly switched from an on state to an off state.
  • the clock feedthrough effect in the prior art implementations causes an undesired voltage step change to slightly forward bias the junction diode formed by the switch element in the off state until the voltage potential has returned to ground.
  • FIG. 1 is a schematic diagram of a typical Voltage Controlled Oscillator (VCO) circuit used in a frequency synthesizer according to the prior art.
  • VCO Voltage Controlled Oscillator
  • FIG. 2 shows a switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.
  • FIG. 3 shows a differential type switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.
  • FIG. 4 shows a switched capacitor circuit according to the first embodiment of the present invention.
  • FIG. 5 shows a time domain plot of the control signals for the switched capacitor circuit of FIG. 4
  • FIG. 6 shows a differential switched capacitor circuit according to the second embodiment of the present invention.
  • FIG. 7 shows a time domain plot of the control signals for the differential switched capacitor circuit of FIG. 6.
  • FIG. 8 shows an example switched capacitor circuit according to the third embodiment of the present invention.
  • FIG. 9 shows a time domain plot of the present invention control signals for switching off the switched capacitor circuit of FIG. 8
  • FIG. 10 shows a generalized switched capacitor circuit of FIG. 8 with a low-pass filter added to the control terminal of the smallest switch element.
  • FIG. 11 shows a differential switched capacitor circuit according to the fourth embodiment of the present invention.
  • FIG. 12 shows a time domain plot of the present invention control signals for switching off the differential switched capacitor circuit of FIG. 11.
  • FIG. 13 shows a generalized differential switched capacitor circuit of FIG. 11 with a low-pass filter added to the control terminal of the smallest pull down switch element at the positive side and its corresponding pull down switch element at the negative side.
  • FIG. 14 shows a method flowchart for minimizing clock feedthrough effect when switching off a switched capacitor circuit according to the present invention.
  • FIG. 15 shows a method flowchart for minimizing clock feedthrough effect when switching off a differential switched capacitor circuit according to the present invention.
  • FIG. 4 shows a switched capacitor circuit 20 c according to the first embodiment of the present invention.
  • the switched capacitor circuit 20 c comprises a capacitor 50 , a switch element 52 , and a low-pass filter 54 .
  • the capacitor 50 is connected between the first oscillator node OSC_P and a node A.
  • the switch element 52 selectively connects the node A to ground.
  • the switch element 52 is turned on, the capacitance associated with the capacitor 50 is added to the overall capacitance in the VCO 10 .
  • the switch element 52 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor 50 and the off state capacitance associated with the switch element 32 .
  • a low-pass filter 54 is connected to a control terminal of the switch element 52 for making the switch element 52 gradually switch off.
  • FIG. 5 is a time domain plot of the control signal SW before the low-pass filter 54 and a signal SW_FILTER after the low-pass filter 54 .
  • the low-pass filter 54 causes the signal SW_FILTER at the control terminal of the switch element 52 to gradually change from a logic high to a logic low and minimizes the voltage step change seen at node A.
  • node A is gradually disconnected from ground.
  • the present invention does not forward bias the diode formed by the switch element 52 in the off state. The clock feedthrough effect at each moment in time is reduced.
  • FIG. 6 shows a differential switched capacitor circuit 20 d according to the second embodiment of the present invention.
  • a positive side capacitor 60 is connected between the first oscillator node OSC_P and a node A.
  • a positive side switch element 62 selectively connects node A to ground.
  • a negative side capacitor 64 is connected between the second oscillator node OSC_N and a node B.
  • a negative side switch element 66 selectively connects node B to ground.
  • a center switch element 68 is used to lower the overall turn-on resistance and is connected between node A and node B.
  • a low-pass filter 70 is connected to the control terminals of the positive side switch element 62 and the negative side switch element 66 for making the positive and negative side switch elements 62 , 66 gradually switch off. Without the center switch element 68 , the switched capacitor circuit 20 d is itself another embodiment of the differential type switched capacitor circuit.
  • FIG. 7 is a time domain plot of the control signal SW before the low-pass filter and the signal SW_FILTER after the low-pass filter.
  • the center switch element 68 is directly controlled by the control signal SW while the positive and negative side switch elements 62 , 66 are controlled by the output of the low-pass filter 70 , signal SW_FITLER.
  • the control signal SW changes from a logic high to a logic low and the center switch element 68 immediately changes to an off state.
  • the positive and negative side switch elements 62 , 66 gradually switch off, during a period of delay time, node A and node B are still connected to ground and the clock feedthrough effect due to the center switch element 68 is minimized by the conduction to ground path.
  • the positive and negative side switch elements 62 , 66 gradually switch off, the clock feedthrough effect produced at node A and B at each moment of time is reduced.
  • FIG. 8 shows an example of the switched capacitor circuit 20 e according to the third embodiment of the present invention.
  • the switched capacitor circuit 20 e comprises a capacitor 80 , a sequence controller 88 , and a plurality of differently sized switch elements 82 .
  • FIG. 8 shows two switch elements 84 , 86 but this is meant as an example only and more switch elements could be used.
  • switch element 84 is larger than switch element 86 .
  • the capacitor 80 is connected between the first oscillator node OSC_P and a node A.
  • Each of the switch elements 84 , 86 in the plurality of differently sized switch elements 82 selectively connects node A to ground, and each switch element 84 , 86 in the plurality of differently sized switch elements 82 has its own control signal.
  • the larger switch element 84 has a control signal SW 1 and the smaller switch element 86 has a control signal SW 2 .
  • FIG. 9 shows a time domain plot of the control signals of the present invention method for switching off the switched capacitor circuit 20 e as shown in FIG. 8.
  • the sequence controller 88 ensures that the switch elements 84 , 86 are switched off in decreasing order based on switch size. Because switch element 84 is larger than switch element 86 , switch element 84 is first switched off at time t 1 . At time t 2 , which is after t 1 , switch element 86 is switched off.
  • the present invention takes advantage of this fact because the larger switch elements with larger voltage drops due to turning off the larger switch elements are switched off first. Until the last switch element is switched off, node A is connected to ground and clock feedthrough effect is not a concern. If the last switch element to be switched off is made sufficiently small, the clock feedthrough effect after the last switch is switched off can be made negligible.
  • FIG. 10 shows a generalized third embodiment switched capacitor circuit 20 f schematic.
  • a capacitor 90 is connected between the first oscillator node OSC_P and a node A.
  • a plurality of differently sized switch elements 92 selectively connects node A to ground, and each switch element in the plurality of differently sized switch elements 92 has its own control signal.
  • a largest switch element Switch[ 1 ] has a control signal SW[ 1 ] and a size of W [ 1 ].
  • a smaller switch element Switch[ 2 ] has a control signal SW[ 2 ] and a size of W[ 2 ], where W[ 2 ] is smaller than W[ 1 ].
  • a second smallest switch element Switch[N- 1 ] has a control signal SW[N- 1 ] and a size of W[N- 1 ], where W[N- 1 ] is smaller than W[N- 2 ].
  • a smallest switch element Switch[N] has a control signal SW[N] and a size of W[N], where W[N] is smaller than W[N- 1 ].
  • a sequence controller 96 provides the control signals SW[ 1 ] to SW[N] and ensures that the switch elements are switched off in decreasing order based on switch size.
  • a low-pass filter 94 can be added, or not added, to the control terminal the smallest switch element Switch[N]. Similar to the circuit shown in FIG. 4, the low-pass filter 94 will gradually shut off the last switch element Switch[N] minimizing the clock feedthrough effect of the switched capacitor circuit 20 f.
  • FIG. 11 shows an example of the differential switched capacitor circuit 20 g according to the fourth embodiment of the present invention.
  • the differential switched capacitor circuit 20 g comprises a positive side capacitor 100 , a negative side capacitor 102 , a center switch element 104 , a sequence controller 116 , a plurality of differently sized positive side switch elements 106 , and for each switch element in the plurality of the differently sized positive side switch elements 106 , a corresponding negative side switch element having substantially the same size as the positive side switch element.
  • FIG. 11 shows two positive side switch elements 108 , 110 and two corresponding negative side switch elements 112 , 114 but this is meant as an example only and more switch elements could be used.
  • switch elements 108 and 112 are of substantially the same size and are larger than switch elements 110 and 114 , which are also of substantially the same size.
  • the positive side capacitor 100 is connected between the first oscillator node OSC_P and a node A.
  • Each of the switch elements 108 , 110 in the plurality of differently sized positive side switch elements 106 selectively connects node A to ground and each switch element in the plurality of differently sized positive side switch elements 106 has its own control signal.
  • the negative side capacitor 102 is connected between the second oscillator node OSC_N and a node B. Node B is selectively connected to ground by each of the corresponding negative side switch elements 112 , 114 depending on the control signal of the positive side switch element 108 , 110 respectively.
  • FIG. 12 shows a time domain plot of the control signals of the present invention method for switching off the forth embodiment of the switched capacitor circuit 20 g as shown in FIG. 11.
  • the sequence controller 116 ensures that the center switch element 104 is first switched off (at time t 1 ) and then the remaining switch elements are switched off in pairs in decreasing order based on switch size.
  • t 2 which is after t 1
  • switch elements 108 and 112 are switched off.
  • t 3 which is after t 2
  • switch elements 110 and 114 are switched off.
  • the positive side switch element 108 and its corresponding negative side switch element 112 are larger in size than the positive side switch element 110 and its corresponding negative side switch element 114 , the positive side switch element 108 and the negative side switch element 112 are switched off next. Until the last positive and negative side switch elements 110 , 114 are switched off, node A and node B are connected to ground and clock feedthrough effect is not a concern. If the last switch element pair to be switched off is made sufficiently small, the clock feedthrough effect of the differential switch circuit 20 g can be made negligible.
  • FIG. 13 shows a generalized fourth embodiment differential switched capacitor circuit 20 h .
  • a positive side capacitor 120 is connected between the first oscillator node OSC_P and a node A.
  • a plurality of differently sized positive side switch elements 122 selectively connects node A to ground and each switch element in the plurality of differently sized positive side switch elements 122 has its own control signal.
  • a largest positive side switch element P_Switch[ 1 ] has a control signal SW[ 1 ] and a size of W[ 1 ].
  • a smaller positive side switch element P_Switch[ 2 ] has a control signal SW[ 2 ] and a size of W[ 2 ], where W[ 2 ] is smaller than W[ 1 ].
  • a second smallest positive side switch element P_Switch[N- 1 ] has a control signal SW[N- 1 ] and a size of W[N- 1 ], where W[N- 1 ] is smaller than W[N- 2 ].
  • a smallest positive side switch element P_Switch[N] has a control signal SW[N] and a size of W [N], where W[N] is smaller than W[N- 1 ].
  • a corresponding negative side switch element having substantially the same size as the positive side switch element selectively connects a node B to ground depending on the same control signal as the positive side switch element.
  • a largest negative side switch element N_Switch[ 1 ] has the control signal SW[ 1 ] and the size of W[ 1 ].
  • a smaller negative side switch element N_Switch[ 2 ] has the control signal SW[ 2 ] and the size of W[ 2 ].
  • a second smallest negative side switch element N_Switch[N- 1 ] has the control signal SW[N- 1 ] and the size of W[N- 1 ].
  • a smallest negative side switch element N_Switch[N] has the control signal SW[N] and a size of W[N].
  • a negative side capacitor 124 is connected between node B and the second oscillator node OSC_N.
  • a center switch element 126 selectively connects node A to node B depending on a control signal SW_CENTER.
  • a low-pass filter 128 can be connected, or not connected, to the control terminals for the smallest switch element pair. Similar to the circuit in FIG. 6, the low-pass filter 128 will gradually shut off the last switch element pair P_Switch[N], N_Switch[N] minimizing the clock feedthrough effect of the differential switched capacitor circuit 20 h .
  • a sequence controller 130 provides the control signals SW_CENTER and SW[ 1 ] to SW[N] and ensures that the center switch element is first switched off and then the remaining switch elements are switched off in pairs in decreasing order based on switch size. Without the center switch element 126 , the switched capacitor circuit 30 h is itself another embodiment of the differential type switched capacitor circuit.
  • FIG. 14 shows a method flowchart 198 for minimizing clock feedthrough effect when switching off a switched capacitor circuit 20 according to the present invention.
  • the method flowchart 198 contains the following steps:
  • Step 200 Provide a plurality of differently sized switch elements: Each switch element in the plurality of differently sized switch elements is for selectively connecting a first terminal of a capacitor to a node depending upon a control signal applied to a control terminal of the switch element.
  • Step 202 Provide a low-pass filter to gradually switch off the smallest switch element:
  • the low-pass filter is connected to the control terminal of the smallest switch element.
  • Step 204 When switching off, sequence the control signals such that the switch elements are switched off in decreasing order based on size: The largest switch element is switched off first, the next largest is switched off next, and so on until the smallest switch element is switched off last. Until the smallest switch element is switched off, the first terminal of the capacitor is connected to the node and the clock feedthrough effect is not a concern. The low-pass filter will gradually switch off the last switch element minimizing the clock feedthrough effect of the smallest switch element and the switched capacitor circuit 20 as a whole.
  • the node is preferably connected to ground, however, the method according to the present invention is not limited to this configuration.
  • FIG. 15 shows a method flowchart 208 for minimizing clock feedthrough effect when switching off a differential switched capacitor circuit 20 according to the present invention.
  • the method flowchart 208 contains the following steps:
  • Step 210 Provide a plurality of differently sized positive side switch elements: Each positive side switch element in the plurality of differently sized positive side switch elements is for selectively connecting a first terminal of a positive side capacitor to a first node depending upon a control signal applied to a control terminal of each of the switch elements.
  • Step 212 For each positive side switch element, provide a corresponding same size negative side switch element: Each corresponding same size negative side switch element is for selectively connecting a first terminal of a negative side capacitor to a second node depending upon the control signal applied to the control terminal of the positive side switch element.
  • Step 214 Provide a low-pass filter to gradually switch off the smallest positive and negative side switch elements:
  • the low-pass filter is connected to the control terminal of the smallest positive and negative side switch element.
  • Step 216 Provide a center switch element: The center switch element selectively connects the positive side capacitor to the negative side capacitor depending on a control signal applied to a control terminal of the center switch element.
  • Step 218 When switching off, sequence the control signals such that the center switch element is first switched off and then the other switch elements are switched off in pairs in decreasing order based on switch size, whereby the largest positive side switch element and its corresponding negative side switch element are switched off first, the next largest switch element pair is switch off next, and the smallest switch element pair is switched off last. Until the smallest switch element pair is switched off, the first terminal of the positive side capacitor and the first terminal of the negative side capacitor are connected to the first node and the second respectively so that the clock feedthrough effect is not a concern.
  • the low-pass filter gradually switches off the last switch element minimizing the clock feedthrough effect of the smallest switch element and the switched capacitor circuit 20 as a whole.
  • the first node and the second node are preferably connected to ground, however, the method according to the present invention is not limited to this configuration.
  • the present invention gradually switches off the switched capacitor circuit so that the clock feedthrough effect is minimized and accordingly the undesired frequency drift of the VCO 10 frequency is properly reduced.
  • the prior art implementations suffer from clock feedthrough effect that causes a voltage step change to occur at an internal capacitive node of the VCO 10 .
  • the voltage step change causes the junction diode formed by a switch element in the off state to be slightly forward biased until the dropped voltage returns to the ground potential.
  • the voltage step change at the internal capacitive node is minimized.
  • the present invention can minimize the momentary change of the capacitance value of the VCO 10 resonator and the momentary drift in the VCO 10 frequency.

Abstract

A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.

Description

    BACKGROUND OF INVENTION
  • 1. Field of the Inventionbk2E001200303263 [0001]
  • The present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit used in a voltage controlled oscillator (VCO) that can minimize the clock feedthrough effect thereby preventing the VCO frequency drift phenomenon during calibration and the synthesizer phase locking period. [0002]
  • 2. Description of the Prior Art [0003]
  • A voltage controlled oscillator (VCO) is commonly used for frequency synthesis in wireless communication circuits. As Welland, et al. state in U.S. Pat. No. 6,226,506, wireless communication systems typically require frequency synthesis in both the receive path circuitry and the transmit path circuitry. [0004]
  • FIG. 1 shows a VCO circuit according to the prior art. An LC type VCO [0005] 10 used in a frequency synthesizer contains aresonator, the basic resonant structure includes an inductor 12 connected between a first oscillator node OSC_P and a second oscillator node OSC_N. Connected in parallel with the inductor 12 is a continuously variable capacitor 14 and a plurality of discretely variable capacitors 16. The continuously variable capacitor 14 is used for fine-tuning a desired capacitance while the plurality of discretely variable capacitors 16 is used for coarse tuning. The resistive loss of the parallel combination of inductor and capacitors is compensated by a negative resistance generator 18 to sustain the oscillation.
  • Each discretely variable capacitor in the plurality of discretely [0006] variable capacitors 16 is made up of a switched capacitor circuit 20 and each switched capacitor circuit is controlled by an independent control signal 22.
  • Based on this [0007] control signal 22 the switched capacitor circuit 20 can selectively connect or disconnect a capacitor 24 to the resonator of the VCO 10. Different on/off combinations of switched capacitor arrays results in a wider capacitance range of the LC type resonator and hence a wider VCO 10 oscillation frequency coverage.
  • FIG. 2 shows a switched [0008] capacitor circuit 20 a according to the prior art. A capacitor 30 is connected between the first oscillator node OSC_P and a node A. A switch element 32 selectively connects node A to ground, and the switch element 32 is controlled by a control signal SW. When the switch element 32 is turned on, the capacitance associated with the capacitor 30 is added to the overall capacitance in the VCO 10 resonator. When the switch element 32 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor 30 and the off state capacitance associated with the switch element 32.
  • FIG. 3 shows a differential type switched [0009] capacitor circuit 20 b according to the prior art. Differential implementations have much greater common-mode noise rejection and are widely used in high-speed integrated circuit environments. In the differential switched capacitor circuit 20 b, a positive side capacitor 40 is connected between the first oscillator node OSC_P and a node A. A positive side switch element 42 selectively connects node A to ground. A negative side capacitor 44 is connected between the second oscillator node OSC_N and a node B. A negative side switch element 46 selectively connects node B to ground. There is also a center switch element 48 used to lower the overall turn-on switch resistance connected between node A and node B. All three switch elements 42, 46, 48 are controlled by the same control signal SW. When the switch elements 42, 46, 48 are turned on, the capacitance associated with the series combination of the positive and negative side capacitors 40, 44 is added to the overall capacitance in the VCO 10. When the switch elements 42, 46, 48 are turned off, the differential input capacitance is the series combination of the positive and negative side capacitors 40, 44 and other switch parasitic capacitance. The overall input capacitance when all switch elements 42, 46, 48 are turned off is lower than that when all switch elements 42, 46, 48 are turned on. Without the center switch element 48, the switched capacitor circuit 20 b is itself another embodiment of the differential type switch capacitor circuit according to the prior art.
  • Regardless of whether the single ended implementation shown in FIG. 2 or the differential implementation shown in FIG. 3 is used, when the switched [0010] capacitor circuit 20 a or 20 b is turned off, a momentary voltage step change occurs at node A (and in the case of the differential implementation shown in FIG. 3 also at node B). The momentary voltage step causes an undesired change in the overall capacitance, and ultimately, an undesired change in the VCO 10 frequency. This momentary voltage step change in FIG. 2 and FIG. 3, by using NMOS switches, is a voltage drop when the switch elements 32, 42, 46, 48 are turned off.
  • Using the single ended case shown in FIG. 2 as an example, when the [0011] switch element 32 is turned off, charge carriers are injected to the junction capacitance connected between the first terminal and the second terminal of the switch element 32. The injection produces an undesired voltage step change across the capacitive impedance and appears as a voltage drop at node A. This effect is known as clock feedthrough effect and appears as a feedthrough of the control signal SW from the control terminal of the switch element 32 to the first and second terminals of the switch element 32. When the switch element 32 is turned on, node A is connected to ground so the feedthrough of the control signal SW is of no consequence. However, when the switch element 32 is turned off, the feedthrough of the control signal SW causes a voltage step, in the form a voltage drop to appear at node A. Because of the dropped voltage at node A, the diode formed by the N30 diffusion of switch element 32 and the P type substrate in the off state will be slightly forward biased. The voltage level at node A will spike low and then recover to ground potential as the forward biased junction diode formed by the switch element 32 in the off state allows current to flow. The voltage drop and recovery at node A changes the load capacitance of the VCO 10 resonator and causes an undesired momentarily drift in the VCO 10 frequency.
  • When the differential switched [0012] capacitor circuit 20 b shown in FIG. 3 switches off, it suffers from the same clock feedthrough effect problem at node A and at node B. The positive side node A has an undesired voltage step change caused by the clock feedthrough effect of both the positive side switch element 42 and the clock feedthrough effect of the center switch element 48. Similarly, the negative side node B has an undesired voltage step caused by the clock feedthrough effect of both the negative side switch element 46 and the clock feedthrough effect of the center switch element 48. The voltage step change and recovery at node A and node B changes the capacitance of the VCO 10 resonator and causes an undesired momentary drift in the VCO 10 frequency.
  • SUMMARY OF INVENTION
  • It is therefore a primary objective of the present invention to provide a switched capacitor circuit capable of minimizing the clock feedthrough effect, to solve the above-mentioned problem. [0013]
  • According to the present invention, a switched capacitor circuit capable of minimizing clock feedthrough effect. The switched capacitor circuit comprising a switch element having a first terminal connected to a capacitor, a second terminal connected to ground, and a control terminal; and a low-pass filter having an input terminal connected to a control signal and an output terminal connected to the control terminal of the switch element, wherein the low-pass filter is for making the switch element gradually switch off. [0014]
  • According to the present invention, a switched capacitor circuit capable of minimizing clock feedthrough effect, comprising a plurality of differently sized switch elements for selectively connecting a capacitor to a node depending upon a control signal applied to a control terminal of each of the switch elements. A sequence controller having a plurality of control signal outputs for switching off the switch elements in the plurality of differently sized pull down switch elements in sequence based on decreasing order of switch size. The switched capacitor circuit further comprising a means for making the smallest switch elements gradually switch off. [0015]
  • According to the present invention, a method for minimizing clock feedthrough effect when switching a switched capacitor circuit. The method comprises providing a plurality of differently sized switch elements that selectively connect a capacitor to a node depending upon a control signal applied to a control terminal of each of the switch elements. When switching the switched capacitor circuit to an off state, sequencing the control signals such that the switch elements are switched off in decreasing order based on size, whereby the largest switch element is switched off first and the smallest switch element is switched off last. The method further comprising when switching the switched capacitor circuit to an off state, providing a means for making the smallest switch element gradually switch off. [0016]
  • It is a further advantage of the present invention that the switched capacitor circuit is gradually switched off to minimize the clock feedthrough effect and prevent an undesired drift in the [0017] VCO 10 frequency. In the prior art, the switched capacitor circuit is instantly switched from an on state to an off state. The clock feedthrough effect in the prior art implementations causes an undesired voltage step change to slightly forward bias the junction diode formed by the switch element in the off state until the voltage potential has returned to ground.
  • These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.[0018]
  • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a schematic diagram of a typical Voltage Controlled Oscillator (VCO) circuit used in a frequency synthesizer according to the prior art. [0019]
  • FIG. 2 shows a switched capacitor circuit used in the VCO of FIG. 1 according to the prior art. [0020]
  • FIG. 3 shows a differential type switched capacitor circuit used in the VCO of FIG. 1 according to the prior art. [0021]
  • FIG. 4 shows a switched capacitor circuit according to the first embodiment of the present invention. [0022]
  • FIG. 5 shows a time domain plot of the control signals for the switched capacitor circuit of FIG. 4 [0023]
  • FIG. 6 shows a differential switched capacitor circuit according to the second embodiment of the present invention. [0024]
  • FIG. 7 shows a time domain plot of the control signals for the differential switched capacitor circuit of FIG. 6. [0025]
  • FIG. 8 shows an example switched capacitor circuit according to the third embodiment of the present invention. [0026]
  • FIG. 9 shows a time domain plot of the present invention control signals for switching off the switched capacitor circuit of FIG. 8 [0027]
  • FIG. 10 shows a generalized switched capacitor circuit of FIG. 8 with a low-pass filter added to the control terminal of the smallest switch element. [0028]
  • FIG. 11 shows a differential switched capacitor circuit according to the fourth embodiment of the present invention. [0029]
  • FIG. 12 shows a time domain plot of the present invention control signals for switching off the differential switched capacitor circuit of FIG. 11. [0030]
  • FIG. 13 shows a generalized differential switched capacitor circuit of FIG. 11 with a low-pass filter added to the control terminal of the smallest pull down switch element at the positive side and its corresponding pull down switch element at the negative side. [0031]
  • FIG. 14 shows a method flowchart for minimizing clock feedthrough effect when switching off a switched capacitor circuit according to the present invention. [0032]
  • FIG. 15 shows a method flowchart for minimizing clock feedthrough effect when switching off a differential switched capacitor circuit according to the present invention.[0033]
  • DETAILED DESCRIPTION
  • FIG. 4 shows a switched [0034] capacitor circuit 20 c according to the first embodiment of the present invention. In the first embodiment, the switched capacitor circuit 20 c comprises a capacitor 50, a switch element 52, and a low-pass filter 54. The capacitor 50 is connected between the first oscillator node OSC_P and a node A. Depending on the control signal SW, the switch element 52 selectively connects the node A to ground. When the switch element 52 is turned on, the capacitance associated with the capacitor 50 is added to the overall capacitance in the VCO 10. When the switch element 52 is turned off, the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor 50 and the off state capacitance associated with the switch element 32. A low-pass filter 54 is connected to a control terminal of the switch element 52 for making the switch element 52 gradually switch off.
  • FIG. 5 is a time domain plot of the control signal SW before the low-[0035] pass filter 54 and a signal SW_FILTER after the low-pass filter 54. At time t1 the control signal SW changes to a logic low. The low-pass filter 54 causes the signal SW_FILTER at the control terminal of the switch element 52 to gradually change from a logic high to a logic low and minimizes the voltage step change seen at node A. Because the switch element 52 is gradually switched off, node A is gradually disconnected from ground. As the switch element 52 is gradually switched off, during a period of delay time there exists a conduction path of the switch element, even with an increasing resistance, to ground to minimize the clock feedthrough effect. In contrast to the prior art, the present invention does not forward bias the diode formed by the switch element 52 in the off state. The clock feedthrough effect at each moment in time is reduced.
  • FIG. 6 shows a differential switched [0036] capacitor circuit 20 d according to the second embodiment of the present invention. A positive side capacitor 60 is connected between the first oscillator node OSC_P and a node A. A positive side switch element 62 selectively connects node A to ground. A negative side capacitor 64 is connected between the second oscillator node OSC_N and a node B. A negative side switch element 66 selectively connects node B to ground. A center switch element 68 is used to lower the overall turn-on resistance and is connected between node A and node B. A low-pass filter 70 is connected to the control terminals of the positive side switch element 62 and the negative side switch element 66 for making the positive and negative side switch elements 62, 66 gradually switch off. Without the center switch element 68, the switched capacitor circuit 20 d is itself another embodiment of the differential type switched capacitor circuit.
  • FIG. 7 is a time domain plot of the control signal SW before the low-pass filter and the signal SW_FILTER after the low-pass filter. The [0037] center switch element 68 is directly controlled by the control signal SW while the positive and negative side switch elements 62, 66 are controlled by the output of the low-pass filter 70, signal SW_FITLER. At time t1 the control signal SW changes from a logic high to a logic low and the center switch element 68 immediately changes to an off state. Because the positive and negative side switch elements 62, 66 gradually switch off, during a period of delay time, node A and node B are still connected to ground and the clock feedthrough effect due to the center switch element 68 is minimized by the conduction to ground path. As in the single ended embodiment of FIG. 4, as the positive and negative side switch elements 62, 66 gradually switch off, the clock feedthrough effect produced at node A and B at each moment of time is reduced.
  • FIG. 8 shows an example of the switched [0038] capacitor circuit 20 e according to the third embodiment of the present invention. In the third embodiment, the switched capacitor circuit 20 e comprises a capacitor 80, a sequence controller 88, and a plurality of differently sized switch elements 82. FIG. 8 shows two switch elements 84, 86 but this is meant as an example only and more switch elements could be used. In this example, switch element 84 is larger than switch element 86. The capacitor 80 is connected between the first oscillator node OSC_P and a node A. Each of the switch elements 84, 86 in the plurality of differently sized switch elements 82 selectively connects node A to ground, and each switch element 84, 86 in the plurality of differently sized switch elements 82 has its own control signal. In this example the larger switch element 84 has a control signal SW1 and the smaller switch element 86 has a control signal SW2.
  • FIG. 9 shows a time domain plot of the control signals of the present invention method for switching off the switched [0039] capacitor circuit 20 e as shown in FIG. 8. In order to gradually switch the switched capacitor circuit 20 e to an off state, the sequence controller 88 ensures that the switch elements 84, 86 are switched off in decreasing order based on switch size. Because switch element 84 is larger than switch element 86, switch element 84 is first switched off at time t1. At time t2, which is after t1, switch element 86 is switched off. Since the amount of voltage change at node A due to the clock feedthrough effect depends on the parasitic capacitance ratio of control terminal to first terminal and first terminal to second terminal capacitance, the smaller the control terminal to first terminal capacitance the smaller the voltage change due to the feedthrough of the control signal switching from high to low. The present invention takes advantage of this fact because the larger switch elements with larger voltage drops due to turning off the larger switch elements are switched off first. Until the last switch element is switched off, node A is connected to ground and clock feedthrough effect is not a concern. If the last switch element to be switched off is made sufficiently small, the clock feedthrough effect after the last switch is switched off can be made negligible.
  • FIG. 10 shows a generalized third embodiment switched [0040] capacitor circuit 20 f schematic. A capacitor 90 is connected between the first oscillator node OSC_P and a node A. A plurality of differently sized switch elements 92 selectively connects node A to ground, and each switch element in the plurality of differently sized switch elements 92 has its own control signal. A largest switch element Switch[1] has a control signal SW[1] and a size of W [1]. A smaller switch element Switch[2] has a control signal SW[2] and a size of W[2], where W[2] is smaller than W[1]. A second smallest switch element Switch[N-1] has a control signal SW[N-1] and a size of W[N-1], where W[N-1] is smaller than W[N-2]. A smallest switch element Switch[N] has a control signal SW[N] and a size of W[N], where W[N] is smaller than W[N-1]. A sequence controller 96 provides the control signals SW[1] to SW[N] and ensures that the switch elements are switched off in decreasing order based on switch size. As shown in FIG. 10, a low-pass filter 94 can be added, or not added, to the control terminal the smallest switch element Switch[N]. Similar to the circuit shown in FIG. 4, the low-pass filter 94 will gradually shut off the last switch element Switch[N] minimizing the clock feedthrough effect of the switched capacitor circuit 20 f.
  • FIG. 11 shows an example of the differential switched [0041] capacitor circuit 20 g according to the fourth embodiment of the present invention. The differential switched capacitor circuit 20 g comprises a positive side capacitor 100, a negative side capacitor 102, a center switch element 104, a sequence controller 116, a plurality of differently sized positive side switch elements 106, and for each switch element in the plurality of the differently sized positive side switch elements 106, a corresponding negative side switch element having substantially the same size as the positive side switch element. FIG. 11 shows two positive side switch elements 108, 110 and two corresponding negative side switch elements 112, 114 but this is meant as an example only and more switch elements could be used. In this example, switch elements 108 and 112 are of substantially the same size and are larger than switch elements 110 and 114, which are also of substantially the same size. The positive side capacitor 100 is connected between the first oscillator node OSC_P and a node A. Each of the switch elements 108, 110 in the plurality of differently sized positive side switch elements 106 selectively connects node A to ground and each switch element in the plurality of differently sized positive side switch elements 106 has its own control signal. The negative side capacitor 102 is connected between the second oscillator node OSC_N and a node B. Node B is selectively connected to ground by each of the corresponding negative side switch elements 112, 114 depending on the control signal of the positive side switch element 108, 110 respectively. In this example, the larger switch elements 108, 112 have a control signal SW1 and the smaller switch elements 110, 114 have a control signal SW2. Without the center switch element 104, the switched capacitor circuit 20 g is itself another embodiment of the differential type switched capacitor circuit.
  • FIG. 12 shows a time domain plot of the control signals of the present invention method for switching off the forth embodiment of the switched [0042] capacitor circuit 20 g as shown in FIG. 11. In order to gradually switch the switched capacitor circuit 20 g to an off state, the sequence controller 116 ensures that the center switch element 104 is first switched off (at time t1) and then the remaining switch elements are switched off in pairs in decreasing order based on switch size. At t2, which is after t1, switch elements 108 and 112 are switched off. At t3, which is after t2, switch elements 110 and 114 are switched off. Because the positive side switch element 108 and its corresponding negative side switch element 112 are larger in size than the positive side switch element 110 and its corresponding negative side switch element 114, the positive side switch element 108 and the negative side switch element 112 are switched off next. Until the last positive and negative side switch elements 110, 114 are switched off, node A and node B are connected to ground and clock feedthrough effect is not a concern. If the last switch element pair to be switched off is made sufficiently small, the clock feedthrough effect of the differential switch circuit 20 g can be made negligible.
  • FIG. 13 shows a generalized fourth embodiment differential switched [0043] capacitor circuit 20 h. A positive side capacitor 120 is connected between the first oscillator node OSC_P and a node A. A plurality of differently sized positive side switch elements 122 selectively connects node A to ground and each switch element in the plurality of differently sized positive side switch elements 122 has its own control signal. A largest positive side switch element P_Switch[1] has a control signal SW[1] and a size of W[1]. A smaller positive side switch element P_Switch[2] has a control signal SW[2] and a size of W[2], where W[2] is smaller than W[1]. A second smallest positive side switch element P_Switch[N-1] has a control signal SW[N-1] and a size of W[N-1], where W[N-1] is smaller than W[N-2]. A smallest positive side switch element P_Switch[N] has a control signal SW[N] and a size of W [N], where W[N] is smaller than W[N-1]. For each switch element in the plurality of the differently sized positive side switch elements 122, a corresponding negative side switch element having substantially the same size as the positive side switch element selectively connects a node B to ground depending on the same control signal as the positive side switch element. A largest negative side switch element N_Switch[1] has the control signal SW[1] and the size of W[1]. A smaller negative side switch element N_Switch[2] has the control signal SW[2] and the size of W[2]. A second smallest negative side switch element N_Switch[N-1] has the control signal SW[N-1] and the size of W[N-1]. A smallest negative side switch element N_Switch[N] has the control signal SW[N] and a size of W[N]. A negative side capacitor 124 is connected between node B and the second oscillator node OSC_N. A center switch element 126 selectively connects node A to node B depending on a control signal SW_CENTER. A low-pass filter 128 can be connected, or not connected, to the control terminals for the smallest switch element pair. Similar to the circuit in FIG. 6, the low-pass filter 128 will gradually shut off the last switch element pair P_Switch[N], N_Switch[N] minimizing the clock feedthrough effect of the differential switched capacitor circuit 20 h. A sequence controller 130 provides the control signals SW_CENTER and SW[1] to SW[N] and ensures that the center switch element is first switched off and then the remaining switch elements are switched off in pairs in decreasing order based on switch size. Without the center switch element 126, the switched capacitor circuit 30 h is itself another embodiment of the differential type switched capacitor circuit.
  • FIG. 14 shows a [0044] method flowchart 198 for minimizing clock feedthrough effect when switching off a switched capacitor circuit 20 according to the present invention. The method flowchart 198 contains the following steps:
  • Step [0045] 200: Provide a plurality of differently sized switch elements: Each switch element in the plurality of differently sized switch elements is for selectively connecting a first terminal of a capacitor to a node depending upon a control signal applied to a control terminal of the switch element.
  • Step [0046] 202: Provide a low-pass filter to gradually switch off the smallest switch element: The low-pass filter is connected to the control terminal of the smallest switch element.
  • Step [0047] 204: When switching off, sequence the control signals such that the switch elements are switched off in decreasing order based on size: The largest switch element is switched off first, the next largest is switched off next, and so on until the smallest switch element is switched off last. Until the smallest switch element is switched off, the first terminal of the capacitor is connected to the node and the clock feedthrough effect is not a concern. The low-pass filter will gradually switch off the last switch element minimizing the clock feedthrough effect of the smallest switch element and the switched capacitor circuit 20 as a whole.
  • It should be noted that in the [0048] method flowchart 198 shown in FIG. 14 the node is preferably connected to ground, however, the method according to the present invention is not limited to this configuration.
  • FIG. 15 shows a [0049] method flowchart 208 for minimizing clock feedthrough effect when switching off a differential switched capacitor circuit 20 according to the present invention. The method flowchart 208 contains the following steps:
  • Step [0050] 210: Provide a plurality of differently sized positive side switch elements: Each positive side switch element in the plurality of differently sized positive side switch elements is for selectively connecting a first terminal of a positive side capacitor to a first node depending upon a control signal applied to a control terminal of each of the switch elements.
  • Step [0051] 212: For each positive side switch element, provide a corresponding same size negative side switch element: Each corresponding same size negative side switch element is for selectively connecting a first terminal of a negative side capacitor to a second node depending upon the control signal applied to the control terminal of the positive side switch element.
  • Step [0052] 214: Provide a low-pass filter to gradually switch off the smallest positive and negative side switch elements: The low-pass filter is connected to the control terminal of the smallest positive and negative side switch element.
  • Step [0053] 216: Provide a center switch element: The center switch element selectively connects the positive side capacitor to the negative side capacitor depending on a control signal applied to a control terminal of the center switch element.
  • Step [0054] 218: When switching off, sequence the control signals such that the center switch element is first switched off and then the other switch elements are switched off in pairs in decreasing order based on switch size, whereby the largest positive side switch element and its corresponding negative side switch element are switched off first, the next largest switch element pair is switch off next, and the smallest switch element pair is switched off last. Until the smallest switch element pair is switched off, the first terminal of the positive side capacitor and the first terminal of the negative side capacitor are connected to the first node and the second respectively so that the clock feedthrough effect is not a concern. The low-pass filter gradually switches off the last switch element minimizing the clock feedthrough effect of the smallest switch element and the switched capacitor circuit 20 as a whole.
  • Similarly, it should be noted that in the [0055] method flowchart 208 shown in FIG. 15 the first node and the second node are preferably connected to ground, however,the method according to the present invention is not limited to this configuration.
  • In contrast to the prior art, the present invention gradually switches off the switched capacitor circuit so that the clock feedthrough effect is minimized and accordingly the undesired frequency drift of the [0056] VCO 10 frequency is properly reduced. When switching off, the prior art implementations suffer from clock feedthrough effect that causes a voltage step change to occur at an internal capacitive node of the VCO 10. The voltage step change causes the junction diode formed by a switch element in the off state to be slightly forward biased until the dropped voltage returns to the ground potential.
  • According to the present invention, the voltage step change at the internal capacitive node is minimized. When switching off, the present invention can minimize the momentary change of the capacitance value of the [0057] VCO 10 resonator and the momentary drift in the VCO 10 frequency.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims. [0058]

Claims (6)

1. A switched capacitor circuit capable of minimizing clock feedthrough effect, comprising:
a positive side switch element for selectively connecting a positive side first node to a positive side second node depending upon a signal applied to a first control terminal of the positive side switch element, wherein the positive side first node is connected to a positive side capacitor; and
a low-pass filter having an input terminal connected to a control signal and an output terminal connected to the first control terminal of the positive side switch element for making the positive side switch element gradually switch of, wherein the control signal is substantially a two-level signal with a first level for switching off the switched capacitor circuit and a second level for switching on the switched capacitor circuit.
2. The switched capacitor circuit of claim 1, wherein the positive side second node is ground and the positive side switch element is an NMOS transistor.
3. The switched capacitor circuit of claim 1, further comprising:
a negative side switch element of substantially the same size as the positive side switch element for selectively connecting a negative side first node to a negative side second node depending upon the control signal applied to the first control terminal of the positive side switch element, wherein the negative side first node is connected to a negative side capacitor.
4. The switched capacitor circuit of claim 3, further comprising:
a center switch element having a first terminal connected to the positive side first node, a second terminal connected to the negative side first node, and a third control terminal connected to the control signal.
5. The switched capacitor circuit of claim 4, wherein the positive side second node is ground, the negative side second node is ground, and the positive side switch element, the negative side switch element, and the center switch element are NMOS transistors.
6-24. (cancelled)
US10/250,082 2003-06-03 2003-06-03 Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit Abandoned US20040246039A1 (en)

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US10/250,082 US20040246039A1 (en) 2003-06-03 2003-06-03 Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit
US10/605,095 US6815996B1 (en) 2003-06-03 2003-09-09 Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit
US10/709,461 US20040246040A1 (en) 2003-06-03 2004-05-06 Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit
TW093115671A TWI240479B (en) 2003-06-03 2004-06-01 Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit
PCT/CN2004/000599 WO2004107558A1 (en) 2003-06-03 2004-06-03 A switched-capacitive circuit and method for reducing clock feedthrough in voltage controlled oscillator
CN200480006928.5A CN100468953C (en) 2003-06-03 2004-06-03 A switched-capacitive circuit and method for reducing clock feedthrough in voltage controlled oscillator

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7015742B2 (en) * 2003-06-20 2006-03-21 Media Tek Inc. Switched capacitor circuit capable of eliminating clock feedthrough by complementary control signals for digital tuning VCO
JP4698592B2 (en) * 2004-06-25 2011-06-08 スパンション エルエルシー Voltage control circuit and semiconductor device
US7071790B2 (en) * 2004-10-29 2006-07-04 Broadcom Corporation Method and system for a differential switched capacitor array for a voltage controlled oscillator (VCO) or a local oscillator (LO) buffer
US7312646B2 (en) * 2005-05-13 2007-12-25 Packet Digital Method and apparatus for controlling switching transients
DE102006027419A1 (en) * 2006-06-13 2007-12-20 Xignal Technologies Ag Circuit arrangements for digital coarse adjustment of voltage-controlled oscillator and oscillation frequency adjustment of oscillator, has field effect transistors connected to secondary connection with reference potential
WO2008047416A1 (en) * 2006-10-18 2008-04-24 Spansion Llc Voltage detecting circuit
JP5229218B2 (en) * 2007-03-21 2013-07-03 富士通セミコンダクター株式会社 Switching capacitor generation circuit, voltage controlled oscillator, and LC bandpass filter
US8044739B2 (en) * 2009-06-09 2011-10-25 Qualcomm Incorporated Capacitor switching circuit
JP5608436B2 (en) * 2010-06-22 2014-10-15 ルネサスエレクトロニクス株式会社 Variable capacitance element
TW201246786A (en) * 2011-05-13 2012-11-16 Realtek Semiconductor Corp Switched capacitor circuit having switching loss compensation mechanism and compensation method thereof
TWI482434B (en) * 2012-04-17 2015-04-21 Realtek Semiconductor Corp Switched capacitor circuit and method of controlling switched capacitor circuit
US9356557B1 (en) * 2015-08-26 2016-05-31 Nxp B.V. Capacitor arrangement for oscillator
US10727847B1 (en) 2019-02-07 2020-07-28 International Business Machines Corporation Digital control of a voltage controlled oscillator frequency

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909748A (en) * 1974-05-30 1975-09-30 Rca Corp Digitally controlled oscillator using semiconductor capacitance elements
US4602222A (en) * 1985-04-19 1986-07-22 General Electric Company Circuit for bandswitching a voltage controlled oscillator
US4713631A (en) * 1986-01-06 1987-12-15 Motorola Inc. Varactor tuning circuit having plural selectable bias voltages
US5281870A (en) * 1991-02-28 1994-01-25 Nec Corporation Current controller
US5625325A (en) * 1995-12-22 1997-04-29 Microtune, Inc. System and method for phase lock loop gain stabilization
US5686864A (en) * 1995-09-05 1997-11-11 Motorola, Inc. Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer
US5739730A (en) * 1995-12-22 1998-04-14 Microtune, Inc. Voltage controlled oscillator band switching technique
US5745012A (en) * 1995-02-15 1998-04-28 Seiko Epson Corporation Voltage-controlled oscillator having a semiconductor integrated circuit, a piezoelectrics resonator and a diode and variable-capacitance diode
US5789964A (en) * 1997-02-14 1998-08-04 International Business Machines Corporation Decoupling capacitor network for off-state operation
US5801596A (en) * 1994-07-27 1998-09-01 Citizen Watch Co., Ltd. Temperature compensation type quartz oscillator
US5898345A (en) * 1996-08-12 1999-04-27 Matsushita Electric Industrial Co., Ltd. Oscillator circuit with first and second frequency control elements
US5912632A (en) * 1997-01-08 1999-06-15 International Business Machines Corporation Single chip RF tag oscillator circuit synchronized by base station modulation frequency
US5936474A (en) * 1996-04-02 1999-08-10 U.S. Philips Corporation Oscillator having correction element switchable by a fuse
US6147567A (en) * 1998-05-29 2000-11-14 Silicon Laboratories Inc. Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications
US6226506B1 (en) * 1998-05-29 2001-05-01 Silicon Laboratories, Inc. Method and apparatus for eliminating floating voltage nodes within a discreetly variable capacitance used for synthesizing high-frequency signals for wireless communications
US6323736B2 (en) * 1999-05-03 2001-11-27 Silicon Wave, Inc. Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device
US20020162382A1 (en) * 2001-05-02 2002-11-07 Kazuhiro Fujii Method and apparatus for inspecting airtightness of gas sensor
US6753738B1 (en) * 2001-06-25 2004-06-22 Silicon Laboratories, Inc. Impedance tuning circuit

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62220026A (en) * 1986-03-20 1987-09-28 Toshiba Corp Output buffer circuit
DE3920008A1 (en) * 1989-06-20 1991-01-10 Philips Patentverwaltung PHASE CONTROL CIRCUIT
US5130571A (en) * 1990-08-29 1992-07-14 Ventritex Optimizing speed and charge injection parameters of a switched capacitor circuit
US5473229A (en) * 1992-05-27 1995-12-05 General Electric Company Interface between programmable electronically commutated motor and personal computer and method of operation
JPH06152244A (en) * 1992-11-11 1994-05-31 Asahi Kasei Micro Syst Kk Piezoelectric oscillation circuit
US5483188A (en) * 1994-09-27 1996-01-09 Intel Corporation Gil edge rate control circuit
US5764112A (en) * 1996-08-27 1998-06-09 Microclock Incorporated Fully integrated voltage-controlled crystal oscillator
JPH10209752A (en) * 1997-01-22 1998-08-07 New Japan Radio Co Ltd Oscillation circuit configured as microwave integrated circuit
US5825219A (en) * 1997-02-21 1998-10-20 Silicon Integrated System Corp. Fast edge rate signal driver
US6154095A (en) * 1997-02-27 2000-11-28 Seiko Epson Corporation Phase locked loop clock source provided with a plurality of frequency adjustments
JP3829525B2 (en) * 1998-04-02 2006-10-04 セイコーエプソン株式会社 Capacitance array unit and oscillation circuit
US6563392B2 (en) * 1999-12-14 2003-05-13 Broadcom Corporation Varactor folding technique for phase noise reduction in electronic oscillators
DE10061241A1 (en) * 2000-12-08 2002-06-27 Infineon Technologies Ag oscillator circuit
US6583675B2 (en) * 2001-03-20 2003-06-24 Broadcom Corporation Apparatus and method for phase lock loop gain control using unit current sources
US6633202B2 (en) * 2001-04-12 2003-10-14 Gennum Corporation Precision low jitter oscillator circuit
US6501307B1 (en) * 2001-11-12 2002-12-31 Pericom Semiconductor Corp. Spread-spectrum clock buffer/driver that modulates clock period by switching loads

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909748A (en) * 1974-05-30 1975-09-30 Rca Corp Digitally controlled oscillator using semiconductor capacitance elements
US4602222A (en) * 1985-04-19 1986-07-22 General Electric Company Circuit for bandswitching a voltage controlled oscillator
US4713631A (en) * 1986-01-06 1987-12-15 Motorola Inc. Varactor tuning circuit having plural selectable bias voltages
US5281870A (en) * 1991-02-28 1994-01-25 Nec Corporation Current controller
US5801596A (en) * 1994-07-27 1998-09-01 Citizen Watch Co., Ltd. Temperature compensation type quartz oscillator
US5745012A (en) * 1995-02-15 1998-04-28 Seiko Epson Corporation Voltage-controlled oscillator having a semiconductor integrated circuit, a piezoelectrics resonator and a diode and variable-capacitance diode
US5686864A (en) * 1995-09-05 1997-11-11 Motorola, Inc. Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer
US5625325A (en) * 1995-12-22 1997-04-29 Microtune, Inc. System and method for phase lock loop gain stabilization
US5739730A (en) * 1995-12-22 1998-04-14 Microtune, Inc. Voltage controlled oscillator band switching technique
US5936474A (en) * 1996-04-02 1999-08-10 U.S. Philips Corporation Oscillator having correction element switchable by a fuse
US5898345A (en) * 1996-08-12 1999-04-27 Matsushita Electric Industrial Co., Ltd. Oscillator circuit with first and second frequency control elements
US5912632A (en) * 1997-01-08 1999-06-15 International Business Machines Corporation Single chip RF tag oscillator circuit synchronized by base station modulation frequency
US5789964A (en) * 1997-02-14 1998-08-04 International Business Machines Corporation Decoupling capacitor network for off-state operation
US6147567A (en) * 1998-05-29 2000-11-14 Silicon Laboratories Inc. Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications
US6226506B1 (en) * 1998-05-29 2001-05-01 Silicon Laboratories, Inc. Method and apparatus for eliminating floating voltage nodes within a discreetly variable capacitance used for synthesizing high-frequency signals for wireless communications
US6323736B2 (en) * 1999-05-03 2001-11-27 Silicon Wave, Inc. Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device
US20020162382A1 (en) * 2001-05-02 2002-11-07 Kazuhiro Fujii Method and apparatus for inspecting airtightness of gas sensor
US6753738B1 (en) * 2001-06-25 2004-06-22 Silicon Laboratories, Inc. Impedance tuning circuit

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CN1762090A (en) 2006-04-19
US6815996B1 (en) 2004-11-09
TW200505151A (en) 2005-02-01
WO2004107558A1 (en) 2004-12-09

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