US20040155274A1 - Capacitor structures with recessed hemispherical grain silicon - Google Patents
Capacitor structures with recessed hemispherical grain silicon Download PDFInfo
- Publication number
- US20040155274A1 US20040155274A1 US10/771,042 US77104204A US2004155274A1 US 20040155274 A1 US20040155274 A1 US 20040155274A1 US 77104204 A US77104204 A US 77104204A US 2004155274 A1 US2004155274 A1 US 2004155274A1
- Authority
- US
- United States
- Prior art keywords
- layer
- cavity
- opening
- hemispherical grain
- grain silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Definitions
- the present invention relates to semiconductor manufacturing. More particularly, the present invention provides capacitor structures including recessed hemispherical grain silicon and methods of forming the same.
- DRAMs dynamic random access memories
- SRAMs static random access memories
- FE ferroelectric memories
- conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers of contact holes, vias, etc.
- HSG hemispherical grains
- CMP is effective at separating the containers, it leaves a structure in which the hemispherical grain silicon precursor layer (i.e., the layer from which the hemispherical grain silicon is formed) and the underlying doped silicon layer both extend to the upper edge of the capacitor plates.
- the hemispherical grain silicon precursor layer i.e., the layer from which the hemispherical grain silicon is formed
- the underlying doped silicon layer both extend to the upper edge of the capacitor plates.
- the hemispherical grain silicon precursor layer i.e., the layer from which the hemispherical grain silicon is formed
- the underlying doped silicon layer both extend to the upper edge of the capacitor plates.
- Grains or particles from the exposed edge of the hemispherical grain silicon layer are, however, susceptible to separation from the hemispherical grain silicon layer. Once separated or broken off, the loose particles can fall between adjacent capacitors, resulting in electrical shorts between the adjacent capacitors. Such defects adversely affect the output of the manufacturing processes used to form the capacitors. Although typically associated with cup-shaped capacitors, these problems are also experienced in connection with other capacitor structures, e.g., trench, tub, etc.
- the present invention provides capacitor structures with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures.
- the resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput.
- the present invention also includes methods of forming the capacitor structures in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.
- the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity over about 20% or less of the distance between the opening and the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity and having a depth of about 2000 Angstroms or less from the opening of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity over about 20% or less of the distance between the opening and the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon
- the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity and having a depth of about 2000 Angstroms or less from the opening of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer including doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration greater than 2.25% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration greater than 2.25% (by weight) and less than 3% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hem
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and removing the hemispherical grain silicon in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity including a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer including doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration of greater than 2.25% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the
- the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration greater than 2.25% (by weight) and less than 3% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hem
- the present invention provides a capacitor including a cavity having a sidewall structure, an opening, and a bottom opposite the opening, the sidewall structure extending between the opening and the bottom of the cavity; a first electrode including an electrically conductive first layer located on an inner surface of the sidewall structure, a second layer including hemispherical grain silicon located on the first layer, and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, wherein the edge zone extends from the opening of the cavity towards the bottom of the cavity, and further wherein the edge zone is substantially free of the hemispherical grain silicon; a dielectric layer located on at least a portion of the first electrode; and a second electrode located on the dielectric layer.
- FIG. 1 is a cross-sectional view of an in-process capacitor structure at a stage in the fabrication following formation of a cavity 20 .
- FIG. 2 is a cross-sectional view of the capacitor structure of FIG. 1 following formation of a first layer 32 in the cavity 20 .
- FIG. 3 is a cross-sectional view of the capacitor structure of FIG. 2 following formation of a second layer 34 on the first layer 32 .
- FIG. 4 is a cross-sectional view of the capacitor structure of FIG. 3 following formation of a layer of fill material 40 in the cavity 20 .
- FIG. 5 is a cross-sectional view of the capacitor structure of FIG. 4 following planarization to remove the fill material 40 outside of the cavity 20 .
- FIG. 6 is a cross-sectional view of the capacitor structure of FIG. 5 following removal of a portion of the second layer 34 .
- FIG. 7 is a cross-sectional view of the capacitor structure of FIG. 6 following removal of the fill material and formation of hemispherical grain silicon from the second layer 34 .
- FIG. 8 is a cross-sectional view of the capacitor structure of FIG. 6 following formation of a dielectric layer 50 and a second electrode layer 60 .
- FIG. 9 is a cross-sectional view of an alternative capacitor structure including a hemispherical grain silicon on a first layer 132 in a cavity 120 .
- FIG. 10 is a cross-sectional view of the capacitor structure of FIG. 9 following formation of a layer of fill material 140 in the cavity 120 .
- FIG. 11 is a cross-sectional view of the capacitor structure of FIG. 10 following planarization to remove the fill material 140 and hemispherical grain silicon outside of the cavity 20 .
- FIG. 6 is a cross-sectional view of the capacitor structure of FIG. 5 following removal of a portion of the second layer 34 .
- FIG. 12 is an illustrative diagram of a container capacitor structure using a recessed hemispherical grain electrode formed according to the present invention in a storage cell capacitor application.
- FIG. 13 illustrates the capacitor structure of Example 1.
- FIG. 14 illustrates the capacitor structure of Example 2.
- FIG. 15 illustrates the capacitor structure of Example 3.
- the present invention is particularly useful for providing the lower electrode of a capacitor structure for a memory device, e.g., a DRAM, an SRAM, an FE memory, etc.
- a memory device e.g., a DRAM, an SRAM, an FE memory, etc.
- the methods of providing recessed hemispherical grain silicon layers can be used in any application or structure in which a recessed hemispherical grain silicon layer would be useful.
- substrate assembly refers to either a semiconductor substrate such as the base semiconductor layer, e.g., the lowest layer of a silicon material on a wafer, or a silicon layer deposited on another material, such as silicon on sapphire, or a semiconductor substrate having one or more layers or structures formed thereon or regions formed therein.
- a semiconductor substrate such as the base semiconductor layer, e.g., the lowest layer of a silicon material on a wafer, or a silicon layer deposited on another material, such as silicon on sapphire, or a semiconductor substrate having one or more layers or structures formed thereon or regions formed therein.
- various process steps may have been previously used to form or define regions, junctions, various structures or features, and openings such as vias, contact openings, high aspect ratio openings, etc.
- substrate assembly may refer to a structure upon which a lower electrode of a capacitor structure is formed.
- annealing includes exposing a structure being formed to any combination of temperature and pressure for a predetermined time that will affect the physical properties of the referenced layer or material. Annealing may be performed in a gas atmosphere and with or without plasma enhancement.
- capacitor structure may, and typically are, fabricated in arrays. In other words, a plurality of capacitor structures are manufactured simultaneously on substrate assemblies using the methods of the present invention.
- FIGS. 1 - 8 illustrate a method of forming a lower electrode for a container structure according to one method of the present invention.
- the lower electrode of capacitor structure shown in FIG. 8 is formed using a rough conductive layer of hemispherical grain silicon according to the present invention.
- FIG. 1 illustrates a substrate assembly 10 including a first substrate portion 12 and a second substrate portion 14 .
- Substrate portion 14 is formed on substrate portion 12 and includes a cavity 20 defined therein by a bottom surface 22 on the first substrate portion 12 and one or more side walls 24 of second substrate portion 14 .
- the first substrate portion 12 may include a region (not shown) to which a lower electrode of capacitor structure (see FIG. 8) can be electrically connected.
- the second portion 14 of the substrate assembly 10 is preferably an insulative layer such as an oxide layer, e.g., silicon dioxide, BPSG, PSG, etc.
- the second substrate portion 14 is a layer of BPSG, although other materials that allow for proper cavity formation may be used for the substrate assembly 10 .
- each portion of the substrate assembly 10 is depicted as a homogenous, single layer, each portion of the substrate assembly 10 may be provided as a non-homogeneous layer and/or multiple layers of the same or different materials.
- Cavity 20 is defined in substrate assembly 10 by bottom surface 22 and the one or more side walls 24 . It is preferred, but not required, that the bottom surface 22 of the cavity 20 be formed by an exposed portion of the first substrate portion 12 and that the sidewall or sidewalls 24 of the cavity are formed by the second substrate portion 14 . Furthermore, it is preferred that the sidewalls 24 are substantially vertical where the upper surface 16 of the second substrate portion 14 defines a horizontal plane. By “substantially vertical” it is meant that the sidewalls 24 form an angle of 90 degrees plus or minus several degrees with the upper surface 16 of the second substrate portion 14 . When the terms “vertical” or “normal” are used in this disclosure, exact verticality is not required, as perfect geometric relationships exist only in theory.
- the cavity 20 may have any desired shape that is conducive to use as a capacitor.
- the cavity 20 may be generally cylindrical and in other cases the cavity 20 may be elongated along one axis to form a tub-shaped or trench capacitor structure.
- the capacitor structures are described herein in the context of container capacitors (i.e., those fabricated at least partly above the level of the access transistor gates), the present invention may also be applied to the formation of capacitors in a substrate.
- the methods of providing recessed hemispherical grain silicon layers described herein may be used for one or more numerous applications, e.g., interconnection applications, capacitor applications, etc.
- the present invention is useful when forming recessed hemispherical grain silicon layers in small high aspect ratio openings.
- small high aspect ratio openings have feature sizes or critical dimensions below about 1 micron (e.g., such as a diameter or width of an opening being less than about 1 micron), and aspect ratios greater than about 1.
- Such aspect ratios are applicable to contact holes, vias, trenches, and any other configured openings, such as container or trench openings for formation of capacitor structures.
- a trench having an opening of 1 micron and a depth of 3 microns has an aspect ratio of 3.
- the capacitor structure of FIG. 8 is formed with a rough hemispherical grain lower electrode as illustrated in FIGS. 1 - 8 by providing a first layer 32 in the cavity 20 and on surfaces such as upper surface 16 of second substrate portion 14 .
- the first layer 32 and the other layers described herein may typically be deposited using CVD processes such that conformal coverage or step coverage within the cavity 20 and at various other portions of the structure, such as corners 26 , are conformally covered with the material being deposited.
- the first layer 32 is preferably electrically conductive because it will form a portion of one electrode in a capacitor as described below.
- the first layer 32 is formed using doped silicon, more preferably the first layer 32 consists essentially of doped silicon.
- the doped silicon used for the first layer 32 may be either doped amorphous silicon or doped polysilicon.
- the first layer 32 preferably covers the upper surface 16 of the second substrate portion 14 and conformally lines the walls bottom 22 and sidewalls 24 of cavity 20 . It will also be noted that, where the cavity 20 is cup-shaped, the first layer 32 preferably conformally forms a cup-shaped structure within the cavity 20 .
- a second layer 34 is then formed on the first layer 32 via any suitable technique.
- the second layer 34 preferably conformally covers the first layer 32 both inside and outside the cavity 20 .
- the second layer 34 may alternately be referred to a hemispherical grain silicon precursor layer because it should be formed of materials that are amenable to the formation of hemispherical grain silicon. As a result, the second layer 34 includes some silicon in its composition. In one embodiment of the invention, the second layer 34 is formed of undoped amorphous silicon, more preferably the second layer 34 consists essentially of undoped amorphous silicon.
- the second layer 34 it should be selectively removable as compared to the first layer 32 .
- one preferred combination of materials for the first layer 32 and the second layer 34 is doped polysilicon for the first layer 32 and undoped amorphous silicon for the second layer 34 . Both layers 32 and 34 may preferably consist essentially of these materials.
- the second layer 34 is substantially undoped when the first layer 32 is doped silicon, it may be possible that the second layer 34 includes a dopant provided that the dopant concentration in the second layer 34 does not prevent hemispherical grain silicon formation in that layer (as discussed below) and that selective removal of the second layer 34 relative to the first layer 32 is also not substantially affected.
- the cavity 20 is filled with a suitable fill material 40 as illustrated in FIG. 4.
- the fill material 40 will be provided in the form of a planarizing layer, i.e., a layer applied in sufficient amounts to fill the cavities 20 and provide a generally continuous layer of the fill material on the upper surfaces of the structure between the cavities 20 .
- suitable fill materials 40 include, but are not limited to: photoresists; spin-on-glass (SOG); and low temperature deposited (e.g., less than 500° C.) silicon oxide, silicon oxynitride, or silicon nitride. Regardless of the exact material used, the fill material 40 should exhibit a relatively low etch rate relative to the second layer 34 or at least an etch rate that is not substantially greater than the etch rate of the second layer 34 .
- the portions of the first layer 32 , the second layer 34 and the fill material 40 outside of the cavity 20 are removed as illustrated in FIG. 5.
- the first layer 32 , second layer 34 and fill material 40 within each cavity 20 are separated from the corresponding layers in other cavities 20 .
- Removal of the exposed portions of the first layer 32 , second layer 34 and fill material 40 can be performed by any suitable technique.
- a chemical-mechanical polishing (CMP) technique may be practiced on the array to remove the exposed portions of the first layer 32 , second layer 34 and fill material 40 , i.e., those portions outside of the cavity 20 .
- an edge 33 of the first layer 32 and an edge 35 of the second layer 34 are exposed about the upper perimeter of the cavity 20 as illustrated in FIG. 5.
- a suitable selective removal process is then performed to remove a portion of the second layer 34 along its exposed edge 35 .
- the removal techniques used selectively remove the second layer 34 over the first layer 32 , with a preferred selectivity of at least about 2:1 or greater.
- one suitable selective removal process may be an etching process with a preferred selectivity for the second layer 34 over the first layer 32 and the fill material 40 of at least about 2:1 or greater. More preferably, the selectivity of the etching process is at least about 4:1 or greater.
- one suitable etching process involves the use of a TMAH (tetramethyl ammonium hydroxide) wet etch process in which the TMAH is held at a concentration greater than 2.25% (by weight) at a temperature of about 30° C., more preferably the concentration of the TMAH is about 2.5% or greater at a temperature of about 30° C., and still more preferably, the TMAH concentration is about 2.6% at a temperature of about 30° C. It may also be preferred that the concentration of TMAH in the etch solution be about 3% (by weight) or less when the etchant is at a temperature of about 30° C.
- TMAH tetramethyl ammonium hydroxide
- the capacitor structures are preferably immersed in the TMAH solution for a period sufficient to remove the second layer 34 a sufficient amount relative to the first layer 32 .
- immersion for about 5 minutes or less, more preferably about 1 minute is typically sufficient to provide the desired edge zone depth as described below.
- TMAH wet etch process is used to selectively remove an undoped amorphous silicon layer 34 over a doped polysilicon first layer 32 . It is preferred that the doped polysilicon in the first layer 32 is not annealed after deposition to maintain desire selectivity in the removal of the preferred doped amorphous silicon in the second layer 34 .
- the preferred selective removal process leaves the second substrate portion 14 and the fill material 40 in the cavity 20 substantially unaffected. It may, however, also be possible to remove a portion of the second layer 34 and the fill material 40 either together in a removal process that is selective to the second layer 34 and the fill material 40 over the first layer 32 . Alternatively, it may be possible to selectively remove a portion of the fill material 40 within the cavity 20 to a desired depth, followed by selective removal of the second layer 34 over the first layer 32 . At the completion of the selective removal process (regardless of which form it takes), an edge zone 28 is created about the upper portion of the sidewall or sidewalls 24 of the cavity 20 that is substantially free of second layer 34 .
- the depth of the edge zone 28 can be measured by a number of techniques. For example, the edge zone depth may be determined based on a percentage of the depth of the cavity 20 itself. When so measured, the depth of the cavity 20 is determined before the first layer 32 and the second layer 34 are deposited and is measured along a vertical axis from the upper surface 16 of the second substrate portion 14 to the bottom 22 of the cavity 20 . When measured as a percentage of cavity depth, it may be preferred that the depth of the edge zone 28 be about 20% or less of the cavity depth, more preferably about 10% or less, and even more preferably about 5% or less. It is further preferred that the edge zone 28 have some depth, i.e., that the depth of the edge zone 28 is greater than 0%.
- the depth of the edge zone 28 may alternatively be measured in terms of distance from the upper surface 16 of the second substrate portion 14 to the bottom of the edge zone 28 along a substantially vertical axis after processing to reach the structure depicted in FIG. 6. When so measured, it may be preferred that the edge zone depth be about 2000 Angstroms or less, more preferably about 1000 Angstroms or less, and even more preferably about 500 Angstroms or less. It is further preferred that the edge zone 28 have some depth, i.e., that the depth of the edge zone 28 is greater than zero.
- the fill material within the cavity 20 is removed by any suitable technique. Suitable techniques for removal of the fill material 40 are those that leave the remainder of the structure substantially unaffected. If the fill material 40 is a photoresist, it is preferably chemically stripped from the cavity 20 .
- the second layer 34 is converted to hemispherical grain silicon via any suitable technique.
- the resulting structure is illustrated in FIG. 7. Because an edge zone 28 that is substantially free of the second layer 34 was created about the upper portions of the sidewall or sidewalls 24 of the cavity 20 , that edge zone 28 is also substantially free of any hemispherical grain silicon. With the hemispherical grain silicon recessed within the cavity 20 , subsequent processing steps are unlikely to dislodge grains of HSG silicon that could fall outside of the cavity 20 and short adjacent capacitor structures or cause other defects.
- Formation of hemispherical grain silicon from second layer 34 may take place via any suitable technique.
- the second layer 34 may be seeded and annealed under conditions suitable to the formation of hemispherical grain silicon.
- a variety of techniques useful in the formation of hemispherical grain silicon may be used. Examples include, but are not limited to those described in U.S. Pat. Nos. 5,407,534; 5,418,180; 5,837,580; 5,759,262; and 5,882,979.
- the first layer 32 is preferably not converted to hemispherical grain silicon. If, for example, the first layer 32 is doped amorphous silicon, it may not convert to hemispherical grain silicon under the same conditions as will the substantially undoped amorphous silicon preferably used for second layer 34 .
- the result of the hemispherical grain silicon formation from second layer 34 is a first electrode as illustrated in FIG. 7, where the first electrode is the combination of first layer 32 and hemispherical grain silicon in the second layer 34 .
- a dielectric layer 50 can be provided within the cavity 20 .
- at least some of the second substrate portion 14 outside of the first layer 32 may also be removed to allow the outside surface of the first layer 32 to further contribute to overall capacitance.
- the dielectric layer 50 may be any suitable material having a suitable dielectric constant.
- a suitable dielectric constant is a high dielectric constant material such as those materials having a dielectric constant of greater than about 25.
- Suitable dielectric constant materials for forming dielectric layer 50 may include, but are not limited to: silicon nitride, silicon oxynitride, tantalum pentoxide (Ta 2 O 5 ), Ba x Sr (1-x) TiO 3 [BST], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 [PZT], (Pb,La)(Zr,Ti)O 3 [PLZT], (Pb,La)TiO 3 [PLT], KNO 3 , LiNbO 3 , and combinations of any two or more of these materials.
- a second electrode 60 can be formed on the dielectric material 50 opposite from the first electrode (layers 32 and 34 ).
- the second electrode 60 may be formed of any suitably conductive material. Examples include, but are not limited to: doped polysilicon, tungsten nitride, titanium nitride, tantalum nitride, platinum metals and alloys thereof, ruthenium, and ruthenium oxide.
- the dielectric layer 50 , second electrode layer 60 can then be selectively removed from outside of the cavity 20 to form the desired capacitor structure. Such a structure may or may not include removal of all or a portion of the second substrate portion 14 .
- FIGS. 9 - 11 illustrate another method of providing a capacitor structure with recessed HSG silicon according to the present invention.
- This method begins with a structure similar to that of FIG. 3 which, in FIG. 9, includes a cavity 120 formed in a substrate assembly 110 .
- the cavity 120 is lined with a first layer 132 of doped silicon (polysilicon or amorphous) on which a second layer 134 of hemispherical grain silicon precursor is deposited.
- the hemispherical grain silicon precursor in the second layer 134 is converted to hemispherical grain silicon before the fill material 140 is deposited therein as illustrated in FIG. 10.
- the conversion into hemispherical grain silicon can be by any suitable technique as discussed above with respect to layer 34 .
- the fill material 140 will typically be provided in the form of a planarizing layer, i.e., a layer applied in sufficient amounts to fill the cavity 120 and provide a generally continuous layer of the fill material on the upper surfaces of the structure between adjacent cavities. Examples of suitable fill materials 140 are discussed above.
- the portions of the first layer 132 , the second layer 134 (now hemispherical grain silicon) and the fill material 140 outside of the cavity 120 are removed as illustrated in FIG. 11.
- the first layer 132 , second layer 134 and fill material 140 within each cavity 120 are separated from the corresponding layers in other cavities. Removal of the expose d portions of the first layer 132 , second layer 134 and fill material 140 can be performed by any suitable technique as discussed above.
- an edge 133 of the first layer 132 and an edge 135 of the second layer 134 are exposed about the upper perimeter of the cavity 120 as illustrated in FIG. 11.
- a suitable selective removal process is then performed to remove a portion of the hemispherical grain silicon in the second layer 134 along its exposed edge 135 in the manners and techniques described above with respect to second layer 34 .
- a device structure 200 is fabricated in accordance with conventional processing techniques through the formation of a cavity 220 . Such processing is performed prior to depositing a first electrode structure 230 on the surfaces defining the cavity 220 using the methods in accordance with the present invention.
- the first electrode 230 is formed according to the methods described above and, as such, includes a conductive layer 232 and a recessed hemispherical grain silicon layer 234 including an edge zone 228 .
- the device structure 200 includes field oxide regions 285 and active regions, i.e., those regions of the substrate 287 not covered by field oxide.
- a word line 291 and a field effect transistor (FET) 292 are formed relative to the field oxide 285 .
- Suitable source/drain regions 293 , 294 are created in silicon substrate 287 .
- An insulative conformal layer of oxide material 295 is formed over regions of FET 292 and word line 291 .
- a polysilicon plug 296 is formed to provide electrical communication between substrate 287 and a storage cell capacitor to be formed thereover.
- Various barrier layers are formed over the polysilicon plug 296 , such as, for example, layers 297 and 298 .
- layers may be titanium nitride, tungsten nitride, or any other metal nitride which acts as a barrier.
- another insulative layer 299 is formed and the opening 220 is defined therein.
- the device structure 200 includes a dielectric layer 250 formed of material such as described above is then formed relative to the first electrode 230 .
- a second electrode 260 is formed relative to the dielectric layer 250 , such that the first electrode 230 , dielectric layer 250 and second electrode 260 form a capacitor as a part of device structure 200 .
- a structure similar to that illustrated in FIG. 9 was provided.
- the upper portion of a substrate assembly 110 was formed of BPSG.
- a cavity 120 with an aspect ratio of about 7:1 (depth:width) was formed in the BPSG and lined with a first layer 132 of doped polysilicon (phosphorus dopant at a concentration of 10 20 /cm 3 ) by low pressure CVD to a thickness of about 500 Angstroms.
- doped polysilicon phosphorus dopant at a concentration of 10 20 /cm 3
- a layer of undoped amorphous silicon was provided as layer 134 by CVD to a thickness of about 500 Angstroms and converted to HSG silicon by seeding and annealing.
- Fill material 140 in the form of a photoresist was provided in the remainder of the cavity 120 , with the resulting structure illustrated in FIG. 10.
- the next step was to employ a chemical-mechanical polishing (CMP) process to isolate the cavities 120 , followed by decapping of the polysilicon in layer 132 in an etch solution of hydrofluoric acid (HF) and TMAH.
- CMP chemical-mechanical polishing
- the structure was planarized down to the level of the BPSG and the native oxide is removed from the exposed doped silicon in layer 132 and undoped HSG silicon in layer 134 .
- the resulting structure is illustrated in FIG. 11.
- the photoresist 140 is removed from the cavity 120 by stripping.
- the BPSG layer surrounding the cavities is then etched back from around the cavity in a 10:1 HF dip and the resulting structure is depicted in FIG. 13, where it can be seen that the hemispherical grain silicon extends above the outer layer of polysilicon for each of the cavities.
- FIG. 15 The resulting structures are depicted in FIG. 15 after etch-back of the BPSG layer. It can be seen that the hemispherical grain silicon layer is recessed within the container structure formed by the outer layer of doped polysilicon.
Abstract
Capacitor structures and capacitors with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Also disclosed are methods of forming the capacitor structures and capacitors in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.
Description
- The present invention relates to semiconductor manufacturing. More particularly, the present invention provides capacitor structures including recessed hemispherical grain silicon and methods of forming the same.
- In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), ferroelectric (FE) memories, etc., conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers of contact holes, vias, etc.
- As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material.
- Further, to the increase the capacitance for a storage cell capacitor of a memory device without increasing the occupation area of the storage cell capacitor, various techniques have been used to increase the surface area of the lower electrode of the capacitor. For example, hemispherical grains (HSG) have been used to enhance such surface area of the lower electrode of a capacitor of a memory device.
- However, in many cases, the use of HSG to enhance surface area of an electrode can be problematic. The manufacturing of container capacitors, such as is described in U.S. Pat. No. 5,270,241 (Dennison et al.) involves a singulation process whereby the continuous conductive material lining the containers and extending between them on the upper surface of the structure is partially removed to separate the conductive material within a container from the conductive material in the other containers. Singulation may be accomplished using a chemical mechanical polishing (CMP) step which removes only the uppermost horizontal expanses of the continuous conductive layer.
- Although CMP is effective at separating the containers, it leaves a structure in which the hemispherical grain silicon precursor layer (i.e., the layer from which the hemispherical grain silicon is formed) and the underlying doped silicon layer both extend to the upper edge of the capacitor plates. As a result, after conversion of the hemispherical grain silicon precursor layer to a layer of hemispherical grain silicon by, e.g., seeding and annealing or any other suitable technique, the hemispherical grain silicon layer typically extends above the outer layer of doped silicon along the edges of the capacitor plates.
- Grains or particles from the exposed edge of the hemispherical grain silicon layer are, however, susceptible to separation from the hemispherical grain silicon layer. Once separated or broken off, the loose particles can fall between adjacent capacitors, resulting in electrical shorts between the adjacent capacitors. Such defects adversely affect the output of the manufacturing processes used to form the capacitors. Although typically associated with cup-shaped capacitors, these problems are also experienced in connection with other capacitor structures, e.g., trench, tub, etc.
- The present invention provides capacitor structures with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput.
- The present invention also includes methods of forming the capacitor structures in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.
- In one aspect, the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity over about 20% or less of the distance between the opening and the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity and having a depth of about 2000 Angstroms or less from the opening of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity over about 20% or less of the distance between the opening and the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon
- In another aspect, the present invention provides a capacitor structure including a cavity having a sidewall structure, an opening, and a bottom opposite the opening; a first layer located on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; a second layer located on the first layer, the second layer including hemispherical grain silicon; and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity and having a depth of about 2000 Angstroms or less from the opening of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer including doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration greater than 2.25% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration greater than 2.25% (by weight) and less than 3% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and removing the hemispherical grain silicon in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity including a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and
- removing the hemispherical grain silicon in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer including doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration of greater than 2.25% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a method of forming a capacitor structure by providing a cavity in a substrate, the cavity having a sidewall structure, an opening, and a bottom opposite the opening of the cavity; providing a first layer on an inner surface of the sidewall structure, wherein the first layer includes doped silicon; providing a second layer on substantially all of the first layer, the second layer including hemispherical grain silicon precursor; providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant including TMAH at a concentration greater than 2.25% (by weight) and less than 3% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
- In another aspect, the present invention provides a capacitor including a cavity having a sidewall structure, an opening, and a bottom opposite the opening, the sidewall structure extending between the opening and the bottom of the cavity; a first electrode including an electrically conductive first layer located on an inner surface of the sidewall structure, a second layer including hemispherical grain silicon located on the first layer, and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, wherein the edge zone extends from the opening of the cavity towards the bottom of the cavity, and further wherein the edge zone is substantially free of the hemispherical grain silicon; a dielectric layer located on at least a portion of the first electrode; and a second electrode located on the dielectric layer.
- These and other features and advantages of the present invention are described below with respect to illustrative embodiments of the apparatus and methods.
- FIG. 1 is a cross-sectional view of an in-process capacitor structure at a stage in the fabrication following formation of a
cavity 20. - FIG. 2 is a cross-sectional view of the capacitor structure of FIG. 1 following formation of a
first layer 32 in thecavity 20. - FIG. 3 is a cross-sectional view of the capacitor structure of FIG. 2 following formation of a
second layer 34 on thefirst layer 32. - FIG. 4 is a cross-sectional view of the capacitor structure of FIG. 3 following formation of a layer of
fill material 40 in thecavity 20. - FIG. 5 is a cross-sectional view of the capacitor structure of FIG. 4 following planarization to remove the
fill material 40 outside of thecavity 20. - FIG. 6 is a cross-sectional view of the capacitor structure of FIG. 5 following removal of a portion of the
second layer 34. - FIG. 7 is a cross-sectional view of the capacitor structure of FIG. 6 following removal of the fill material and formation of hemispherical grain silicon from the
second layer 34. - FIG. 8 is a cross-sectional view of the capacitor structure of FIG. 6 following formation of a
dielectric layer 50 and asecond electrode layer 60. - FIG. 9 is a cross-sectional view of an alternative capacitor structure including a hemispherical grain silicon on a
first layer 132 in acavity 120. - FIG. 10 is a cross-sectional view of the capacitor structure of FIG. 9 following formation of a layer of
fill material 140 in thecavity 120. - FIG. 11 is a cross-sectional view of the capacitor structure of FIG. 10 following planarization to remove the
fill material 140 and hemispherical grain silicon outside of thecavity 20. - FIG. 6 is a cross-sectional view of the capacitor structure of FIG. 5 following removal of a portion of the
second layer 34. - FIG. 12 is an illustrative diagram of a container capacitor structure using a recessed hemispherical grain electrode formed according to the present invention in a storage cell capacitor application.
- FIG. 13 illustrates the capacitor structure of Example 1.
- FIG. 14 illustrates the capacitor structure of Example 2.
- FIG. 15 illustrates the capacitor structure of Example 3.
- The present invention is particularly useful for providing the lower electrode of a capacitor structure for a memory device, e.g., a DRAM, an SRAM, an FE memory, etc. However, it should be understood that the methods of providing recessed hemispherical grain silicon layers can be used in any application or structure in which a recessed hemispherical grain silicon layer would be useful.
- As used in this application, substrate assembly refers to either a semiconductor substrate such as the base semiconductor layer, e.g., the lowest layer of a silicon material on a wafer, or a silicon layer deposited on another material, such as silicon on sapphire, or a semiconductor substrate having one or more layers or structures formed thereon or regions formed therein. When reference is made to a substrate assembly in the following description, various process steps may have been previously used to form or define regions, junctions, various structures or features, and openings such as vias, contact openings, high aspect ratio openings, etc. For example, as used herein, substrate assembly may refer to a structure upon which a lower electrode of a capacitor structure is formed.
- As used in connection with the present invention, the term “annealing” includes exposing a structure being formed to any combination of temperature and pressure for a predetermined time that will affect the physical properties of the referenced layer or material. Annealing may be performed in a gas atmosphere and with or without plasma enhancement.
- Although only one capacitor structure is illustrated in the drawings and discussed below, it will be understood that the capacitor may, and typically are, fabricated in arrays. In other words, a plurality of capacitor structures are manufactured simultaneously on substrate assemblies using the methods of the present invention.
- FIGS.1-8 illustrate a method of forming a lower electrode for a container structure according to one method of the present invention. The lower electrode of capacitor structure shown in FIG. 8 is formed using a rough conductive layer of hemispherical grain silicon according to the present invention.
- FIG. 1 illustrates a
substrate assembly 10 including afirst substrate portion 12 and asecond substrate portion 14.Substrate portion 14 is formed onsubstrate portion 12 and includes acavity 20 defined therein by abottom surface 22 on thefirst substrate portion 12 and one ormore side walls 24 ofsecond substrate portion 14. Thefirst substrate portion 12 may include a region (not shown) to which a lower electrode of capacitor structure (see FIG. 8) can be electrically connected. - The
second portion 14 of thesubstrate assembly 10 is preferably an insulative layer such as an oxide layer, e.g., silicon dioxide, BPSG, PSG, etc. In one embodiment of the invention, thesecond substrate portion 14 is a layer of BPSG, although other materials that allow for proper cavity formation may be used for thesubstrate assembly 10. Also, although each portion of thesubstrate assembly 10 is depicted as a homogenous, single layer, each portion of thesubstrate assembly 10 may be provided as a non-homogeneous layer and/or multiple layers of the same or different materials. -
Cavity 20 is defined insubstrate assembly 10 bybottom surface 22 and the one ormore side walls 24. It is preferred, but not required, that thebottom surface 22 of thecavity 20 be formed by an exposed portion of thefirst substrate portion 12 and that the sidewall or sidewalls 24 of the cavity are formed by thesecond substrate portion 14. Furthermore, it is preferred that thesidewalls 24 are substantially vertical where the upper surface 16 of thesecond substrate portion 14 defines a horizontal plane. By “substantially vertical” it is meant that thesidewalls 24 form an angle of 90 degrees plus or minus several degrees with the upper surface 16 of thesecond substrate portion 14. When the terms “vertical” or “normal” are used in this disclosure, exact verticality is not required, as perfect geometric relationships exist only in theory. - The
cavity 20 may have any desired shape that is conducive to use as a capacitor. In some instances, thecavity 20 may be generally cylindrical and in other cases thecavity 20 may be elongated along one axis to form a tub-shaped or trench capacitor structure. Also, although the capacitor structures are described herein in the context of container capacitors (i.e., those fabricated at least partly above the level of the access transistor gates), the present invention may also be applied to the formation of capacitors in a substrate. In other variations, the methods of providing recessed hemispherical grain silicon layers described herein may be used for one or more numerous applications, e.g., interconnection applications, capacitor applications, etc. - The present invention is useful when forming recessed hemispherical grain silicon layers in small high aspect ratio openings. As described herein, small high aspect ratio openings have feature sizes or critical dimensions below about 1 micron (e.g., such as a diameter or width of an opening being less than about 1 micron), and aspect ratios greater than about 1. Such aspect ratios are applicable to contact holes, vias, trenches, and any other configured openings, such as container or trench openings for formation of capacitor structures. For example, a trench having an opening of 1 micron and a depth of 3 microns has an aspect ratio of 3.
- The capacitor structure of FIG. 8 is formed with a rough hemispherical grain lower electrode as illustrated in FIGS.1-8 by providing a
first layer 32 in thecavity 20 and on surfaces such as upper surface 16 ofsecond substrate portion 14. Thefirst layer 32 and the other layers described herein may typically be deposited using CVD processes such that conformal coverage or step coverage within thecavity 20 and at various other portions of the structure, such as corners 26, are conformally covered with the material being deposited. - The
first layer 32 is preferably electrically conductive because it will form a portion of one electrode in a capacitor as described below. In one embodiment of the invention, thefirst layer 32 is formed using doped silicon, more preferably thefirst layer 32 consists essentially of doped silicon. The doped silicon used for thefirst layer 32 may be either doped amorphous silicon or doped polysilicon. Thefirst layer 32 preferably covers the upper surface 16 of thesecond substrate portion 14 and conformally lines the walls bottom 22 and sidewalls 24 ofcavity 20. It will also be noted that, where thecavity 20 is cup-shaped, thefirst layer 32 preferably conformally forms a cup-shaped structure within thecavity 20. - Referring to FIG. 3, a
second layer 34 is then formed on thefirst layer 32 via any suitable technique. Thesecond layer 34 preferably conformally covers thefirst layer 32 both inside and outside thecavity 20. - The
second layer 34 may alternately be referred to a hemispherical grain silicon precursor layer because it should be formed of materials that are amenable to the formation of hemispherical grain silicon. As a result, thesecond layer 34 includes some silicon in its composition. In one embodiment of the invention, thesecond layer 34 is formed of undoped amorphous silicon, more preferably thesecond layer 34 consists essentially of undoped amorphous silicon. - Regardless of the exact choice of materials for the
second layer 34, it should be selectively removable as compared to thefirst layer 32. For example, one preferred combination of materials for thefirst layer 32 and thesecond layer 34 is doped polysilicon for thefirst layer 32 and undoped amorphous silicon for thesecond layer 34. Both layers 32 and 34 may preferably consist essentially of these materials. Although it is preferred that thesecond layer 34 is substantially undoped when thefirst layer 32 is doped silicon, it may be possible that thesecond layer 34 includes a dopant provided that the dopant concentration in thesecond layer 34 does not prevent hemispherical grain silicon formation in that layer (as discussed below) and that selective removal of thesecond layer 34 relative to thefirst layer 32 is also not substantially affected. - After the
first layer 32 and thesecond layer 34 are deposited, thecavity 20 is filled with asuitable fill material 40 as illustrated in FIG. 4. Typically, thefill material 40 will be provided in the form of a planarizing layer, i.e., a layer applied in sufficient amounts to fill thecavities 20 and provide a generally continuous layer of the fill material on the upper surfaces of the structure between thecavities 20. Examples ofsuitable fill materials 40 include, but are not limited to: photoresists; spin-on-glass (SOG); and low temperature deposited (e.g., less than 500° C.) silicon oxide, silicon oxynitride, or silicon nitride. Regardless of the exact material used, thefill material 40 should exhibit a relatively low etch rate relative to thesecond layer 34 or at least an etch rate that is not substantially greater than the etch rate of thesecond layer 34. - After the
fill material 40 is applied to the structure, the portions of thefirst layer 32, thesecond layer 34 and thefill material 40 outside of thecavity 20 are removed as illustrated in FIG. 5. As a result, thefirst layer 32,second layer 34 and fillmaterial 40 within eachcavity 20 are separated from the corresponding layers inother cavities 20. Removal of the exposed portions of thefirst layer 32,second layer 34 and fillmaterial 40 can be performed by any suitable technique. For example, a chemical-mechanical polishing (CMP) technique may be practiced on the array to remove the exposed portions of thefirst layer 32,second layer 34 and fillmaterial 40, i.e., those portions outside of thecavity 20. - After removal of the
first layer 32,second layer 34 and the fill material 40 (if any) from the areas outside of thecavity 20, an edge 33 of thefirst layer 32 and an edge 35 of thesecond layer 34 are exposed about the upper perimeter of thecavity 20 as illustrated in FIG. 5. A suitable selective removal process is then performed to remove a portion of thesecond layer 34 along its exposed edge 35. The removal techniques used selectively remove thesecond layer 34 over thefirst layer 32, with a preferred selectivity of at least about 2:1 or greater. - Where the
first layer 32 is doped polysilicon and thesecond layer 34 is undoped amorphous silicon, one suitable selective removal process may be an etching process with a preferred selectivity for thesecond layer 34 over thefirst layer 32 and thefill material 40 of at least about 2:1 or greater. More preferably, the selectivity of the etching process is at least about 4:1 or greater. - Where the
first layer 32 is doped polysilicon, thesecond layer 34 is undoped amorphous silicon, one suitable etching process involves the use of a TMAH (tetramethyl ammonium hydroxide) wet etch process in which the TMAH is held at a concentration greater than 2.25% (by weight) at a temperature of about 30° C., more preferably the concentration of the TMAH is about 2.5% or greater at a temperature of about 30° C., and still more preferably, the TMAH concentration is about 2.6% at a temperature of about 30° C. It may also be preferred that the concentration of TMAH in the etch solution be about 3% (by weight) or less when the etchant is at a temperature of about 30° C. - The capacitor structures are preferably immersed in the TMAH solution for a period sufficient to remove the second layer34 a sufficient amount relative to the
first layer 32. With the preferred combination of undoped amorphous silicon, doped polysilicon and photoresist, immersion for about 5 minutes or less, more preferably about 1 minute is typically sufficient to provide the desired edge zone depth as described below. - Furthermore, where a TMAH wet etch process is used to selectively remove an undoped
amorphous silicon layer 34 over a doped polysiliconfirst layer 32, it is preferred that the doped polysilicon in thefirst layer 32 is not annealed after deposition to maintain desire selectivity in the removal of the preferred doped amorphous silicon in thesecond layer 34. - Other selective removal techniques for selectively removing the
second layer 34 relative to thefirst layer 32, including other etching processes, will be known to those skilled in the art and may be substituted for those specifically recited herein. - As illustrated in FIG. 6, the preferred selective removal process leaves the
second substrate portion 14 and thefill material 40 in thecavity 20 substantially unaffected. It may, however, also be possible to remove a portion of thesecond layer 34 and thefill material 40 either together in a removal process that is selective to thesecond layer 34 and thefill material 40 over thefirst layer 32. Alternatively, it may be possible to selectively remove a portion of thefill material 40 within thecavity 20 to a desired depth, followed by selective removal of thesecond layer 34 over thefirst layer 32. At the completion of the selective removal process (regardless of which form it takes), anedge zone 28 is created about the upper portion of the sidewall or sidewalls 24 of thecavity 20 that is substantially free ofsecond layer 34. - The depth of the
edge zone 28 can be measured by a number of techniques. For example, the edge zone depth may be determined based on a percentage of the depth of thecavity 20 itself. When so measured, the depth of thecavity 20 is determined before thefirst layer 32 and thesecond layer 34 are deposited and is measured along a vertical axis from the upper surface 16 of thesecond substrate portion 14 to the bottom 22 of thecavity 20. When measured as a percentage of cavity depth, it may be preferred that the depth of theedge zone 28 be about 20% or less of the cavity depth, more preferably about 10% or less, and even more preferably about 5% or less. It is further preferred that theedge zone 28 have some depth, i.e., that the depth of theedge zone 28 is greater than 0%. - The depth of the
edge zone 28 may alternatively be measured in terms of distance from the upper surface 16 of thesecond substrate portion 14 to the bottom of theedge zone 28 along a substantially vertical axis after processing to reach the structure depicted in FIG. 6. When so measured, it may be preferred that the edge zone depth be about 2000 Angstroms or less, more preferably about 1000 Angstroms or less, and even more preferably about 500 Angstroms or less. It is further preferred that theedge zone 28 have some depth, i.e., that the depth of theedge zone 28 is greater than zero. - Following the selective removal of a portion of the
second layer 34, the fill material within thecavity 20 is removed by any suitable technique. Suitable techniques for removal of thefill material 40 are those that leave the remainder of the structure substantially unaffected. If thefill material 40 is a photoresist, it is preferably chemically stripped from thecavity 20. - After removal of the fill material from the
cavity 20, thesecond layer 34 is converted to hemispherical grain silicon via any suitable technique. The resulting structure is illustrated in FIG. 7. Because anedge zone 28 that is substantially free of thesecond layer 34 was created about the upper portions of the sidewall or sidewalls 24 of thecavity 20, thatedge zone 28 is also substantially free of any hemispherical grain silicon. With the hemispherical grain silicon recessed within thecavity 20, subsequent processing steps are unlikely to dislodge grains of HSG silicon that could fall outside of thecavity 20 and short adjacent capacitor structures or cause other defects. - Formation of hemispherical grain silicon from
second layer 34 may take place via any suitable technique. For example, thesecond layer 34 may be seeded and annealed under conditions suitable to the formation of hemispherical grain silicon. A variety of techniques useful in the formation of hemispherical grain silicon may be used. Examples include, but are not limited to those described in U.S. Pat. Nos. 5,407,534; 5,418,180; 5,837,580; 5,759,262; and 5,882,979. Thefirst layer 32 is preferably not converted to hemispherical grain silicon. If, for example, thefirst layer 32 is doped amorphous silicon, it may not convert to hemispherical grain silicon under the same conditions as will the substantially undoped amorphous silicon preferably used forsecond layer 34. - As a result of the hemispherical grain silicon formation process, some diffusion of the dopant from the preferred doped polysilicon of the
first layer 32 into the hemispherical grain silicon of thesecond layer 34 may be experienced, although such diffusion is typically limited. - The result of the hemispherical grain silicon formation from
second layer 34 is a first electrode as illustrated in FIG. 7, where the first electrode is the combination offirst layer 32 and hemispherical grain silicon in thesecond layer 34. After completion of the first electrode and cavity structure as depicted in FIG. 7, adielectric layer 50 can be provided within thecavity 20. Although not shown, at least some of thesecond substrate portion 14 outside of thefirst layer 32 may also be removed to allow the outside surface of thefirst layer 32 to further contribute to overall capacitance. - The
dielectric layer 50 may be any suitable material having a suitable dielectric constant. Preferably, a suitable dielectric constant is a high dielectric constant material such as those materials having a dielectric constant of greater than about 25. Suitable dielectric constant materials for formingdielectric layer 50 may include, but are not limited to: silicon nitride, silicon oxynitride, tantalum pentoxide (Ta2O5), BaxSr(1-x)TiO3 [BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3 [PZT], (Pb,La)(Zr,Ti)O3 [PLZT], (Pb,La)TiO3 [PLT], KNO3, LiNbO3, and combinations of any two or more of these materials. - Further, after formation of the
dielectric layer 50, asecond electrode 60 can be formed on thedielectric material 50 opposite from the first electrode (layers 32 and 34). Thesecond electrode 60 may be formed of any suitably conductive material. Examples include, but are not limited to: doped polysilicon, tungsten nitride, titanium nitride, tantalum nitride, platinum metals and alloys thereof, ruthenium, and ruthenium oxide. Thedielectric layer 50,second electrode layer 60 can then be selectively removed from outside of thecavity 20 to form the desired capacitor structure. Such a structure may or may not include removal of all or a portion of thesecond substrate portion 14. - FIGS.9-11 illustrate another method of providing a capacitor structure with recessed HSG silicon according to the present invention. This method begins with a structure similar to that of FIG. 3 which, in FIG. 9, includes a
cavity 120 formed in asubstrate assembly 110. Thecavity 120 is lined with afirst layer 132 of doped silicon (polysilicon or amorphous) on which asecond layer 134 of hemispherical grain silicon precursor is deposited. - The hemispherical grain silicon precursor in the
second layer 134 is converted to hemispherical grain silicon before thefill material 140 is deposited therein as illustrated in FIG. 10. The conversion into hemispherical grain silicon can be by any suitable technique as discussed above with respect tolayer 34. After conversion, thefill material 140 will typically be provided in the form of a planarizing layer, i.e., a layer applied in sufficient amounts to fill thecavity 120 and provide a generally continuous layer of the fill material on the upper surfaces of the structure between adjacent cavities. Examples ofsuitable fill materials 140 are discussed above. - After the
fill material 140 is applied to the structure, the portions of thefirst layer 132, the second layer 134 (now hemispherical grain silicon) and thefill material 140 outside of thecavity 120 are removed as illustrated in FIG. 11. As a result, thefirst layer 132,second layer 134 and fillmaterial 140 within eachcavity 120 are separated from the corresponding layers in other cavities. Removal of the expose d portions of thefirst layer 132,second layer 134 and fillmaterial 140 can be performed by any suitable technique as discussed above. - After removal of the
first layer 132,second layer 134 and the fill material 140 (if any) from the areas outside of thecavity 120, anedge 133 of thefirst layer 132 and anedge 135 of thesecond layer 134 are exposed about the upper perimeter of thecavity 120 as illustrated in FIG. 11. A suitable selective removal process is then performed to remove a portion of the hemispherical grain silicon in thesecond layer 134 along its exposededge 135 in the manners and techniques described above with respect tosecond layer 34. - A more specific illustration of using the above-described processes is described below with reference to FIG. 12 wherein a rough conductive
first electrode 230 is formed according to one of the processes described herein for a high dielectric capacitor of a storage cell. There are other semiconductor processes and structures for various devices, e.g., CMOS devices, memory devices, etc., that would benefit from the present invention and in no manner is the present invention limited to the illustrative embodiments described herein, e.g., an electrode structure. - As shown in FIG. 12, a
device structure 200 is fabricated in accordance with conventional processing techniques through the formation of acavity 220. Such processing is performed prior to depositing afirst electrode structure 230 on the surfaces defining thecavity 220 using the methods in accordance with the present invention. Thefirst electrode 230 is formed according to the methods described above and, as such, includes aconductive layer 232 and a recessed hemisphericalgrain silicon layer 234 including anedge zone 228. - As described in U.S. Pat. No. 5,392,189 to Fazan et al., entitled “Capacitor Compatible with High Dielectric Constant Materials Having Two Independent Insulative Layers and the Method for Forming Same,” issued Feb. 21, 1995, the
device structure 200 includesfield oxide regions 285 and active regions, i.e., those regions of thesubstrate 287 not covered by field oxide. Aword line 291 and a field effect transistor (FET) 292 are formed relative to thefield oxide 285. Suitable source/drain regions silicon substrate 287. An insulative conformal layer ofoxide material 295 is formed over regions ofFET 292 andword line 291. Apolysilicon plug 296 is formed to provide electrical communication betweensubstrate 287 and a storage cell capacitor to be formed thereover. Various barrier layers are formed over thepolysilicon plug 296, such as, for example, layers 297 and 298. For example, such layers may be titanium nitride, tungsten nitride, or any other metal nitride which acts as a barrier. Thereafter, anotherinsulative layer 299 is formed and theopening 220 is defined therein. - The
device structure 200 includes adielectric layer 250 formed of material such as described above is then formed relative to thefirst electrode 230. Following formation of the layer of dielectric material, asecond electrode 260 is formed relative to thedielectric layer 250, such that thefirst electrode 230,dielectric layer 250 andsecond electrode 260 form a capacitor as a part ofdevice structure 200. - The following non-limiting examples were performed to illustrate the present invention.
- A structure similar to that illustrated in FIG. 9 was provided. The upper portion of a
substrate assembly 110 was formed of BPSG. Acavity 120 with an aspect ratio of about 7:1 (depth:width) was formed in the BPSG and lined with afirst layer 132 of doped polysilicon (phosphorus dopant at a concentration of 1020/cm3) by low pressure CVD to a thickness of about 500 Angstroms. - A layer of undoped amorphous silicon was provided as
layer 134 by CVD to a thickness of about 500 Angstroms and converted to HSG silicon by seeding and annealing.Fill material 140 in the form of a photoresist was provided in the remainder of thecavity 120, with the resulting structure illustrated in FIG. 10. - Following application of the photoresist, the next step was to employ a chemical-mechanical polishing (CMP) process to isolate the
cavities 120, followed by decapping of the polysilicon inlayer 132 in an etch solution of hydrofluoric acid (HF) and TMAH. In other words, the structure was planarized down to the level of the BPSG and the native oxide is removed from the exposed doped silicon inlayer 132 and undoped HSG silicon inlayer 134. The resulting structure is illustrated in FIG. 11. - With edges of both the doped
silicon layer 132 and the undopedHSG silicon layer 134 exposed at the top of the cavity (the remainder of which is filled with photoresist 140), the structure was subjected to a wet etch of 2% TMAH (by weight) at 30 degrees Celsius for a period of 5 minutes. - After etching, the
photoresist 140 is removed from thecavity 120 by stripping. - The BPSG layer surrounding the cavities is then etched back from around the cavity in a 10:1 HF dip and the resulting structure is depicted in FIG. 13, where it can be seen that the hemispherical grain silicon extends above the outer layer of polysilicon for each of the cavities.
- Structures were manufactured according to Example 1, with the exception that, after decapping, the edges of the doped
polysilicon 132 and theundoped HSG silicon 134 were etched with a 2.25% TMAH solution (by weight) at 30 degrees Celsius. - The resulting structures are depicted in FIG. 14 after etch-back of the BPSG surrounding the cavities. It can be seen that the height of the hemispherical grain silicon relative is reduced relative to the outer layer of doped polysilicon.
- Structures were manufactured according to Example 1, with the exception that, after decapping, the edges of the doped
polysilicon 132 and the undopedhemispherical grain silicon 34 were etched with a 2.6% TMAH solution (by weight) at 30 degrees Celsius. - The resulting structures are depicted in FIG. 15 after etch-back of the BPSG layer. It can be seen that the hemispherical grain silicon layer is recessed within the container structure formed by the outer layer of doped polysilicon.
- All patents, patent documents and other references cited herein are incorporated in their entirety as if each were incorporated separately. This invention has been described with reference to illustrative embodiments and is not meant to be construed in a limiting sense. As described previously, one skilled in the art will recognize that various other illustrative applications may utilize the recessed hemispherical grain silicon layers as described herein. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that may fall within the scope of the present invention as defined by the accompanying claims.
Claims (46)
1. A capacitor structure comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening;
a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive;
a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and
an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
2. A capacitor structure according to claim 1 , wherein the cavity is cup-shaped.
3. A capacitor structure comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening;
a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive;
a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and
an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity over about 20% or less of the distance between the opening and the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
4. A capacitor structure according to claim 3 , wherein the edge zone extends over about 10% or less of the distance between the opening and the bottom of the cavity.
5. A capacitor structure comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening;
a first layer located on an inner surface of the sidewall structure, wherein the first layer is electrically conductive;
a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and
an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity and having a depth of about 2000 Angstroms or less from the opening of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
6. A capacitor structure according to claim 5 , wherein the edge zone has a depth of about 1000 Angstroms or less from the opening of the cavity.
7. A capacitor structure comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening;
a first layer located on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and
an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
8. A capacitor structure according to claim 7 , wherein the first layer consists essentially of doped silicon.
9. A capacitor structure according to claim 7 , wherein the second layer consists essentially of hemispherical grain silicon.
10. A capacitor structure according to claim 7 , wherein the cavity is cup-shaped.
11. A capacitor structure comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening;
a first layer located on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and
an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity over about 20% or less of the distance between the opening and the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
12. A capacitor structure according to claim 11 , wherein the first layer consists essentially of doped silicon and the second layer consists essentially of hemispherical grain silicon.
13. A capacitor structure according to claim 11 , wherein the cavity is cup-shaped.
14. A capacitor structure comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening;
a first layer located on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
a second layer located on the first layer, the second layer comprising hemispherical grain silicon; and
an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity and having a depth of about 2000 Angstroms or less from the opening of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
15. A capacitor structure according to claim 14 , wherein the first layer consists essentially of doped silicon and the second layer consists essentially of hemispherical grain silicon.
16. A capacitor structure according to claim 14 , wherein the cavity is cup-shaped.
17. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon precursor;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity;
removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and
converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
18. A method according to claim 17 , wherein removing the hemispherical grain silicon precursor in the second layer comprises selectively etching the second layer relative to the first layer in an etch process with a selectivity for etching the hemispherical grain silicon precursor in the second layer over the first layer of at least about 2:1.
19. A method according to claim 17 , wherein removing the hemispherical grain silicon precursor in the second layer comprises selectively etching the second layer relative to the first layer in an etch process with a selectivity for etching the hemispherical grain silicon precursor in the second layer over the first layer of at least about 4:1.
20. A method according to claim 17 , wherein the cavity is cup-shaped.
21. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon precursor;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity;
removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and
converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
22. A method according to claim 21 , wherein removing the hemispherical grain silicon precursor in the second layer comprises selectively etching the second layer relative to the first layer by contacting at least the exposed edge of the second layer with an etchant having a selectivity for etching the hemispherical grain silicon precursor in the second layer over the first layer of at least about 2:1.
23. A method according to claim 21 , wherein removing the hemispherical grain silicon precursor in the second layer comprises selectively etching the second layer relative to the first layer by contacting at least the exposed edge of the second layer with an etchant having a selectivity for etching the hemispherical grain silicon precursor in the second layer over the first layer of at least about 4:1.
24. A method according to claim 21 , wherein the cavity is cup-shaped.
25. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon precursor;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity;
removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant comprising TMAH at a concentration of greater than 2.25% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and
converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
26. A method according to claim 25 , wherein the etchant comprises TMAH at a concentration of about 2.5% (by weight) or greater.
27. A method according to claim 25 , wherein the etching is performed at a temperature of about 30 degrees Celsius.
28. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon precursor;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity;
removing the hemispherical grain silicon precursor in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant comprising TMAH at a concentration of greater than 2.25% (by weight) and less than 3% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity; and
converting the hemispherical grain silicon precursor in the second layer to hemispherical grain silicon, wherein the edge zone is substantially free of the hemispherical grain silicon.
29. A method according to claim 28 , wherein the etching is performed at a temperature of about 30 degrees Celsius.
30. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer is electrically conductive;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and
removing the hemispherical grain silicon in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
31. A method according to claim 30 , wherein removing the hemispherical grain silicon in the second layer comprises selectively etching the second layer relative to the first layer in an etch process with a selectivity for etching the hemispherical grain silicon in the second layer over the first layer of at least about 2:1.
32. A method according to claim 30 , wherein removing the hemispherical grain silicon in the second layer comprises selectively etching the second layer relative to the first layer in an etch process with a selectivity for etching the hemispherical grain silicon in the second layer over the first layer of at least about 4:1.
33. A method according to claim 30 , wherein the cavity is cup-shaped.
34. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and
removing the hemispherical grain silicon in the second layer proximate the opening of the cavity to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
35. A method according to claim 34 , wherein removing the hemispherical grain silicon in the second layer comprises selectively etching the second layer relative to the first layer by contacting at least the exposed edge of the second layer with an etchant having a selectivity for etching the hemispherical grain silicon in the second layer over the first layer of at least about 2:1.
36. A method according to claim 34 , wherein removing the hemispherical grain silicon in the second layer comprises selectively etching the second layer relative to the first layer by contacting at least the exposed edge of the second layer with an etchant having a selectivity for etching the hemispherical grain silicon in the second layer over the first layer of at least about 4:1.
37. A method according to claim 34 , wherein the cavity is cup-shaped.
38. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and
removing the hemispherical grain silicon of the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant comprising TMAH at a concentration of greater than 2.25% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
39. A method according to claim 38 , wherein the etchant comprises TMAH at a concentration of about 2.5% (by weight) or greater.
40. A method according to claim 38 , wherein the etching is performed at a temperature of about 30 degrees Celsius.
41. A method of forming a capacitor structure comprising:
providing a cavity in a substrate, the cavity comprising a sidewall structure, an opening, and a bottom opposite the opening of the cavity;
providing a first layer on an inner surface of the sidewall structure, wherein the first layer comprises doped silicon;
providing a second layer on substantially all of the first layer, the second layer comprising hemispherical grain silicon;
providing fill material in the cavity, wherein at least an edge of the second layer is exposed proximate the opening of the cavity; and
removing the hemispherical grain silicon in the second layer proximate the opening of the cavity by contacting at least the exposed edge of the second layer with an etchant comprising TMAH at a concentration of greater than 2.25% (by weight) and less than 3% (by weight) to form an edge zone about the opening of the cavity, the edge zone extending from the opening of the cavity towards the bottom of the cavity, wherein the edge zone is substantially free of the hemispherical grain silicon.
42. A method according to claim 41 , wherein the etching is performed at a temperature of about 30 degrees Celsius.
43. A capacitor comprising:
a cavity comprising a sidewall structure, an opening, and a bottom opposite the opening, the sidewall structure extending between the opening and the bottom of the cavity;
a first electrode comprising an electrically conductive first layer located on an inner surface of the sidewall structure, a second layer comprising hemispherical grain silicon located on the first layer, and an edge zone on the inner surface of the sidewall structure proximate the opening of the cavity, wherein the edge zone extends from the opening of the cavity towards the bottom of the cavity, and further wherein the edge zone is substantially free of the hemispherical grain silicon;
a dielectric layer located on at least a portion of the first electrode; and
a second electrode located on the dielectric layer.
44. A capacitor according to claim 43 , wherein the first layer of the first electrode comprises doped silicon.
45. A capacitor according to claim 43 , wherein the first layer of the first electrode consists essentially of doped silicon.
46. A capacitor according to claim 43 , wherein the second layer of the first electrode consists essentially of hemispherical grain silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/771,042 US20040155274A1 (en) | 1999-08-30 | 2004-02-03 | Capacitor structures with recessed hemispherical grain silicon |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/385,786 US6693320B1 (en) | 1999-08-30 | 1999-08-30 | Capacitor structures with recessed hemispherical grain silicon |
US10/771,042 US20040155274A1 (en) | 1999-08-30 | 2004-02-03 | Capacitor structures with recessed hemispherical grain silicon |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/385,786 Continuation US6693320B1 (en) | 1999-08-30 | 1999-08-30 | Capacitor structures with recessed hemispherical grain silicon |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040155274A1 true US20040155274A1 (en) | 2004-08-12 |
Family
ID=28792095
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/385,786 Expired - Lifetime US6693320B1 (en) | 1999-08-30 | 1999-08-30 | Capacitor structures with recessed hemispherical grain silicon |
US09/652,910 Expired - Lifetime US6632719B1 (en) | 1999-08-30 | 2000-08-31 | Capacitor structures with recessed hemispherical grain silicon |
US10/771,042 Abandoned US20040155274A1 (en) | 1999-08-30 | 2004-02-03 | Capacitor structures with recessed hemispherical grain silicon |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/385,786 Expired - Lifetime US6693320B1 (en) | 1999-08-30 | 1999-08-30 | Capacitor structures with recessed hemispherical grain silicon |
US09/652,910 Expired - Lifetime US6632719B1 (en) | 1999-08-30 | 2000-08-31 | Capacitor structures with recessed hemispherical grain silicon |
Country Status (1)
Country | Link |
---|---|
US (3) | US6693320B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050073801A1 (en) * | 2003-08-28 | 2005-04-07 | Tessera, Inc. | Capacitor having low resistance electrode including a thin silicon layer |
US20120292763A1 (en) * | 2010-02-09 | 2012-11-22 | International Business Machines Corporation | Electromigration immune through-substrate vias |
US20120319181A1 (en) * | 2011-06-20 | 2012-12-20 | Beijing Nmc Co., Ltd. | Semiconductor structure and method for manufacturing the same |
US20180012811A1 (en) * | 2016-07-07 | 2018-01-11 | Semiconductor Manufacturing International (Shanghai)Corporation | Semiconductor device and fabrication method thereof |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6693320B1 (en) * | 1999-08-30 | 2004-02-17 | Micron Technology, Inc. | Capacitor structures with recessed hemispherical grain silicon |
JP4005805B2 (en) * | 2001-12-17 | 2007-11-14 | 株式会社東芝 | Semiconductor device |
US6617222B1 (en) * | 2002-02-27 | 2003-09-09 | Micron Technology, Inc. | Selective hemispherical silicon grain (HSG) conversion inhibitor for use during the manufacture of a semiconductor device |
KR100477807B1 (en) * | 2002-09-17 | 2005-03-22 | 주식회사 하이닉스반도체 | Capacitor and method for fabricating the same |
US6994151B2 (en) * | 2002-10-22 | 2006-02-07 | Cooligy, Inc. | Vapor escape microchannel heat exchanger |
US20040076408A1 (en) * | 2002-10-22 | 2004-04-22 | Cooligy Inc. | Method and apparatus for removeably coupling a heat rejection device with a heat producing device |
US7156159B2 (en) * | 2003-03-17 | 2007-01-02 | Cooligy, Inc. | Multi-level microchannel heat exchangers |
US7000684B2 (en) * | 2002-11-01 | 2006-02-21 | Cooligy, Inc. | Method and apparatus for efficient vertical fluid delivery for cooling a heat producing device |
US20040112571A1 (en) * | 2002-11-01 | 2004-06-17 | Cooligy, Inc. | Method and apparatus for efficient vertical fluid delivery for cooling a heat producing device |
AU2003286855A1 (en) * | 2002-11-01 | 2004-06-07 | Cooligy, Inc. | Method and apparatus for achieving temperature uniformity and hot spot cooling in a heat producing device |
US7836597B2 (en) | 2002-11-01 | 2010-11-23 | Cooligy Inc. | Method of fabricating high surface to volume ratio structures and their integration in microheat exchangers for liquid cooling system |
US6986382B2 (en) * | 2002-11-01 | 2006-01-17 | Cooligy Inc. | Interwoven manifolds for pressure drop reduction in microchannel heat exchangers |
US7806168B2 (en) | 2002-11-01 | 2010-10-05 | Cooligy Inc | Optimal spreader system, device and method for fluid cooled micro-scaled heat exchange |
US7044196B2 (en) * | 2003-01-31 | 2006-05-16 | Cooligy,Inc | Decoupled spring-loaded mounting apparatus and method of manufacturing thereof |
US7090001B2 (en) * | 2003-01-31 | 2006-08-15 | Cooligy, Inc. | Optimized multiple heat pipe blocks for electronics cooling |
US7201012B2 (en) * | 2003-01-31 | 2007-04-10 | Cooligy, Inc. | Remedies to prevent cracking in a liquid system |
US20040233639A1 (en) * | 2003-01-31 | 2004-11-25 | Cooligy, Inc. | Removeable heat spreader support mechanism and method of manufacturing thereof |
US7017654B2 (en) * | 2003-03-17 | 2006-03-28 | Cooligy, Inc. | Apparatus and method of forming channels in a heat-exchanging device |
US7091085B2 (en) * | 2003-11-14 | 2006-08-15 | Micron Technology, Inc. | Reduced cell-to-cell shorting for memory arrays |
DE102004022176B4 (en) * | 2004-05-05 | 2009-07-23 | Atmel Germany Gmbh | Method for producing passive components on a substrate |
US7499124B2 (en) * | 2005-05-05 | 2009-03-03 | Industrial Technology Research Institute | Polymer dispersed liquid crystal device conditioned with a predetermined anchoring energy, a predetermined polymer concentration by weight percent and a predetermined cell gap to enhance phase separation and to make smaller and more uniform liquid crystal droplets |
US8157001B2 (en) | 2006-03-30 | 2012-04-17 | Cooligy Inc. | Integrated liquid to air conduction module |
US9297571B1 (en) | 2008-03-10 | 2016-03-29 | Liebert Corporation | Device and methodology for the removal of heat from an equipment rack by means of heat exchangers mounted to a door |
US8250877B2 (en) | 2008-03-10 | 2012-08-28 | Cooligy Inc. | Device and methodology for the removal of heat from an equipment rack by means of heat exchangers mounted to a door |
CN102016970B (en) * | 2008-05-01 | 2014-04-16 | 希毕克斯影像有限公司 | Color display devices |
Citations (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4803535A (en) * | 1986-03-03 | 1989-02-07 | Fujitus Limited | Dynamic random access memory trench capacitor |
US5270241A (en) * | 1992-03-13 | 1993-12-14 | Micron Technology, Inc. | Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing |
US5283453A (en) * | 1992-10-02 | 1994-02-01 | International Business Machines Corporation | Trench sidewall structure |
US5384152A (en) * | 1992-05-12 | 1995-01-24 | International Business Machines Corporation | Method for forming capacitors with roughened single crystal plates |
US5392189A (en) * | 1993-04-02 | 1995-02-21 | Micron Semiconductor, Inc. | Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same |
US5407534A (en) * | 1993-12-10 | 1995-04-18 | Micron Semiconductor, Inc. | Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal |
US5418180A (en) * | 1994-06-14 | 1995-05-23 | Micron Semiconductor, Inc. | Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon |
US5521407A (en) * | 1993-11-08 | 1996-05-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device having cell isolation structure |
US5555520A (en) * | 1993-12-03 | 1996-09-10 | Kabushiki Kaisha Toshiba | Trench capacitor cells for a dram having single monocrystalline capacitor electrode |
US5753558A (en) * | 1994-11-02 | 1998-05-19 | Micron Technology, Inc. | Method of forming a capacitor |
US5759262A (en) * | 1995-11-03 | 1998-06-02 | Micron Technology, Inc. | Method of forming hemispherical grained silicon |
US5837580A (en) * | 1993-12-10 | 1998-11-17 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon |
US5882979A (en) * | 1996-02-29 | 1999-03-16 | Micron Technology, Inc. | Method for forming controllable surface enhanced three dimensional objects |
US5963801A (en) * | 1996-12-19 | 1999-10-05 | Lsi Logic Corporation | Method of forming retrograde well structures and punch-through barriers using low energy implants |
US5963814A (en) * | 1997-10-28 | 1999-10-05 | Micron Technology, Inc. | Method of forming recessed container cells by wet etching conductive layer and dissimilar layer formed over conductive layer |
US6020609A (en) * | 1997-10-31 | 2000-02-01 | Texas Instruments - Acer Incorporated | DRAM cell with a rugged stacked trench (RST) capacitor |
US6025247A (en) * | 1996-09-21 | 2000-02-15 | Nanya Technology Corporation | Method for manufacturing capacitor structure of dynamic memory cell |
US6046083A (en) * | 1998-06-26 | 2000-04-04 | Vanguard International Semiconductor Corporation | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications |
US6090655A (en) * | 1996-05-07 | 2000-07-18 | Micron Technology, Inc. | Increased interior volume for integrated memory cell |
US6127239A (en) * | 1998-02-26 | 2000-10-03 | Micron Technology, Inc. | Semiconductor processing methods, and methods of forming capacitors |
US6153679A (en) * | 1996-06-28 | 2000-11-28 | Toray Industries, Inc. | Titanium oxide and resin composition |
US6159785A (en) * | 1998-08-17 | 2000-12-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6177696B1 (en) * | 1998-08-13 | 2001-01-23 | International Business Machines Corporation | Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices |
US6207524B1 (en) * | 1998-09-29 | 2001-03-27 | Siemens Aktiengesellschaft | Memory cell with a stacked capacitor |
US6259127B1 (en) * | 1995-12-19 | 2001-07-10 | Micron Technology, Inc. | Integrated circuit container having partially rugged surface |
US6303956B1 (en) * | 1999-02-26 | 2001-10-16 | Micron Technology, Inc. | Conductive container structures having a dielectric cap |
US6326277B1 (en) * | 1999-08-30 | 2001-12-04 | Micron Technology, Inc. | Methods of forming recessed hemispherical grain silicon capacitor structures |
US6376328B1 (en) * | 1999-06-01 | 2002-04-23 | Nec Corporation | Method for producing capacitor elements, and capacitor element |
US6391712B2 (en) * | 2000-08-11 | 2002-05-21 | Hynix Semiconductor, Inc. | Method of forming a storage node of a capacitor that prevents HSG(Hemi-Spherical Grain) bridging |
US6399439B1 (en) * | 1998-02-19 | 2002-06-04 | Nec Corporation | Method for manufacturing semiconductor device |
US6632719B1 (en) * | 1999-08-30 | 2003-10-14 | Micron Technology, Inc. | Capacitor structures with recessed hemispherical grain silicon |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5963804A (en) | 1997-03-14 | 1999-10-05 | Micron Technology, Inc. | Method of making a doped silicon structure with impression image on opposing roughened surfaces |
TW402811B (en) * | 1999-04-26 | 2000-08-21 | Taiwan Semiconductor Mfg | The manufacture method of the DRAM capacitor |
-
1999
- 1999-08-30 US US09/385,786 patent/US6693320B1/en not_active Expired - Lifetime
-
2000
- 2000-08-31 US US09/652,910 patent/US6632719B1/en not_active Expired - Lifetime
-
2004
- 2004-02-03 US US10/771,042 patent/US20040155274A1/en not_active Abandoned
Patent Citations (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4803535A (en) * | 1986-03-03 | 1989-02-07 | Fujitus Limited | Dynamic random access memory trench capacitor |
US5270241A (en) * | 1992-03-13 | 1993-12-14 | Micron Technology, Inc. | Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing |
US5384152A (en) * | 1992-05-12 | 1995-01-24 | International Business Machines Corporation | Method for forming capacitors with roughened single crystal plates |
US5283453A (en) * | 1992-10-02 | 1994-02-01 | International Business Machines Corporation | Trench sidewall structure |
US5392189A (en) * | 1993-04-02 | 1995-02-21 | Micron Semiconductor, Inc. | Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same |
US5521407A (en) * | 1993-11-08 | 1996-05-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device having cell isolation structure |
US5555520A (en) * | 1993-12-03 | 1996-09-10 | Kabushiki Kaisha Toshiba | Trench capacitor cells for a dram having single monocrystalline capacitor electrode |
US5407534A (en) * | 1993-12-10 | 1995-04-18 | Micron Semiconductor, Inc. | Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal |
US5837580A (en) * | 1993-12-10 | 1998-11-17 | Micron Technology, Inc. | Method to form hemi-spherical grain (HSG) silicon |
US5418180A (en) * | 1994-06-14 | 1995-05-23 | Micron Semiconductor, Inc. | Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon |
US5753558A (en) * | 1994-11-02 | 1998-05-19 | Micron Technology, Inc. | Method of forming a capacitor |
US5759262A (en) * | 1995-11-03 | 1998-06-02 | Micron Technology, Inc. | Method of forming hemispherical grained silicon |
US6259127B1 (en) * | 1995-12-19 | 2001-07-10 | Micron Technology, Inc. | Integrated circuit container having partially rugged surface |
US5882979A (en) * | 1996-02-29 | 1999-03-16 | Micron Technology, Inc. | Method for forming controllable surface enhanced three dimensional objects |
US6090655A (en) * | 1996-05-07 | 2000-07-18 | Micron Technology, Inc. | Increased interior volume for integrated memory cell |
US6153679A (en) * | 1996-06-28 | 2000-11-28 | Toray Industries, Inc. | Titanium oxide and resin composition |
US6025247A (en) * | 1996-09-21 | 2000-02-15 | Nanya Technology Corporation | Method for manufacturing capacitor structure of dynamic memory cell |
US5963801A (en) * | 1996-12-19 | 1999-10-05 | Lsi Logic Corporation | Method of forming retrograde well structures and punch-through barriers using low energy implants |
US5963814A (en) * | 1997-10-28 | 1999-10-05 | Micron Technology, Inc. | Method of forming recessed container cells by wet etching conductive layer and dissimilar layer formed over conductive layer |
US6020609A (en) * | 1997-10-31 | 2000-02-01 | Texas Instruments - Acer Incorporated | DRAM cell with a rugged stacked trench (RST) capacitor |
US6399439B1 (en) * | 1998-02-19 | 2002-06-04 | Nec Corporation | Method for manufacturing semiconductor device |
US6127239A (en) * | 1998-02-26 | 2000-10-03 | Micron Technology, Inc. | Semiconductor processing methods, and methods of forming capacitors |
US6046083A (en) * | 1998-06-26 | 2000-04-04 | Vanguard International Semiconductor Corporation | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications |
US6177696B1 (en) * | 1998-08-13 | 2001-01-23 | International Business Machines Corporation | Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices |
US6159785A (en) * | 1998-08-17 | 2000-12-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6207524B1 (en) * | 1998-09-29 | 2001-03-27 | Siemens Aktiengesellschaft | Memory cell with a stacked capacitor |
US6303956B1 (en) * | 1999-02-26 | 2001-10-16 | Micron Technology, Inc. | Conductive container structures having a dielectric cap |
US6376328B1 (en) * | 1999-06-01 | 2002-04-23 | Nec Corporation | Method for producing capacitor elements, and capacitor element |
US6326277B1 (en) * | 1999-08-30 | 2001-12-04 | Micron Technology, Inc. | Methods of forming recessed hemispherical grain silicon capacitor structures |
US6566222B2 (en) * | 1999-08-30 | 2003-05-20 | Micron Technology, Inc. | Methods of forming recessed hemispherical grain silicon capacitor structures |
US6632719B1 (en) * | 1999-08-30 | 2003-10-14 | Micron Technology, Inc. | Capacitor structures with recessed hemispherical grain silicon |
US6693320B1 (en) * | 1999-08-30 | 2004-02-17 | Micron Technology, Inc. | Capacitor structures with recessed hemispherical grain silicon |
US6391712B2 (en) * | 2000-08-11 | 2002-05-21 | Hynix Semiconductor, Inc. | Method of forming a storage node of a capacitor that prevents HSG(Hemi-Spherical Grain) bridging |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050073801A1 (en) * | 2003-08-28 | 2005-04-07 | Tessera, Inc. | Capacitor having low resistance electrode including a thin silicon layer |
US7170736B2 (en) * | 2003-08-28 | 2007-01-30 | Tessera, Inc. | Capacitor having low resistance electrode including a thin silicon layer |
US20120292763A1 (en) * | 2010-02-09 | 2012-11-22 | International Business Machines Corporation | Electromigration immune through-substrate vias |
US9153558B2 (en) * | 2010-02-09 | 2015-10-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
US20120319181A1 (en) * | 2011-06-20 | 2012-12-20 | Beijing Nmc Co., Ltd. | Semiconductor structure and method for manufacturing the same |
US8546910B2 (en) * | 2011-06-20 | 2013-10-01 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor structure and method for manufacturing the same |
US20180012811A1 (en) * | 2016-07-07 | 2018-01-11 | Semiconductor Manufacturing International (Shanghai)Corporation | Semiconductor device and fabrication method thereof |
US10431501B2 (en) * | 2016-07-07 | 2019-10-01 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device with high-K gate dielectric layer and fabrication method thereof |
Also Published As
Publication number | Publication date |
---|---|
US6693320B1 (en) | 2004-02-17 |
US6632719B1 (en) | 2003-10-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6693320B1 (en) | Capacitor structures with recessed hemispherical grain silicon | |
US5998257A (en) | Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry | |
US6121084A (en) | Semiconductor processing methods of forming hemispherical grain polysilicon layers, methods of forming capacitors, and capacitors | |
US5354705A (en) | Technique to fabricate a container structure with rough inner and outer surfaces | |
US6403442B1 (en) | Methods of forming capacitors and resultant capacitor structures | |
US6207523B1 (en) | Methods of forming capacitors DRAM arrays, and monolithic integrated circuits | |
US7112508B2 (en) | Method for forming conductive material in opening and structure regarding same | |
US6232168B1 (en) | Memory circuitry and method of forming memory circuitry | |
US5994197A (en) | Method for manufacturing dynamic random access memory capable of increasing the storage capacity of the capacitor | |
JP2000216362A (en) | Capacitor structure of integrated circuit | |
US6312986B1 (en) | Concentric container fin capacitor and method | |
US7732851B2 (en) | Method for fabricating a three-dimensional capacitor | |
US6566222B2 (en) | Methods of forming recessed hemispherical grain silicon capacitor structures | |
US6277687B1 (en) | Method of forming a pair of capacitors having a common capacitor electrode, method of forming DRAM circuitry, integrated circuitry and DRAM circuitry | |
JP3233051B2 (en) | Method for manufacturing semiconductor device | |
US6448146B1 (en) | Methods of manufacturing integrated circuit capacitors having hemispherical grain electrodes | |
JPH0870100A (en) | Ferroelectric substance capacitor preparation | |
US6383886B1 (en) | Method to reduce floating grain defects in dual-sided container capacitor fabrication | |
US20040159897A1 (en) | Methods of forming spaced conductive regions, and methods of forming capacitor constructions | |
US20020043681A1 (en) | Hole-type storage cell structure and method for making the structure | |
KR19990086181A (en) | Capacitor of Semiconductor Device and Manufacturing Method Thereof | |
KR20030093792A (en) | Method of fabricating capacitor in semiconductor | |
KR20020000323A (en) | A method for formation of cylindrical capacitors of semiconductor devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |