US20040152294A1 - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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Publication number
US20040152294A1
US20040152294A1 US10/720,976 US72097603A US2004152294A1 US 20040152294 A1 US20040152294 A1 US 20040152294A1 US 72097603 A US72097603 A US 72097603A US 2004152294 A1 US2004152294 A1 US 2004152294A1
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film
forming
insulating film
interlayer insulating
spacer
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Kyeong Choi
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MagnaChip Semiconductor Ltd
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and, more specifically, to a method for forming a metal line of a semiconductor device, wherein a spacer is formed at a side wall of a trench which is formed in an interlayer insulating film, thereby compensating for vulnerability of mechanical properties of the interlayer insulating film and suppressing such a phenomenon that the interlayer film is eroded or the metal line is dished.
  • a metal line is thick and an interval between the metal lines is narrow, so that there is a problem that an interlayer insulating film is broken during a chemical mechanical polishing (CMP) process of the metal line formation.
  • CMP chemical mechanical polishing
  • the problem is more critical in case of using an oxide film having a low dielectric constant as an interlayer insulating film.
  • the low dielectric oxide film used as the interlayer insulating film is porous and contains a large quantity of carbon, it is vulnerable to a mechanical stress. In particular, as the line is still thicker, the vulnerability of the mechanical properties is further worsened.
  • the low dielectric oxide film must be inevitably used in order to obtain a high Quality factor (Q factor).
  • Q factor Quality factor
  • the present invention is directed to provide a method for manufacturing a semiconductor device and, more specifically, to a method for forming a metal line of a semiconductor device, wherein a spacer is formed at a side wall of a trench which is formed in an interlayer insulating film, thereby compensating for vulnerability of mechanical properties of the interlayer insulating film and suppressing such a phenomenon that the interlayer film is eroded and the metal line is dished.
  • One aspect of the present invention is to provide a method for forming a metal line of a semiconductor device comprising the steps of: forming a via plug on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate, on which the via plug is formed; forming a trench by patterning the interlayer insulating film in order to form an upper line to be connected to the via plug; depositing a spacer insulating film, which is more invulnerable to a mechanical stress than the interlayer insulating film, on the semiconductor substrate on which the trench is formed; forming a spacer on a side wall of the trench by performing an anisotropic-dry-etching of the spacer insulating film; and forming a metal line by burying the trench with a conductive material.
  • the spacer insulating film is formed by using an Si 3 N 4 film or an SiC film which has a mechanical strength stronger than that of the interlayer insulation film and can be used as a metal diffusion barrier film. Further, the spacer insulating film is preferably deposited by using a plasma-enhanced chemical vapor deposition (PE-CVD) method at a temperature in the range of 200° C. to 450° C. under a pressure in the range of 0.01 torr to 500 torr.
  • PE-CVD plasma-enhanced chemical vapor deposition
  • the spacer insulating film is deposited to have a thickness in the range of 50 ⁇ to 1500 ⁇ .
  • the anisotropic-drying-etching may be a reactive ion etching.
  • the interlayer insulating film is an oxide film having a lower dielectric constant and formed by using an spin on glass (SOG) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a carbon doped dielectric (COD) film or a porous low dielectric oxide film.
  • SOG spin on glass
  • F-TEOS fluorine doped tetra ethyl ortho silicate
  • CDOD carbon doped dielectric
  • the step of forming the via plug comprises the steps of: forming a lower line on the semiconductor substrate; forming a second interlayer insulating film on the semiconductor substrate, on which the lower line is formed; forming a via hole by patterning the second interlayer insulating film in order to connect the lower line with the upper line; and forming a via plug by burying the via hole with a conductive metal.
  • the step of forming the metal line comprises the steps of: depositing a diffusion barrier film along a step difference of the semiconductor substrate on which the spacer is formed; depositing a copper seed layer on the diffusion barrier film; forming a copper film on the copper seed layer by using an electroplating method, thereby burying an opening portion; and forming the metal line by planarizing the copper film.
  • FIGS. 1 to 6 are cross-sectional views for explaining a method for forming a metal line of a semiconductor in accordance with a preferred embodiment of the present invention.
  • FIGS. 1 to 6 are cross-sectional views for explaining a method for forming a metal line of a semiconductor in accordance with a preferred embodiment of the present invention.
  • a semiconductor substrate 100 where a semiconductor device (not shown) such as a transistor is formed is prepared.
  • a lower line 102 is formed on the semiconductor substrate 100 .
  • the lower line 102 is formed with a conductive film such as a Cu film, an Al film, a W film, and so on.
  • a first interlayer insulating film 104 is formed on the lower line 102 .
  • the first interlayer insulating film 104 is formed with such as an spin on glass (SOG) film, a tetra ethyl ortho silicate (TEOS) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a phosphorus silicate glass (PSG) film, a boro phosphorus silicate glass (BPSG) film, and so on.
  • SOG spin on glass
  • TEOS tetra ethyl ortho silicate
  • F-TEOS fluorine doped tetra ethyl ortho silicate
  • PSG phosphorus silicate glass
  • BPSG boro phosphorus silicate glass
  • a first photosensitive film pattern (not shown) for defining a via hole which opens the lower line 102 is formed on the first interlayer insulating film 104 .
  • the first interlayer insulating film 104 is subjected to an etching process by using the first photosensitive film pattern as a mask to form the via hole.
  • the etching process for forming the via hole utilizes a mixed gas of C 4 F 8 gas or C 5 F 8 gas, with O 2 gas, N 2 gas, and Ar gas.
  • the etching process is carried out by injecting a mixed gas of C 4 F 8 gas or C 5 F 8 gas in the range of 3 sccm to 200 sccm, O 2 gas in the range of 5 sccm to 500 sccm, N 2 gas in the range of 10 sccm to 2000 sccm, and Ar gas in the range of 100 sccm to 3000 sccm under conditions of a pressure in the range of 10 mT to 400 mT, a source power in the range of 100 W to 3000 W, and a bias power in the range of 500 W to 1800 W.
  • a mixed gas of C 4 F 8 gas or C 5 F 8 gas in the range of 3 sccm to 200 sccm
  • O 2 gas in the range of 5 sccm to 500 sccm
  • N 2 gas in the range of 10 sccm to 2000 sccm
  • Ar gas in the range of 100 sccm to 3000
  • the via hole is buried with a conductive material to form a via plug 106 .
  • the via plug 106 is formed with a Cu film, a Pt film, an Ag film, an Al film, or a W film.
  • a second interlayer insulating film 108 is formed on the via plug 106 and the first interlayer insulating film 104 .
  • the second interlayer insulating film 108 is formed by using a low dielectric oxide film.
  • the interlayer second insulating film 108 is formed by using an spin on glass (SOG) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a carbon doped dielectric (COD) film or a porous low dielectric oxide film.
  • SOG spin on glass
  • F-TEOS fluorine doped tetra ethyl ortho silicate
  • CDOD carbon doped dielectric
  • the second interlayer insulating film 108 is deposited to have a thickness in the range of 0.5 ⁇ m to an order of 10 ⁇ m in order to satisfy a desired quality factor (Q).
  • Q quality factor
  • a second photosensitive film pattern (not shown) for defining a trench 109 is formed on the semiconductor substrate 100 .
  • the second interlayer insulating film 108 is subjected to an etching process by using the second photosensitive film pattern as a mask to form the trench 109 for exposing the via plug 106 .
  • plasma that is made by activating C 4 F 8 gas, O 2 gas, N 2 gas, or Ar gas, for example, is used for etching the second interlayer insulating film 108 to form the trench 109 .
  • an etching protection film is formed at the lower portion of the second interlayer insulating film 108 to be used as an etching stopper layer at the time of the trench formation.
  • a spacer insulating film is deposited along the step difference on the product where the trench 109 is formed, and subsequently, an anisotropic-dry-etching process is carried out to form a spacer 110 .
  • the spacer insulating film is formed by using an Si 3 N 4 film or an SiC film which has a mechanical strength stronger than that of the second interlayer insulation film 108 and can be used as a metal diffusion barrier film. Since the second interlayer insulating film 108 having a low dielectric constant is vulnerable to a mechanical stress generated in a chemical mechanical polishing (CMP) process, or the like, the spacer is formed on the side wall of the trench formed in the second interlayer insulating film 108 in order to compensate for its vulnerability.
  • CMP chemical mechanical polishing
  • the spacer insulating film is deposited by using a plasma-enhanced chemical vapor deposition (PE-CVD) method at a temperature in the range of 200° C. to 450° C. under a pressure in the range of 0.01 torr to 500 torr.
  • PE-CVD plasma-enhanced chemical vapor deposition
  • the spacer insulating film is deposited to have a thickness in the range of 50 ⁇ to 1500 ⁇ .
  • the anisotropic-drying-etching process is carried out by using a reactive ion etching method.
  • a diffusion barrier film 112 is deposited along the step difference on the product where the spacer 110 is formed.
  • the diffusing barrier film 112 is deposited to have a thickness of 100 ⁇ to 1500 ⁇ .
  • the diffusing barrier film 112 may be formed by using a Ta film, a Ti film, a TaN film, a TiN film, or the like, which has a good adhesive property to the second interlayer insulating film 108 and a metal line which is to be formed during the subsequent process and is capable of preventing metals from being diffused.
  • a copper seed layer 114 is formed on the diffusion barrier film 112 .
  • the copper seed layer 114 is formed to have a thickness in the range of 500 ⁇ to 2000 ⁇ .
  • a copper film 116 is buried in the trench by using an electroplating method on the copper seed layer 114 .
  • the copper film 116 is formed to have a thickness greater than that of the second interlayer insulating film 108 , so that it may have a thickness of, 0.5 ⁇ m to an order of 10 ⁇ m, for example.
  • an annealing process is carried out to densify the copper film 116 .
  • a chemical mechanical polishing process is carried out to remove the copper film 116 , the copper seed layer 114 , and the diffusion barrier film 112 above the second interlayer insulating film 108 .
  • a planarized upper line is formed.
  • a first passivation film 118 is formed on the product where the upper line is formed.
  • the first passivation film 118 is formed by using an Si 3 N 4 film or an SiC film to have a thickness in the range of 500 ⁇ to 1500 ⁇ .
  • a second passivation film 120 is formed on the first passivation film 118 .
  • the second passivation film 120 is formed by using a TEOS film to have a thickness in the range of 1,000 ⁇ to 10,000 ⁇ for wire bonding. If bonding method is chanced, the passivation thickness and structure can be changed.
  • the first and second passivation films 118 and 120 are patterned to form an opening portion (not shown) for forming a pad.
  • a diffusion barrier film is deposited along the step difference on the product where the opening portion for forming the pad is formed.
  • the diffusion barrier film is formed to have a thickness in the range of 100 ⁇ to 1000 ⁇ .
  • the diffusing barrier film may be formed by using a Ta film, a Ti film, a TaN film, a TiN film, or the like, which has a good adhesive property to the metal line and is capable of preventing metals which is to be formed as the pad from being diffused.
  • a conductive film is deposited on the diffusion barrier film and a pattering is carried out to form the pad (not shown).
  • the pad may be formed by using a metal film such as an Al film and so on.
  • the CMP process is carried out with using a substance having a strong mechanical strength such as Si 3 N 4 film, or the like, as the spacer for the interlayer insulating film to compensate for the weak mechanical strength of the low dielectric oxide film, so that it is possible to minimize of occurrence of breakage of the interlayer insulating film and erosion of the oxide film which occurs due to the CMP process.
  • the diffusion of Cu atoms in the subsequent thermal annealing process is suppressed by using the spacer insulating film, so that it is possible to improve the reliability of the line of the semiconductor devices.
  • the dishing in the metal line can be minimized, so that it is possible to obtain the high value of the quality factor (Q) and to minimize of physical failures of the metal line.
  • the spacer oxide film on the side wall of the trench can improve the layer covering property of the Cu diffusion barrier film in the Cu line, so that it is possible to improve the properties of the diffusion barrier film.

Abstract

The present invention provides a method for forming a metal line of a semiconductor device comprising the steps of: forming a via plug on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate, on which the via plug is formed; forming a trench by patterning the interlayer insulating film in order to form an upper line to be connected to the via plug; depositing a spacer insulating film, which is more invulnerable to a mechanical stress than the interlayer insulating film, on the semiconductor substrate on which the trench is formed; forming a spacer on a side wall of the trench by performing an anisotropic-dry-etching of the spacer insulating film; and forming a metal line by burying the trench with a conductive material.

Description

    BACKGROUND
  • 1. Field of the Invention [0001]
  • The present invention relates to a method for manufacturing a semiconductor device and, more specifically, to a method for forming a metal line of a semiconductor device, wherein a spacer is formed at a side wall of a trench which is formed in an interlayer insulating film, thereby compensating for vulnerability of mechanical properties of the interlayer insulating film and suppressing such a phenomenon that the interlayer film is eroded or the metal line is dished. [0002]
  • 2. Discussion of Related Art [0003]
  • In an inductor of a semiconductor device, a metal line is thick and an interval between the metal lines is narrow, so that there is a problem that an interlayer insulating film is broken during a chemical mechanical polishing (CMP) process of the metal line formation. The problem is more critical in case of using an oxide film having a low dielectric constant as an interlayer insulating film. In general, since the low dielectric oxide film used as the interlayer insulating film is porous and contains a large quantity of carbon, it is vulnerable to a mechanical stress. In particular, as the line is still thicker, the vulnerability of the mechanical properties is further worsened. Unfortunately, the low dielectric oxide film must be inevitably used in order to obtain a high Quality factor (Q factor). Moreover, there are problems that the interlayer is eroded and the metal line is dished. [0004]
  • Accordingly, there has been a necessity for solving the aforementioned problems, such as the vulnerability of the mechanical properties, the erosion of the oxide film, the dishing in the metal line, and so on, which occur in case of using the low dielectric film as an interlayer insulating film. [0005]
    • SUMMARY OF THE INVENTION
  • The present invention is directed to provide a method for manufacturing a semiconductor device and, more specifically, to a method for forming a metal line of a semiconductor device, wherein a spacer is formed at a side wall of a trench which is formed in an interlayer insulating film, thereby compensating for vulnerability of mechanical properties of the interlayer insulating film and suppressing such a phenomenon that the interlayer film is eroded and the metal line is dished. [0006]
  • One aspect of the present invention is to provide a method for forming a metal line of a semiconductor device comprising the steps of: forming a via plug on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate, on which the via plug is formed; forming a trench by patterning the interlayer insulating film in order to form an upper line to be connected to the via plug; depositing a spacer insulating film, which is more invulnerable to a mechanical stress than the interlayer insulating film, on the semiconductor substrate on which the trench is formed; forming a spacer on a side wall of the trench by performing an anisotropic-dry-etching of the spacer insulating film; and forming a metal line by burying the trench with a conductive material. [0007]
  • In the aforementioned of a method for forming a metal line of a semiconductor device according to another embodiment of the present invention, the spacer insulating film is formed by using an Si[0008] 3N4 film or an SiC film which has a mechanical strength stronger than that of the interlayer insulation film and can be used as a metal diffusion barrier film. Further, the spacer insulating film is preferably deposited by using a plasma-enhanced chemical vapor deposition (PE-CVD) method at a temperature in the range of 200° C. to 450° C. under a pressure in the range of 0.01 torr to 500 torr.
  • In the aforementioned of a method for forming a metal line of a semiconductor device according to another embodiment of the present invention, the spacer insulating film is deposited to have a thickness in the range of 50 Å to 1500 Å. [0009]
  • In the aforementioned of a method for forming a metal line of a semiconductor device according to another embodiment of the present invention, the anisotropic-drying-etching may be a reactive ion etching. [0010]
  • In the aforementioned of a method for forming a metal line of a semiconductor device according to another embodiment of the present invention, the interlayer insulating film is an oxide film having a lower dielectric constant and formed by using an spin on glass (SOG) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a carbon doped dielectric (COD) film or a porous low dielectric oxide film. [0011]
  • In the aforementioned of a method for forming a metal line of a semiconductor device according to another embodiment of the present invention, the step of forming the via plug comprises the steps of: forming a lower line on the semiconductor substrate; forming a second interlayer insulating film on the semiconductor substrate, on which the lower line is formed; forming a via hole by patterning the second interlayer insulating film in order to connect the lower line with the upper line; and forming a via plug by burying the via hole with a conductive metal. [0012]
  • In the aforementioned of a method for forming a metal line of a semiconductor device according to another embodiment of the present invention, the step of forming the metal line comprises the steps of: depositing a diffusion barrier film along a step difference of the semiconductor substrate on which the spacer is formed; depositing a copper seed layer on the diffusion barrier film; forming a copper film on the copper seed layer by using an electroplating method, thereby burying an opening portion; and forming the metal line by planarizing the copper film.[0013]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0014] 1 to 6 are cross-sectional views for explaining a method for forming a metal line of a semiconductor in accordance with a preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Now the preferred embodiments according to the present invention will be described with reference to the accompanying drawings. Since the preferred embodiments are provided for the purpose that the ordinary skilled in the art are able to understand the present invention, they may be modified in various manners and the scope of the present invention is not limited by the preferred embodiment described later. The later referred phrase, “a layer is formed on the other layer” means that the former layer is formed just on the latter layer, otherwise that some layers may be disposed between the former and latter layers. In addition, in the scale of the drawings, the thickness or size of the layers may be exaggeratedly illustrated for convenience and clearness of explanation of the present invention. The same reference numerals on the drawings indicate the same components. [0015]
  • FIGS. [0016] 1 to 6 are cross-sectional views for explaining a method for forming a metal line of a semiconductor in accordance with a preferred embodiment of the present invention.
  • Referring to FIG. 1, a [0017] semiconductor substrate 100 where a semiconductor device (not shown) such as a transistor is formed is prepared. A lower line 102 is formed on the semiconductor substrate 100. The lower line 102 is formed with a conductive film such as a Cu film, an Al film, a W film, and so on. Subsequently, a first interlayer insulating film 104 is formed on the lower line 102. The first interlayer insulating film 104 is formed with such as an spin on glass (SOG) film, a tetra ethyl ortho silicate (TEOS) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a phosphorus silicate glass (PSG) film, a boro phosphorus silicate glass (BPSG) film, and so on. The first interlayer insulating film 104 is formed to have a thickness of 3,000 Å to 10,000 Å by a deposition process in accordance with a design rule.
  • A first photosensitive film pattern (not shown) for defining a via hole which opens the [0018] lower line 102 is formed on the first interlayer insulating film 104. The first interlayer insulating film 104 is subjected to an etching process by using the first photosensitive film pattern as a mask to form the via hole. The etching process for forming the via hole utilizes a mixed gas of C4F8 gas or C5F8 gas, with O2 gas, N2 gas, and Ar gas. More specifically, the etching process is carried out by injecting a mixed gas of C4F8 gas or C5F8 gas in the range of 3 sccm to 200 sccm, O2 gas in the range of 5 sccm to 500 sccm, N2 gas in the range of 10 sccm to 2000 sccm, and Ar gas in the range of 100 sccm to 3000 sccm under conditions of a pressure in the range of 10 mT to 400 mT, a source power in the range of 100 W to 3000 W, and a bias power in the range of 500 W to 1800 W.
  • The via hole is buried with a conductive material to form a [0019] via plug 106. The via plug 106 is formed with a Cu film, a Pt film, an Ag film, an Al film, or a W film.
  • Referring to FIG. 2, a second [0020] interlayer insulating film 108 is formed on the via plug 106 and the first interlayer insulating film 104. The second interlayer insulating film 108 is formed by using a low dielectric oxide film. For example, the interlayer second insulating film 108 is formed by using an spin on glass (SOG) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a carbon doped dielectric (COD) film or a porous low dielectric oxide film. The second interlayer insulating film 108 is deposited to have a thickness in the range of 0.5 μm to an order of 10 μm in order to satisfy a desired quality factor (Q).
  • Subsequently, a second photosensitive film pattern (not shown) for defining a [0021] trench 109 is formed on the semiconductor substrate 100. The second interlayer insulating film 108 is subjected to an etching process by using the second photosensitive film pattern as a mask to form the trench 109 for exposing the via plug 106. More specifically, plasma that is made by activating C4F8 gas, O2 gas, N2 gas, or Ar gas, for example, is used for etching the second interlayer insulating film 108 to form the trench 109. On the other hand, in accordance with the etching selective ratio, an etching protection film is formed at the lower portion of the second interlayer insulating film 108 to be used as an etching stopper layer at the time of the trench formation.
  • Referring to FIG. 3, a spacer insulating film is deposited along the step difference on the product where the [0022] trench 109 is formed, and subsequently, an anisotropic-dry-etching process is carried out to form a spacer 110. The spacer insulating film is formed by using an Si3N4 film or an SiC film which has a mechanical strength stronger than that of the second interlayer insulation film 108 and can be used as a metal diffusion barrier film. Since the second interlayer insulating film 108 having a low dielectric constant is vulnerable to a mechanical stress generated in a chemical mechanical polishing (CMP) process, or the like, the spacer is formed on the side wall of the trench formed in the second interlayer insulating film 108 in order to compensate for its vulnerability. It is preferable that the spacer insulating film is deposited by using a plasma-enhanced chemical vapor deposition (PE-CVD) method at a temperature in the range of 200° C. to 450° C. under a pressure in the range of 0.01 torr to 500 torr. The spacer insulating film is deposited to have a thickness in the range of 50 Å to 1500 Å. The anisotropic-drying-etching process is carried out by using a reactive ion etching method.
  • Referring to FIG. 4, a [0023] diffusion barrier film 112 is deposited along the step difference on the product where the spacer 110 is formed. The diffusing barrier film 112 is deposited to have a thickness of 100 Å to 1500 Å. The diffusing barrier film 112 may be formed by using a Ta film, a Ti film, a TaN film, a TiN film, or the like, which has a good adhesive property to the second interlayer insulating film 108 and a metal line which is to be formed during the subsequent process and is capable of preventing metals from being diffused.
  • A [0024] copper seed layer 114 is formed on the diffusion barrier film 112. The copper seed layer 114 is formed to have a thickness in the range of 500 Å to 2000 Å.
  • Referring to FIG. 5, a [0025] copper film 116 is buried in the trench by using an electroplating method on the copper seed layer 114. The copper film 116 is formed to have a thickness greater than that of the second interlayer insulating film 108, so that it may have a thickness of, 0.5 μm to an order of 10 μm, for example. Next, an annealing process is carried out to densify the copper film 116.
  • A chemical mechanical polishing process is carried out to remove the [0026] copper film 116, the copper seed layer 114, and the diffusion barrier film 112 above the second interlayer insulating film 108. By such a chemical mechanical polishing process, a planarized upper line is formed.
  • Referring to FIG. 6, a [0027] first passivation film 118 is formed on the product where the upper line is formed. The first passivation film 118 is formed by using an Si3N4 film or an SiC film to have a thickness in the range of 500 Å to 1500 Å. Next, a second passivation film 120 is formed on the first passivation film 118. The second passivation film 120 is formed by using a TEOS film to have a thickness in the range of 1,000 Å to 10,000 Å for wire bonding. If bonding method is chanced, the passivation thickness and structure can be changed.
  • The first and [0028] second passivation films 118 and 120 are patterned to form an opening portion (not shown) for forming a pad. A diffusion barrier film is deposited along the step difference on the product where the opening portion for forming the pad is formed. The diffusion barrier film is formed to have a thickness in the range of 100 Å to 1000 Å. The diffusing barrier film may be formed by using a Ta film, a Ti film, a TaN film, a TiN film, or the like, which has a good adhesive property to the metal line and is capable of preventing metals which is to be formed as the pad from being diffused.
  • A conductive film is deposited on the diffusion barrier film and a pattering is carried out to form the pad (not shown). The pad may be formed by using a metal film such as an Al film and so on. [0029]
  • According to the method of forming the metal line of the semiconductor of the present invention, the CMP process is carried out with using a substance having a strong mechanical strength such as Si[0030] 3N4 film, or the like, as the spacer for the interlayer insulating film to compensate for the weak mechanical strength of the low dielectric oxide film, so that it is possible to minimize of occurrence of breakage of the interlayer insulating film and erosion of the oxide film which occurs due to the CMP process. In addition, the diffusion of Cu atoms in the subsequent thermal annealing process is suppressed by using the spacer insulating film, so that it is possible to improve the reliability of the line of the semiconductor devices.
  • Furthermore, according to the present invention, the dishing in the metal line can be minimized, so that it is possible to obtain the high value of the quality factor (Q) and to minimize of physical failures of the metal line. [0031]
  • Moreover, the spacer oxide film on the side wall of the trench can improve the layer covering property of the Cu diffusion barrier film in the Cu line, so that it is possible to improve the properties of the diffusion barrier film. [0032]
  • Although the foregoing description has made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims. [0033]

Claims (8)

What is claimed is:
1. A method for forming a metal line of a semiconductor device comprising the steps of:
forming a via plug on a semiconductor substrate;
forming an interlayer insulating film on the semiconductor substrate, on which the via plug is formed;
forming a trench by patterning the interlayer insulating film in order to form an upper line to be connected to the via plug;
depositing a spacer insulating film, which is more invulnerable to a mechanical stress than the interlayer insulating film, on the semiconductor substrate on which the trench is formed;
forming a spacer on a side wall of the trench by performing an anisotropic-dry-etching of the spacer insulating film; and
forming a metal line by burying the trench with a conductive material.
2. The method of claim 1, wherein the spacer insulating film is formed by using an Si3N4 film or an SiC film which has a mechanical strength stronger than that of the interlayer insulation film and can be used as a metal diffusion barrier film.
3. The method of claim 2, wherein the spacer insulating film is deposited by using a plasma-enhanced chemical vapor deposition (PE-CVD) method at a temperature in the range of 200° C. to 450° C. under a pressure in the range of 0.01 torr to 500 torr.
4. The method of claim 1, wherein the spacer insulating film is deposited to have a thickness in the range of 50 Å to 1500 Å.
5. The method of claim 1, wherein the anisotropic-drying-etching is a reactive ion etching.
6. The method of claim 1, wherein the interlayer insulating film is an oxide film having a lower dielectric constant and formed by using an spin on glass (SOG) film, an fluorine doped tetra ethyl ortho silicate (F-TEOS) film, a carbon doped dielectric (COD) film or a porous low dielectric oxide film.
7. The method of claim 1, wherein the step of forming the via plug comprises the steps of:
forming a lower line on the semiconductor substrate;
forming a second interlayer insulating film on the semiconductor substrate, on which the lower line is formed;
forming a via hole by patterning the second interlayer insulating film in order to connect the lower line with the upper line; and
forming a via plug by burying the via hole with a conductive metal.
8. The method of claim 1, wherein the step of forming the metal line comprises the steps of:
depositing a diffusion barrier film along a step difference of the semiconductor substrate on which the spacer is formed;
depositing a copper seed layer on the diffusion barrier film;
forming a copper film on the copper seed layer by using an electroplating method, thereby burying an opening portion; and
forming the metal line by planarizing the copper film.
US10/720,976 2003-02-05 2003-11-24 Method for forming metal line of semiconductor device Abandoned US20040152294A1 (en)

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CN107026134A (en) * 2015-12-21 2017-08-08 台湾积体电路制造股份有限公司 Semiconductor structure and its manufacture method
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