US20040140481A1 - Optimized blocking impurity placement for SiGe HBTs - Google Patents

Optimized blocking impurity placement for SiGe HBTs Download PDF

Info

Publication number
US20040140481A1
US20040140481A1 US10/753,001 US75300104A US2004140481A1 US 20040140481 A1 US20040140481 A1 US 20040140481A1 US 75300104 A US75300104 A US 75300104A US 2004140481 A1 US2004140481 A1 US 2004140481A1
Authority
US
United States
Prior art keywords
concentration
approximately
peak
diffusion
base region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/753,001
Inventor
Basanth Jagannathan
Alvin Joseph
Xuefeng Liu
Kathryn Schonenberg
Ryan Wuthrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/753,001 priority Critical patent/US20040140481A1/en
Publication of US20040140481A1 publication Critical patent/US20040140481A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • H01L29/7378Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Definitions

  • the invention relates to silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs).
  • HBTs It is generally known to form HBTs by using wafers that include one or more layers of silicon germanium (SiGe) on a silicon substrate.
  • SiGe silicon germanium
  • the germanium atoms create mechanical strain in the composite film due to the difference in lattice constant between the SiGe film and the silicon substrate.
  • the larger lattice constant of the SiGe lattice is compressed onto the smaller lattice constant of the silicon substrate.
  • the SiGe layer lattice constant is greater than that of the silicon substrate and thus is under tensile stress. This strain together with the Ge atom itself, creates a bandgap offset between the SiGe film and the underlaying native Si substrate.
  • This bandgap offset provides the unique advantages of the SiGe HBT by creating a grading field in the base to enhance carrier diffusion across the base and thus improve transistor speed.
  • SiGe HBTs have been used as transistors for small signal amplifiers (i.e. switching approximately 5 volts or less) to provide the switching speeds necessary for current wireless communications devices.
  • SiGe enhances charge mobility by introducing mechanical strain due to the lattice mismatches inherent in the Si—Ge compound; if there is too much Ge, or if the SiGe layer is too thick, the accepted wisdom in the art is that the resulting crystal dislocations will reduce both performance and yield.
  • the performance penalty would be due to dislocations relieving the mechanical stresses that create the bandgap offsets that SiGe provides.
  • the yield penalty would be due to the defects disturbing the crystallography of the substrate.
  • a high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness, wherein said base region includes diffusion-limiting impurities throughout said thickness at a concentration below that of boron in said base region, and wherein said diffusion limiting impurities are physically located relative to both said base region and a portion of said SiGe layer having a relatively high concentration of Ge to optimize performance and yield of said SiGe HBT
  • Another aspect of the invention is a high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20%, a boron-doped base region formed therein having a thickness, and a region of diffusion-limiting impurities at a concentration, thickness, and spacing relative to said base region and a portion of said SiGe layer having a peak concentration of Ge that optimizes both performance and yield of said SiGe HBT.
  • a further aspect of the invention is a method for forming a high performance SiGe layer on a Si substrate, comprising the steps of introducing germanium atoms during formation of a Si layer; introducing diffusion-limiting impurities and boron atoms during formation of said Si layer, while said germanium atoms are still being introduced; and terminating both said diffusion-limiting impurities and said boron atoms approximately simultaneously, said diffusion limiting impurities being introduced at a concentration and for a duration that optimizes both performance and yield.
  • FIG. 1 is a plot of concentration versus thickness of a SiGe HBT during the deposition process.
  • FIG. 2 is a plot of performance versus yield as a function of peak boron diffusion limiting implant versus peak Ge concentration.
  • the inventors have found that when the boron diffusion limiting impurity (preferably carbon, but other atoms described elsewhere that provide similar properties could be used) is optimized such that it has a particular peak concentration location relative to the peak Ge concentration, both performance and yield are optimized.
  • the boron diffusion limiting impurity preferably carbon, but other atoms described elsewhere that provide similar properties could be used
  • FIG. 1 is a schematic show of LTE growth profile in accordance with a preferred embodiment of the invention.
  • the Ge concentration is between approximately 20% to 30% and the total SiGe layer is on the order of 900-300 angstroms (A) in thickness.
  • the Ge has a peak (or plateau) thickness of approximately 100-20 angstroms, respectively, such that the total SiGe layer is within the SiGe stability limit.
  • peak thickness or “plateau” or “peak concentration thickness” refer to the thickness of that portion of the SiGe layer that has the highest concentration of Ge.
  • the base region is approximately 10-150 A in thickness, and features a peak boron concentration B on the order of 5-9 ⁇ 10 E 19/cm3.
  • the carbon C has a peak concentration of 1-4 ⁇ 10 E 19/cm3, and the carbon-doped region has a thickness of approximately 10-500 A in thickness.
  • FIG. 1 is best understood as being read left-to right, because that indicates the sequence of impurity introduction.
  • the carbon is first introduced as of when the Ge reaches it peak concentration, and is terminated when the boron is no longer incorporated into the film. As such, carbon is incorporated at its peak concentration throughout the thickness of the base region.
  • the optimal concentration profiles and placement are achieved by switching on the Ethylene gas at or about when the peak Germane gas flow rate becomes constant during the low temperature epitaxial (LTE) growth of the SiGe layer on a Si substrate.
  • the carbon doped SiGe layer is formed by turning on the Germane flow with a ratio of 1.6 relative to silane, and then ethylene is turned on at a flow ratio of 2.4 relative to silane.
  • Alternate carbon sources could be methylsilane, methane, and other embodiments of C.
  • the Ethylene gas is turned on at a rate of 40 SCCM.
  • Base Thickness 75A Boron peak concentration: 8.5 ⁇ 10 E 19/cm 3
  • Thickness of Ge peak concentration plateau 50
  • AThickness of C layer 170
  • Resulting Ft 120
  • GhzResulting Fmax 100 GHz
  • Molecular beam epitaxy MBE or ultra high vacuum chemical vapor deposition (UHVCVD) that may alter the particular deposition parameters utilized.
  • MBE Molecular beam epitaxy
  • UHVCVD ultra high vacuum chemical vapor deposition
  • SiGe layer is described as having a “plateau” of peak Ge concentration, in practice that “plateau” could range from narrow (an SiGe layer where the peak content is a “point”, not a “plateau”) to quite wide (up to and including a SiGe layer where the Ge concentration is uniform throughout the SiGe layer), depending upon the exact performance attributes desired in the particular SiGe application of interest.

Abstract

A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

Description

    BACKGROUND OF THE INVENTION TECHNICAL FIELD
  • The invention relates to silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). [0001]
  • It is generally known to form HBTs by using wafers that include one or more layers of silicon germanium (SiGe) on a silicon substrate. On such substrates, the germanium atoms create mechanical strain in the composite film due to the difference in lattice constant between the SiGe film and the silicon substrate. In the plane of the silicon substrate the larger lattice constant of the SiGe lattice is compressed onto the smaller lattice constant of the silicon substrate. In the plane perpendicular to the the silicon substrate, the SiGe layer lattice constant is greater than that of the silicon substrate and thus is under tensile stress. This strain together with the Ge atom itself, creates a bandgap offset between the SiGe film and the underlaying native Si substrate. This bandgap offset provides the unique advantages of the SiGe HBT by creating a grading field in the base to enhance carrier diffusion across the base and thus improve transistor speed. SiGe HBTs have been used as transistors for small signal amplifiers (i.e. switching approximately 5 volts or less) to provide the switching speeds necessary for current wireless communications devices. [0002]
  • SiGe enhances charge mobility by introducing mechanical strain due to the lattice mismatches inherent in the Si—Ge compound; if there is too much Ge, or if the SiGe layer is too thick, the accepted wisdom in the art is that the resulting crystal dislocations will reduce both performance and yield. The performance penalty would be due to dislocations relieving the mechanical stresses that create the bandgap offsets that SiGe provides. The yield penalty would be due to the defects disturbing the crystallography of the substrate. In fact, this general understanding has become so widespread that it is generally acknowledged as the “Matthews-Blakesley stability criterion” or the “Stiffler limit,” in recognition of the researchers who first reported these interrelationships (Stiffler et al., Journal of Applied Physics, Vol. 71, No.10, pp. 4820-4825 (1994); Matthews and Blakeslee, “Defects in Epitaxial Multilayers,” Journal of Crystal Growth 27 pp.118-125 (1974)). For ease of future reference, these results will be referred to as the “SiGe stability limits.”[0003]
  • The introduction of carbon (C) or other intert impurty atoms into the SiGebase region via low temperature epitaxy (LTE) growth is an effective way to restrict base boron (B) outdiffusion. Typically, both boron and carbon are introduced into the ambient during the LTE process, at different times and at different concentrations. See for example “Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation,” Lanzerotti, L. D.; Sturm, J. C.; Stach, E.; Hull, R.; Buyuklimanli, T.; Magee, C. This paper appears in: Electron Devices Meeting 1996, International, page(s): 249-252, 8-11 Dec. 1996. [0004]
  • In order to enhance the performance of the SiGe HBT, it is preferred to increase the concentration of Ge to above 20% or so. This increases the mobility advantages of SiGe substrates, and is required for applications with an Ft greater than approximately 100 Ghz. However, the inventors found that HBTs built with this high Ge concentration in the presence of a boron-diffusion-limiting impurity (eg. Carbon) suffered from yield issues. Thus, a need has developed in the art for a high performance SiGe HBT with a boron-doped base region and a boron-diffusion-limiting impurity region which avoids yield deterrents. [0005]
  • Brief Summary of the Invention [0006]
  • It is thus an object of the present invention to provide a high performance SiGe HBT with a boron-doped base region and a boron-diffusion-limiting impurity region. [0007]
  • It is another object of the invention to provide a high performance SiGe HBT that does not suffer from performance or yield problems. [0008]
  • The foregoing and other objects of the invention are realized, in a first aspect, by a high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness, wherein said base region includes diffusion-limiting impurities throughout said thickness at a concentration below that of boron in said base region, and wherein said diffusion limiting impurities are physically located relative to both said base region and a portion of said SiGe layer having a relatively high concentration of Ge to optimize performance and yield of said SiGe HBT [0009]
  • Another aspect of the invention is a high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20%, a boron-doped base region formed therein having a thickness, and a region of diffusion-limiting impurities at a concentration, thickness, and spacing relative to said base region and a portion of said SiGe layer having a peak concentration of Ge that optimizes both performance and yield of said SiGe HBT. [0010]
  • A further aspect of the invention is a method for forming a high performance SiGe layer on a Si substrate, comprising the steps of introducing germanium atoms during formation of a Si layer; introducing diffusion-limiting impurities and boron atoms during formation of said Si layer, while said germanium atoms are still being introduced; and terminating both said diffusion-limiting impurities and said boron atoms approximately simultaneously, said diffusion limiting impurities being introduced at a concentration and for a duration that optimizes both performance and yield. Brief Description of the Several Views of the Drawings [0011]
  • The foregoing and other features of the invention will become more apparent upon review of the detailed description of the invention as rendered below. In the description to follow, reference will be made to the several figures of the accompanying Drawing, in which: [0012]
  • FIG. 1 is a plot of concentration versus thickness of a SiGe HBT during the deposition process; and [0013]
  • FIG. 2 is a plot of performance versus yield as a function of peak boron diffusion limiting implant versus peak Ge concentration.[0014]
  • DETAILED DESCRIPTION OF THE INVENTION
  • The inventors have found that when the boron diffusion limiting impurity (preferably carbon, but other atoms described elsewhere that provide similar properties could be used) is optimized such that it has a particular peak concentration location relative to the peak Ge concentration, both performance and yield are optimized. [0015]
  • FIG. 1 is a schematic show of LTE growth profile in accordance with a preferred embodiment of the invention. [0016]
  • At a Ge dose of approximately 4×10 E 16/cm3, the Ge concentration is between approximately 20% to 30% and the total SiGe layer is on the order of 900-300 angstroms (A) in thickness. The Ge has a peak (or plateau) thickness of approximately 100-20 angstroms, respectively, such that the total SiGe layer is within the SiGe stability limit. The phrases “peak thickness” or “plateau” or “peak concentration thickness” refer to the thickness of that portion of the SiGe layer that has the highest concentration of Ge. The base region is approximately 10-150 A in thickness, and features a peak boron concentration B on the order of 5-9×10 E 19/cm3. The carbon C has a peak concentration of 1-4×10 E 19/cm3, and the carbon-doped region has a thickness of approximately 10-500 A in thickness. [0017]
  • Note that FIG. 1 is best understood as being read left-to right, because that indicates the sequence of impurity introduction. As such, note that the carbon is first introduced as of when the Ge reaches it peak concentration, and is terminated when the boron is no longer incorporated into the film. As such, carbon is incorporated at its peak concentration throughout the thickness of the base region. [0018]
  • The inventors ran a variety of experiments in order to understand the interplay between carbon placement relative to boron placement relative to peak Ge placement. As shown in FIG. 2, it appears that optimized performance results when the boron diffusion-limiting atoms are introduced within approximately 100-150 angstroms of the peak concentration plateau of Ge. As shown, if such atoms are introduced too early, yield degrades significantly. As a practical matter, this yield loss is due to excess carbon atoms that produce a bumpy surface on top of the SiGe film. Yield also decreased if if the C concentration was too high (above approximately 4×10 E 19/cm3). On the other hand, if the atoms were introduced too late, performance degraded due to extended boron diffusion, due to a combination of the peak carbon content not extending enough into the base region and insufficient carbon (below approximately 1×10 E 19/cm[0019] 3) being incorporated into the base region. Moreover, while not explicitly shown in FIG. 2, note also that the boron region is within approximately 200-250 A of the peak Ge content. The inventors believe this also plays a role in enhancing performance properties of the HBT.
  • In practice, the optimal concentration profiles and placement are achieved by switching on the Ethylene gas at or about when the peak Germane gas flow rate becomes constant during the low temperature epitaxial (LTE) growth of the SiGe layer on a Si substrate. Specifically, the carbon doped SiGe layer is formed by turning on the Germane flow with a ratio of 1.6 relative to silane, and then ethylene is turned on at a flow ratio of 2.4 relative to silane. Alternate carbon sources could be methylsilane, methane, and other embodiments of C. Specifically, once the Germane gas flow rate ramped up to 28 SCCM, the Ethylene gas is turned on at a rate of 40 SCCM. [0020]
  • An example of the preferred embodiment of the invention is set forth below: [0021]
  • Example 1
  • Base Thickness: 75A Boron peak concentration: 8.5×10 E 19/cm[0022] 3 Thickness of Ge peak concentration plateau: 50 AThickness of C layer: 170 A Ge concentration: 25% C peak concentration 1.5×10 E 19/cm3 Resulting Ft: 120 GhzResulting Fmax: 100 GHz
  • While the invention has been described above with reference to the preferred embodiments thereof, it is to be understood that the spirit and scope of the invention is not limited thereby. Rather, various modifications may be made to the invention as described above without departing from the overall scope of the invention as described above and as set forth in the several claims appended hereto. For example, while in the examples set forth above the Ge concentration that ramps up at a given rate, plateaus for a given thickness, then ramps down at the same rate, such ramp rates and plateau thickness can vary. While the examples above are rendered in the environment of LTE growth of the SiGe layer, other growth environments could be used (e.g. Molecular beam epitaxy (MBE) or ultra high vacuum chemical vapor deposition (UHVCVD)) that may alter the particular deposition parameters utilized. While the SiGe layer is described as having a “plateau” of peak Ge concentration, in practice that “plateau” could range from narrow (an SiGe layer where the peak content is a “point”, not a “plateau”) to quite wide (up to and including a SiGe layer where the Ge concentration is uniform throughout the SiGe layer), depending upon the exact performance attributes desired in the particular SiGe application of interest. [0023]

Claims (20)

What is claimed is:
1. A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness, wherein said base region includes diffusion-limiting impurities throughout said thickness at a concentration below that of boron in said base region, and wherein said diffusion limiting impurities are physically located relative to both said base region and a portion of said SiGe layer having a Ge concentration of 20% to optimize performance and yield of said SiGe HBT.
2. A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20%, a boron-doped base region formed therein having a thickness, and a region of diffusion-limiting impurities at a concentration, thickness, and spacing relative to said base region and a portion of said SiGe layer having said peak concentration of Ge that optimizes both performance and yield of said SiGe HBT.
3. A method of producing a SiGe layer on a Si substrate, comprising the steps of:
introducing germanium atoms during formation of a Si layer, such that at least a portion of said SiGe layer has a peak Ge concentration of at least 20%;
introducing diffusion-limiting impurities and boron atoms during formation of said Si layer, while said germanium atoms are still being introduced; and
terminating both said diffusion-limiting impurities and said boron atoms approximately simultaneously, said diffusion limiting impurities being introduced at a concentration and for a duration that optimizes both performance and yield.
4. The device of claim 1, wherein said SiGe layer is of a thickness of approximately 300-900 A.
5. The device of claim 1, wherein the Ge has a peak concentration thickness of approximately 20-100 angstroms.
6. The device of claim 5, wherein said base region is approximately 10-150 angstroms in thickness.
7. The device of claim 6, wherein the base region has a peak boron concentration of boron of approximately 8.5×10 E 19/cm3.
8. The device of claim 1, wherein said diffusion limiting impurity comprises carbon.
9. The device of claim 8, wherein said carbon has a peak concentration between approximately 1×10 e 19/cm3 and 4×0 e 19/cm3.
10. The device of claim 8, wherein said carbon defines a dopant region that is approximately 10-500 angstroms in thickness.
11. The device of claim 8, wherein said carbon has defines a dopant region having an upper bound and a lower bound, wherein said peak concentration thickness of said Ge has an upper bound and a lower bound, and wherein said lower bound of said carbon region is within approximately 150 angstroms of said upper bound of said peak concentration thickness of said Ge.
12. The device of claim 10, wherein said base region is within approximately 200-250 angstroms of said upper bound of said peak concentration thickness of said Ge.
13. The method of claim 3, wherein said diffusion-limiting impurities comprise carbon, and wherein said carbon is first introduced when said Ge reaches a plateau concentration.
14. The method of claim 11, wherein said diffusion-limiting impurities come from a gaseous source.
15. The method of claim 12, wherein said gaseous source comprises ethylene.
16. The method of claim 13, wherein when said germanium atoms are introduced at a peak flow rate of Germane at 28 SCCM, said ethylene is provided at a rate of 40 SCCM.
17. A SiGe HBT comprising an SiGe layer, a base region, and a diffusion-limiting region, in which said diffusion-limiting region extends substantially throughout said base region and has a dopant concentration less than that of said base region, and wherein both said base region and said diffusion-limiting region are spaced within a given distance of a portion of said SiGe layer having a Ge concentration of at least approximately 20% so as to optimize both performance and yield of said SiGe HBT.
18. The device of claim 16, wherein said base region is within approximately 250 A of said portion of said SiGe layer having a peak Ge concentration.
19. The device of claim 17, wherein said diffusion-limiting region is within approximately 150A of said portion of said SiGe layer having a peak Ge concentration.
20. The device of claim 17, wherein said base region is within approximately 250 A of said portion of said SiGe layer having a peak Ge concentration, and wherein said diffusion-limiting region is within approximately 150A of said portion of said SiGe layer having a peak Ge concentration.
US10/753,001 2002-03-08 2004-01-07 Optimized blocking impurity placement for SiGe HBTs Abandoned US20040140481A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/753,001 US20040140481A1 (en) 2002-03-08 2004-01-07 Optimized blocking impurity placement for SiGe HBTs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/683,983 US6744079B2 (en) 2002-03-08 2002-03-08 Optimized blocking impurity placement for SiGe HBTs
US10/753,001 US20040140481A1 (en) 2002-03-08 2004-01-07 Optimized blocking impurity placement for SiGe HBTs

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/683,983 Division US6744079B2 (en) 1999-11-01 2002-03-08 Optimized blocking impurity placement for SiGe HBTs

Publications (1)

Publication Number Publication Date
US20040140481A1 true US20040140481A1 (en) 2004-07-22

Family

ID=29550431

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/683,983 Expired - Lifetime US6744079B2 (en) 1999-11-01 2002-03-08 Optimized blocking impurity placement for SiGe HBTs
US10/753,001 Abandoned US20040140481A1 (en) 2002-03-08 2004-01-07 Optimized blocking impurity placement for SiGe HBTs

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/683,983 Expired - Lifetime US6744079B2 (en) 1999-11-01 2002-03-08 Optimized blocking impurity placement for SiGe HBTs

Country Status (1)

Country Link
US (2) US6744079B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145992A1 (en) * 2003-09-09 2005-07-07 Dureseti Chidambarrao Method for reduced N+ diffusion in strained Si on SiGe substrate

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7172949B2 (en) * 2004-08-09 2007-02-06 Micron Technology, Inc. Epitaxial semiconductor layer and method
US20070054460A1 (en) * 2005-06-23 2007-03-08 Atmel Corporation System and method for providing a nanoscale, highly selective, and thermally resilient silicon, germanium, or silicon-germanium etch-stop
US20080050883A1 (en) * 2006-08-25 2008-02-28 Atmel Corporation Hetrojunction bipolar transistor (hbt) with periodic multilayer base
US20060292809A1 (en) * 2005-06-23 2006-12-28 Enicks Darwin G Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection
US20070102834A1 (en) * 2005-11-07 2007-05-10 Enicks Darwin G Strain-compensated metastable compound base heterojunction bipolar transistor
US8530934B2 (en) 2005-11-07 2013-09-10 Atmel Corporation Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto
US20070148890A1 (en) * 2005-12-27 2007-06-28 Enicks Darwin G Oxygen enhanced metastable silicon germanium film layer
JP2007250903A (en) * 2006-03-16 2007-09-27 Matsushita Electric Ind Co Ltd Heterojunction bipolar transistor and manufacturing method therefor
US20070262295A1 (en) * 2006-05-11 2007-11-15 Atmel Corporation A method for manipulation of oxygen within semiconductor materials
US7569913B2 (en) * 2006-10-26 2009-08-04 Atmel Corporation Boron etch-stop layer and methods related thereto
US7495250B2 (en) * 2006-10-26 2009-02-24 Atmel Corporation Integrated circuit structures having a boron- and carbon-doped etch-stop and methods, devices and systems related thereto
US7550758B2 (en) 2006-10-31 2009-06-23 Atmel Corporation Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306661A (en) * 1992-06-12 1994-04-26 The United States Of America As Represented By The Secretary Of The Navy Method of making a semiconductor device using a nanochannel glass matrix
US5581091A (en) * 1994-12-01 1996-12-03 Moskovits; Martin Nanoelectric devices
US5880525A (en) * 1995-01-27 1999-03-09 The Whitaker Corporation Anodic aluminum oxide passive alignment structures
US6034468A (en) * 1994-08-18 2000-03-07 Isis Innovation Limited Field emitter device having porous dielectric anodic oxide layer
US6044981A (en) * 1994-03-07 2000-04-04 The Regents Of The University Of California Microfabricated filter with specially constructed channel walls, and containment well and capsule constructed with such filters
US6177291B1 (en) * 1993-11-02 2001-01-23 Matsushita Electric Industrial Co., Ltd. Method of making aggregate of semiconductor micro-needles
US6231744B1 (en) * 1997-04-24 2001-05-15 Massachusetts Institute Of Technology Process for fabricating an array of nanowires
US20020011617A1 (en) * 1996-09-17 2002-01-31 Minoru Kubo Semiconductor device and method of producing the same
US20030201461A1 (en) * 2002-04-30 2003-10-30 Fujitsu Limited Heterobipolar transistor and method of fabricating the same
US20030203599A1 (en) * 2000-03-27 2003-10-30 Matsushita Electric Industrial Co. , Ltd. Semiconductor wafer and method for fabricating the same
US6649496B2 (en) * 2000-03-23 2003-11-18 Matsushita Electric Industrial Co., Ltd. Production method for semiconductor crystal
US6667489B2 (en) * 2001-11-29 2003-12-23 Hitachi, Ltd. Heterojunction bipolar transistor and method for production thereof
US20040007185A1 (en) * 2002-02-06 2004-01-15 Hitachi Kokusai Electric Inc. Method of manufacturing a semiconductor device and a semiconductor manufacture system
US20040048439A1 (en) * 2002-08-21 2004-03-11 Ravindra Soman Method for fabricating a bipolar transistor base
US20040092085A1 (en) * 2001-01-31 2004-05-13 Yoshihiko Kanzawa Semiconductor crystal film and method for preparation thereof
US6750119B2 (en) * 2001-04-20 2004-06-15 International Business Machines Corporation Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
US20040126978A1 (en) * 2002-04-09 2004-07-01 Alexander Kalnitsky Self-aligned NPN transistor with raised extrinsic base
US20040198010A1 (en) * 2001-06-05 2004-10-07 Takeyoshi Koumoto Semiconductor layer and forming method thereof, and semiconductor device and manufaturing method thereof
US6906400B2 (en) * 2003-01-14 2005-06-14 Interuniversitair Microelektronica Centrum (Imec) SiGe strain relaxed buffer for high mobility devices and a method of fabricating it

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362065B1 (en) * 2001-02-26 2002-03-26 Texas Instruments Incorporated Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306661A (en) * 1992-06-12 1994-04-26 The United States Of America As Represented By The Secretary Of The Navy Method of making a semiconductor device using a nanochannel glass matrix
US6177291B1 (en) * 1993-11-02 2001-01-23 Matsushita Electric Industrial Co., Ltd. Method of making aggregate of semiconductor micro-needles
US6044981A (en) * 1994-03-07 2000-04-04 The Regents Of The University Of California Microfabricated filter with specially constructed channel walls, and containment well and capsule constructed with such filters
US6034468A (en) * 1994-08-18 2000-03-07 Isis Innovation Limited Field emitter device having porous dielectric anodic oxide layer
US5581091A (en) * 1994-12-01 1996-12-03 Moskovits; Martin Nanoelectric devices
US5880525A (en) * 1995-01-27 1999-03-09 The Whitaker Corporation Anodic aluminum oxide passive alignment structures
US20020011617A1 (en) * 1996-09-17 2002-01-31 Minoru Kubo Semiconductor device and method of producing the same
US6231744B1 (en) * 1997-04-24 2001-05-15 Massachusetts Institute Of Technology Process for fabricating an array of nanowires
US6359288B1 (en) * 1997-04-24 2002-03-19 Massachusetts Institute Of Technology Nanowire arrays
US6649496B2 (en) * 2000-03-23 2003-11-18 Matsushita Electric Industrial Co., Ltd. Production method for semiconductor crystal
US20030203599A1 (en) * 2000-03-27 2003-10-30 Matsushita Electric Industrial Co. , Ltd. Semiconductor wafer and method for fabricating the same
US20040092085A1 (en) * 2001-01-31 2004-05-13 Yoshihiko Kanzawa Semiconductor crystal film and method for preparation thereof
US6750119B2 (en) * 2001-04-20 2004-06-15 International Business Machines Corporation Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD
US20040198010A1 (en) * 2001-06-05 2004-10-07 Takeyoshi Koumoto Semiconductor layer and forming method thereof, and semiconductor device and manufaturing method thereof
US6667489B2 (en) * 2001-11-29 2003-12-23 Hitachi, Ltd. Heterojunction bipolar transistor and method for production thereof
US20040007185A1 (en) * 2002-02-06 2004-01-15 Hitachi Kokusai Electric Inc. Method of manufacturing a semiconductor device and a semiconductor manufacture system
US20040126978A1 (en) * 2002-04-09 2004-07-01 Alexander Kalnitsky Self-aligned NPN transistor with raised extrinsic base
US20030201461A1 (en) * 2002-04-30 2003-10-30 Fujitsu Limited Heterobipolar transistor and method of fabricating the same
US20040048439A1 (en) * 2002-08-21 2004-03-11 Ravindra Soman Method for fabricating a bipolar transistor base
US6906400B2 (en) * 2003-01-14 2005-06-14 Interuniversitair Microelektronica Centrum (Imec) SiGe strain relaxed buffer for high mobility devices and a method of fabricating it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145992A1 (en) * 2003-09-09 2005-07-07 Dureseti Chidambarrao Method for reduced N+ diffusion in strained Si on SiGe substrate
US7345329B2 (en) * 2003-09-09 2008-03-18 International Business Machines Corporation Method for reduced N+ diffusion in strained Si on SiGe substrate

Also Published As

Publication number Publication date
US6744079B2 (en) 2004-06-01
US20030170960A1 (en) 2003-09-11

Similar Documents

Publication Publication Date Title
US7173274B2 (en) Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology
JP4060580B2 (en) Heterojunction bipolar transistor
JP4117914B2 (en) Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby
US6906400B2 (en) SiGe strain relaxed buffer for high mobility devices and a method of fabricating it
US6744079B2 (en) Optimized blocking impurity placement for SiGe HBTs
US20030071277A1 (en) Silicon germanium hetero bipolar transistor having a germanium concentration profile in the base layer
US20030071278A1 (en) Silicon germanium hetero bipolar transistor
JP2005011915A (en) Semiconductor device, semiconductor circuit module and its manufacturing method
US6346452B1 (en) Method for controlling an N-type dopant concentration depth profile in bipolar transistor epitaxial layers
CN100345254C (en) Formation of high-mobility silicon-germanium structures by low-energy plasma enhanced chemical vapor deposition
CN101390216A (en) An oxygen enhanced metastable silicon germanium film layer
US20020038874A1 (en) Hetero-bipolar transistor and method of manufacture thereof
CN112750689A (en) Gallium nitride material with gallium polar surface and homoepitaxial growth method
US6013129A (en) Production of heavily-doped silicon
CN113913931A (en) Epitaxial structure with P-type buffer layer and preparation method thereof
JP2002241195A (en) Method for producing epitaxial multilayer film and epitaxial multilayer film
JP2007042936A (en) Group iii-v compound semiconductor epitaxial wafer
US6838359B2 (en) Suppression of n-type autodoping in low-temperature Si and SiGe epitaxy
CN112750691A (en) Nitrogen polar surface GaN material and homoepitaxial growth method
CN114709261A (en) Silicon-based high electron mobility transistor and preparation method thereof
Li et al. Effect of Carrier Gas on Silicon Doped GaN Epilayer Characteristics
WO2003092079A1 (en) Enhanced cutoff frequency silicon germanium transistor
JPH06236852A (en) Semiconductor device and manufacture thereof
JP2007258752A (en) Heterojunction bipolar transistor and manufacturing method thereof
JPH01217967A (en) Semiconductor device and its manufacture

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910