US20040113196A1 - Method and structure for an oxide layer overlying an oxidation-resistant layer - Google Patents
Method and structure for an oxide layer overlying an oxidation-resistant layer Download PDFInfo
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- US20040113196A1 US20040113196A1 US10/722,791 US72279103A US2004113196A1 US 20040113196 A1 US20040113196 A1 US 20040113196A1 US 72279103 A US72279103 A US 72279103A US 2004113196 A1 US2004113196 A1 US 2004113196A1
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000003647 oxidation Effects 0.000 title abstract description 15
- 238000007254 oxidation reaction Methods 0.000 title abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 55
- 238000007667 floating Methods 0.000 claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 115
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 230000015654 memory Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 230000001590 oxidative effect Effects 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910003915 SiCl2H2 Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000035876 healing Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Definitions
- the invention relates generally to the field of nonvolatile semiconductor memories, and more specifically to the field of floating gate programmable memories.
- Floating gate memory devices such as flash memories include an array of electrically programmable and electrically erasable memory cells.
- each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor, including a floating gate interposed between a control (input) gate and a channel.
- NMOS metal oxide semiconductor
- a layer of high-quality tunnel oxide used as gate oxide separates the transistor channel and the floating gate, and an oxide-nitride-oxide (ONO) dielectric stack separates the floating gate from the control gate.
- the ONO stack typically comprises a layer of silicon nitride (Si 3 N 4 ) interposed between an underlying layer and an overlying layer of silicon dioxide (SiO 2 ).
- the underlying layer of SiO 2 is typically grown on the first doped polycrystalline silicon (poly) layer.
- the nitride layer is deposited over the underlying oxide layer, and the overlying oxide layer can be either grown or deposited on the nitride layer.
- the ONO layer maximizes the capacitive coupling between the floating gate and the control gate and minimizes the leakage of current through the film.
- the bottom and top silicon dioxide layers in the ONO stack with current technology are typically about 40 ⁇ thick and the silicon nitride layer is typically about 100 ⁇ thick.
- This silicon dioxide layer passivates any pinhole defects in the nitride, which are common with nitride layers. Oxidizing the nitride layer to form the overlying silicon dioxide layer has improved pinhole passivation over deposited oxide layers. Further, the thickness of the top silicon dioxide layer is easier to control when grown rather than deposited.
- the Si—N bond is very stable and silicon nitride has a low availability of unreacted silicon, it is difficult and time consuming to oxidize nitride at lower temperatures.
- the nitride oxidation process is typically performed at relatively high temperatures for example at 950° C. or higher. If the oxidation temperature is lowered to 900° C. or below, it will require at least 120 minutes to form a 40 ⁇ film.
- Increased processing temperatures such as those for growing silicon dioxide on nitride, are known to cause various problems in the field of semiconductor device manufacturing, and failures related to flash memory devices in particular. For example, increased temperatures are known to stress the interfaces of previously grown films such as the tunnel oxide and field oxide. These films then become more prone to charge trapping, which degrades the operation of the device.
- the siliconized (silicon-rich) nitride layer enhances the formation of the second oxide layer and allows for its growth at lower temperatures than conventional processes. Growing the second oxide layer rather than depositing the second oxide layer provides improved healing of pinhole defects in the nitride layer. Growing the second oxide layer at lower temperatures than can be done with conventional processing reduces problems associated with a tunnel oxide layer of a flash memory device and reduces other temperature-induced failures.
- the instant embodiment of the invention relates to the formation of the ONO layer.
- the gate oxide 12 , floating gate poly layer 14 and first oxide layer 16 of an ONO stack are formed according to means known in the art.
- Poly layer 14 for example, is partially oxidized to form a first layer of silicon dioxide dielectric of from about 30 ⁇ thick to about 45 ⁇ thick over the floating gate poly layer 14 .
- a blanket silicon nitride layer 18 is deposited on the first silicon dioxide layer 16 .
- Silicon nitride layers are known in the art to resist oxidation, and thus high-temperature processing is conventionally required to oxidize the layer.
- at least an upper portion of the nitride is siliconized such that it comprises a concentration of silicon atoms greater than a lower portion of the nitride.
- a conventional first lower portion of the nitride layer can be formed in combination with a second upper portion which is silicon-rich. The lower portion resists oxidation so that the nitride layer is not over-oxidized and is self-limiting. This allows the desirable electrical properties of nitride to be maintained, while the upper portion is more readily oxidized due to the concentration of silicon atoms.
- the wafer substrate assembly having oxide layer 16 is placed in (or remains from the prior process in) a low pressure chemical vapor deposition (LPCVD) furnace at a temperature of between about 400° C. and about 800° C., for example about 720° C.
- LPCVD low pressure chemical vapor deposition
- Silane gas (SiH 4 ) or dichlorosilane gas (DCS, SiCl 2 H 2 ) and ammonia gas (NH 3 ) are introduced into the chamber.
- a DCS flow rate is between about 20 sccm and about 100 sccm, for example about 30 sccm, and the ammonia flow rate is between about 150 sccm and 300 sccm, for example about 180 sccm. If silane is used, the values listed herein for DCS can be modified by one of ordinary skill in the art for silane. After about 20 minutes the flow of the ammonia is reduced and/or the flow rate of the DCS is increased which results in the availability of more silicon atoms for incorporation into the nitride. The flow rate to which the ammonia gas is reduced or the rate at which the DCS is increased is a function of initial flow and the required oxidation properties of the siliconized nitride film.
- a reduced ammonia flow rate of between about 10 sccm and about 30 sccm and/or an increased DCS flow rate of between about 30 sccm and about 110 sccm would be sufficient.
- the chemical formula for the siliconized nitride layer will be Si x N 4 , where x>3.
- the change of the ammonia and/or DCS flow rates can be performed over an extended period of time to provide a gradated silicon concentration. A more rapid change, for example with an instant change over one second or less would provide a more abrupt silicon concentration change. For this process, a nitride layer 100 ⁇ would be formed.
- the structure having a siliconized nitride layer 18 is depicted in FIG. 1.
- the lower portion of the silicon nitride layer is predominantly Si 3 N 4 although other molecules may exist. Further, while the formula of the siliconized nitride is predominantly Si x N 4 where x>3 and is denoted as such herein, some Si 3 N 4 or other molecules may be incorporated into the film.
- the siliconized nitride is oxidized to form the upper oxide layer 20 in the ONO stack from about 10 ⁇ to about 40 ⁇ thick as depicted in FIG. 2.
- the wafer assembly substrate is placed into an oxidation furnace (atmospheric furnace).
- the nitride is subjected to a temperature of between about 750° C. and about 900° C. (for example 900° C.) for between about five minutes and about 90 minutes (for example 30 minutes) in a dry oxidizing atmosphere of oxygen or a wet oxidizing atmosphere of oxygen and hydrogen.
- H 2 and O 2 flow rates of between about 1.0 standard liters/min (SLM) to about 10 SLM would be sufficient.
- FIG. 3 depicts the patterned gate oxide 30 , floating gate 32 , lower oxide 34 of the ONO layer, nitride 36 of the ONO layer, upper oxide 38 of the ONO layer, control gate 40 , and an oxide layer 42 overlying the control gate 40 .
- Another embodiment of the invention includes forming the tunnel oxide 12 over a semiconductor wafer 10 , forming the floating gate poly layer 14 , and forming the first oxide layer 16 and a nitride layer 50 of the ONO stack as depicted in FIG. 4. These layers can be conventionally formed. Subsequently, a thin blanket layer of poly or amorphous silicon 52 is formed on the nitride layer. A poly or amorphous silicon layer can be deposited over the nitride in an LPCVD furnace at a temperature of between about 500° C. and about. 700° C., for example 620° C., typically using silane gas as a source. The process continues for between about 30 seconds to about 150 seconds to form a poly layer between about 5 ⁇ thick to about 25 ⁇ thick, for example about 20 ⁇ thick.
- the poly or amorphous silicon layer is formed over the nitride layer the poly is oxidized, for example in a diffusion furnace to form the top oxide layer 54 of the ONO stack as depicted in FIG. 5.
- the structure is elevated to a temperature of between about 750° C. and about 900° C., for example 900° C. in the presence of O 2 gas having a flow rate of between about 2.0 SLM and about 10.5 SLM, for example about 9 SLM for between about 5 minutes and 15 minutes.
- O 2 gas having a flow rate of between about 2.0 SLM and about 10.5 SLM, for example about 9 SLM for between about 5 minutes and 15 minutes.
- the layer is exposed to O 2 and H 2 gas.
- a poly layer having a thickness of between about 5 ⁇ and about 25 ⁇ thick results in a top oxide layer from about 10 ⁇ to about 60 ⁇ thick.
- the thin poly layer 52 overlying the nitride 50 in FIG. 4 is completely oxidized to form layer 54 of FIG. 5 so that subsequent processing steps are not adversely affected by any unoxidized poly. Wafer processing then continues according to means known in the art, for example to form the control gate poly layer 56 over the ONO stack 16 , 52 , 54 , masking 58 then etching layers 12 - 56 of FIG. 5 to pattern the floating gate, the control gate, and the ONO stack.
- An advantage of the silicon-rich nitride layer portion is that the growth of the second oxide layer over the nitride layer is self-limiting. As the silicon concentration decreases deeper into the nitride layer the oxidation rate decreases and oxide formation slows. Thus the thickness of the second oxide layer overlying the nitride may be more controllable than a deposited oxide layer or an oxide layer which is grown on a conventional nitride layer. Further, forming the ONO layer at decreased temperatures over conventional processes improves the charge trapping properties of the tunnel oxide. Similarly, forming a poly layer over a nitride layer then oxidizing the poly has similar advantages over conventional processes as the poly is more readily oxidized at lower temperatures than is nitride. Further, oxidizing a poly layer overlying the nitride is also somewhat limiting as the poly oxidizes at a much faster rate than the nitride.
Abstract
A method used during the formation of a semiconductor device such as a flash memory device comprises the steps of forming a floating gate layer over a semiconductor wafer substrate then forming a first oxide layer over the floating gate layer. An oxidation-resistant layer such as a nitride layer is formed over the first oxide layer wherein a first portion of the oxidation-resistant layer oxidizes more readily than a second portion of the oxidation-resistant layer. To accomplish this the first portion of the oxidation-resistant layer can be formed to have a higher silicon concentration than the second portion. The first portion of the oxidation-resistant layer is oxidized to form a second oxide layer and a control gate layer is formed over the second oxide layer. An in-process semiconductor device is also described.
Description
- This is a continuation of U.S. application Ser. No. 09/969,464 filed Oct. 1, 2001 and issued Nov. 25, 2003 as U.S. Pat. No. 6,653,683, which was a division of U.S. application Ser. No. 09/205,140 filed Dec. 2, 1998 and issued Oct. 2, 2001 as U.S. Pat. No. 6,298,092.
- The invention relates generally to the field of nonvolatile semiconductor memories, and more specifically to the field of floating gate programmable memories.
- Floating gate memory devices such as flash memories include an array of electrically programmable and electrically erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor, including a floating gate interposed between a control (input) gate and a channel. A layer of high-quality tunnel oxide used as gate oxide separates the transistor channel and the floating gate, and an oxide-nitride-oxide (ONO) dielectric stack separates the floating gate from the control gate. The ONO stack typically comprises a layer of silicon nitride (Si3N4) interposed between an underlying layer and an overlying layer of silicon dioxide (SiO2). The underlying layer of SiO2 is typically grown on the first doped polycrystalline silicon (poly) layer. The nitride layer is deposited over the underlying oxide layer, and the overlying oxide layer can be either grown or deposited on the nitride layer. The ONO layer maximizes the capacitive coupling between the floating gate and the control gate and minimizes the leakage of current through the film.
- In order to program a flash cell the drain region and the control gate are raised to predetermined potentials above a potential applied to the source region. For example 12 volts are applied to the control gate, 0.0 volts are applied to the source, and 6.0 volts are applied to the drain. These voltages produce “hot electrons” which are accelerated from the substrate across the gate oxide layer to the floating gate. To erase a flash cell a high positive potential, for example 12 volts, is applied to the source region, the control gate is grounded, and the drain is allowed to float. These voltages are applied for a timed period, and the longer the period the more the cell becomes erased. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate across the tunnel oxide to the source region, for example by Fowler-Nordheim tunneling.
- The bottom and top silicon dioxide layers in the ONO stack with current technology are typically about 40 Å thick and the silicon nitride layer is typically about 100 Å thick. This silicon dioxide layer passivates any pinhole defects in the nitride, which are common with nitride layers. Oxidizing the nitride layer to form the overlying silicon dioxide layer has improved pinhole passivation over deposited oxide layers. Further, the thickness of the top silicon dioxide layer is easier to control when grown rather than deposited. However, because the Si—N bond is very stable and silicon nitride has a low availability of unreacted silicon, it is difficult and time consuming to oxidize nitride at lower temperatures. Thus the nitride oxidation process is typically performed at relatively high temperatures for example at 950° C. or higher. If the oxidation temperature is lowered to 900° C. or below, it will require at least 120 minutes to form a 40 Å film.
- Increased processing temperatures, such as those for growing silicon dioxide on nitride, are known to cause various problems in the field of semiconductor device manufacturing, and failures related to flash memory devices in particular. For example, increased temperatures are known to stress the interfaces of previously grown films such as the tunnel oxide and field oxide. These films then become more prone to charge trapping, which degrades the operation of the device.
- A method for forming a semiconductor device, particularly a flash memory device, which allows for the improved formation of a silicon dioxide layer over a layer which resists oxide formation, such as a nitride layer in an ONO stack, would be desirable.
- The present invention provides a new method for forming an interlayer dielectric, for example an oxide-nitride-oxide (ONO) layer between a floating gate layer and a control gate layer, which allows for the growth of an oxide layer over a nitride layer at decreased temperatures compared with conventional processes. In accordance with one embodiment of the invention a first oxide layer is grown or deposited over a floating gate poly layer, then a nitride layer is formed over the first oxide layer. During the nitride formation, at least an upper portion of the nitride layer is siliconized. Finally, a second oxide layer is grown over the nitride layer. The siliconized (silicon-rich) nitride layer enhances the formation of the second oxide layer and allows for its growth at lower temperatures than conventional processes. Growing the second oxide layer rather than depositing the second oxide layer provides improved healing of pinhole defects in the nitride layer. Growing the second oxide layer at lower temperatures than can be done with conventional processing reduces problems associated with a tunnel oxide layer of a flash memory device and reduces other temperature-induced failures.
- In a second embodiment a pure silicon layer, such as a thin polycrystalline silicon layer is formed over a nitride layer in the ONO stack. The polycrystalline silicon layer is more easily oxidized than the nitride layer, thereby decreasing processing time.
- Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
- FIGS.1-3 are cross sections of a first embodiment of the invention using a concentration of oxidation-enhancing material such as silicon within a oxidation-resistant layer such as nitride; and
- FIGS.4-5 are cross sections of a second embodiment of the invention using a thin layer which is readily oxidized, such as polycrystalline silicon, over a nitride layer to form an oxide-nitride-oxide layer between a floating gate and a control gate.
- It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.
- FIG. 1 depicts a memory structure comprising a semiconductor wafer substrate assembly comprising a
semiconductor wafer 10, a gate oxide layer such as atunnel oxide layer 12, and a first polycrystalline silicon (poly) layer which forms, for example, a flashtransistor floating gate 14. FIG. 1 further comprises anoxide layer 16 and asilicon nitride layer 18 which form a portion of an oxide-nitride-oxide (ONO) layer. - The instant embodiment of the invention relates to the formation of the ONO layer. The
gate oxide 12, floatinggate poly layer 14 andfirst oxide layer 16 of an ONO stack are formed according to means known in the art.Poly layer 14, for example, is partially oxidized to form a first layer of silicon dioxide dielectric of from about 30 Å thick to about 45 Å thick over the floatinggate poly layer 14. - Next, a blanket
silicon nitride layer 18 is deposited on the firstsilicon dioxide layer 16. Silicon nitride layers are known in the art to resist oxidation, and thus high-temperature processing is conventionally required to oxidize the layer. To provide a nitride layer which is more readily oxidized at lower temperatures, at least an upper portion of the nitride is siliconized such that it comprises a concentration of silicon atoms greater than a lower portion of the nitride. Thus a conventional first lower portion of the nitride layer can be formed in combination with a second upper portion which is silicon-rich. The lower portion resists oxidation so that the nitride layer is not over-oxidized and is self-limiting. This allows the desirable electrical properties of nitride to be maintained, while the upper portion is more readily oxidized due to the concentration of silicon atoms. - To form the silicon nitride layer having a low concentration of silicon in a lower portion and a higher concentration of silicon in an upper portion, the wafer substrate assembly having
oxide layer 16 is placed in (or remains from the prior process in) a low pressure chemical vapor deposition (LPCVD) furnace at a temperature of between about 400° C. and about 800° C., for example about 720° C. Silane gas (SiH4) or dichlorosilane gas (DCS, SiCl2H2) and ammonia gas (NH3) are introduced into the chamber. A DCS flow rate is between about 20 sccm and about 100 sccm, for example about 30 sccm, and the ammonia flow rate is between about 150 sccm and 300 sccm, for example about 180 sccm. If silane is used, the values listed herein for DCS can be modified by one of ordinary skill in the art for silane. After about 20 minutes the flow of the ammonia is reduced and/or the flow rate of the DCS is increased which results in the availability of more silicon atoms for incorporation into the nitride. The flow rate to which the ammonia gas is reduced or the rate at which the DCS is increased is a function of initial flow and the required oxidation properties of the siliconized nitride film. Generally, a reduced ammonia flow rate of between about 10 sccm and about 30 sccm and/or an increased DCS flow rate of between about 30 sccm and about 110 sccm would be sufficient. The chemical formula for the siliconized nitride layer will be SixN4, where x>3. The change of the ammonia and/or DCS flow rates can be performed over an extended period of time to provide a gradated silicon concentration. A more rapid change, for example with an instant change over one second or less would provide a more abrupt silicon concentration change. For this process, a nitride layer 100 Å would be formed. The structure having asiliconized nitride layer 18 is depicted in FIG. 1. - It should be noted that the lower portion of the silicon nitride layer is predominantly Si3N4 although other molecules may exist. Further, while the formula of the siliconized nitride is predominantly SixN4 where x>3 and is denoted as such herein, some Si3N4 or other molecules may be incorporated into the film.
- Next, the siliconized nitride is oxidized to form the
upper oxide layer 20 in the ONO stack from about 10 Å to about 40 Å thick as depicted in FIG. 2. The wafer assembly substrate is placed into an oxidation furnace (atmospheric furnace). The nitride is subjected to a temperature of between about 750° C. and about 900° C. (for example 900° C.) for between about five minutes and about 90 minutes (for example 30 minutes) in a dry oxidizing atmosphere of oxygen or a wet oxidizing atmosphere of oxygen and hydrogen. For a wet oxidation, H2 and O2 flow rates of between about 1.0 standard liters/min (SLM) to about 10 SLM would be sufficient. The temperatures of this step are much less than the temperatures normally required to oxidize a nitride layer, which are typically in the range of from 950° C. to 1050° C. Wafer processing then continues according to means known in the art, for example to form the controlgate poly layer 22 over the ONO stack,additional oxide layers 24 over thecontrol gate poly 22 then masking 26 and etching the two layers of poly and the ONO stack to pattern the structure. FIG. 3 depicts the patternedgate oxide 30, floatinggate 32,lower oxide 34 of the ONO layer,nitride 36 of the ONO layer,upper oxide 38 of the ONO layer,control gate 40, and anoxide layer 42 overlying thecontrol gate 40. - Another embodiment of the invention includes forming the
tunnel oxide 12 over asemiconductor wafer 10, forming the floatinggate poly layer 14, and forming thefirst oxide layer 16 and anitride layer 50 of the ONO stack as depicted in FIG. 4. These layers can be conventionally formed. Subsequently, a thin blanket layer of poly oramorphous silicon 52 is formed on the nitride layer. A poly or amorphous silicon layer can be deposited over the nitride in an LPCVD furnace at a temperature of between about 500° C. and about. 700° C., for example 620° C., typically using silane gas as a source. The process continues for between about 30 seconds to about 150 seconds to form a poly layer between about 5 Å thick to about 25 Å thick, for example about 20 Å thick. - After the poly or amorphous silicon layer is formed over the nitride layer the poly is oxidized, for example in a diffusion furnace to form the
top oxide layer 54 of the ONO stack as depicted in FIG. 5. For a dry oxidation, the structure is elevated to a temperature of between about 750° C. and about 900° C., for example 900° C. in the presence of O2 gas having a flow rate of between about 2.0 SLM and about 10.5 SLM, for example about 9 SLM for between about 5 minutes and 15 minutes. For a wet oxidation, the layer is exposed to O2 and H2 gas. Beginning with a poly layer having a thickness of between about 5 Å and about 25 Å thick results in a top oxide layer from about 10 Å to about 60 Å thick. Preferably, thethin poly layer 52 overlying thenitride 50 in FIG. 4 is completely oxidized to formlayer 54 of FIG. 5 so that subsequent processing steps are not adversely affected by any unoxidized poly. Wafer processing then continues according to means known in the art, for example to form the controlgate poly layer 56 over theONO stack - An advantage of the silicon-rich nitride layer portion is that the growth of the second oxide layer over the nitride layer is self-limiting. As the silicon concentration decreases deeper into the nitride layer the oxidation rate decreases and oxide formation slows. Thus the thickness of the second oxide layer overlying the nitride may be more controllable than a deposited oxide layer or an oxide layer which is grown on a conventional nitride layer. Further, forming the ONO layer at decreased temperatures over conventional processes improves the charge trapping properties of the tunnel oxide. Similarly, forming a poly layer over a nitride layer then oxidizing the poly has similar advantages over conventional processes as the poly is more readily oxidized at lower temperatures than is nitride. Further, oxidizing a poly layer overlying the nitride is also somewhat limiting as the poly oxidizes at a much faster rate than the nitride.
- While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
Claims (6)
1. A floating gate memory device comprising a plurality of transistor gate layers, comprising:
a transistor floating gate layer;
a first silicon dioxide layer overlying said floating gate;
a silicon nitride layer overlying said first silicon dioxide layer, said silicon nitride layer having a lower portion and an upper portion;
a concentration of silicon atoms in said lower portion;
a concentration of silicon atoms in said upper portion,
wherein said silicon atom concentration in said lower portion of said nitride layer is less than said silicon atom concentration in said upper portion of said nitride layer, and said silicon concentration generally stays the same or increases throughout said nitride layer from said lower portion to said upper portion.
2. An in-process floating gate memory device comprising a transistor gate stack assembly, said assembly comprising:
a blanket unetched conductive floating gate layer;
a silicon dioxide layer overlying said unetched floating gate layer;
a silicon nitride layer overlying said silicon dioxide layer; and
an oxidizable layer consisting essentially of a material selected from the group consisting of polycrystalline silicon and amorphous silicon,
wherein said gate stack assembly of said in-process floating gate memory device is absent any portion of a conductive control gate layer.
3. (previously added) An in-process semiconductor device, comprising:
a semiconductor wafer substrate assembly comprising a semiconductor wafer, a gate oxide layer, and a conductive floating gate layer;
a silicon nitride layer overlying said floating gate layer, said silicon nitride layer having lower surface, an upper surface, and an enhanced concentration of silicon atoms, wherein said enhanced concentration of silicon atoms has a gradation which stays the same or increases throughout said silicon nitride layer from said lower surface to said upper surface.
4. The in-process semiconductor device of claim 3 , wherein said in-process semiconductor device is absent any conductive control gate layer.
5. The in-process semiconductor device of claim 3 further comprising a lower portion of said silicon nitride layer and an upper portion of said silicon nitride layer, wherein said upper portion of said silicon nitride layer comprises all of said silicon nitride layer except said lower portion and said concentration of silicon atoms remains the same throughout said lower portion of said silicon nitride layer and said concentration of silicon atoms increases throughout said upper portion of said silicon nitride layer.
6. The in-process semiconductor device of claim 3 further comprising a lower portion of said silicon nitride layer and an upper portion of said silicon nitride layer, wherein said upper portion of said silicon nitride layer comprises all of said silicon nitride layer except said lower portion and said concentration of silicon atoms remains the same throughout said lower portion of said silicon nitride layer and remains the same throughout said upper portion of said silicon nitride layer, and said concentration of said silicon atoms in said upper portion is higher than said concentration of said silicon atoms is said lower portion.
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US10/722,791 US20040113196A1 (en) | 1998-12-02 | 2003-11-25 | Method and structure for an oxide layer overlying an oxidation-resistant layer |
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US09/205,140 US6297092B1 (en) | 1998-12-02 | 1998-12-02 | Method and structure for an oxide layer overlaying an oxidation-resistant layer |
US09/969,464 US6653683B2 (en) | 1998-12-02 | 2001-10-01 | Method and structure for an oxide layer overlying an oxidation-resistant layer |
US10/722,791 US20040113196A1 (en) | 1998-12-02 | 2003-11-25 | Method and structure for an oxide layer overlying an oxidation-resistant layer |
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US09/205,140 Expired - Fee Related US6297092B1 (en) | 1998-12-02 | 1998-12-02 | Method and structure for an oxide layer overlaying an oxidation-resistant layer |
US09/969,464 Expired - Lifetime US6653683B2 (en) | 1998-12-02 | 2001-10-01 | Method and structure for an oxide layer overlying an oxidation-resistant layer |
US10/722,791 Abandoned US20040113196A1 (en) | 1998-12-02 | 2003-11-25 | Method and structure for an oxide layer overlying an oxidation-resistant layer |
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US09/969,464 Expired - Lifetime US6653683B2 (en) | 1998-12-02 | 2001-10-01 | Method and structure for an oxide layer overlying an oxidation-resistant layer |
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Also Published As
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US6653683B2 (en) | 2003-11-25 |
US20020014654A1 (en) | 2002-02-07 |
US6297092B1 (en) | 2001-10-02 |
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