US20040095162A1 - Pseudo-NMOS logic having a feedback controller - Google Patents
Pseudo-NMOS logic having a feedback controller Download PDFInfo
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- US20040095162A1 US20040095162A1 US10/700,150 US70015003A US2004095162A1 US 20040095162 A1 US20040095162 A1 US 20040095162A1 US 70015003 A US70015003 A US 70015003A US 2004095162 A1 US2004095162 A1 US 2004095162A1
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- pfet
- circuit
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- feedback
- signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
Definitions
- the present invention generally relates to CMOS logic circuits, and more particularly to a pseudo-NMOS logic circuit with numerous inputs.
- a pseudo-NMOS logic implemented in a CMOS circuit typically includes a load PFET (PMOS) with its gate tied to ground (GND), so that the load PFET is always ON.
- the source and the drain of the load PFET are connected between the supply voltage (VDD) and a “pulldown” NFET tree or circuit, respectively.
- a typical conventional pseudo-NMOS logic implemented in a CMOS circuit is shown in FIG. 3, where Z is the output node of the pseudo-NMOS logic.
- the pulldown NFET tree implements the desired equations of the pseudo-NMOS logic.
- a conventional pseudo-NMOS logic implementing a NOR equation, for example, is shown in FIG. 4.
- the size (i.e., the width) of the load PFET can be increased to counter input noise and NFET leakage. In this manner the PFET becomes stronger (i.e., able to drive more current) so that there is less impact on the PFET by the leakage.
- this approach undesirably increases the voltage output level (VOL) when the NFETs are turned ON to produce a logical LOW value at the output Z.
- VOL voltage output level
- the size of the NFETs can be decreased. However, this method also results in increasing VOL.
- a pseudo-NMOS circuit includes a first PFET electrically connected between a power supply and an output node.
- An NFET circuit is connected between the output node and ground and has a plurality of inputs.
- a second PFET is electrically connected between the power supply and the output node, and has a gate which is controlled by a signal at the output node.
- FIG. 1 is a circuit diagram of a pseudo-NMOS logic circuit in accordance with one embodiment of the present invention
- FIG. 2 is the pseudo-NMOS logic circuit of FIG. 1 implementing a large high fan-in input NOR gate
- FIG. 3 is a conventional pseudo-NMOS logic circuit; and, FIG. 4 is a conventional pseudo-NMOS logic circuit of FIG. 3 implementing a high fan-in input NOR gate.
- a pseudo-NMOS circuit in accordance one embodiment of the present invention is indicated generally at 10 and includes a load PFET (or PMOS) 12 having a gate 14 tied to ground (GND) so that the PFET is always ON.
- a source 16 of the load PFET 12 is connected to the supply voltage (VDD), and a drain 18 is connected to a “pulldown” NFET tree or circuit 20 at an output node Z of the pseudo-NMOS circuit 10 .
- the NFET tree 20 is also connected to ground GND.
- the NFET tree 20 implements the desired equation of the pseudo-NMOS logic 10 and produces the result at the output node Z.
- a feedback PFET (or PMOS) 22 is also connected between VDD and the NFET tree 20 , parallel to the load PFET 12 .
- a source 24 and a drain 26 of the feedback PFET 22 are connected respectively to VDD and the ouput node Z, as with the load PFET 12 .
- a gate 28 of the feedback PFET 22 is connected to an output node FB of an inverter circuit 30 .
- the inverter circuit 30 includes a PFET (or PMOS) 32 connected to an NFET (or NMOS) 34 , with a drain 36 of the PFET 32 connected to a drain 38 of the NFET 34 at the output node FB.
- a source 40 of the PFET 32 is connected to VDD, and a source 42 of NFET 34 is connected to GND.
- Gates 44 , 46 of PFET 32 and NFET 34 are both commonly connected to the output node Z.
- the NFET tree 20 is shown implementing a NOR gate 49 , for example, having a plurality of inputs IN_ 1 to IN_N for corresponding NFETs 48 that make up the NOR gate.
- the NFETs 48 are connected in parallel to each other with their gates 50 tied to the corresponding inputs IN_ 1 to IN_N. Drains 52 of the NFETs 48 are all connected to the output node Z, and sources 54 are connected to GND.
- the feedback PFET 22 helps to maintain VOH (i.e., the voltage output level at the output node Z) when the NFETs 48 of the NOR gate 49 are turned OFF to produce a logical HIGH value in the presence of input noise or GND differentials on the inputs of the NOR gate NFETS.
- VOH i.e., the voltage output level at the output node Z
- the output node Z transitions to a LOW voltage (a logical zero).
- the load PFET 12 continues to conduct current, since its gate 14 is tied to GND. Initially, the feedback PFET 22 will also conduct current. However, as the output node Z transitions LOW past the trip point of the feedback inverter 30 , the node FB goes HIGH. This causes the feedback PFET 22 to turn OFF.
- the P-N ratio resulting from the sizing of the PFET 32 relative to the NFET 34 of the feedback inverter 30 determines how quickly the feedback PFET will turn OFF.
- VOL decreases thereby improving the noise margin (i.e., the range of input voltage that is interpreted as being a logical LOW) of a circuit (not shown) that receives its input from the output node Z.
- a second PFET is connected in parallel to the load PFET and controlled via a feedback signal from the output of the pseudo-NMOS circuit. This arrangement results in improved input/output noise margin and reduced power consumption.
Abstract
A pseudo-NMOS circuit includes a load PFET electrically connected between a power supply and an output node, and an NFET circuit having a plurality of inputs connected between the output node and ground. A feedback PFET is electrically connected between the power supply and the output node, in parallel with the load PFET, and is controlled by a signal at the output node of the pseudo-NMOS circuit.
Description
- The present invention generally relates to CMOS logic circuits, and more particularly to a pseudo-NMOS logic circuit with numerous inputs.
- A pseudo-NMOS logic implemented in a CMOS circuit typically includes a load PFET (PMOS) with its gate tied to ground (GND), so that the load PFET is always ON. The source and the drain of the load PFET are connected between the supply voltage (VDD) and a “pulldown” NFET tree or circuit, respectively. A typical conventional pseudo-NMOS logic implemented in a CMOS circuit is shown in FIG. 3, where Z is the output node of the pseudo-NMOS logic. The pulldown NFET tree implements the desired equations of the pseudo-NMOS logic. A conventional pseudo-NMOS logic implementing a NOR equation, for example, is shown in FIG. 4.
- In a wide “fan-in” implementation of the pseudo-NMOS logic having numerous inputs to the pulldown tree, such as the NOR circuit shown in FIG. 4, “leakage” in the NFETs of the pulldown tree becomes a problem when the output at the node Z is high. A leakage occurs when there is undesirable current flow from source to drain even when the input voltage to the NFETs is zero or near zero. In other words, the NFETs do not act as a perfect switch. Power differential or noise at the inputs to the NFETs exacerbates the leakage problem, which results in noise being transmitted to other circuits that are connected to the output node Z of the pseudo-NMOS circuit.
- The size (i.e., the width) of the load PFET can be increased to counter input noise and NFET leakage. In this manner the PFET becomes stronger (i.e., able to drive more current) so that there is less impact on the PFET by the leakage. However, this approach undesirably increases the voltage output level (VOL) when the NFETs are turned ON to produce a logical LOW value at the output Z. Alternatively, the size of the NFETs can be decreased. However, this method also results in increasing VOL.
- In accordance with one embodiment of the present invention, a pseudo-NMOS circuit includes a first PFET electrically connected between a power supply and an output node. An NFET circuit is connected between the output node and ground and has a plurality of inputs. A second PFET is electrically connected between the power supply and the output node, and has a gate which is controlled by a signal at the output node.
- FIG. 1 is a circuit diagram of a pseudo-NMOS logic circuit in accordance with one embodiment of the present invention;
- FIG. 2 is the pseudo-NMOS logic circuit of FIG. 1 implementing a large high fan-in input NOR gate;
- FIG. 3 is a conventional pseudo-NMOS logic circuit; and, FIG. 4 is a conventional pseudo-NMOS logic circuit of FIG. 3 implementing a high fan-in input NOR gate.
- Turning now to FIG. 1, a pseudo-NMOS circuit in accordance one embodiment of the present invention is indicated generally at10 and includes a load PFET (or PMOS) 12 having a
gate 14 tied to ground (GND) so that the PFET is always ON. Asource 16 of theload PFET 12 is connected to the supply voltage (VDD), and adrain 18 is connected to a “pulldown” NFET tree orcircuit 20 at an output node Z of thepseudo-NMOS circuit 10. TheNFET tree 20 is also connected to ground GND. The NFETtree 20 implements the desired equation of thepseudo-NMOS logic 10 and produces the result at the output node Z. - A feedback PFET (or PMOS)22 is also connected between VDD and the
NFET tree 20, parallel to theload PFET 12. Asource 24 and adrain 26 of thefeedback PFET 22 are connected respectively to VDD and the ouput node Z, as with theload PFET 12. Agate 28 of thefeedback PFET 22, however, is connected to an output node FB of aninverter circuit 30. - The
inverter circuit 30 includes a PFET (or PMOS) 32 connected to an NFET (or NMOS) 34, with adrain 36 of thePFET 32 connected to adrain 38 of the NFET 34 at the output node FB. Asource 40 of thePFET 32 is connected to VDD, and asource 42 of NFET 34 is connected to GND. Gates 44, 46 ofPFET 32 and NFET 34, respectively, are both commonly connected to the output node Z. - Turning now to FIG. 2, the NFET
tree 20 is shown implementing aNOR gate 49, for example, having a plurality of inputs IN_1 to IN_N forcorresponding NFETs 48 that make up the NOR gate. TheNFETs 48 are connected in parallel to each other with theirgates 50 tied to the corresponding inputs IN_1 to IN_N.Drains 52 of theNFETs 48 are all connected to the output node Z, andsources 54 are connected to GND. - In operation, when all inputs IN_1 to IN_N transition LOW, voltage at the output node Z rises due to the
load PFET 12 conducting current. As the output Z goes HIGH (a logical 1), theinverter circuit 30 outputs a LOW at the node FB, since thegates PFET 32 and NFET 34 are connected to the output node Z. As a result, the feedback PFET 22 (thegate 28 of which is connected to the output node FB) turns ON, thereby aiding in the transition of the output node Z to HIGH. In this manner, thefeedback PFET 22 helps to maintain VOH (i.e., the voltage output level at the output node Z) when theNFETs 48 of theNOR gate 49 are turned OFF to produce a logical HIGH value in the presence of input noise or GND differentials on the inputs of the NOR gate NFETS. - As one or more of the inputs IN_1 to IN_N to the
NFETs 48 transitions HIGH, the output node Z transitions to a LOW voltage (a logical zero). Theload PFET 12 continues to conduct current, since itsgate 14 is tied to GND. Initially, thefeedback PFET 22 will also conduct current. However, as the output node Z transitions LOW past the trip point of the feedback inverter 30, the node FB goes HIGH. This causes thefeedback PFET 22 to turn OFF. Those skilled in the art will recognize that the P-N ratio resulting from the sizing of thePFET 32 relative to the NFET 34 of thefeedback inverter 30 determines how quickly the feedback PFET will turn OFF. Turning OFF thefeedback PFET 22 allows the output node Z transition going LOW to occur faster, since the pulldown NFET tree 20 (i.e., theNOR gate 49 in the example above) does not have to “fight” with thefeedback PFET 22 in an attempt to pull the output to GND. With thefeedback PFET 22 turned OFF, VOL decreases thereby improving the noise margin (i.e., the range of input voltage that is interpreted as being a logical LOW) of a circuit (not shown) that receives its input from the output node Z. - From the foregoing description, it should be understood that an improved circuit topology of a pseudo-NMOS logic has been shown and described which has many desirable attributes and advantages. In accordance with one embodiment, a second PFET is connected in parallel to the load PFET and controlled via a feedback signal from the output of the pseudo-NMOS circuit. This arrangement results in improved input/output noise margin and reduced power consumption.
- While various embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.
- Various features of the invention are set forth in the appended claims.
Claims (14)
1. A pseudo-NMOS circuit comprising:
a first PFET electrically connected between a power supply and an output node;
an NFET circuit connected between said output node and ground and having a plurality of inputs; and,
a second PFET electrically connected between said power supply and said output node, said second PFET being controlled by a signal at said output node.
2. The circuit as defined in claim 1 further including a control circuit for turning said second PFET ON and OFF based on said signal at said output node.
3. The circuit as defined in claim 2 wherein said control circuit is electrically connected between said power supply and said ground, and has an input connected to said output node.
4. The circuit as defined in claim 3 wherein said control circuit is an inverter circuit including a PFET connected in series to an NFET, and wherein said PFET is electrically connected to said power supply, said NFET is connected to said ground, and gates of said PFET and NFET are connected to said output node.
5. The circuit as defined in claim 4 wherein a gate to said second PFET is connected to a feedback node connecting a drain of said PFET and a drain of said NFET of said inverter circuit.
6. The circuit as defined in claim 5 wherein a signal at said feedback node transitions LOW to turn ON said second PFET when said signal at said output node is HIGH, and said signal at said feedback node transitions HIGH to turn OFF said second PFET when said signal at said output node is LOW.
7. The circuit as defined in claim 1 wherein a gate of said first PFET is connected to said ground, and a gate of said second PFET is connected to a feedback signal from said output node.
8. The circuit as defined in claim 7 wherein said second PFET is turned ON when a signal at said output node is HIGH, and turned OFF when said signal at said output node is LOW.
9. A pseudo-NMOS circuit for reducing output noise, said circuit comprising:
a load PFET electrically connected between a power supply and an output node;
an NFET circuit having a plurality of inputs connected between said output node and ground for performing a predetermined function based on signals applied to said inputs and outputting a signal to said output node; and,
a feedback PFET electrically connected between said power supply and said output node for reducing noise at said output node based on said signal at said output node.
10. The circuit as defined in claim 9 further including a feedback circuit electrically connected to said feedback PFET, wherein said feedback circuit sets said feedback PFET to ON when said signal at said output node is HIGH, and sets said feedback PFET to OFF when said signal at said output node is LOW.
11. The circuit as defined in claim 10 wherein an output of said feedback circuit is LOW when said signal at said output node is HIGH, and said output of said feedback circuit is HIGH when said signal at said output node is LOW.
12. A method for reducing noise at an output of a pseudo-NMOS circuit having a load PFET and an NFET function circuit, said method comprising the steps of:
providing a second PFET in parallel with the load PFET between a power source and the NFET function circuit; and,
turning said second PFET ON when said output of the pseudo-NMOS circuit is HIGH, and turned OFF said second PFET when said output of the pseudo-NMOS circuit is LOW.
13. The method as defined in claim 12 , wherein said second PFET is turned ON and OFF by a feedback circuit connected to an output node of the pseudo-NMOS circuit.
14. The method as defined in claim 13 , wherein said feedback circuit is an inverter circuit having an input connected to said output of the pseudo-NMOS circuit and an output connected to said second PFET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/700,150 US20040095162A1 (en) | 2002-03-19 | 2003-11-03 | Pseudo-NMOS logic having a feedback controller |
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US10/100,781 US6664813B2 (en) | 2002-03-19 | 2002-03-19 | Pseudo-NMOS logic having a feedback controller |
US10/700,150 US20040095162A1 (en) | 2002-03-19 | 2003-11-03 | Pseudo-NMOS logic having a feedback controller |
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US10/100,781 Continuation US6664813B2 (en) | 2002-03-19 | 2002-03-19 | Pseudo-NMOS logic having a feedback controller |
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US10/100,781 Expired - Fee Related US6664813B2 (en) | 2002-03-19 | 2002-03-19 | Pseudo-NMOS logic having a feedback controller |
US10/700,150 Abandoned US20040095162A1 (en) | 2002-03-19 | 2003-11-03 | Pseudo-NMOS logic having a feedback controller |
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US10/100,781 Expired - Fee Related US6664813B2 (en) | 2002-03-19 | 2002-03-19 | Pseudo-NMOS logic having a feedback controller |
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FR (1) | FR2838257A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060176081A1 (en) * | 2005-02-04 | 2006-08-10 | International Business Machines Corporation | Fast pulse powered NOR decode apparatus for semiconductor devices |
US7170320B2 (en) | 2005-02-04 | 2007-01-30 | International Business Machines Corporation | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6972599B2 (en) | 2002-08-27 | 2005-12-06 | Micron Technology Inc. | Pseudo CMOS dynamic logic with delayed clocks |
JP2017063300A (en) * | 2015-09-24 | 2017-03-30 | エスアイアイ・セミコンダクタ株式会社 | Input circuit |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5831452A (en) * | 1997-02-20 | 1998-11-03 | International Business Machines Corporation | Leak tolerant low power dynamic circuits |
US6060910A (en) * | 1997-08-08 | 2000-05-09 | Nec Corporation | Dynamic logic circuit |
US6130559A (en) * | 1997-04-04 | 2000-10-10 | Board Of Regents Of The University Of Texas System | QMOS digital logic circuits |
US6172529B1 (en) * | 1998-09-28 | 2001-01-09 | International Business Machines Corporation | Compound domino logic circuit having output noise elimination |
US6201415B1 (en) * | 1999-08-05 | 2001-03-13 | Intel Corporation | Latched time borrowing domino circuit |
US6208907B1 (en) * | 1998-01-30 | 2001-03-27 | International Business Machines Corporation | Domino to static circuit technique |
US6466057B1 (en) * | 2000-01-21 | 2002-10-15 | Hewlett-Packard Company | Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3911289A (en) * | 1972-08-18 | 1975-10-07 | Matsushita Electric Ind Co Ltd | MOS type semiconductor IC device |
JPS5178683A (en) * | 1974-12-24 | 1976-07-08 | Ibm | Cmos toranjisutaronrikairo |
-
2002
- 2002-03-19 US US10/100,781 patent/US6664813B2/en not_active Expired - Fee Related
-
2003
- 2003-03-18 FR FR0303282A patent/FR2838257A1/en not_active Withdrawn
- 2003-11-03 US US10/700,150 patent/US20040095162A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5831452A (en) * | 1997-02-20 | 1998-11-03 | International Business Machines Corporation | Leak tolerant low power dynamic circuits |
US6130559A (en) * | 1997-04-04 | 2000-10-10 | Board Of Regents Of The University Of Texas System | QMOS digital logic circuits |
US6060910A (en) * | 1997-08-08 | 2000-05-09 | Nec Corporation | Dynamic logic circuit |
US6208907B1 (en) * | 1998-01-30 | 2001-03-27 | International Business Machines Corporation | Domino to static circuit technique |
US6172529B1 (en) * | 1998-09-28 | 2001-01-09 | International Business Machines Corporation | Compound domino logic circuit having output noise elimination |
US6201415B1 (en) * | 1999-08-05 | 2001-03-13 | Intel Corporation | Latched time borrowing domino circuit |
US6466057B1 (en) * | 2000-01-21 | 2002-10-15 | Hewlett-Packard Company | Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060176081A1 (en) * | 2005-02-04 | 2006-08-10 | International Business Machines Corporation | Fast pulse powered NOR decode apparatus for semiconductor devices |
US7170320B2 (en) | 2005-02-04 | 2007-01-30 | International Business Machines Corporation | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering |
US7176725B2 (en) | 2005-02-04 | 2007-02-13 | International Business Machines Corporation | Fast pulse powered NOR decode apparatus for semiconductor devices |
Also Published As
Publication number | Publication date |
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US20030179013A1 (en) | 2003-09-25 |
FR2838257A1 (en) | 2003-10-10 |
US6664813B2 (en) | 2003-12-16 |
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