US20040089922A1 - Semiconductor device and method therefor - Google Patents
Semiconductor device and method therefor Download PDFInfo
- Publication number
- US20040089922A1 US20040089922A1 US10/290,959 US29095902A US2004089922A1 US 20040089922 A1 US20040089922 A1 US 20040089922A1 US 29095902 A US29095902 A US 29095902A US 2004089922 A1 US2004089922 A1 US 2004089922A1
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- integrated circuit
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000000034 method Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000004020 conductor Substances 0.000 claims abstract description 48
- 238000005538 encapsulation Methods 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 230000008901 benefit Effects 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- MTLMVEWEYZFYTH-UHFFFAOYSA-N 1,3,5-trichloro-2-phenylbenzene Chemical compound ClC1=CC(Cl)=CC(Cl)=C1C1=CC=CC=C1 MTLMVEWEYZFYTH-UHFFFAOYSA-N 0.000 description 4
- UTMWFJSRHLYRPY-UHFFFAOYSA-N 3,3',5,5'-tetrachlorobiphenyl Chemical compound ClC1=CC(Cl)=CC(C=2C=C(Cl)C=C(Cl)C=2)=C1 UTMWFJSRHLYRPY-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- -1 for example Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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Abstract
Description
- The invention relates generally to a semiconductor device and more particularly to a package semiconductor device having improved thermal dissipation.
- In packaging integrated circuits, it important to provide packages which allow for dissipation of heat that is generated by operation of the integrated circuit die. Generally, to remove the heat, a heat spreader is connected to a surface of the integrated circuit to allow the heat to be removed. The heat spreader may be a conductive portion of the package that is typically connected the bottom, or non-active surface, of the integrated circuit die. However, the addition of a heat spreader to the bottom of the die may increase the thickness of the package. In some applications, such as for example, a cellular telephone, a lower profile package is desirable to reduce the size of the phone. Therefore, it is desirable to have a low profile packaged integrated circuit while still having good thermal dissipation.
- The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:
- FIGS.1-5 include illustrations of sequential cross-sectional views of a package device formed in accordance with a first embodiment of the present invention; and
- FIGS.6-10 include illustrations of sequential cross-sectional views of a package device formed in accordance with a second embodiment of the present invention.
- FIG. 11 illustrates a top down view of a package substrate for use in the first and second embodiments of the present invention.
- Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention.
- Generally, the present invention provides a low profile semiconductor device having improved heat dissipation, where a semiconductor die having active circuitry on one surface is positioned in a cavity of a package substrate. The package substrate has a first surface, and a second surface opposite the first surface. The cavity is formed in the first surface and extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. The integrated circuit die has a first surface and a second surface opposite the first surface. An outer wall, or edge, of the die is substantially perpendicular to the first and second surfaces of the cavity. The die may be temporarily held in place using tape, or other temporary support. A conductive material is dispensed into the space between the die and the cavity wall. The conductive material thermally couples the outer wall of the die to the cavity wall. In one embodiment, the backside of the die is exposed when the temporary support is removed. In another embodiment, the package substrate cavity includes a heat spreader to function, at least in part, as a support during manufacture.
- By inserting the conductive adhesive between the die and the cavity wall, the package substrate functions as the heat spreader, while providing a low profile package.
- FIGS.1-5 include illustrations of sequential cross-sectional views of a package device formed in accordance with a first embodiment of the present invention.
- FIG. 1 illustrates a
semiconductor device 10 in accordance with one embodiment of the present invention.Semiconductor device 10 includes apackage substrate 12 and asemiconductor die 20. The package substrate includes a top surface having a plurality ofwire bond pads 14 and acavity 22. A bottom surface ofsubstrate 12 includespads 16.Pads 16 are conductive and may be used for a variety of purposes. For example,pads 16 may be used to mount discrete devices, may be used to receive test probes for testing purposes, or may be used to receive conductive interconnects (e.g. solder balls). FIG. 1 also illustrates atemporary support 18 that is applied to the bottom ofsubstrate 12. In the illustrated embodiment,temporary support 18 is a tape coated with an adhesive on one side that attachestemporary support 18 to the substrate. In one embodiment of the present invention,substrate 12 contains electrical conductors such as traces and vias that may be used to interconnect one or more die to external contacts (not shown). In addition,substrate 12 may include multiple internal metal layers (not shown). - A die20 is placed on top of
temporary support 18 in the center ofcavity 22 with the bottom surface of die 20 affixed totemporary support 18.Temporary support 18 is used as a supporting member to fix die 20 withincavity 22 during subsequent manufacturing steps. Note that a die attach material may be used on the bottom of die 20 but is not shown in FIG. 1.Temporary support 18 may or may not extend over the entire bottom surface ofsubstrate 12. Note that in the illustrated embodiment, the top surface of die 20 extends out ofcavity 22 and above the surface ofsubstrate 12. However, in other embodiments, die 20 may be entirely withincavity 22. - FIG. 2 illustrates
semiconductor device 10 afterconductive material 24 is dispensed in the space between the wall ofcavity 22 and die 20. In the illustrated embodiment,conductive material 24 is a conductive epoxy based adhesive. For example,conductive material 24 may be a silver filled epoxy. As illustrated in FIG. 2,conductive material 24 completely fillscavity 22 and optionally overlaps the top surface ofsubstrate 12. However, reasonable thermal performance may be achieved if the cavity is only substantially filled. - FIG. 3 illustrates
semiconductor device 10 afterwire bonds 26 are attached betweenpads 14 and pads on die 20 (not shown). Note thattemporary support 18 may be removed before attachingwire bonds 26 or after the encapsulation step illustrated below in FIG. 4. - FIG. 4 illustrates
semiconductor device 10 after encapsulation. Anencapsulation material 28 can be applied by one of transfer molding, glob top dispensing, or other encapsulation method. Note that the thermal conductivity of theconductive material 24 is greater than the thermal conductivity of theencapsulation material 28. - FIG. 5 illustrates
semiconductor device 10 being attached to a printed circuit board (PCB) 30. Electrical connections can be made betweensemiconductor device 10 andPCB 30 in a number of ways. FIG. 5 illustrates a land grid array using screen printedsolder 36 to connectpads 32 in PCB 30 topads 16 onsubstrate 12. Screen printedsolder 38 is used to connect the exposed backside of die 20 to apad 34. One skilled in the art will realize that the backside of die 20 will need a solderable surface in order to connect the exposed backside of die 20 in this manner. Alternately, thermally conductive underfill or interface material may be used if the backside of die 20 does not have a solderable surface or the use of solder is undesirable in a particular application. In the embodiment of FIG. 5, heat generated during operation of die 20 will be conducted throughconnection 38 and throughconductive material 24. The heat spread viaconductive material 24 topackage substrate 12 will be conducted to PCB 30 throughconnections 36. Heat conducted throughconductive material 24 tosubstrate 12 will also be dissipated from the top of the packaged integrated circuit device. Heat spreading to the package substrate throughconductive material 24 provides a substantial enhancement over the thermal performance that can be achieved by conduction throughconnection 38 alone. In another embodiment,connection 38 may be omitted and heat will be conducted viaconductive material 24 tosubstrate 12 andPCB 30, allowing for improved thermal conduction, easier printed circuit board assembly, reduced cost and a lower profile device compared to presently available lower profile packages. - FIGS.6-10 include illustrations of sequential cross-sectional views of a package device formed in accordance with a second embodiment of the present invention.
- FIG. 6 illustrates a
semiconductor device 50 in accordance with another embodiment of the present invention.Semiconductor device 50 includes apackage substrate 52 and asemiconductor die 60. The package substrate includes a top surface having a plurality ofwire bond pads 54 and acavity 70. A bottom surface ofsubstrate 52 includespads 56.Pads 56 are conductive and may be used for a variety of purposes. For example,pads 56 may be used to mount discrete devices, may be used to receive test probes for testing purposes, or may be used to receive conductive interconnects (e.g. solder balls). FIG. 6 also illustratessubstrate 52 having an integral die attach pad extending across a bottom ofcavity 70. Asolder mask ridge 58 is formed at the top edge of the cavity wall. In the illustrated embodiment, the integral die attach pad is formed from a conductive material, such as for example, copper. In one embodiment of the present invention,substrate 52 contains electrical conductors such as traces and vias that may be used to interconnect one or more die to external contacts (not shown). In addition,substrate 52 may include multiple internal metal layers (not shown). - A
die 60 is placed in the center ofcavity 70 with the bottom surface ofdie 60 affixed to the integral die attach pad with die attachmaterial 64. Integrated circuit die 60 has a top, or active, surface and a bottom surface opposite the top surface. An outer wall, or edge, of the die is substantially perpendicular to the first and second surfaces of the cavity. In one embodiment, the bottom surface of the integrated circuit die is substantially coplanar with the bottom surface of the package substrate.Die 60 includesledge portions 62 cut into a top edge of the active surface. In one embodiment,ledge portions 62 may be formed at the time the wafer is sawed into multiple die.Ledge portions 62 result from a two-step sawing process. In the first step, a wider saw blade is used to make a first, partial, cut. In the second step, a second cut, started in the first partial cut, using a narrower saw blade completes separating the wafer into multiple die. Note thatledge portions 62 may be formed in other ways in other embodiments. -
Substrate 52 includes asolder mask ridge 58 along a perimeter ofcavity 70. The solder mask ridge is deposited to prevent the dispensedconductive material 72 from coveringpads 54. - FIG. 7 illustrates
semiconductor device 50 afterconductive material 72 is dispensed in the space between the wall ofcavity 70 and die 60. In the illustrated embodiment,conductive material 72 is a conductive epoxy based adhesive and conductively bonds the edge, or outer wall, ofdie 60 to the wall ofcavity 70. For example,conductive material 72 may be a silver filled epoxy. As illustrated in FIG. 7,conductive material 72fills cavity 70 up toledge 62 ondie 60 andsolder mask ridge 58 onsubstrate 52.Solder mask ridge 58 functions to keepconductive material 72 from inadvertently coveringwire bond pads 54. Likewise,ledge 62 functions to preventconductive material 72 from covering the active surface ofdie 60. - FIG. 8 illustrates
semiconductor device 50 afterwire bonds 74 are attached betweenpads 54 and pads on die 60 (not shown). - FIG. 9 illustrates
semiconductor device 50 after encapsulation. Anencapsulation material 78 may be applied by one of transfer molding, glob top dispensing, or other encapsulation method. Note that the thermal conductivity ofconductive material 72 is greater than the thermal conductivity of the encapsulation layer. - FIG. 10 illustrates
semiconductor device 50 being attached to a printed circuit board (PCB) 80. Electrical connections can be made betweensemiconductor device 50 andPCB 80 in a number of ways. FIG. 10 illustrates a land grid array using screen printedsolder 86 to connectpads 82 inPCB 80 topads 56 onsubstrate 52. Optionally, screen printedsolder 88 is used to connect the bottom ofsubstrate 52 to apad 84. Alternately, thermally conductive underfill, or interface material, may be used if the bottom ofsubstrate 52 does not have a solderable surface or the use of solder is undesirable in a particular application. - In the embodiment of FIG. 10, heat generated during operation of
die 60 will primarily be conducted throughconnection 88 and throughconductive material 72. Heat may also be conducted via integral die pad toconductive material 72. The heat spread viaconductive material 72 to packagesubstrate 52 will be conducted toPCB 80 throughconnections 86. Heat conducted throughconductive material 72 tosubstrate 52 will also be dissipated from the top of the packaged integrated circuit device. Heat spreading to the package substrate throughconductive material 72 is enhanced over the thermal performance that can be achieved by conduction throughconnection 88 alone. In another embodiment,connection 88 may be omitted and heat will be conducted viaconductive material 72 tosubstrate 52 andPCB 80, allowing for easier printed circuit board assembly and reduced cost in a lower profile device with improved thermal performance. - FIG. 11 illustrates a top down view of a
package substrate 90 intended for use in the first and second embodiments of the present invention. For example,substrate 90 may be substituted forsubstrate 12 in the embodiment illustrated in FIG. 1-FIG. 5, orsubstrate 52 illustrated in FIG. 6-FIG. 10.Package substrate 90 includes acavity 91 for receiving adie 94. The walls ofcavity 91 have a plurality of plated cut-outportions 92. In one embodiment, the plated cut-outportions 92 are formed by drilling holes spaced along a line defining the cavity wall. The holes are then plated with a conductive material, such as for example, nickel or copper. In other embodiments, the holes may be plated with other thermally conductive materials. The cavity is routed leaving half of the plated via as illustrated. Conductive material dispensed in the cavity forms a conductive connection between the die and the plated cut-out out portions.Substrate 90 provides enhanced thermal coupling to the conductive internal planes (not shown) insubstrate 90 because there is a direct metal connection established between the plated vias and the internal planes. Alternately, the walls of the cavity may be plated without using vias to provide a similar result. - Note that traces and vias (not shown) within
substrate 90 are used to selectively interconnect various portions ofsubstrate 90. - Note also that die attach materials may be any type of appropriate material, such as, for example, adhesive tape or non-solid adhesive (e.g. glue, epoxy). Dies20 and 60 may be any type of integrated circuit, semiconductor device, or other type of electrically active substrate. Alternate embodiments of the present invention may have any number of
die - In the foregoing specification the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, any appropriate die attach processes, wire bond processes, and tape processes may be used in the formation of the illustrated embodiments, of which there are many known in the art. Also, a lead frame may be substituted for the substrate. Accordingly, the specification and figures are to be regarded in an illustrative rather than restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Benefits, other advantages, and solutions to problems have been described with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any of the claims.
Claims (21)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/290,959 US6847102B2 (en) | 2002-11-08 | 2002-11-08 | Low profile semiconductor device having improved heat dissipation |
PCT/US2003/027436 WO2004044983A1 (en) | 2002-11-08 | 2003-08-22 | Semiconductor device and method therefor |
AU2003265881A AU2003265881A1 (en) | 2002-11-08 | 2003-08-22 | Semiconductor device and method therefor |
TW092128309A TWI313929B (en) | 2002-11-08 | 2003-10-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/290,959 US6847102B2 (en) | 2002-11-08 | 2002-11-08 | Low profile semiconductor device having improved heat dissipation |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040089922A1 true US20040089922A1 (en) | 2004-05-13 |
US6847102B2 US6847102B2 (en) | 2005-01-25 |
Family
ID=32229161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/290,959 Expired - Lifetime US6847102B2 (en) | 2002-11-08 | 2002-11-08 | Low profile semiconductor device having improved heat dissipation |
Country Status (4)
Country | Link |
---|---|
US (1) | US6847102B2 (en) |
AU (1) | AU2003265881A1 (en) |
TW (1) | TWI313929B (en) |
WO (1) | WO2004044983A1 (en) |
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WO2006079865A1 (en) * | 2005-01-27 | 2006-08-03 | Infineon Technologies Ag | Semiconductor package and method of assembling the same |
WO2006090199A1 (en) * | 2005-02-28 | 2006-08-31 | Infineon Technologies Ag | Semiconductor package, a panel and methods of assembling the same |
US20080093606A1 (en) * | 2006-10-24 | 2008-04-24 | Chipmos Technologies Inc. | Light emitting chip package and manufacturing method thereof |
US9510495B2 (en) | 2012-11-27 | 2016-11-29 | Freescale Semiconductor, Inc. | Electronic devices with cavity-type, permeable material filled packages, and methods of their manufacture |
US9598280B2 (en) | 2014-11-10 | 2017-03-21 | Nxp Usa, Inc. | Environmental sensor structure |
US20170148746A1 (en) * | 2015-11-19 | 2017-05-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
WO2018125097A1 (en) * | 2016-12-28 | 2018-07-05 | Xu Yi Elyn | Embedded component and methods of making the same |
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US7374971B2 (en) | 2005-04-20 | 2008-05-20 | Freescale Semiconductor, Inc. | Semiconductor die edge reconditioning |
US20060286706A1 (en) * | 2005-06-21 | 2006-12-21 | Salian Arvind S | Method of making a substrate contact for a capped MEMS at the package level |
US20070111399A1 (en) * | 2005-11-14 | 2007-05-17 | Goida Thomas M | Method of fabricating an exposed die package |
US8426960B2 (en) * | 2007-12-21 | 2013-04-23 | Alpha & Omega Semiconductor, Inc. | Wafer level chip scale packaging |
US9070657B2 (en) | 2013-10-08 | 2015-06-30 | Freescale Semiconductor, Inc. | Heat conductive substrate for integrated circuit package |
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Also Published As
Publication number | Publication date |
---|---|
US6847102B2 (en) | 2005-01-25 |
TW200416989A (en) | 2004-09-01 |
AU2003265881A1 (en) | 2004-06-03 |
WO2004044983A1 (en) | 2004-05-27 |
TWI313929B (en) | 2009-08-21 |
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