US20040080576A1 - Monolithic common carrier - Google Patents
Monolithic common carrier Download PDFInfo
- Publication number
- US20040080576A1 US20040080576A1 US10/692,884 US69288403A US2004080576A1 US 20040080576 A1 US20040080576 A1 US 20040080576A1 US 69288403 A US69288403 A US 69288403A US 2004080576 A1 US2004080576 A1 US 2004080576A1
- Authority
- US
- United States
- Prior art keywords
- carrier
- chips
- common carrier
- unprocessed
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract 2
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000007766 curtain coating Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002918 waste heat Substances 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/1623—Manufacturing processes bonding and adhesion
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/14—Structure thereof only for on-demand ink jet heads
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/145—Arrangement thereof
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/1631—Manufacturing processes photolithography
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/1632—Manufacturing processes machining
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
- B41J2/135—Nozzles
- B41J2/16—Production of nozzles
- B41J2/1621—Manufacturing processes
- B41J2/164—Manufacturing processes thin film formation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
- B41J2202/01—Embodiments of or processes related to ink-jet heads
- B41J2202/19—Assembling head units
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2202/00—Embodiments of or processes related to ink-jet or thermal heads
- B41J2202/01—Embodiments of or processes related to ink-jet heads
- B41J2202/20—Modules
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to precision alignment of integrated circuit devices on a common carrier. More specifically, the present invention relates to precision alignment of integrated circuit devices corresponding to thermal ink jets on a common carrier.
- an inkjet printer for applications that require a hardcopy printout on a sheet of media.
- an inkjet printer it is commonplace to use an inkjet printer to print on sheets of paper, transparencies, labels, and the like.
- a carriage holds one or more ink cartridges.
- Each cartridge has an inkjet printhead (pen) that includes several nozzles from which ink is ejected in a direction that causes the ink to impinge on the sheet of media.
- the carriage must travel across the media so that each pen can reach the full area of the media.
- the media to be printed on is usually driven along a media axis of motion and the pen is driven along a carriage axis of motion that is perpendicular to the media axis.
- two or more cartridges are needed to print color images.
- a color inkjet printer can have four cartridges (black, cyan, magenta, and yellow) with a pen for each color. Consequently, in a four cartridge printer, the carriage must travel the width of the media, plus the width of the four pens, plus the space between pens. Therefore, the width of the inkjet printer is determined to a large extent by the distance the carriage must travel in order to print images on the full area of the media. For example, in an inkjet plotter, the carriag may have to travel a distance greater than the width of a D-size sheet of media.
- the time it takes to print images includes the travel time for the carriage. Additionally, the mechanical components that move the carriage add to the complexity, size, and weight of the printer and are a source of noise and vibration that can be annoying to a user of the printer.
- the pens in inkjet printers require periodic alignment to ensure consistent quality in the printed image. Because the pens are mounted in separate cartridges, there is always a risk of misalignment between pens, particularly when one or more cartridges are replaced.
- the waste heat can raise the temperature of the pens resulting in an increase in the pens drop volume.
- a temperature differential exists among the printheads so that the drop volumes of the printheads can vary depending on their location on the substrate.
- th thermal conductivity of the substrate and the printheads would be identical so that there is no temperature differential between the printheads resulting in consistent drop volumes among the printheads.
- a common carrier substrate is formed having one or more precisely formed pockets.
- the sides of each pocket are formed to have a side profile that is a near perfect compliment of the side profile of each of a set of fully integrated chips. Due to the complementary side profiles, the chip can be positioned in near perfect self-alignment with all other chips on the substrate.
- alignment according to this technique is achieved by the precise formation of the pockets and the precise formation of the complimentary edges of the chips.
- the present invention is embodied in a common carrier that includes a carrier substrate for adhering a plurality of unprocessed integrateable chips. Once adhered, the carrier substrate is lithographically processed to form integrated chips that are aligned on the carrier substrate is within lithographic alignment tolerances.
- a common carrier is formed to include a plurality of integrated chips and a carrier substrate, where the unprocessed integrateable chip form of the integrated chips are first adhered using a first placement alignment tolerence to the carrier substrate and then are lithographically processed to obtain the plurality of integrated chips on the carrier substrate such that the integrated chips are aligned with each other and the substrate with a second alignment tolerance having lithographic processing precision.
- the plurality of integrated chips correspond to a plurality of inkjet printhead IC devices.
- FIG. 1 shows a first embodiment of the method of forming a monolithic common carrier.
- FIG. 2 shows a second embodiment of the method of forming a monolithic common carrier in which unprocessed, integrateable chips are adhered into slots.
- FIG. 3 shows a third embodiment of the method of forming a monolithic common carrier in which unprocessed, integrateable chips are adhered directly onto the surface of a carrier substrate.
- FIG. 4 shows a plan view of slots formed into a carrier substrate.
- FIGS. 5A and 5B shows a plan view of unprocessed, integrateable chips adhered within the carrier substrate slots.
- the present invention is a monolithic common carrier having adhered on its upper surface a plurality of integrated chips, in which the integrated chips are aligned according to lithographic process tolerances.
- the monolithic common carrier is formed by initially adhering unprocessed integrateable chips to a carrier substrate and then subsequently lithographically processing the chips to form integrated chips on the carrier substrate.
- lithographic processing alignment precision is achieved between the integrated chips and between the substrate and the integrated chips.
- an unprocessed, integrateable chip is defined as a workpiece of material which can be lithographically processed to form an integrated device or chip, and which has not yet been exposed to lithographic processing steps.
- an integrated device is formed by exposing a workpiece of material to lithographic processing steps to alter the electrical, electromechanical, mechanical or physical characteristics of the workpiece.
- FIG. 1 shows one embodiment of the method of forming the monolithic common carrier of the present invention including the steps of adhering a plurality of unprocessed, integrateable chips to a carrier substrate using a first placement alignment tolerance (step 10 ) and lithographically processing the plurality of unprocessed chips to form a plurality of integrated chips (step 11 ), where the integrated chips are aligned according to lithographic processing tolerances.
- FIG. 2 shows a second embodiment of the method of forming the common carrier of the present invention.
- a plurality of slots is formed within the upper surface of the carrier substrate (step 12 ) and a plurality of unprocessed, integrateable chips is adhered into the slots—one chip per slot (step 13 ).
- a filler is deposited to fill the gaps formed between the interior edges of the slots and the peripheral edges of the unprocessed chips (step 14 ).
- the surface of the carrier substrate is then polished so at to smooth out the surface topology of the carrier substrate such that the top surface of the chips and the carrier substrate are in essentially the same plane (step 15 ). This step is performed so as to put the carrier substrate in condition for subsequent lithographic processing steps.
- the unprocessed, integrateable chips are lithographically processed so as to form a plurality of integrated circuit chips on the carrier substrate (step 16 ).
- the carrier substrate is embodied as multiple smaller carrier substrates, the carrier substrate can then be separated into individual smaller carrier substrates (not shown in FIG. 2).
- unprocessed, integrateable chips are adhered directly to the top surface of the carrier substrate instead of into formed slots (step 17 ) and then the unprocessed chips are lithographically processed to form integrated chips (step 18 ).
- subsequent processing steps are adapted to account for the uneven topology of the carrier substrate. For instance, after adhering the unprocessed chips to the carrier substrate, the lithographic processing step of depositing photoresist onto the surface of the substrate carrier is performed using curtain or sheet coating, instead of the conventional spin-type photoresist deposition technique. Other alternative lithographic processing steps may be required to account for the uneven topology of the carrier surface.
- conductive nodes or bonding pads are formed on the integrated circuit so as to conductively wire bond the integrated circuit chip to one of another integrated circuit and/or the carrier substrate.
- FIG. 4 shows a carrier substrate having a plurality of slots 19 formed into the upper surface 20 of the carrier substrate 21 (FIG. 4).
- Slot dimensions i.e., length and width
- the placement tool has a tolerance that is significantly less than the lithographic processing steps to be performed in subsequent steps.
- the placement tool has a tolerance range of +/ ⁇ 1 milimeter.
- the depth of the slots is designed such that the upper surface of the unprocessed chips when adhered into the slot is essentially in the same plane as the upper surface of the carrier substrate.
- the carrier substrate and the adhesive are composed of a material that has essentially the same coefficient of thermal expansion (CTE) as the unprocessed chips.
- CTE coefficient of thermal expansion
- the size of the carrier substrate can be selected dependent on subsequent processing steps for forming the common carrier. For instance, in one embodiment, the carrier substrate size is selected to be adaptable to subsequent lithographic processing steps or equipment used to perform the subsequent lithographic processing steps. Carrier substrate size is also dependent on the number of devices that are to be adhered on it. In one embodiment in which the unprocessed chips are silicon chips, the carrier substrate and adhesive can be composed of polysilicon, glass, metal, ceramic, or similar compositions.
- the size of carrier substrate 21 can be selected so that it can form a plurality of smaller carrier substrates.
- FIG. 4 shows three carrier substrates 21 A (dashed lines).
- multiple carrier substrates 21 A can be formed simultaneously and then separated in later processing st ps.
- the adhesive is selected so as to retain adher nce reliability when exposed to subsequent processing steps performed on the common carrier.
- FIG. 5A shows the carrier substrate 21 having a plurality of unprocessed, integrateable chips 22 adhered to the carrier substrate within the plurality of slots 19 .
- a filler is used to fill the gap 23 formed between the interior edge of slot 19 and the peripheral edges of the chip 22 (FIG. 5B).
- a relatively continuous top surface is formed on the carrier substrate.
- the top surfaces of the unprocessed chips and carrier substrate are polished to even out the common carrier surface topology in order to facilitate subsequent processing steps.
- the surface is polished such that the top surfaces of the chips are in the same plane as the top surface of the substrate.
- the filler is selected to have the same or sustantially the same CTE as the integrated chip.
- the filler is glass frit.
- the plurality of chips correspond to printhead integrated circuit devices and each of the individual carrier substrates 21 A corresponds to a printhead of a single color. In another embodiment, the plurality of chips corresponds to printhead IC devices and each of the individual carrier substrates corresponds to a printhead containing all of the colors for printing for a given printer device.
- the plurality of chips is a component selected from a group consisting of an inkjet printhead, a thermal inkjet printhead, an integrated circuit, an ASIC, a MicroElectroMechanical System, and a fluidic device.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
A common carrier for forming multiple printheads thereon and method of forming thereof is described. The common carrier includes a carrier substrate for adhering a plurality of unprocessed, integrateable semiconductor chips. Once adhered, the carrier substrate is lithographically processed to form a plurality of integrated circuit (IC) printhead chips such that alignment of the IC chips on the carrier substrate has the precision of lithographic alignment tolerances which is well within printhead alignment requirements.
Description
- The present invention relates generally to precision alignment of integrated circuit devices on a common carrier. More specifically, the present invention relates to precision alignment of integrated circuit devices corresponding to thermal ink jets on a common carrier.
- Articles and publications set forth herein are presented for the information contained therein: none of the information is admitted to be statutory “prior art” and we reserve the right to establish prior inventorship with respect to any such information.
- It is well known in the art to use an inkjet printer for applications that require a hardcopy printout on a sheet of media. For example, it is commonplace to use an inkjet printer to print on sheets of paper, transparencies, labels, and the like. In a typical inkjet printer, a carriage holds one or more ink cartridges. Each cartridge has an inkjet printhead (pen) that includes several nozzles from which ink is ejected in a direction that causes the ink to impinge on the sheet of media. Typically, the carriage must travel across the media so that each pen can reach the full area of the media. The media to be printed on is usually driven along a media axis of motion and the pen is driven along a carriage axis of motion that is perpendicular to the media axis. In color inkjet printers, two or more cartridges are needed to print color images. For instance, a color inkjet printer can have four cartridges (black, cyan, magenta, and yellow) with a pen for each color. Consequently, in a four cartridge printer, the carriage must travel the width of the media, plus the width of the four pens, plus the space between pens. Therefore, the width of the inkjet printer is determined to a large extent by the distance the carriage must travel in order to print images on the full area of the media. For example, in an inkjet plotter, the carriag may have to travel a distance greater than the width of a D-size sheet of media.
- Because the carriage must travel across the media, the time it takes to print images includes the travel time for the carriage. Additionally, the mechanical components that move the carriage add to the complexity, size, and weight of the printer and are a source of noise and vibration that can be annoying to a user of the printer.
- Moreover, the pens in inkjet printers require periodic alignment to ensure consistent quality in the printed image. Because the pens are mounted in separate cartridges, there is always a risk of misalignment between pens, particularly when one or more cartridges are replaced.
- Prior attempts to solve the above mentioned limitations and disadvantages of multiple cartridge inkjet printers include mounting a plurality of inkjet printheads onto a wide substrate such as a multi-layer ceramic substrate or flexible substrate. Those solutions have several disadvantages.
- First, expensive precision tooling is required to align the printheads to the substrate. Second, a mismatch between the coefficient of thermal expansion for the printhead and the substrate can result in thermal induced stress on the interconnect used to electrically connect the substrate to the printheads. Additionally, the mismatch can result in misalignment between the substrate and the printheads. Third, the interconnect, the materials used for the substrate, and adhesives used to attach the printheads to the substrate are subject to failures due to the corrosive effects of the ink used in inkjet printers. Forth, the inkjet pens are sensitive to temperature variations caused by waste heat from the printheads. The substrate must have a high thermal conductivity so that the waste heat can be dissipated. If the substrate has a low thermal conductivity, then the waste heat can raise the temperature of the pens resulting in an increase in the pens drop volume. Subsequently, a temperature differential exists among the printheads so that the drop volumes of the printheads can vary depending on their location on the substrate. Ideally, th thermal conductivity of the substrate and the printheads would be identical so that there is no temperature differential between the printheads resulting in consistent drop volumes among the printheads.
- One manner in which multiple printhead alignment can be achieved is described in an application filed by the assignee of the present application. According to this technique, a common carrier substrate is formed having one or more precisely formed pockets. The sides of each pocket are formed to have a side profile that is a near perfect compliment of the side profile of each of a set of fully integrated chips. Due to the complementary side profiles, the chip can be positioned in near perfect self-alignment with all other chips on the substrate. Hence alignment according to this technique is achieved by the precise formation of the pockets and the precise formation of the complimentary edges of the chips.
- Therefore, there is a need for a carrier that can mount one or more inkjet printheads in alignment with one another without the need to form precise pockets within the carrier.
- Broadly, the present invention is embodied in a common carrier that includes a carrier substrate for adhering a plurality of unprocessed integrateable chips. Once adhered, the carrier substrate is lithographically processed to form integrated chips that are aligned on the carrier substrate is within lithographic alignment tolerances.
- In accordance with one embodiment of the common carrier of the present invention and method of forming thereof, a common carrier is formed to include a plurality of integrated chips and a carrier substrate, where the unprocessed integrateable chip form of the integrated chips are first adhered using a first placement alignment tolerence to the carrier substrate and then are lithographically processed to obtain the plurality of integrated chips on the carrier substrate such that the integrated chips are aligned with each other and the substrate with a second alignment tolerance having lithographic processing precision.
- In one embodiment the plurality of integrated chips correspond to a plurality of inkjet printhead IC devices.
- FIG. 1 shows a first embodiment of the method of forming a monolithic common carrier.
- FIG. 2 shows a second embodiment of the method of forming a monolithic common carrier in which unprocessed, integrateable chips are adhered into slots.
- FIG. 3 shows a third embodiment of the method of forming a monolithic common carrier in which unprocessed, integrateable chips are adhered directly onto the surface of a carrier substrate.
- FIG. 4 shows a plan view of slots formed into a carrier substrate.
- FIGS. 5A and 5B shows a plan view of unprocessed, integrateable chips adhered within the carrier substrate slots.
- In the following detailed description and in the several figures of the drawings, like elements are identified with like reference numerals.
- In general, the present invention is a monolithic common carrier having adhered on its upper surface a plurality of integrated chips, in which the integrated chips are aligned according to lithographic process tolerances. The monolithic common carrier is formed by initially adhering unprocessed integrateable chips to a carrier substrate and then subsequently lithographically processing the chips to form integrated chips on the carrier substrate. As a result, lithographic processing alignment precision is achieved between the integrated chips and between the substrate and the integrated chips. One of the main advantages of this type of formation of a common carrier is that integrated chips formed on the carrier are aligned according to lithographic tolerances without the requirement of a precision placement tool.
- It should be noted that for purposes of the present invention an unprocessed, integrateable chip is defined as a workpiece of material which can be lithographically processed to form an integrated device or chip, and which has not yet been exposed to lithographic processing steps. In addition, an integrated device is formed by exposing a workpiece of material to lithographic processing steps to alter the electrical, electromechanical, mechanical or physical characteristics of the workpiece.
- FIG. 1 shows one embodiment of the method of forming the monolithic common carrier of the present invention including the steps of adhering a plurality of unprocessed, integrateable chips to a carrier substrate using a first placement alignment tolerance (step10) and lithographically processing the plurality of unprocessed chips to form a plurality of integrated chips (step 11), where the integrated chips are aligned according to lithographic processing tolerances.
- FIG. 2 shows a second embodiment of the method of forming the common carrier of the present invention. In this embodiment, a plurality of slots is formed within the upper surface of the carrier substrate (step12) and a plurality of unprocessed, integrateable chips is adhered into the slots—one chip per slot (step 13). Next, a filler is deposited to fill the gaps formed between the interior edges of the slots and the peripheral edges of the unprocessed chips (step 14). The surface of the carrier substrate is then polished so at to smooth out the surface topology of the carrier substrate such that the top surface of the chips and the carrier substrate are in essentially the same plane (step 15). This step is performed so as to put the carrier substrate in condition for subsequent lithographic processing steps. Next, the unprocessed, integrateable chips are lithographically processed so as to form a plurality of integrated circuit chips on the carrier substrate (step 16). Optionally, if the carrier substrate is embodied as multiple smaller carrier substrates, the carrier substrate can then be separated into individual smaller carrier substrates (not shown in FIG. 2).
- In an alternative embodiment of the method (shown in FIG. 3), unprocessed, integrateable chips are adhered directly to the top surface of the carrier substrate instead of into formed slots (step17) and then the unprocessed chips are lithographically processed to form integrated chips (step 18). In this embodiment, due to the uneven surface of the carrier substrate resulting from adhering the chips directly to the upper surface, subsequent processing steps are adapted to account for the uneven topology of the carrier substrate. For instance, after adhering the unprocessed chips to the carrier substrate, the lithographic processing step of depositing photoresist onto the surface of the substrate carrier is performed using curtain or sheet coating, instead of the conventional spin-type photoresist deposition technique. Other alternative lithographic processing steps may be required to account for the uneven topology of the carrier surface.
- In one embodiment in which the unprocessed chips are lithographically processed to form integrated circuit devices, conductive nodes or bonding pads are formed on the integrated circuit so as to conductively wire bond the integrated circuit chip to one of another integrated circuit and/or the carrier substrate.
- FIG. 4 shows a carrier substrate having a plurality of
slots 19 formed into theupper surface 20 of the carrier substrate 21 (FIG. 4). Slot dimensions (i.e., length and width) are designed to be slightly larger than the dimensions (i.e., length and width) of the unprocessed chips to account for placement tool misalignment of the chips. In this embodiment, the placement tool has a tolerance that is significantly less than the lithographic processing steps to be performed in subsequent steps. In one embodiment, the placement tool has a tolerance range of +/−1 milimeter. The depth of the slots is designed such that the upper surface of the unprocessed chips when adhered into the slot is essentially in the same plane as the upper surface of the carrier substrate. - In accordance with one embodiment of the common carrier, the carrier substrate and the adhesive are composed of a material that has essentially the same coefficient of thermal expansion (CTE) as the unprocessed chips. The reason for the carrier substrate and adhesive having the same CTE as the integrated chips is that in the event of temperature fluctuations, the substrate, adhesive and integrated chips will expand at the same rate, thereby minimizing structural damage to the finished common carrier during periods of temperature fluctuations.
- The size of the carrier substrate can be selected dependent on subsequent processing steps for forming the common carrier. For instance, in one embodiment, the carrier substrate size is selected to be adaptable to subsequent lithographic processing steps or equipment used to perform the subsequent lithographic processing steps. Carrier substrate size is also dependent on the number of devices that are to be adhered on it. In one embodiment in which the unprocessed chips are silicon chips, the carrier substrate and adhesive can be composed of polysilicon, glass, metal, ceramic, or similar compositions.
- It should be noted that in another embodiment, the size of
carrier substrate 21 can be selected so that it can form a plurality of smaller carrier substrates. For example, FIG. 4 shows threecarrier substrates 21A (dashed lines). In this embodiment,multiple carrier substrates 21A can be formed simultaneously and then separated in later processing st ps. In one embodiment, the adhesive is selected so as to retain adher nce reliability when exposed to subsequent processing steps performed on the common carrier. - FIG. 5A shows the
carrier substrate 21 having a plurality of unprocessed,integrateable chips 22 adhered to the carrier substrate within the plurality ofslots 19. In one embodiment, a filler is used to fill thegap 23 formed between the interior edge ofslot 19 and the peripheral edges of the chip 22 (FIG. 5B). In this way, a relatively continuous top surface is formed on the carrier substrate. In one embodiment, the top surfaces of the unprocessed chips and carrier substrate are polished to even out the common carrier surface topology in order to facilitate subsequent processing steps. In one embodiment, the surface is polished such that the top surfaces of the chips are in the same plane as the top surface of the substrate. - In one embodiment, the filler is selected to have the same or sustantially the same CTE as the integrated chip. In another embodiment, the filler is glass frit.
- In one embodiment, the plurality of chips correspond to printhead integrated circuit devices and each of the
individual carrier substrates 21A corresponds to a printhead of a single color. In another embodiment, the plurality of chips corresponds to printhead IC devices and each of the individual carrier substrates corresponds to a printhead containing all of the colors for printing for a given printer device. - In still another embodiment of the common carrier of the present invention, the plurality of chips is a component selected from a group consisting of an inkjet printhead, a thermal inkjet printhead, an integrated circuit, an ASIC, a MicroElectroMechanical System, and a fluidic device.
- In the preceding description, numerous specific details are set forth, such as specific processing steps and materials in order to provide a through understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known lithographic processing steps have not been described in detail in order to avoid unnecessarily obscuring the present invention.
- In addition, although elements of the present invention have been described in conjunction with certain embodiments, it is appreciated that the invention can be implement in a variety of other ways. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration is in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recited only those features regarded as essential to the invention.
Claims (21)
1. A common carrier, comprising:
a carrier substrate having an upper surface; and
a plurality of integrated chips, the integrated chips being first adhered to the upper surface of the carrier substrate in their unprocessed, integrateable chip form according to a placement alignment tolerance and then lithographically processed to form the integrated chips, wherein the integrated chips are aligned according to lithographic alignment tolerance with each other and the substrate.
2. The common carrier as described in claim 1 , wherein the unprocessed integrateable form of the integrated chips are adhered to the carrier substrate using an adhesive which retains adherence reliability when exposed to subsequent processing steps performed on the common carrier.
3. The common carrier as described in claim 1 , wherein the carrier substrate, the adhesive, and the integrated chips have essentially the same coefficient of thermal expansion (CTE).
4. The common carrier as described in claim 1 wherein the carrier substrate comprises one of polysilicon, glass, metal, and ceramic.
5. The common carrier as described in claim 1 , wherein the carrier substrate includes a plurality of slots for adhering the plurality of chips, one chip per slot.
6. The common carrier as described in claim 5 , wherein the carrier substrate and the integrated chips each have parallel top surfaces which reside essentially within the same plane.
7. The common carrier as described in claim 6 , wherein the upper surface of the carrier substrate and the unprocessed, integrateable form of the integrated chips are polished prior to being lithographically processed.
8. The common carrier as described in claim 1 , wherein the carrier substrate and the integrated chips each have parallel top surfaces which do not reside within the same plane.
9. The common carrier as described in claim 8 , wherein the unprocessed, integrateable chip form of the plurality of chips is lithographically processed using a curtain coating photoresist deposition.
10. The common carrier as described in claim 7 further comprising a filler material adapted to fill a peripheral gap between the interior edges of each of the slots and the peripheral edges of each of the unprocessed, integrateable form of the integrated chips when each chip is adhered within each slot and prior to being polished.
11. The common carrier as described in claim 9 wherein the filler material comprises glass frit.
12. The common carrier as described in claim 1 further comprising:
at least two electrically conductive nodes, the electrically conductive nodes are disposed on either one of the chip and the carrier substrate; and
an interconnect adapted to electrically connect the electrically conductive nodes.
13. The common carrier of claim 1 , wherein the plurality of integrated chips is a component selected from a group consisting of an inkjet printhead, a thermal inkjet printhead, a semiconductor, an integrated circuit, an ASIC, a MicroElectroMechanical System, and a fluidic device.
14. A method of forming a common carrier comprising the steps of:
adhering an unprocessed, integrateable form of a plurality of chips on the upper surface of a carrier substrate according to a first placement alignment precision;
lithographically processing the unprocessed, integrateable form of the plurality of chips to form a plurality of integrated chips on the upper surface, wherein the integrated chips are aligned with each other and the substrate with a second alignment precision having lithographic processing tolerances.
15. The method of forming the common carrier as described in claim 14 wherein the first alignment precision has a greater tolerance range than the lithographic processing tolerances.
16. The method of forming the common carrier as described in claim 14 wherein the first alignment precision has a tolerance in the range of +/−1 milimeter and the second alignment precision has a tolerance in the range of less than 1 micron.
17. The method of forming the common carrier as described in claim 14 further comprising the steps of:
forming a plurality of slots within the upper surface of the carrier substrate according to the first alignment precision; and
adhering the unprocessed, integrateable form of the integrated chips within the plurality of slots.
18. The method of forming the common carrier as described in claims 17 further comprising the step of depositing a filler so as to fill a peripheral gap between the interior edges of each of the slots and the peripheral edges of each of the unprocessed, integrateable form of the integrated chips when each unprocessed chip is adhered within each slot.
19. The method of forming the common carrier as described in claim 18 further comprising the step of polishing the upper surface of the plurality of chips to be in essentially the same parallel plane as the upper surface of the carrier substrate.
20. The method of forming the common carrier as described in claim 14 further comprising the step of adhering the unprocessed, integrateable form of the integrated chips directly on the upper surface of the carrier substrate such that the upper surface of the unprocessed, integrateable chips is in a parallel, but different, plane than the upper surface of the substrate carrier.
21. The method of forming the common carrier as described in claim 20 further comprising the step of lithographically processing using curtain coating deposition.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/692,884 US7163844B2 (en) | 2000-09-05 | 2003-10-24 | Monolithic common carrier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/655,197 US6812564B1 (en) | 2000-09-05 | 2000-09-05 | Monolithic common carrier |
US10/692,884 US7163844B2 (en) | 2000-09-05 | 2003-10-24 | Monolithic common carrier |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/655,197 Division US6812564B1 (en) | 2000-09-05 | 2000-09-05 | Monolithic common carrier |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040080576A1 true US20040080576A1 (en) | 2004-04-29 |
US7163844B2 US7163844B2 (en) | 2007-01-16 |
Family
ID=27613724
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/655,197 Expired - Fee Related US6812564B1 (en) | 2000-09-05 | 2000-09-05 | Monolithic common carrier |
US10/692,884 Expired - Fee Related US7163844B2 (en) | 2000-09-05 | 2003-10-24 | Monolithic common carrier |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/655,197 Expired - Fee Related US6812564B1 (en) | 2000-09-05 | 2000-09-05 | Monolithic common carrier |
Country Status (2)
Country | Link |
---|---|
US (2) | US6812564B1 (en) |
TW (1) | TW503453B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103561958A (en) * | 2011-05-31 | 2014-02-05 | 惠普发展公司,有限责任合伙企业 | Printhead die |
Citations (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4254445A (en) * | 1979-05-07 | 1981-03-03 | International Business Machines Corporation | Discretionary fly wire chip interconnection |
US4326180A (en) * | 1979-11-05 | 1982-04-20 | Microphase Corporation | Microwave backdiode microcircuits and method of making |
US4646142A (en) * | 1984-09-26 | 1987-02-24 | Rca Corporation | Method and apparatus for aligning solid-state imagers |
US4797780A (en) * | 1986-08-18 | 1989-01-10 | Siemens Aktiengesellschaft | Component with filled layers and electrical contacts and methods for its production |
US4890157A (en) * | 1986-01-31 | 1989-12-26 | Texas Instruments Incorporated | Integrated circuit product having a polyimide film interconnection structure |
US5055425A (en) * | 1989-06-01 | 1991-10-08 | Hewlett-Packard Company | Stacked solid via formation in integrated circuit systems |
US5055907A (en) * | 1989-01-25 | 1991-10-08 | Mosaic, Inc. | Extended integration semiconductor structure with wiring layers |
US5276289A (en) * | 1990-03-30 | 1994-01-04 | Hitachi, Ltd. | Electronic circuit device and method of producing the same |
US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5285108A (en) * | 1991-06-21 | 1994-02-08 | Compaq Computer Corporation | Cooling system for integrated circuits |
US5319244A (en) * | 1991-12-13 | 1994-06-07 | International Business Machines Corporation | Triazine thin film adhesives |
US5371029A (en) * | 1991-01-22 | 1994-12-06 | National Semiconductor Corporation | Process for making a leadless chip resistor capacitor carrier using thick and thin film printing |
US5394010A (en) * | 1991-03-13 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
US5450109A (en) * | 1993-03-24 | 1995-09-12 | Hewlett-Packard Company | Barrier alignment and process monitor for TIJ printheads |
US5474458A (en) * | 1993-07-13 | 1995-12-12 | Fujitsu Limited | Interconnect carriers having high-density vertical connectors and methods for making the same |
US5510273A (en) * | 1995-04-03 | 1996-04-23 | Xerox Corporation | Process of mounting semiconductor chips in a full-width-array image |
US5565113A (en) * | 1994-05-18 | 1996-10-15 | Xerox Corporation | Lithographically defined ejection units |
US5625221A (en) * | 1994-03-03 | 1997-04-29 | Samsung Electronics Co., Ltd. | Semiconductor assembly for a three-dimensional integrated circuit package |
US5654121A (en) * | 1994-04-28 | 1997-08-05 | Agfa-Gevaert Ag | Positive-working radiation-sensitive mixture |
US6100594A (en) * | 1998-01-14 | 2000-08-08 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US6123410A (en) * | 1997-10-28 | 2000-09-26 | Hewlett-Packard Company | Scalable wide-array inkjet printhead and method for fabricating same |
US6163068A (en) * | 1999-04-22 | 2000-12-19 | Yao; Hsia Kuang | Multi-chip semiconductor encapsulation method and its finished product |
US6248942B1 (en) * | 1995-11-22 | 2001-06-19 | Gore Enterprise Holdings, Inc. | Strings for musical instruments |
US20010014488A1 (en) * | 1998-10-06 | 2001-08-16 | Salman Akram | Multi chip semiconductor package and method of construction |
US6362117B1 (en) * | 1998-08-04 | 2002-03-26 | Texas Instruments Incorporated | Method of making integrated circuit with closely spaced components |
US20020041026A1 (en) * | 1997-02-14 | 2002-04-11 | Ball Michael B. | Method and apparatus for routing die interconnections using intermediate connection elements secured to the die face |
US6372539B1 (en) * | 2000-03-20 | 2002-04-16 | National Semiconductor Corporation | Leadless packaging process using a conductive substrate |
US6473966B1 (en) * | 1999-02-01 | 2002-11-05 | Casio Computer Co., Ltd. | Method of manufacturing ink-jet printer head |
US20030036249A1 (en) * | 2001-08-06 | 2003-02-20 | Bauer Donald G. | Chip alignment and placement apparatus for integrated circuit, MEMS, photonic or other devices |
US20040104466A1 (en) * | 1998-09-21 | 2004-06-03 | Miller Joseph P. | Integrated circuit device/circuit board connection apparatus |
US7005319B1 (en) * | 2004-11-19 | 2006-02-28 | International Business Machines Corporation | Global planarization of wafer scale package with precision die thickness control |
US7107562B2 (en) * | 2002-11-28 | 2006-09-12 | Infineon Technologies Ag | Method and apparatus for the arrangement of contact-making elements of components of an integrated circuit, computer-readable storage medium and program element |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6175287B1 (en) * | 1997-05-28 | 2001-01-16 | Raytheon Company | Direct backside interconnect for multiple chip assemblies |
DE19944042A1 (en) * | 1999-09-14 | 2001-04-12 | Siemens Ag | Illumination unit for medical examination device |
-
2000
- 2000-09-05 US US09/655,197 patent/US6812564B1/en not_active Expired - Fee Related
-
2001
- 2001-06-15 TW TW090114604A patent/TW503453B/en not_active IP Right Cessation
-
2003
- 2003-10-24 US US10/692,884 patent/US7163844B2/en not_active Expired - Fee Related
Patent Citations (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4254445A (en) * | 1979-05-07 | 1981-03-03 | International Business Machines Corporation | Discretionary fly wire chip interconnection |
US4326180A (en) * | 1979-11-05 | 1982-04-20 | Microphase Corporation | Microwave backdiode microcircuits and method of making |
US4646142A (en) * | 1984-09-26 | 1987-02-24 | Rca Corporation | Method and apparatus for aligning solid-state imagers |
US4890157A (en) * | 1986-01-31 | 1989-12-26 | Texas Instruments Incorporated | Integrated circuit product having a polyimide film interconnection structure |
US4797780A (en) * | 1986-08-18 | 1989-01-10 | Siemens Aktiengesellschaft | Component with filled layers and electrical contacts and methods for its production |
US5055907A (en) * | 1989-01-25 | 1991-10-08 | Mosaic, Inc. | Extended integration semiconductor structure with wiring layers |
US5055425A (en) * | 1989-06-01 | 1991-10-08 | Hewlett-Packard Company | Stacked solid via formation in integrated circuit systems |
US5276289A (en) * | 1990-03-30 | 1994-01-04 | Hitachi, Ltd. | Electronic circuit device and method of producing the same |
US5371029A (en) * | 1991-01-22 | 1994-12-06 | National Semiconductor Corporation | Process for making a leadless chip resistor capacitor carrier using thick and thin film printing |
US5394010A (en) * | 1991-03-13 | 1995-02-28 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
US5285108A (en) * | 1991-06-21 | 1994-02-08 | Compaq Computer Corporation | Cooling system for integrated circuits |
US5319244A (en) * | 1991-12-13 | 1994-06-07 | International Business Machines Corporation | Triazine thin film adhesives |
US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5450109A (en) * | 1993-03-24 | 1995-09-12 | Hewlett-Packard Company | Barrier alignment and process monitor for TIJ printheads |
US5474458A (en) * | 1993-07-13 | 1995-12-12 | Fujitsu Limited | Interconnect carriers having high-density vertical connectors and methods for making the same |
US5625221A (en) * | 1994-03-03 | 1997-04-29 | Samsung Electronics Co., Ltd. | Semiconductor assembly for a three-dimensional integrated circuit package |
US5654121A (en) * | 1994-04-28 | 1997-08-05 | Agfa-Gevaert Ag | Positive-working radiation-sensitive mixture |
US5565113A (en) * | 1994-05-18 | 1996-10-15 | Xerox Corporation | Lithographically defined ejection units |
US5510273A (en) * | 1995-04-03 | 1996-04-23 | Xerox Corporation | Process of mounting semiconductor chips in a full-width-array image |
US6248942B1 (en) * | 1995-11-22 | 2001-06-19 | Gore Enterprise Holdings, Inc. | Strings for musical instruments |
US20020041026A1 (en) * | 1997-02-14 | 2002-04-11 | Ball Michael B. | Method and apparatus for routing die interconnections using intermediate connection elements secured to the die face |
US6123410A (en) * | 1997-10-28 | 2000-09-26 | Hewlett-Packard Company | Scalable wide-array inkjet printhead and method for fabricating same |
US6100594A (en) * | 1998-01-14 | 2000-08-08 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US6362117B1 (en) * | 1998-08-04 | 2002-03-26 | Texas Instruments Incorporated | Method of making integrated circuit with closely spaced components |
US20040104466A1 (en) * | 1998-09-21 | 2004-06-03 | Miller Joseph P. | Integrated circuit device/circuit board connection apparatus |
US20010014488A1 (en) * | 1998-10-06 | 2001-08-16 | Salman Akram | Multi chip semiconductor package and method of construction |
US6473966B1 (en) * | 1999-02-01 | 2002-11-05 | Casio Computer Co., Ltd. | Method of manufacturing ink-jet printer head |
US6163068A (en) * | 1999-04-22 | 2000-12-19 | Yao; Hsia Kuang | Multi-chip semiconductor encapsulation method and its finished product |
US6372539B1 (en) * | 2000-03-20 | 2002-04-16 | National Semiconductor Corporation | Leadless packaging process using a conductive substrate |
US20030036249A1 (en) * | 2001-08-06 | 2003-02-20 | Bauer Donald G. | Chip alignment and placement apparatus for integrated circuit, MEMS, photonic or other devices |
US7107562B2 (en) * | 2002-11-28 | 2006-09-12 | Infineon Technologies Ag | Method and apparatus for the arrangement of contact-making elements of components of an integrated circuit, computer-readable storage medium and program element |
US7005319B1 (en) * | 2004-11-19 | 2006-02-28 | International Business Machines Corporation | Global planarization of wafer scale package with precision die thickness control |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103561958A (en) * | 2011-05-31 | 2014-02-05 | 惠普发展公司,有限责任合伙企业 | Printhead die |
Also Published As
Publication number | Publication date |
---|---|
TW503453B (en) | 2002-09-21 |
US7163844B2 (en) | 2007-01-16 |
US6812564B1 (en) | 2004-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6366468B1 (en) | Self-aligned common carrier | |
Kamisuki et al. | A low power, small, electrostatically-driven commercial inkjet head | |
EP0822082B1 (en) | Ink-jet recording head, process for producing the head and ink-jet recording apparatus employing the head | |
CN1307053C (en) | Inkjet printhead having thermal bend actuator heating element electrically isolated from nozzle chamber ink | |
EP1179430B1 (en) | Print head and manufacturing method therefor | |
EP0434946A2 (en) | Ink jet printhead having ionic passivation of electrical circuitry | |
EP1432585B1 (en) | An adhesive-based ink jet print head assembly | |
US5396042A (en) | Anodic bonding process and method of producing an ink-jet print head using the same process | |
EP0955166B1 (en) | Thin film ink jet printhead | |
US6951383B2 (en) | Fluid ejection device having a substrate to filter fluid and method of manufacture | |
KR102247763B1 (en) | Overmolded ink delivery device | |
EP1177903B1 (en) | Liquid discharge recording head and liquid discharge recording apparatus | |
US6812564B1 (en) | Monolithic common carrier | |
US6209993B1 (en) | Structure and fabricating method for ink-jet printhead chip | |
CN108263097A (en) | Printhead chip and method of manufacturing the same | |
US6260952B1 (en) | Apparatus and method for routing power and ground lines in a ink-jet printhead | |
US6802595B2 (en) | Ink-jet recording head and ink-jet recording apparatus | |
US6749289B2 (en) | Liquid ejection apparatus and inkjet printer, and method of manufacturing them | |
EP0970812A1 (en) | Ink jet printhead with large size silicon wafer and relative manufacturing process | |
US5568176A (en) | Thermal print head and method of making the same | |
JP5159952B2 (en) | Liquid discharge recording head | |
JPH11138814A (en) | Ink-jet recording head | |
US5902492A (en) | Liquid jet recording head manufacturing method by anisotropic etching | |
JP4213268B2 (en) | Inkjet head | |
EP1186418A1 (en) | Manufacturing method for print head |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Expired due to failure to pay maintenance fee |
Effective date: 20150116 |