US20040038442A1 - Optically interactive device packages and methods of assembly - Google Patents

Optically interactive device packages and methods of assembly Download PDF

Info

Publication number
US20040038442A1
US20040038442A1 US10/228,411 US22841102A US2004038442A1 US 20040038442 A1 US20040038442 A1 US 20040038442A1 US 22841102 A US22841102 A US 22841102A US 2004038442 A1 US2004038442 A1 US 2004038442A1
Authority
US
United States
Prior art keywords
layer
electronic device
interactive electronic
carrier substrate
optically interactive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/228,411
Inventor
Larry Kinsman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/228,411 priority Critical patent/US20040038442A1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KINSMAN, LARRY D.
Publication of US20040038442A1 publication Critical patent/US20040038442A1/en
Priority to US11/103,019 priority patent/US7541658B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y10/00—Processes of additive manufacturing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y80/00—Products made by additive manufacturing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes

Definitions

  • the present invention relates to packaging of optically interactive electronic devices. More particularly, the present invention relates to a package for a solid-state image sensor and methods for simultaneously assembling a plurality of such packages.
  • Solid-state image sensors for example, charge coupled device (CCD) or complementary metal-oxide semiconductor (CMOS) chips
  • CCD charge coupled device
  • CMOS complementary metal-oxide semiconductor
  • CCD charge coupled device
  • CMOS complementary metal-oxide semiconductor
  • CCD charge coupled device
  • CMOS complementary metal-oxide semiconductor
  • These image sensor chips have been packaged within a discrete housing for protection from environmental stresses and to provide electrical communication with other components of the larger electronic device into which they are incorporated.
  • the typical housing is a unitary ceramic or plastic shell having a cavity into which an image sensor chip is mounted.
  • the chip is wire bonded to conductive elements within the cavity, and a window or at least partially optically transparent lid covers the cavity to allow light or other forms of electromagnetic radiation to pass through to sensing circuitry on the active surface of the chip.
  • the transparent lid may also be formed to provide an optical function such as focusing the light or other radiation and/or filtering selected wavelengths thereof.
  • the materials and structure involved with this packaging technique require a fabrication process that can be time consuming, costly and consist of several precision assembly steps. Due to the competitive nature of today's semiconductor industry, even a small reduction in packaging cost would be of great benefit, especially when considered in terms of the high volume of components being manufactured to meet growing demands.
  • U.S. Pat. No. 5,811,799 to Wu discloses an image sensor package formed by attaching a plurality of preformed or glue walls to an array of printed wiring frames having image sensors thereon and sealing the walls with transparent material. The printed wiring frames are then diced to form discrete packages. Once again, this arrangement may require the attachment or formation of multiple components during fabrication, and the disclosed printed wiring frames have a conductive via output arrangement that may not be suitable for certain high I/O image sensor chips.
  • a plurality of packages for image sensors and other optically interactive electronic devices are simultaneously fabricated to minimize assembly steps and reduce the cost associated with each individual package.
  • a carrier substrate is provided with an array of image sensor chip or other optically interactive electronic device attachment areas.
  • a layer of barrier material having apertures coinciding with the chip or device attachment areas is formed on, or secured to, the substrate surface to create an array of cavities, each sized and configured for containing an image sensor chip or other optically interactive electronic device.
  • An image sensor chip or other optically interactive electronic device is mounted within each cavity and wire bonded to conductive traces on the carrier substrate.
  • a unitary, at least partially optically transparent cover is then sealed in place over the unitary layer of barrier material.
  • the assembly is cut or otherwise divided along lines running between adjacent cavities to form a plurality of individual packages. If required, the packages may then proceed through additional fabrication steps such as solder ball attachment or castellated pad formation, or these steps may be completed prior to dividing the assembly into individual packages.
  • optically interactive as used herein is meant to encompass devices sensitive to various wavelengths of light or other forms of radiation, including, but not limited to, CCD and CMOS image sensors, EPROM's, and photodiodes, as well as light-emitting devices including semiconductor lasers and light-emitting diodes.
  • FIG. 1 is a top view of a carrier substrate according to the present invention having an array of image sensor chip attachment areas.
  • FIG. 2 is a side view of the carrier substrate of FIG. 1 having a layer of barrier material formed on its top surface.
  • FIGS. 3A through 3C are schematic sectional side views showing a first method for forming the layer of barrier material depicted in FIG. 2 by molding it onto the carrier substrate.
  • FIG. 3D is a top view of the carrier substrate depicted in FIG. 1 after the addition of the layer of barrier material.
  • FIGS. 4A and 4B are partial sectional side views showing a second method for forming the layer of barrier material depicted in FIG. 2 by depositing layers of a cure-hardened liquid onto the carrier substrate.
  • FIGS. 5A and 5B are sectional side views showing a third method for forming the layer of barrier material depicted in FIG. 2 by using stereolithography.
  • FIGS. 6 and 7 are perspective views showing a fourth method for forming the layer of barrier material depicted in FIG. 2 by attaching a preformed unitary frame to the carrier substrate.
  • FIG. 8 is a sectional side view showing image sensor chips mounted and wire bonded within chip cavities formed by the carrier substrate and the layer of barrier material.
  • FIG. 9 is a sectional side view showing a unitary transparent cover sealed to the assembly depicted in FIG. 8
  • FIG. 10 is a perspective view of an image sensor array prior to singulation.
  • FIG. 11 is a perspective view of an individual image sensor package which has been separated from the image sensor array depicted in FIG. 10.
  • FIG. 12 is a sectional side view of the image sensor package depicted in FIG. 11, wherein castellated solder pads have been added to form a leadless chip carrier.
  • FIG. 13 is a side sectional view of the image sensor package depicted in FIG. 11, wherein an array of discrete conductive elements has been added to form a ball grid array package.
  • a carrier substrate 2 shown in FIG. 1, is provided with an array of image sensor chip attachment areas 4 formed on its top surface 6 .
  • Broken section lines 100 are shown running in mutually perpendicular horizontal and vertical directions on top surface 6 to indicate the boundary between adjacent image sensor chip attachment areas 4 .
  • Carrier substrate 2 may be a printed circuit board (PCB) having conductive traces 8 (see FIGS. 12 and 13) thereon, and may be formed using conventional PCB fabrication techniques.
  • PCB printed circuit board
  • Carrier substrate 2 may be constructed with common PCB materials such as a BT resin or FR-4 or FR-5 laminate in order to reduce cost, but other materials such as silicon, ceramics or plastics may be used as well.
  • Each image sensor chip attachment area 4 includes a chip adherence surface 9 bounded by a plurality of wire bonding locations 10 for wire bonding to conductive traces 8 , one of which is shown in broken lines in FIG. 1, conductive traces 8 extending to locations for electrical connection of the completed image sensor package to higher-level packaging, such as a circuit board, for operation.
  • the length, orientation and configuration of conductive traces 8 may be as desired, depending on the I/O format used to connect the completed image sensor package, and so will not be discussed further at this juncture.
  • a layer of barrier material 12 having apertures 14 therein coinciding with image sensor chip attachment areas 4 is then formed on, or secured to, the carrier substrate top surface 6 , as illustrated in FIG. 2.
  • layer of barrier material 12 is formed from a mold compound 16 which is molded directly onto top surface 6 .
  • FIGS. 3A through 3C This method is depicted in FIGS. 3A through 3C.
  • a transfer molding tool or platen 18 including contiguous mold cavities 20 is placed in sealing relationship against top surface 6 of carrier substrate 2 with mold cavities 20 positioned over the perimeter of carrier substrate 2 and over areas coinciding with, and preferably bisected by, section lines 100 defining boundaries between adjacent image sensor chip attachment areas 4 .
  • FIG. 3A a transfer molding tool or platen 18 including contiguous mold cavities 20 is placed in sealing relationship against top surface 6 of carrier substrate 2 with mold cavities 20 positioned over the perimeter of carrier substrate 2 and over areas coinciding with, and preferably bisected by, section lines 100 defining boundaries between adjacent image sensor chip attachment areas 4 .
  • FIG. 3B shows that a liquified or otherwise molten mold compound 16 , such as a thermoplastic, silicon-filled polymer, is rapidly transferred under pressure from a reservoir 22 into mold cavities 20 via a plurality of runners 24 , the general process of transfer molding being well known in the art.
  • the mold compound 16 then cures and hardens as it cools, and molding tool 18 is removed from the top surface 6 of carrier substrate 2 , leaving the structure as seen in FIG. 3C.
  • the cured mold compound 16 comprises a contiguous matrix of raised walls 26 that surround each image sensor chip attachment area 4 to define apertures 14 , leaving the portion of image sensor chip attachment areas 4 containing chip adherence surface 9 and wire bonding locations 10 exposed, creating an array of chip cavities 28 sized and configured for receiving image sensor chips 52 , which are described in further detail below.
  • FIG. 3D is a top view of carrier substrate 2 showing the arrangement of raised walls 26 surrounding chip attachment areas 4 .
  • mold compound 16 may be a thermoplastic polymer or other suitable encapsulant material as known in the art. Further, a filler material such as fine silicon particles may be incorporated within the mold compound to reduce cost, also as known in the art. It should also be understood that while the present invention is described in terms of transfer molding, other molding techniques such as injection molding or pot molding could be used with an appropriately formulated mold compound. Other suitable materials for mold compounds as known in the art include, without limitation, thermoset polymers and epoxy compounds.
  • Another approach to forming a layer of barrier material 12 onto top surface 6 includes disposing a flowable material on top surface 6 in one or more sequentially cured layers to build the contiguous matrix of raised walls 26 .
  • a high-viscosity liquid or gel 30 is dispensed from a nozzle 32 around the perimeter of carrier substrate 2 and along section lines 100 (not shown). The high-viscosity liquid or gel 30 is then cured to form a first hardened layer 34 .
  • FIG. 4B an additional layer of high-viscosity liquid or gel 30 is dispensed over first hardened layer 34 and cured to form second hardened layer 36 .
  • Liquid or gel 30 may comprise an activated epoxy or any other curable resin-type material that may be hardened by reaction of constituents thereof, application of heat thereto, or otherwise as known in the art.
  • STL stereolithographic
  • STL involves the formation of solid structures by selectively curing portions of volumes of a liquid polymer or resin material contained within a tank or reservoir. Depending on the liquid material composition, curing may be accomplished by exposure to irradiation with selected wavelengths of light or other electromagnetic radiation, for instance, when curing a material susceptible to initiation of cross-linking by exposure to ultraviolet (UV) radiation, such as through use of a UV laser beam.
  • UV radiation ultraviolet
  • FIGS. 5A and 5B illustrate this technique.
  • carrier substrate 2 is placed to a selected depth below the surface of a photocurable liquid 38 contained within a reservoir 40 .
  • the use of a photocurable liquid 38 is only exemplary, and liquid materials cured by other activating agents could also be used.
  • a focused beam of light such as a laser beam 42 is directed over the surface of photocurable liquid 38 in a pattern that coincides with the perimeter of carrier substrate 2 and section lines 100 between image sensor chip attachment areas 4 .
  • FIG. 5B shows that carrier substrate 2 may then be lowered another selected depth within reservoir 40 , and the beam of light 42 directed over the same pattern to form a second layer of cured material 46 on top of the first layer 44 .
  • subsequent layers may be added until the desired height for layer of barrier material 12 is reached.
  • Complete and accelerated curing of the photocurable material may be effected by devoted temperatures after cross-linking is initiated.
  • Suitable equipment for forming a barrier layer as described is commercially available from 3D Systems, Inc. of Valencia, Calif.
  • Suitable photocurable liquids which may be used with the 3D Systems, Inc. equipment is available from Ciba Specialty Chemicals Corporation.
  • FIG. 6 shows an exemplary preformed unitary frame 48 used for this purpose.
  • Unitary frame 48 may be preformed by one of the previously described molding techniques, or may be formed from a sheet of solid material such as a plastic, silicon or green ceramic by removal of selected portions thereof.
  • the array of apertures 14 may be directly molded into unitary frame 48 .
  • apertures 14 may be cut, stamped, milled or etched into a sheet of material, the process employed being dictated by the material selected.
  • unitary frame 48 may be secured to top surface 6 of carrier substrate 2 with an adhesive material 50 , as illustrated in FIG. 7.
  • Adhesive material 50 may be in the form of an epoxy, a silicone, an acrylic or other liquid-type adhesive applied to top surface 6 and/or unitary frame 48 , or may comprise a double-sided adhesive-coated tape segment or film, such as a polyimide.
  • a two-component resin may be employed, with one component applied in an appropriate pattern to top surface 6 of carrier substrate 2 and the other to a surface of frame 48 to be placed in contact with top surface 6 to prevent premature component reaction and adhesion.
  • an image sensor chip 52 is mounted within each of the chip cavities 28 on chip adherence surface 9 .
  • Image sensor chips 52 are secured to chip adherence surface 9 with a layer of adhesive material 54 , as shown in FIG. 8.
  • the layer of adhesive material 54 may be an epoxy, a silicone, an acrylic or other liquid-type adhesive, a two-component resin, or a double-sided adhesive-coated tape segment or film.
  • adhesive material 54 may comprise a conductive adhesive or bonding agent to ground or electrically bias the back side of image sensor chips 52 , in which instance a conductive or conductor-filled epoxy, a silver solder or a Z-axis anisotropic conductive adhesive may be employed. If a preformed frame 48 is used for layer of barrier material 12 and raised walls 26 , adhesive material 50 and the layer of adhesive material 54 may be applied to top surface 6 of carrier substrate 2 at the same time, in a single step, before preformed frame 48 is aligned with carrier substrate 2 and placed on top surface 6 .
  • bond pads 56 on the active surface 58 of each image sensor chip 52 are connected to wire bonding locations 10 on top surface 6 with gold or aluminum wire bonds 60 , as known in the art. It is contemplated that, if a preformed frame 48 is used for layer of barrier material 12 , image sensor chips 52 may be placed, wire bonds 60 formed, and then preformed frame 48 carrying adhesive on the surface thereof facing top surface 6 of carrier substrate 2 aligned and adhered to top surface 6 to provide enhanced clearance for a wire bonding capillary.
  • Unitary transparent cover 62 is configured to substantially conform to the configuration of carrier substrate 2 , so that it covers the entire array of chip cavities 28 and extends over the peripherally outer portions of the contiguous matrix of raised walls 26 . Stated another way, unitary transparent cover 62 is dimensioned substantially the same as carrier substrate 2 , such term including both slightly smaller and slightly larger dimensions. In FIG. 9, unitary transparent cover 62 is aligned with carrier substrate 2 , placed on the top of the layer of barrier material 12 and continuously sealed in place along the tops of the matrix of raised walls 26 . Unitary transparent cover 62 may be formed of an at least partially optically transparent material such as borosilicate glass (BSG).
  • BSG borosilicate glass
  • unitary transparent cover 62 may be formed to provide an optical function, for example, shaping its surface at locations corresponding to chip cavities 28 to act as focusing microlenses, as shown in broken lines 65 .
  • a bead of epoxy, silicone gel or other liquid or gel adhesive 64 may be applied to the tops of raised walls 26 of the layer of barrier material 12 , directly to unitary transparent cover 62 along selected lines, or both, prior to attachment.
  • a two-component adhesive resin may be employed, with one component applied to the tops of raised walls 26 and the other to unitary transparent cover 62 so that a cure will not commence until the two components are in contact.
  • Other sealing mechanisms such as the previously described double-sided adhesive-coated tape, may be used as well, as long as they provide a suitable hermetic bond.
  • any adhesive used be of a type which does not outgas volatiles or other compounds when curing, so as not to compromise the properties of the image sensor chips 52 .
  • a snap-cure epoxy as known in the art, may be suitable, as may an epoxy cured to a B-stage, or tacky state, prior to application of unitary transparent cover 62 .
  • the layer of barrier material 12 may be of a composition such that a thermal- or pressure-initiated bonding process may be used to adhere unitary transparent cover 62 directly to layer of barrier material 12 without the aid of an additional adhesive. As seen in FIG.
  • a vertical gap 63 exists between active surfaces 58 of image sensor chips 52 and unitary transparent cover 62 .
  • active surface 58 it is often a requirement that active surface 58 be free of contact from any covering material to prevent interference with sensing circuitry and unwanted refraction of light. Accordingly, when one of these high-end image sensor chips is packaged using the present invention, gap 63 will be left free of any filler material. Gap 63 also maintains unitary transparent cover 62 above the tops of wire bonds 60 . If an image sensor chip 52 not having the requirement of a material-free gap is used, a transparent encapsulant material 67 may be used to fill chip cavities 28 .
  • Such transparent encapsulant material 67 which is indicated by a broken lead line extending into chip cavity 28 in FIG. 9, may also be used to provide a transitional index of refraction between the image sensor and the index of refraction of the unitary transparent cover 62 , if desired. This approach would also secure and protect wire bonds 60 , and the transparent encapsulant material 67 may also be used as the adhesive mechanism for securing unitary transparent cover 62 .
  • Example materials for transparent encapsulant material 67 may include clear epoxy, silicone, acrylic or other suitably transparent resin type materials.
  • a raised lip 66 may be formed around the perimeter of the layer of barrier material 12 , as shown in FIG. 9. Raised lip 66 may be formed integrally with, and at the same time as, forming the layer of barrier material 12 by any previously described technique. Unitary transparent cover 62 may then be aligned with the layer of barrier material 12 by placement within raised lip 66 .
  • FIG. 10 is a perspective view of image sensor package array 68 , having the location of section lines 100 indicated above the top surface thereof.
  • Carrier substrate 2 , the layer of barrier material 12 and unitary transparent cover 62 are simultaneously cut along section lines 100 which run along the centers of raised walls 26 and divide image sensor package array 68 into individual image sensor packages 70 , as shown in FIG. 11.
  • This may be accomplished, for example, by cutting or scribing (followed by snapping image sensor packages 70 apart along the scribe lines) with a conventional wafer saw.
  • the individual image sensor packages 70 may be singulated using a laser or other high energy beam.
  • metallized pads or other contact interfaces for electrical communication of image sensor chip 52 through conductive traces 8 are required.
  • a plurality of castellated solder pads 72 in respective communication with different traces 8 may be formed by techniques known in the art around the perimeter of a singulated image sensor package 70 to form a leadless chip-carrier (LCC) image sensor package.
  • LCC leadless chip-carrier
  • discrete conductive elements 74 such as tin/lead solder balls, gold bumps or conductive or conductor-filled epoxy bumps, columns or pillars may be formed on or attached to the lower ends of vias 76 extending from conductive traces 8 in an array pattern on the bottom of singulated image sensor package 70 to form a ball-grid array (BGA)-type image sensor package, as illustrated by FIG. 13.
  • a redistribution layer (RDL) of conductive traces 78 may also be applied to or formed on the bottom surface 80 of carrier substrate 2 in communication with the lower ends of selected vias 76 to configure a suitable pad array for formation or disposition of discrete conductive elements 74 thereon.
  • discrete conductive elements 74 be attached to image sensor package array 68 prior to its singulation into individual image sensor packages 70 . This would be advantageous as discrete conductive elements 74 may thus be formed on or applied to all of the image sensor packages 70 of a given image sensor package array in a single step.
  • unitary transparent cover 62 and barrier material 12 would then be secured to the top surface 6 of carrier substrate 2 after attachment and electrical connection of image sensor chips 52 to image sensor chip attachment areas 4 .
  • securing and hermetic sealing of barrier material 12 to carrier substrate 2 may be accomplished with a bead of epoxy, silicone or other liquid or gel adhesive, double-sided adhesive-coated tape or thermal or pressure initiated bonding.

Abstract

An image sensor package and methods for simultaneously fabricating a plurality of such packages. A layer of barrier material comprising a matrix of raised walls is formed around chip attachment areas located in an array on a carrier substrate to create chip cavities. Image sensor chips are wire bonded within the chip cavities, and a unitary transparent cover is sealed in place over the entire assembly. The resultant image sensor package array is then singulated along lines running between the chip attachment areas and in parallel to the raised walls to provide individual image sensor packages. The layer of barrier material may be formed directly on the carrier substrate by molding methods or by depositing a series of curable layers of liquid or flowable material in a stacked fashion. Alternatively, the layer of barrier material may be preformed as a unitary frame and then secured to the carrier substrate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to packaging of optically interactive electronic devices. More particularly, the present invention relates to a package for a solid-state image sensor and methods for simultaneously assembling a plurality of such packages. [0002]
  • 2. State of the Art [0003]
  • Solid-state image sensors, for example, charge coupled device (CCD) or complementary metal-oxide semiconductor (CMOS) chips, are increasingly in demand for incorporation into electronic devices. They may be used for a variety of applications including consumer electronics like digital cameras, cellular telephones and hand-held scanners. Conventionally, these image sensor chips have been packaged within a discrete housing for protection from environmental stresses and to provide electrical communication with other components of the larger electronic device into which they are incorporated. The typical housing is a unitary ceramic or plastic shell having a cavity into which an image sensor chip is mounted. The chip is wire bonded to conductive elements within the cavity, and a window or at least partially optically transparent lid covers the cavity to allow light or other forms of electromagnetic radiation to pass through to sensing circuitry on the active surface of the chip. The transparent lid may also be formed to provide an optical function such as focusing the light or other radiation and/or filtering selected wavelengths thereof. The materials and structure involved with this packaging technique require a fabrication process that can be time consuming, costly and consist of several precision assembly steps. Due to the competitive nature of today's semiconductor industry, even a small reduction in packaging cost would be of great benefit, especially when considered in terms of the high volume of components being manufactured to meet growing demands. [0004]
  • In response to large-scale production requirements, various attempts have been made to simplify the construction of image sensor packaging. U.S. Pat. No. 6,351,027 to Giboney et al. and U.S. Pat. No. 6,285,064 to Foster, for instance, disclose wafer-level packaging formed by laying a solid sidewall piece or an adhesive matrix over a wafer having an array of sensor devices and covering it with a transparent top piece. The wafer is then singulated to create discrete chip-scale packages. While this approach reduces material costs and assembly steps, it does not completely protect the semiconductor chips from the environment and requires attaching material directly to the wafer surface, which could damage the sensor devices. U.S. Pat. No. 6,266,197 to Glenn et al. discloses a method for forming image sensor packages wherein an array of image sensors is wire bonded to a carrier substrate, and a molded window array is placed over the array of image sensors. The substrate and attached molded window array are then singulated to form a plurality of individual image sensor packages. The molded window array of Glenn et al., however, still suffers from the fact that individual transparent windows must be formed within or later attached to the molded array, requiring additional assembly and alignment steps during fabrication. U.S. Pat. No. 5,811,799 to Wu discloses an image sensor package formed by attaching a plurality of preformed or glue walls to an array of printed wiring frames having image sensors thereon and sealing the walls with transparent material. The printed wiring frames are then diced to form discrete packages. Once again, this arrangement may require the attachment or formation of multiple components during fabrication, and the disclosed printed wiring frames have a conductive via output arrangement that may not be suitable for certain high I/O image sensor chips. [0005]
  • As is evident from the foregoing description of the state of the art, what is needed is a simplified method for forming an image sensor package that is conducive to mass production while still offering suitable and robust protection for an image sensor chip. [0006]
    • BRIEF SUMMARY OF THE INVENTION
  • In accordance with the present invention, a plurality of packages for image sensors and other optically interactive electronic devices are simultaneously fabricated to minimize assembly steps and reduce the cost associated with each individual package. A carrier substrate is provided with an array of image sensor chip or other optically interactive electronic device attachment areas. A layer of barrier material having apertures coinciding with the chip or device attachment areas is formed on, or secured to, the substrate surface to create an array of cavities, each sized and configured for containing an image sensor chip or other optically interactive electronic device. An image sensor chip or other optically interactive electronic device is mounted within each cavity and wire bonded to conductive traces on the carrier substrate. A unitary, at least partially optically transparent cover is then sealed in place over the unitary layer of barrier material. Next, the assembly is cut or otherwise divided along lines running between adjacent cavities to form a plurality of individual packages. If required, the packages may then proceed through additional fabrication steps such as solder ball attachment or castellated pad formation, or these steps may be completed prior to dividing the assembly into individual packages. [0007]
  • While described primarily in terms of an image sensor package, it is to be understood that the present invention may be used for packaging various other optically interactive electronic devices which require a window for access to a device surface. The term “optically interactive” as used herein is meant to encompass devices sensitive to various wavelengths of light or other forms of radiation, including, but not limited to, CCD and CMOS image sensors, EPROM's, and photodiodes, as well as light-emitting devices including semiconductor lasers and light-emitting diodes. [0008]
  • Other and further features and advantages will be apparent from the following detailed description of the present invention when read in conjunction with the accompanying drawings. It should be understood that the described embodiments are provided for illustrative and exemplary purposes only, and that variations to, and combinations of, the several elements and features thereof are contemplated as being within the scope of the invention.[0009]
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention: [0010]
  • FIG. 1 is a top view of a carrier substrate according to the present invention having an array of image sensor chip attachment areas. [0011]
  • FIG. 2 is a side view of the carrier substrate of FIG. 1 having a layer of barrier material formed on its top surface. [0012]
  • FIGS. 3A through 3C are schematic sectional side views showing a first method for forming the layer of barrier material depicted in FIG. 2 by molding it onto the carrier substrate. [0013]
  • FIG. 3D is a top view of the carrier substrate depicted in FIG. 1 after the addition of the layer of barrier material. [0014]
  • FIGS. 4A and 4B are partial sectional side views showing a second method for forming the layer of barrier material depicted in FIG. 2 by depositing layers of a cure-hardened liquid onto the carrier substrate. [0015]
  • FIGS. 5A and 5B are sectional side views showing a third method for forming the layer of barrier material depicted in FIG. 2 by using stereolithography. [0016]
  • FIGS. 6 and 7 are perspective views showing a fourth method for forming the layer of barrier material depicted in FIG. 2 by attaching a preformed unitary frame to the carrier substrate. [0017]
  • FIG. 8 is a sectional side view showing image sensor chips mounted and wire bonded within chip cavities formed by the carrier substrate and the layer of barrier material. [0018]
  • FIG. 9 is a sectional side view showing a unitary transparent cover sealed to the assembly depicted in FIG. 8 [0019]
  • FIG. 10 is a perspective view of an image sensor array prior to singulation. [0020]
  • FIG. 11 is a perspective view of an individual image sensor package which has been separated from the image sensor array depicted in FIG. 10. [0021]
  • FIG. 12 is a sectional side view of the image sensor package depicted in FIG. 11, wherein castellated solder pads have been added to form a leadless chip carrier. [0022]
  • FIG. 13 is a side sectional view of the image sensor package depicted in FIG. 11, wherein an array of discrete conductive elements has been added to form a ball grid array package.[0023]
    • DETAILED DESCRIPTION OF THE INVENTION
  • Referring in general to the accompanying drawings, various aspects of the present invention are illustrated to show exemplary image sensor package structures and methods for assembly of a package for housing an image sensor chip. Common elements of the illustrated embodiments are designated with like reference numerals. It should be understood that the figures presented are not meant to be illustrative of actual views of any particular portion of a particular image sensor package structure, but are merely idealized schematic representations which are employed to more clearly and fully depict the invention. It should further be understood that while depicted in terms of an image sensor, the package embodiments and methods presented herein would work equally well for housing other types of optically interactive electronic devices as described above. [0024]
  • Turning to FIGS. 1 through 13, methods for simultaneously assembling a plurality of image sensor packages according to the present invention are illustrated. A [0025] carrier substrate 2, shown in FIG. 1, is provided with an array of image sensor chip attachment areas 4 formed on its top surface 6. Broken section lines 100 are shown running in mutually perpendicular horizontal and vertical directions on top surface 6 to indicate the boundary between adjacent image sensor chip attachment areas 4. Carrier substrate 2 may be a printed circuit board (PCB) having conductive traces 8 (see FIGS. 12 and 13) thereon, and may be formed using conventional PCB fabrication techniques. Carrier substrate 2 may be constructed with common PCB materials such as a BT resin or FR-4 or FR-5 laminate in order to reduce cost, but other materials such as silicon, ceramics or plastics may be used as well. Each image sensor chip attachment area 4 includes a chip adherence surface 9 bounded by a plurality of wire bonding locations 10 for wire bonding to conductive traces 8, one of which is shown in broken lines in FIG. 1, conductive traces 8 extending to locations for electrical connection of the completed image sensor package to higher-level packaging, such as a circuit board, for operation. The length, orientation and configuration of conductive traces 8 may be as desired, depending on the I/O format used to connect the completed image sensor package, and so will not be discussed further at this juncture.
  • A layer of [0026] barrier material 12 having apertures 14 therein coinciding with image sensor chip attachment areas 4 is then formed on, or secured to, the carrier substrate top surface 6, as illustrated in FIG. 2. In a currently preferred embodiment of the present invention, layer of barrier material 12 is formed from a mold compound 16 which is molded directly onto top surface 6. This method is depicted in FIGS. 3A through 3C. As shown in FIG. 3A, a transfer molding tool or platen 18 including contiguous mold cavities 20 is placed in sealing relationship against top surface 6 of carrier substrate 2 with mold cavities 20 positioned over the perimeter of carrier substrate 2 and over areas coinciding with, and preferably bisected by, section lines 100 defining boundaries between adjacent image sensor chip attachment areas 4. FIG. 3B shows that a liquified or otherwise molten mold compound 16, such as a thermoplastic, silicon-filled polymer, is rapidly transferred under pressure from a reservoir 22 into mold cavities 20 via a plurality of runners 24, the general process of transfer molding being well known in the art. The mold compound 16 then cures and hardens as it cools, and molding tool 18 is removed from the top surface 6 of carrier substrate 2, leaving the structure as seen in FIG. 3C. The cured mold compound 16 comprises a contiguous matrix of raised walls 26 that surround each image sensor chip attachment area 4 to define apertures 14, leaving the portion of image sensor chip attachment areas 4 containing chip adherence surface 9 and wire bonding locations 10 exposed, creating an array of chip cavities 28 sized and configured for receiving image sensor chips 52, which are described in further detail below. FIG. 3D is a top view of carrier substrate 2 showing the arrangement of raised walls 26 surrounding chip attachment areas 4.
  • As noted above, [0027] mold compound 16 may be a thermoplastic polymer or other suitable encapsulant material as known in the art. Further, a filler material such as fine silicon particles may be incorporated within the mold compound to reduce cost, also as known in the art. It should also be understood that while the present invention is described in terms of transfer molding, other molding techniques such as injection molding or pot molding could be used with an appropriately formulated mold compound. Other suitable materials for mold compounds as known in the art include, without limitation, thermoset polymers and epoxy compounds.
  • Another approach to forming a layer of [0028] barrier material 12 onto top surface 6 includes disposing a flowable material on top surface 6 in one or more sequentially cured layers to build the contiguous matrix of raised walls 26. In one exemplary embodiment of this method shown in FIG. 4A, a high-viscosity liquid or gel 30 is dispensed from a nozzle 32 around the perimeter of carrier substrate 2 and along section lines 100 (not shown). The high-viscosity liquid or gel 30 is then cured to form a first hardened layer 34. In FIG. 4B, an additional layer of high-viscosity liquid or gel 30 is dispensed over first hardened layer 34 and cured to form second hardened layer 36. Subsequent layers of liquid or gel 30 may be added, as desired, until the desired height for layer of barrier material 12 is reached. Liquid or gel 30 may comprise an activated epoxy or any other curable resin-type material that may be hardened by reaction of constituents thereof, application of heat thereto, or otherwise as known in the art.
  • Another exemplary embodiment of this layering approach exists in using a stereolithographic (STL) deposition process to form the contiguous matrix of raised [0029] walls 26 on top surface 6. As defined in the art, STL involves the formation of solid structures by selectively curing portions of volumes of a liquid polymer or resin material contained within a tank or reservoir. Depending on the liquid material composition, curing may be accomplished by exposure to irradiation with selected wavelengths of light or other electromagnetic radiation, for instance, when curing a material susceptible to initiation of cross-linking by exposure to ultraviolet (UV) radiation, such as through use of a UV laser beam. By curing one or more successive layers of the liquid material, intricate solid structures of almost any shape may be formed. It is also possible to add elements to an existing structure using STL, as would be the case with the present invention. FIGS. 5A and 5B illustrate this technique. In FIG. 5A, carrier substrate 2 is placed to a selected depth below the surface of a photocurable liquid 38 contained within a reservoir 40. The use of a photocurable liquid 38 is only exemplary, and liquid materials cured by other activating agents could also be used. A focused beam of light such as a laser beam 42 is directed over the surface of photocurable liquid 38 in a pattern that coincides with the perimeter of carrier substrate 2 and section lines 100 between image sensor chip attachment areas 4. The portions of the photocurable liquid 38 exposed to laser beam 42 cures to at least a semisolid state, forming a first layer of cured material 44 on top surface 6. FIG. 5B shows that carrier substrate 2 may then be lowered another selected depth within reservoir 40, and the beam of light 42 directed over the same pattern to form a second layer of cured material 46 on top of the first layer 44. As with the previous dispensing embodiment, subsequent layers may be added until the desired height for layer of barrier material 12 is reached. Complete and accelerated curing of the photocurable material may be effected by devoted temperatures after cross-linking is initiated. Suitable equipment for forming a barrier layer as described is commercially available from 3D Systems, Inc. of Valencia, Calif. Suitable photocurable liquids which may be used with the 3D Systems, Inc. equipment is available from Ciba Specialty Chemicals Corporation.
  • In certain situations, it may be desirable to preform the layer of [0030] barrier material 12 defined by raised walls 26 and then secure it to carrier substrate 2. FIG. 6 shows an exemplary preformed unitary frame 48 used for this purpose. Unitary frame 48 may be preformed by one of the previously described molding techniques, or may be formed from a sheet of solid material such as a plastic, silicon or green ceramic by removal of selected portions thereof. In the case of molding, the array of apertures 14 may be directly molded into unitary frame 48. When formed from a solid material, apertures 14 may be cut, stamped, milled or etched into a sheet of material, the process employed being dictated by the material selected. Once completed, unitary frame 48 may be secured to top surface 6 of carrier substrate 2 with an adhesive material 50, as illustrated in FIG. 7. Adhesive material 50 may be in the form of an epoxy, a silicone, an acrylic or other liquid-type adhesive applied to top surface 6 and/or unitary frame 48, or may comprise a double-sided adhesive-coated tape segment or film, such as a polyimide. Alternatively, a two-component resin may be employed, with one component applied in an appropriate pattern to top surface 6 of carrier substrate 2 and the other to a surface of frame 48 to be placed in contact with top surface 6 to prevent premature component reaction and adhesion.
  • After formation or attachment of the layer of [0031] barrier material 12 on top surface 6, an image sensor chip 52 is mounted within each of the chip cavities 28 on chip adherence surface 9. Image sensor chips 52 are secured to chip adherence surface 9 with a layer of adhesive material 54, as shown in FIG. 8. As with adhesive material 50, the layer of adhesive material 54 may be an epoxy, a silicone, an acrylic or other liquid-type adhesive, a two-component resin, or a double-sided adhesive-coated tape segment or film. If required or desired, adhesive material 54 may comprise a conductive adhesive or bonding agent to ground or electrically bias the back side of image sensor chips 52, in which instance a conductive or conductor-filled epoxy, a silver solder or a Z-axis anisotropic conductive adhesive may be employed. If a preformed frame 48 is used for layer of barrier material 12 and raised walls 26, adhesive material 50 and the layer of adhesive material 54 may be applied to top surface 6 of carrier substrate 2 at the same time, in a single step, before preformed frame 48 is aligned with carrier substrate 2 and placed on top surface 6. Once image sensor chips 52 are in place, bond pads 56 on the active surface 58 of each image sensor chip 52 are connected to wire bonding locations 10 on top surface 6 with gold or aluminum wire bonds 60, as known in the art. It is contemplated that, if a preformed frame 48 is used for layer of barrier material 12, image sensor chips 52 may be placed, wire bonds 60 formed, and then preformed frame 48 carrying adhesive on the surface thereof facing top surface 6 of carrier substrate 2 aligned and adhered to top surface 6 to provide enhanced clearance for a wire bonding capillary.
  • The resulting assembly is now ready to receive a unitary [0032] transparent cover 62. Unitary transparent cover 62 is configured to substantially conform to the configuration of carrier substrate 2, so that it covers the entire array of chip cavities 28 and extends over the peripherally outer portions of the contiguous matrix of raised walls 26. Stated another way, unitary transparent cover 62 is dimensioned substantially the same as carrier substrate 2, such term including both slightly smaller and slightly larger dimensions. In FIG. 9, unitary transparent cover 62 is aligned with carrier substrate 2, placed on the top of the layer of barrier material 12 and continuously sealed in place along the tops of the matrix of raised walls 26. Unitary transparent cover 62 may be formed of an at least partially optically transparent material such as borosilicate glass (BSG). Of course, other types of glass, quartz or even plastic which allow the passage of a desired range of wavelengths of light or other forms of electromagnetic radiation may also be used. Furthermore, unitary transparent cover 62 may be formed to provide an optical function, for example, shaping its surface at locations corresponding to chip cavities 28 to act as focusing microlenses, as shown in broken lines 65.
  • To secure unitary [0033] transparent cover 62 in place along the tops of raised walls 26 and hermetically seal the image sensor chips 52 within each respective chip cavity 28, a bead of epoxy, silicone gel or other liquid or gel adhesive 64 may be applied to the tops of raised walls 26 of the layer of barrier material 12, directly to unitary transparent cover 62 along selected lines, or both, prior to attachment. If desired, a two-component adhesive resin may be employed, with one component applied to the tops of raised walls 26 and the other to unitary transparent cover 62 so that a cure will not commence until the two components are in contact. Other sealing mechanisms, such as the previously described double-sided adhesive-coated tape, may be used as well, as long as they provide a suitable hermetic bond. It is desirable, so that the optical capabilities of image chip sensors 52 are not compromised, that any adhesive used be of a type which does not outgas volatiles or other compounds when curing, so as not to compromise the properties of the image sensor chips 52. A snap-cure epoxy, as known in the art, may be suitable, as may an epoxy cured to a B-stage, or tacky state, prior to application of unitary transparent cover 62. In some instances, the layer of barrier material 12 may be of a composition such that a thermal- or pressure-initiated bonding process may be used to adhere unitary transparent cover 62 directly to layer of barrier material 12 without the aid of an additional adhesive. As seen in FIG. 9, a vertical gap 63 exists between active surfaces 58 of image sensor chips 52 and unitary transparent cover 62. For high-end image sensor chips 52, it is often a requirement that active surface 58 be free of contact from any covering material to prevent interference with sensing circuitry and unwanted refraction of light. Accordingly, when one of these high-end image sensor chips is packaged using the present invention, gap 63 will be left free of any filler material. Gap 63 also maintains unitary transparent cover 62 above the tops of wire bonds 60. If an image sensor chip 52 not having the requirement of a material-free gap is used, a transparent encapsulant material 67 may be used to fill chip cavities 28. Such transparent encapsulant material 67, which is indicated by a broken lead line extending into chip cavity 28 in FIG. 9, may also be used to provide a transitional index of refraction between the image sensor and the index of refraction of the unitary transparent cover 62, if desired. This approach would also secure and protect wire bonds 60, and the transparent encapsulant material 67 may also be used as the adhesive mechanism for securing unitary transparent cover 62. Example materials for transparent encapsulant material 67 may include clear epoxy, silicone, acrylic or other suitably transparent resin type materials.
  • In order to promote proper alignment of unitary [0034] transparent cover 62, a raised lip 66 may be formed around the perimeter of the layer of barrier material 12, as shown in FIG. 9. Raised lip 66 may be formed integrally with, and at the same time as, forming the layer of barrier material 12 by any previously described technique. Unitary transparent cover 62 may then be aligned with the layer of barrier material 12 by placement within raised lip 66.
  • Once unitary [0035] transparent cover 62 is sealed in place, the assembly essentially comprises an image sensor package array 68. Image sensor package array 68 may now be cut or otherwise singulated to separate out individual image sensor packages. FIGS. 10 and 11 illustrate this process. FIG. 10 is a perspective view of image sensor package array 68, having the location of section lines 100 indicated above the top surface thereof. Carrier substrate 2, the layer of barrier material 12 and unitary transparent cover 62 are simultaneously cut along section lines 100 which run along the centers of raised walls 26 and divide image sensor package array 68 into individual image sensor packages 70, as shown in FIG. 11. This may be accomplished, for example, by cutting or scribing (followed by snapping image sensor packages 70 apart along the scribe lines) with a conventional wafer saw. Alternatively, the individual image sensor packages 70 may be singulated using a laser or other high energy beam.
  • For attachment of an [0036] image sensor package 70 to a higher-level packaging component such as an assembly substrate for communication with other components of an electronic device, metallized pads or other contact interfaces for electrical communication of image sensor chip 52 through conductive traces 8 are required. In one exemplary embodiment of the present invention shown in FIG. 12, a plurality of castellated solder pads 72 in respective communication with different traces 8 may be formed by techniques known in the art around the perimeter of a singulated image sensor package 70 to form a leadless chip-carrier (LCC) image sensor package. In another exemplary embodiment shown in FIG. 13, discrete conductive elements 74 such as tin/lead solder balls, gold bumps or conductive or conductor-filled epoxy bumps, columns or pillars may be formed on or attached to the lower ends of vias 76 extending from conductive traces 8 in an array pattern on the bottom of singulated image sensor package 70 to form a ball-grid array (BGA)-type image sensor package, as illustrated by FIG. 13. A redistribution layer (RDL) of conductive traces 78 may also be applied to or formed on the bottom surface 80 of carrier substrate 2 in communication with the lower ends of selected vias 76 to configure a suitable pad array for formation or disposition of discrete conductive elements 74 thereon. It is also contemplated, and currently preferred with a BGA-type arrangement, that discrete conductive elements 74 be attached to image sensor package array 68 prior to its singulation into individual image sensor packages 70. This would be advantageous as discrete conductive elements 74 may thus be formed on or applied to all of the image sensor packages 70 of a given image sensor package array in a single step.
  • All of the above-illustrated embodiments and variations thereof of the present invention provide image sensor packages that are simultaneously fabricated to minimize assembly steps and reduce the cost associated with each individual package. Although the present invention has been depicted and described with respect to the illustrated embodiments, various additions, deletions and modifications are contemplated within its scope. For instance, if so desired, it is also contemplated that the layer of [0037] barrier material 12 may initially be formed on, or secured to, unitary transparent cover 62 rather than carrier substrate 2. Barrier material would be similarly formed on unitary transparent cover 62 using one of the above described molding, deposited layering, or preform attach methods described above. The combination of unitary transparent cover 62 and barrier material 12 would then be secured to the top surface 6 of carrier substrate 2 after attachment and electrical connection of image sensor chips 52 to image sensor chip attachment areas 4. In the same manner, securing and hermetic sealing of barrier material 12 to carrier substrate 2 may be accomplished with a bead of epoxy, silicone or other liquid or gel adhesive, double-sided adhesive-coated tape or thermal or pressure initiated bonding.
  • Furthermore, as previously discussed, the present invention would be suitable for packaging various other types of optically interactive electronic devices. The scope of the invention is, therefore, indicated by the appended claims rather than the foregoing description. Further, all changes which may fall within the meaning and range of equivalency of the claims and elements and features thereof are to be embraced within their scope. [0038]

Claims (57)

What is claimed is:
1. A method for simultaneously fabricating a plurality of packaged optically interactive electronic devices, comprising:
providing a carrier substrate having an array of device attachment areas on a surface thereof, each of the device attachment areas comprising a chip attachment surface and at least one associated wire bonding location in communication with at least one conductive trace on the carrier substrate;
forming a layer of barrier material having an array of apertures therethrough on the surface of the carrier substrate, each of the apertures exposing the chip attachment surface and the at least one associated wire bonding location of one of the device attachment areas to form an array of chip cavities;
attaching an optically interactive electronic device having at least one bond pad on an active surface thereof to the chip attachment surface in at least one chip cavity of the array of chip cavities;
forming a wire bond between the at least one bond pad on the active surface of the optically interactive electronic device and the at least one associated wire bonding location in the at least one chip cavity;
covering the layer of barrier material with a unitary transparent cover having dimensions substantially equal to dimensions of the carrier substrate to form a package array; and
separating the package array along lines extending between the device attachment areas to form a plurality of individual optically interactive electronic device packages.
2. The method according to claim 1, wherein forming a layer of barrier material comprises:
molding a contiguous matrix of raised walls onto the surface of the carrier substrate with a mold compound supplied to a molding tool in sealing engagement with the surface of the carrier substrate.
3. The method according to claim 2, wherein molding a contiguous matrix of raised walls comprises using one of the group consisting of transfer molding, injection molding and pot molding.
4. The method according to claim 2, wherein the mold compound is selected to comprise a polymer mold compound.
5. The method according to claim 4, further comprising adding a filler material to the polymer mold compound prior to molding the contiguous matrix of raised walls.
6. The method according to claim 5, wherein the filler material is selected to comprise silicon particles.
7. The method according to claim 1, wherein forming a layer of barrier material comprises forming a contiguous matrix of raised walls by:
dispensing a layer of flowable material onto the surface of the carrier substrate;
curing the flowable material to form a first hardened layer and, optionally:
dispensing at least one additional layer of flowable material over the first hardened layer; and
curing the at least one additional layer of flowable material.
8. The method according to claim 7, wherein the flowable material is selected from the group consisting of a mold compound, an activated epoxy, a thermoplastic resin material and a thermoset resin material.
9. The method according to claim 1, wherein forming a layer of barrier material comprises forming a contiguous matrix of raised walls by:
placing the carrier substrate in a reservoir at a first point below a surface of a curable liquid contained in the reservoir;
exposing a selected volume of the curable liquid to an activating agent to form a first layer of hardened material on the surface of the carrier substrate and, optionally:
lowering the carrier substrate to at least one additional point below the surface of the curable liquid; and
exposing at least one additional selected volume of the curable liquid to the activating agent over the first layer of hardened material.
10. The method according to claim 9, wherein the curable liquid is selected to comprise a photocurable liquid and the activating agent is selected to comprise a beam of electromagnetic radiation.
11. The method according to claim 9, wherein the curable liquid is selected from the group consisting of a liquid polymer and a liquid resin material.
12. The method according to claim 1, wherein forming a layer of barrier material comprises:
preforming a unitary frame; and
securing the unitary frame to the surface of the carrier substrate.
13. The method according to claim 12, wherein preforming a unitary frame comprises molding the unitary frame with a mold compound using one of the group consisting of transfer molding, injection molding and pot molding.
14. The method according to claim 13, wherein the mold compound is selected to comprise a polymer mold compound.
15. The method according to claim 14, further comprising adding a filler material to the polymer mold compound prior to molding the unitary frame.
16. The method according to claim 15, wherein the filler material is selected to comprise silicon particles.
17. The method according to claim 12, wherein preforming a unitary frame comprises selectively removing material from a sheet of material.
18. The method according to claim 12, wherein securing the unitary frame to the surface of the carrier substrate comprises securing the unitary frame to the surface with an adhesive material.
19. The method according to claim 18, wherein the adhesive material is selected from the group consisting of a liquid epoxy adhesive, an acrylic adhesive, a two-component resin adhesive and a double-sided adhesive-coated tape.
20. The method according to claim 1, wherein covering the layer of barrier material with a unitary transparent cover comprises sealing the unitary transparent cover to the layer of barrier material with a layer of adhesive material.
21. The method according to claim 20, wherein the layer of adhesive material is selected from the group consisting of a liquid epoxy adhesive, a silicone adhesive, an acrylic adhesive, a two-component resin adhesive and a double-sided adhesive-coated tape.
22. The method according to claim 1, wherein covering the layer of barrier material with a unitary transparent cover comprises sealing the unitary transparent cover to the layer of barrier material using one of the group consisting of thermal bonding and pressure bonding.
23. The method according to claim 1, wherein the unitary transparent cover is selected from the group of materials consisting of glass, quartz and plastic.
24. The method according to claim 23, wherein the unitary transparent cover is selected to be borosilicate glass.
25. The method according to claim 1, further comprising:
filling the at least one chip cavity with a transparent encapsulant material prior to covering the layer of barrier material with the unitary transparent cover; and
sealing the unitary transparent cover to the layer of barrier material.
26. The method according to claim 1, further comprising:
dimensioning the unitary transparent cover to be slightly smaller than dimensions of the carrier substrate;
forming a raised lip around a perimeter of the layer of barrier material; and
aligning the unitary transparent cover over the layer of barrier material within the raised lip.
27. The method according to claim 26, wherein forming a raised lip around the perimeter of the layer of barrier material comprises forming the raised lip integrally with the layer of barrier material.
28. The method according to claim 1, wherein separating the package array comprises cutting the package array with a saw.
29. The method according to claim 1, wherein separating the package array comprises scoring at least one surface of the package array and snapping the package array into individual pieces.
30. The method according to claim 1, wherein the optically interactive electronic device is selected to comprise a solid-state image sensor.
31. The method according to claim 1, further comprising:
forming at least one castellated solder pad in communication with the at least one conductive trace on an edge of at least one of the individual optically interactive electronic device packages.
32. The method according to claim 1, further comprising:
attaching at least one discrete conductive element in communication with the at least one conductive trace to a bottom side of the carrier substrate.
33. The method according to claim 32, wherein the at least one discrete conductive element is attached to the bottom side of the carrier substrate prior to separating the package array.
34. An optically interactive electronic device package array comprising:
a carrier substrate having an array of device attachment areas on a surface thereof, each of the device attachment areas comprising a chip attachment surface and at least one associated wire bonding location in communication with at least one conductive trace on the carrier substrate;
a layer of barrier material having an array of apertures therethrough secured to the surface of the carrier substrate, each of the apertures exposing the chip attachment surface and the at least one associated wire bonding location of one of the device attachment areas to form an array of chip cavities;
an optically interactive electronic device having at least one bond pad on an active surface thereof attached to the chip attachment surface in at least one chip cavity;
a wire bond connecting the at least one bond pad on the active surface of the optically interactive electronic device and the at least one associated wire bonding location in the at least one chip cavity; and
a unitary transparent cover having dimensions substantially equal to those of the carrier substrate sealed to a top surface of the layer of barrier material.
35. The optically interactive electronic device package array of claim 34, wherein the layer of barrier material comprises a contiguous matrix of raised walls attached directly to the surface of the carrier substrate.
36. The optically interactive electronic device package array of claim 35, wherein the contiguous martrix of raised walls comprises a polymer mold compound.
37. The optically interactive electronic device package array of claim 36, further comprising:
a filler material incorporated within the polymer mold compound.
38. The optically interactive electronic device package array of claim 37, wherein the filler material comprises silicon particles.
39. The optically interactive electronic device package array of claim 34, wherein the layer of barrier material comprises a contiguous matrix of raised walls formed of a plurality of stacked layers of cured material.
40. The optically interactive electronic device package array of claim 39, wherein the plurality of stacked layers is formed of one of the group consisting of a mold compound, an activated epoxy and a resin material.
41. The optically interactive electronic device package array of claim 39, wherein the plurality of stacked layers is formed of a photocured material.
42. The optically interactive electronic device package array of claim 41, wherein the photocured material is one of the group consisting of a photocured polymer and a photocured resin material.
43. The optically interactive electronic device package array of claim 34, further comprising:
a layer of adhesive material between the surface of the carrier substrate and the layer of barrier material.
44. The optically interactive electronic device package array of claim 43, wherein the layer of adhesive material is one of the group consisting of an epoxy adhesive, an acrylic adhesive, a two-component adhesive resin and a double-sided adhesive-coated tape.
45. The optically interactive electronic device package array of claim 43, wherein the layer of barrier material is a unitary frame formed of a mold compound.
46. The optically interactive electronic device package array of claim 45, further comprising:
a filler material incorporated within the mold compound.
47. The optically interactive electronic device package array of claim 46, wherein the filler material comprises silicon particles.
48. The optically interactive electronic device package array of claim 43, wherein the layer of barrier material is a unitary frame comprising a solid sheet of material having apertures formed therein.
49. The optically interactive electronic device package array of claim 34, further comprising:
a layer of adhesive material between a top surface of the layer of barrier material and the unitary transparent cover.
50. The optically interactive electronic device package array of claim 49, wherein the layer of adhesive material is one of the group consisting of an epoxy adhesive, a silicone adhesive, an acrylic adhesive, a two-component resin and a double-sided adhesive-coated tape.
51. The optically interactive electronic device package array of claim 34, wherein the unitary transparent cover is formed of one of the group consisting of glass, quartz and plastic.
52. The optically interactive electronic device package array of claim 34, wherein the unitary transparent cover is formed of borosilicate glass.
53. The optically interactive electronic device package array of claim 34, further comprising:
a transparent encapsulant material filling a space in the at least one chip cavity between the active surface of the optically interactive electronic device and the unitary transparent cover.
54. The optically interactive electronic device package array of claim 34, further comprising:
a raised lip around a perimeter of the top surface of the layer of barrier material and abutting an outside edge of the unitary transparent cover.
55. The optically interactive electronic device package array of claim 54, wherein the raised lip is integrally formed with the layer of barrier material.
56. The optically interactive electronic device package array of claim 34, wherein the optically interactive electronic device comprises a solid-state image sensor.
57. The optically interactive electronic device package array of claim 34, further comprising:
at least one discrete conductive element attached to the carrier substrate on a surface thereof opposite the surface bearing the device attachment areas and in communication with the at least one conductive trace.
US10/228,411 2002-08-26 2002-08-26 Optically interactive device packages and methods of assembly Abandoned US20040038442A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/228,411 US20040038442A1 (en) 2002-08-26 2002-08-26 Optically interactive device packages and methods of assembly
US11/103,019 US7541658B2 (en) 2002-08-26 2005-04-11 Optically interactive device package array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/228,411 US20040038442A1 (en) 2002-08-26 2002-08-26 Optically interactive device packages and methods of assembly

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/103,019 Division US7541658B2 (en) 2002-08-26 2005-04-11 Optically interactive device package array

Publications (1)

Publication Number Publication Date
US20040038442A1 true US20040038442A1 (en) 2004-02-26

Family

ID=31887611

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/228,411 Abandoned US20040038442A1 (en) 2002-08-26 2002-08-26 Optically interactive device packages and methods of assembly
US11/103,019 Expired - Lifetime US7541658B2 (en) 2002-08-26 2005-04-11 Optically interactive device package array

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/103,019 Expired - Lifetime US7541658B2 (en) 2002-08-26 2005-04-11 Optically interactive device package array

Country Status (1)

Country Link
US (2) US20040038442A1 (en)

Cited By (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222333A1 (en) * 2002-06-04 2003-12-04 Bolken Todd O. Sealed electronic device packages with transparent coverings
US20040041221A1 (en) * 2002-08-28 2004-03-04 Boon Suan Jeung Leadless packaging for image sensor devices and methods of assembly
US20040058488A1 (en) * 2002-05-08 2004-03-25 Arno Jose I. Monitoring system comprising infrared thermopile detetor
US20040113080A1 (en) * 2002-05-08 2004-06-17 Jose Arno Infrared thermopile detector system for semiconductor process monitoring and control
US20040173887A1 (en) * 2003-03-04 2004-09-09 Jang Chae Kyu Test vehicle ball grid array package
US20040191963A1 (en) * 2003-03-31 2004-09-30 Osram Opto Semiconductors Gmbh Encapsulation of thin-film electronic devices
US20040212717A1 (en) * 2003-04-28 2004-10-28 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and method for producing the same
US20040229400A1 (en) * 2002-08-27 2004-11-18 Chua Swee Kwang Multichip wafer level system packages and methods of forming same
US20050062140A1 (en) * 2003-09-18 2005-03-24 Cree, Inc. Molded chip fabrication method and apparatus
US20050063033A1 (en) * 2003-09-18 2005-03-24 Kinsman Larry D. Microelectronic devices and methods for packaging microelectronic devices
US20050074912A1 (en) * 2003-09-03 2005-04-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing solid-state imaging devices
US20050110889A1 (en) * 2003-11-26 2005-05-26 Tuttle Mark E. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US6930377B1 (en) * 2002-12-04 2005-08-16 National Semiconductor Corporation Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages
US20050184219A1 (en) * 2004-02-23 2005-08-25 Kirby Kyle K. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050212118A1 (en) * 2004-03-26 2005-09-29 Denny Chao Chip packaging structure and method of making wafer level packaging
US20050242341A1 (en) * 2003-10-09 2005-11-03 Knudson Christopher T Apparatus and method for supporting a flexible substrate during processing
US20050253213A1 (en) * 2004-05-13 2005-11-17 Tongbi Jiang Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US20050254133A1 (en) * 2004-05-13 2005-11-17 Salman Akram Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
US20050263312A1 (en) * 2003-09-16 2005-12-01 Bolken Todd O Moisture-resistant electronic device package and methods of assembly
US20050275048A1 (en) * 2004-06-14 2005-12-15 Farnworth Warren M Microelectronic imagers and methods of packaging microelectronic imagers
US20050275750A1 (en) * 2004-06-09 2005-12-15 Salman Akram Wafer-level packaged microelectronic imagers and processes for wafer-level packaging
US20050275049A1 (en) * 2004-06-10 2005-12-15 Kirby Kyle K Packaged microelectronic imagers and methods of packging microelectronic imagers
US20050275051A1 (en) * 2004-06-14 2005-12-15 Farnworth Warren M Prefabricated housings for microelectronic imagers and methods for packaging microelectronic imagers
EP1610396A2 (en) * 2004-06-15 2005-12-28 Sharp Kabushiki Kaisha Manufacturing method of a semiconductor wafer having lid parts and manufacturing method of a semiconductor device
US20050287783A1 (en) * 2004-06-29 2005-12-29 Kirby Kyle K Microelectronic devices and methods for forming interconnects in microelectronic devices
US20050285154A1 (en) * 2004-06-29 2005-12-29 Salman Akram Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20060001114A1 (en) * 2004-06-30 2006-01-05 Jen-Yi Chen Apparatus and method of wafer level package
US20060006486A1 (en) * 2004-06-10 2006-01-12 Byoung-Rim Seo Image sensor package and method of manufacturing the same
US20060014313A1 (en) * 2004-07-16 2006-01-19 Hall Frank L Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060024856A1 (en) * 2004-07-28 2006-02-02 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060023107A1 (en) * 2004-08-02 2006-02-02 Bolken Todd O Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers
US20060035402A1 (en) * 2004-08-10 2006-02-16 Street Bret K Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060040421A1 (en) * 2004-08-19 2006-02-23 Farnworth Warren M Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US20060038183A1 (en) * 2004-08-19 2006-02-23 Oliver Steven D Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US20060042952A1 (en) * 2004-08-24 2006-03-02 Oliver Steven D Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US20060043262A1 (en) * 2004-08-30 2006-03-02 Micron Technology, Inc. Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US20060043461A1 (en) * 2002-11-20 2006-03-02 Stmicroelectronics S.R.L. Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure
US20060046332A1 (en) * 2004-08-26 2006-03-02 Derderian James M Microelectronic Imaging units and methods of manufacturing microelectronic imaging units
US20060043509A1 (en) * 2004-08-24 2006-03-02 Watkins Charles M Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
US20060044433A1 (en) * 2004-08-31 2006-03-02 Micron Technology, Inc. Microelectronic imagers having front side contacts and methods of packaging such microelectronic imagers
US20060043599A1 (en) * 2004-09-02 2006-03-02 Salman Akram Through-wafer interconnects for photoimager and memory wafers
US20060043512A1 (en) * 2004-08-24 2006-03-02 Oliver Steven D Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US20060148250A1 (en) * 2004-12-30 2006-07-06 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060177959A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US20060175532A1 (en) * 2005-02-08 2006-08-10 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060177999A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces
US20060180887A1 (en) * 2005-02-15 2006-08-17 Sharp Kabushiki Kaisha Semiconductor device and production method thereof
US20060186492A1 (en) * 2005-02-18 2006-08-24 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US20060192230A1 (en) * 2004-08-16 2006-08-31 Wood Alan G Image sensor packages and frame structure thereof
US20060197201A1 (en) * 2005-02-23 2006-09-07 Hsin Chung H Image sensor structure
US20060217896A1 (en) * 2003-03-28 2006-09-28 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US20060243889A1 (en) * 2004-07-19 2006-11-02 Farnworth Warren M Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US20060289968A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20060290001A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Interconnect vias and associated methods of formation
US20070045858A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US20070090503A1 (en) * 2005-10-21 2007-04-26 Cheng-Wei Huang Semiconductor package having an optical device and the method of making the same
US20070139923A1 (en) * 2005-12-21 2007-06-21 Led Lighting Fixtures, Inc. Lighting device
US20070148807A1 (en) * 2005-08-22 2007-06-28 Salman Akram Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US20070200944A1 (en) * 2005-10-28 2007-08-30 Yasuo Takeuchi Manufacturing method for a solid-state imaging apparatus, and the solid-state imaging apparatus
US7288757B2 (en) 2005-09-01 2007-10-30 Micron Technology, Inc. Microelectronic imaging devices and associated methods for attaching transmissive elements
US20080006775A1 (en) * 2006-06-22 2008-01-10 Arno Jose I Infrared gas detection systems and methods
US20080160315A1 (en) * 2002-11-25 2008-07-03 Henkel Corporation B-stageable die attach adhesives
CN100413042C (en) * 2005-08-25 2008-08-20 矽格股份有限公司 Packaging method for optical sensing semiconductor assembly and its packaging structure
US20080197375A1 (en) * 2007-02-15 2008-08-21 Wen-Kung Sung Lateral-type light-emitting diode and method of manufacture thereof
US20080213925A1 (en) * 2003-03-28 2008-09-04 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US7448910B2 (en) 2004-09-03 2008-11-11 Samsung Electronics Co., Ltd Displaying apparatus
US7569407B2 (en) 2004-09-21 2009-08-04 Cree, Inc. Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
US20090321861A1 (en) * 2008-06-26 2009-12-31 Micron Technology, Inc. Microelectronic imagers with stacked lens assemblies and processes for wafer-level packaging of microelectronic imagers
US20090323334A1 (en) * 2008-06-25 2009-12-31 Cree, Inc. Solid state linear array modules for general illumination
US20100052183A1 (en) * 2005-09-01 2010-03-04 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
EP2169723A1 (en) * 2007-07-12 2010-03-31 Sumitomo Bakelite Co., Ltd. Light receiving device and method of manufacturing light receiving device
US20100194465A1 (en) * 2009-02-02 2010-08-05 Ali Salih Temperature compensated current source and method therefor
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US20110247210A1 (en) * 2008-12-19 2011-10-13 3D Plus Process for the wafer-scale fabrication of electronic modules for surface mounting
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US20120177358A1 (en) * 2011-01-10 2012-07-12 Apple Inc. Systems and methods for coupling a cover to an enclosure
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
WO2012155984A1 (en) * 2011-05-19 2012-11-22 Osram Opto Semiconductors Gmbh Optoelectronic device and method for producing optoelectronic devices
US20130157419A1 (en) * 2011-12-19 2013-06-20 Nitto Denko Corporation Method of manufacturing semiconductor device
CN103205087A (en) * 2012-01-16 2013-07-17 日东电工株式会社 Resin Sheet For Hollow Encapsulation And Production Method For The Sheet, And Production Method For Hollow Electronic Part Apparatus And Hollow Electronic Part Apparatus
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
WO2014193307A1 (en) * 2013-05-31 2014-12-04 Heptagon Micro Optics Pte. Ltd. Mems microphone modules and wafer-level techniques for fabricating the same
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US20150140784A1 (en) * 2013-11-21 2015-05-21 Disco Corporation Wafer processing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US20150147870A1 (en) * 2013-11-25 2015-05-28 Disco Corporation Wafer processing method
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US20150325548A1 (en) * 2014-05-12 2015-11-12 Skyworks Solutions, Inc. Devices and methods for processing singulated radio-frequency units
US9340878B2 (en) 2009-05-29 2016-05-17 Entegris, Inc. TPIR apparatus for monitoring tungsten hexafluoride processing to detect gas phase nucleation, and method and system utilizing same
CN107958915A (en) * 2017-12-22 2018-04-24 成都先锋材料有限公司 A kind of cmos sensor encapsulating structure and its method for packing
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
CN110015635A (en) * 2018-01-08 2019-07-16 罗伯特·博世有限公司 Environmental sensor, environmental sensor intermediate products and the method for manufacturing multiple environmental sensors
US10435185B2 (en) * 2013-10-07 2019-10-08 David A. Divine 3-D printed packaging
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
WO2020156955A1 (en) * 2019-01-31 2020-08-06 Robert Bosch Gmbh Method for producing a plurality of sensor devices, and sensor device
WO2021121608A1 (en) * 2019-12-19 2021-06-24 Ev Group E. Thallner Gmbh Individual encapsulated component and method for the production thereof
CN113140467A (en) * 2019-07-31 2021-07-20 深圳宏芯宇电子股份有限公司 Integrated circuit packaging method and semiconductor device
US20210336104A1 (en) * 2017-08-31 2021-10-28 Beijing Boe Optoelectronics Technology Co., Ltd. Light source structure, electronic device and manufacturing method of light source structure
US20210343915A1 (en) * 2018-10-26 2021-11-04 Barco N.V. Led package
WO2022104927A1 (en) * 2020-11-17 2022-05-27 瑞声声学科技(深圳)有限公司 Method for manufacturing mems sensor

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040266063A1 (en) * 2003-06-25 2004-12-30 Montgomery Stephen W. Apparatus and method for manufacturing thermal interface device having aligned carbon nanotubes
US7498646B2 (en) * 2006-07-19 2009-03-03 Advanced Chip Engineering Technology Inc. Structure of image sensor module and a method for manufacturing of wafer level package
US8362488B2 (en) * 2006-09-12 2013-01-29 Sipix Imaging, Inc. Flexible backplane and methods for its manufacture
US20080136012A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Imagine sensor package and forming method of the same
JP2008192769A (en) * 2007-02-02 2008-08-21 Sharp Corp Resin-sealed semiconductor photodetector and method of manufacturing the resin-sealed semiconductor photodetector, and electronic apparatus using the resin-sealed semiconductor photodetector
JP4912275B2 (en) * 2007-11-06 2012-04-11 新光電気工業株式会社 Semiconductor package
DE102008025491A1 (en) * 2008-05-28 2009-12-03 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component and printed circuit board
US8048708B2 (en) * 2008-06-25 2011-11-01 Micron Technology, Inc. Method and apparatus providing an imager module with a permanent carrier
US8164179B2 (en) * 2008-12-16 2012-04-24 STMicroelectronics Asia Pacific PTE Ltd-Singapore Chip scale package structure with can attachment
KR101078734B1 (en) * 2009-07-07 2011-11-02 주식회사 하이닉스반도체 Semiconductor Package and method for fabricating thereof and Stack Package using the same
TWI495113B (en) * 2010-03-22 2015-08-01 Xintec Inc Optical cover plate with improved solder mask dam on galss for image sensor package and fabrication method thereof
TWI467777B (en) * 2012-06-06 2015-01-01 Pixart Imaging Inc Package structure of optical apparatus
JP2017208468A (en) * 2016-05-19 2017-11-24 キヤノン株式会社 Electronic component
CN107369722B (en) * 2017-06-27 2019-12-13 上海集成电路研发中心有限公司 Sensor packaging structure and preparation method thereof
JP7091696B2 (en) * 2018-02-20 2022-06-28 株式会社デンソー Physical quantity sensor and semiconductor device
US10804229B2 (en) * 2018-08-20 2020-10-13 Sj Semiconductor (Jiangyin) Corporation Fan-out antenna package structure and packaging method
TWI691041B (en) * 2019-01-29 2020-04-11 矽品精密工業股份有限公司 Electronic package and package substrate thereof and method for manufacturing same

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4601526A (en) * 1983-10-28 1986-07-22 Honeywell Inc. Integrated circuit chip carrier
US4878043A (en) * 1986-11-20 1989-10-31 Guy Heusquin Device for indicating hydroculture-related values
US5458716A (en) * 1994-05-25 1995-10-17 Texas Instruments Incorporated Methods for manufacturing a thermally enhanced molded cavity package having a parallel lid
US5709960A (en) * 1996-06-21 1998-01-20 Motorola, Inc. Mold compound
US5811799A (en) * 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US5923958A (en) * 1998-05-28 1999-07-13 Pan Pacific Semiconductor Co., Ltd. Method for semiconductor chip packaging
US6143588A (en) * 1997-09-09 2000-11-07 Amkor Technology, Inc. Method of making an integrated circuit package employing a transparent encapsulant
US6266197B1 (en) * 1999-12-08 2001-07-24 Amkor Technology, Inc. Molded window array for image sensor packages
US6285064B1 (en) * 2000-03-28 2001-09-04 Omnivision Technologies, Inc. Chip scale packaging technique for optical image sensing integrated circuits
US6351027B1 (en) * 2000-02-29 2002-02-26 Agilent Technologies, Inc. Chip-mounted enclosure
US6545332B2 (en) * 2001-01-17 2003-04-08 Siliconware Precision Industries Co., Ltd. Image sensor of a quad flat package
US20030222333A1 (en) * 2002-06-04 2003-12-04 Bolken Todd O. Sealed electronic device packages with transparent coverings
US6809412B1 (en) * 2002-02-06 2004-10-26 Teravictu Technologies Packaging of MEMS devices using a thermoplastic
US20050029549A1 (en) * 2002-02-15 2005-02-10 Micron Technology Inc. Molded stiffener for thin substrates

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270491A (en) * 1990-10-09 1993-12-14 Eastman Kodak Company Hermetically sealed microelectronic package
JPH07231309A (en) * 1994-02-17 1995-08-29 Hitachi Ltd Information distribution system
JP4747403B2 (en) * 2000-08-08 2011-08-17 東洋紡績株式会社 Method for producing multilayer resin film having excellent oxygen gas barrier property
US6811844B2 (en) * 2001-12-21 2004-11-02 E. I. Du Pont De Nemours And Company Multilayer film

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4601526A (en) * 1983-10-28 1986-07-22 Honeywell Inc. Integrated circuit chip carrier
US4878043A (en) * 1986-11-20 1989-10-31 Guy Heusquin Device for indicating hydroculture-related values
US5458716A (en) * 1994-05-25 1995-10-17 Texas Instruments Incorporated Methods for manufacturing a thermally enhanced molded cavity package having a parallel lid
US5709960A (en) * 1996-06-21 1998-01-20 Motorola, Inc. Mold compound
US5811799A (en) * 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US6143588A (en) * 1997-09-09 2000-11-07 Amkor Technology, Inc. Method of making an integrated circuit package employing a transparent encapsulant
US5923958A (en) * 1998-05-28 1999-07-13 Pan Pacific Semiconductor Co., Ltd. Method for semiconductor chip packaging
US6266197B1 (en) * 1999-12-08 2001-07-24 Amkor Technology, Inc. Molded window array for image sensor packages
US6351027B1 (en) * 2000-02-29 2002-02-26 Agilent Technologies, Inc. Chip-mounted enclosure
US6285064B1 (en) * 2000-03-28 2001-09-04 Omnivision Technologies, Inc. Chip scale packaging technique for optical image sensing integrated circuits
US6545332B2 (en) * 2001-01-17 2003-04-08 Siliconware Precision Industries Co., Ltd. Image sensor of a quad flat package
US6809412B1 (en) * 2002-02-06 2004-10-26 Teravictu Technologies Packaging of MEMS devices using a thermoplastic
US20050029549A1 (en) * 2002-02-15 2005-02-10 Micron Technology Inc. Molded stiffener for thin substrates
US20030222333A1 (en) * 2002-06-04 2003-12-04 Bolken Todd O. Sealed electronic device packages with transparent coverings

Cited By (252)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070200065A1 (en) * 2002-05-08 2007-08-30 Arno Jose I Monitoring system comprising infrared thermopile detector
US7172918B2 (en) 2002-05-08 2007-02-06 Advanced Technology Materials, Inc. Infrared thermopile detector system for semiconductor process monitoring and control
US7723685B2 (en) 2002-05-08 2010-05-25 Advanced Technology Materials, Inc. Monitoring system comprising infrared thermopile detector
US20040058488A1 (en) * 2002-05-08 2004-03-25 Arno Jose I. Monitoring system comprising infrared thermopile detetor
US7129519B2 (en) * 2002-05-08 2006-10-31 Advanced Technology Materials, Inc. Monitoring system comprising infrared thermopile detector
US20040113080A1 (en) * 2002-05-08 2004-06-17 Jose Arno Infrared thermopile detector system for semiconductor process monitoring and control
US20090039266A1 (en) * 2002-05-08 2009-02-12 Advanced Technology Materials, Inc. Monitoring system comprising infrared thermopile detector
US7351976B2 (en) 2002-05-08 2008-04-01 Advanced Technology Materials, Inc. Monitoring system comprising infrared thermopile detector
US7419854B2 (en) 2002-06-04 2008-09-02 Micron Technology, Inc. Methods for packaging image sensitive electronic devices
US20060267169A1 (en) * 2002-06-04 2006-11-30 Bolken Todd O Image sensitive electronic device packages
US20030222333A1 (en) * 2002-06-04 2003-12-04 Bolken Todd O. Sealed electronic device packages with transparent coverings
US20030232461A1 (en) * 2002-06-04 2003-12-18 Bolken Todd O. Methods for packaging image sensitive electronic devices
US20060046351A1 (en) * 2002-06-04 2006-03-02 Bolken Todd O Methods for packaging image sensitive electronic devices
US7195940B2 (en) 2002-06-04 2007-03-27 Micron Technology, Inc. Methods for packaging image sensitive electronic devices
US20060051891A1 (en) * 2002-06-04 2006-03-09 Bolken Todd O Methods for packaging image sensitive electronic devices
US20050116355A1 (en) * 2002-06-04 2005-06-02 Bolken Todd O. Packages for image sensitive electronic devices
US6906403B2 (en) 2002-06-04 2005-06-14 Micron Technology, Inc. Sealed electronic device packages with transparent coverings
US7553688B2 (en) 2002-06-04 2009-06-30 Micron Technology, Inc. Methods for packaging image sensitive electronic devices
US20060051892A1 (en) * 2002-06-04 2006-03-09 Bolken Todd O Methods for packaging image sensitive electronic devices
US7387902B2 (en) 2002-06-04 2008-06-17 Micron Technology, Inc. Methods for packaging image sensitive electronic devices
US20050116337A1 (en) * 2002-08-27 2005-06-02 Swee Kwang Chua Method of making multichip wafer level packages and computing systems incorporating same
US20040229400A1 (en) * 2002-08-27 2004-11-18 Chua Swee Kwang Multichip wafer level system packages and methods of forming same
US7485562B2 (en) 2002-08-27 2009-02-03 Micron Technology, Inc. Method of making multichip wafer level packages and computing systems incorporating same
US7112471B2 (en) * 2002-08-28 2006-09-26 Micron Technology, Inc. Leadless packaging for image sensor devices and methods of assembly
US7274094B2 (en) 2002-08-28 2007-09-25 Micron Technology, Inc. Leadless packaging for image sensor devices
US20040084741A1 (en) * 2002-08-28 2004-05-06 Boon Suan Jeung Leadless packaging for image sensor devices and methods of assembly
US20040041221A1 (en) * 2002-08-28 2004-03-04 Boon Suan Jeung Leadless packaging for image sensor devices and methods of assembly
US20060043461A1 (en) * 2002-11-20 2006-03-02 Stmicroelectronics S.R.L. Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure
US20080160315A1 (en) * 2002-11-25 2008-07-03 Henkel Corporation B-stageable die attach adhesives
US7851254B2 (en) * 2002-11-25 2010-12-14 Henkel Corporation B-stageable die attach adhesives
US6930377B1 (en) * 2002-12-04 2005-08-16 National Semiconductor Corporation Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages
US7193315B2 (en) * 2003-03-04 2007-03-20 Hynix Semiconductor Inc. Test vehicle grid array package
US20040173887A1 (en) * 2003-03-04 2004-09-09 Jang Chae Kyu Test vehicle ball grid array package
US20060217896A1 (en) * 2003-03-28 2006-09-28 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US7711496B2 (en) 2003-03-28 2010-05-04 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US7373257B2 (en) 2003-03-28 2008-05-13 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US20080213925A1 (en) * 2003-03-28 2008-09-04 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US8244482B2 (en) 2003-03-28 2012-08-14 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US20100217415A1 (en) * 2003-03-28 2010-08-26 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US7925450B2 (en) 2003-03-28 2011-04-12 Advanced Technology Materials, Inc. Photometrically modulated delivery of reagents
US7365442B2 (en) * 2003-03-31 2008-04-29 Osram Opto Semiconductors Gmbh Encapsulation of thin-film electronic devices
US20040191963A1 (en) * 2003-03-31 2004-09-30 Osram Opto Semiconductors Gmbh Encapsulation of thin-film electronic devices
US20040212717A1 (en) * 2003-04-28 2004-10-28 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and method for producing the same
US7273765B2 (en) * 2003-04-28 2007-09-25 Matsushita Electric Industrial Co., Ltd. Solid-state imaging device and method for producing the same
US7247509B2 (en) * 2003-09-03 2007-07-24 Matsushita Electric Industrial Co., Ltd. Method for manufacturing solid-state imaging devices
US20050074912A1 (en) * 2003-09-03 2005-04-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing solid-state imaging devices
US8508034B2 (en) 2003-09-16 2013-08-13 Micron Technology, Inc. Electronic devices
US20050263312A1 (en) * 2003-09-16 2005-12-01 Bolken Todd O Moisture-resistant electronic device package and methods of assembly
US8115296B2 (en) 2003-09-16 2012-02-14 Micron Technology, Inc. Electronic device package
US7026548B2 (en) 2003-09-16 2006-04-11 Micron Technology, Inc. Moisture-resistant electronic device package and methods of assembly
US20060169490A1 (en) * 2003-09-16 2006-08-03 Bolken Todd O Molding tool and a method of forming an electronic device package
US20100264532A1 (en) * 2003-09-16 2010-10-21 Micron Technology, Inc. Electronic device package
US10164158B2 (en) 2003-09-18 2018-12-25 Cree, Inc. Molded chip fabrication method and apparatus
US7321455B2 (en) 2003-09-18 2008-01-22 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
US20050062140A1 (en) * 2003-09-18 2005-03-24 Cree, Inc. Molded chip fabrication method and apparatus
US7915085B2 (en) * 2003-09-18 2011-03-29 Cree, Inc. Molded chip fabrication method
US9093616B2 (en) 2003-09-18 2015-07-28 Cree, Inc. Molded chip fabrication method and apparatus
US10546978B2 (en) 2003-09-18 2020-01-28 Cree, Inc. Molded chip fabrication method and apparatus
US20050255628A1 (en) * 2003-09-18 2005-11-17 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
US20050063033A1 (en) * 2003-09-18 2005-03-24 Kinsman Larry D. Microelectronic devices and methods for packaging microelectronic devices
US9105817B2 (en) 2003-09-18 2015-08-11 Cree, Inc. Molded chip fabrication method and apparatus
US20050242341A1 (en) * 2003-10-09 2005-11-03 Knudson Christopher T Apparatus and method for supporting a flexible substrate during processing
US7583862B2 (en) 2003-11-26 2009-09-01 Aptina Imaging Corporation Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050110889A1 (en) * 2003-11-26 2005-05-26 Tuttle Mark E. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050231626A1 (en) * 2003-11-26 2005-10-20 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050184219A1 (en) * 2004-02-23 2005-08-25 Kirby Kyle K. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7253397B2 (en) 2004-02-23 2007-08-07 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050212118A1 (en) * 2004-03-26 2005-09-29 Denny Chao Chip packaging structure and method of making wafer level packaging
US7253957B2 (en) 2004-05-13 2007-08-07 Micron Technology, Inc. Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
US20050253213A1 (en) * 2004-05-13 2005-11-17 Tongbi Jiang Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US20050254133A1 (en) * 2004-05-13 2005-11-17 Salman Akram Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
US8816463B2 (en) 2004-06-09 2014-08-26 Round Rock Research, Llc Wafer-level packaged microelectronic imagers having interconnects formed through terminals
US20050275750A1 (en) * 2004-06-09 2005-12-15 Salman Akram Wafer-level packaged microelectronic imagers and processes for wafer-level packaging
US7863702B2 (en) * 2004-06-10 2011-01-04 Samsung Electronics Co., Ltd. Image sensor package and method of manufacturing the same
US20060006486A1 (en) * 2004-06-10 2006-01-12 Byoung-Rim Seo Image sensor package and method of manufacturing the same
US8703518B2 (en) 2004-06-10 2014-04-22 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7498647B2 (en) 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US8035179B2 (en) 2004-06-10 2011-10-11 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050275049A1 (en) * 2004-06-10 2005-12-15 Kirby Kyle K Packaged microelectronic imagers and methods of packging microelectronic imagers
US20060186317A1 (en) * 2004-06-14 2006-08-24 Farnworth Warren M Methods for packaging microelectronic imagers
US20050275051A1 (en) * 2004-06-14 2005-12-15 Farnworth Warren M Prefabricated housings for microelectronic imagers and methods for packaging microelectronic imagers
US20060261340A1 (en) * 2004-06-14 2006-11-23 Farnworth Warren M Microelectronic imagers and methods of packaging microelectronic imagers
US7199439B2 (en) 2004-06-14 2007-04-03 Micron Technology, Inc. Microelectronic imagers and methods of packaging microelectronic imagers
US7262405B2 (en) 2004-06-14 2007-08-28 Micron Technology, Inc. Prefabricated housings for microelectronic imagers
US20050275048A1 (en) * 2004-06-14 2005-12-15 Farnworth Warren M Microelectronic imagers and methods of packaging microelectronic imagers
US7419841B2 (en) 2004-06-14 2008-09-02 Micron Technology, Inc. Microelectronic imagers and methods of packaging microelectronic imagers
US7253390B2 (en) 2004-06-14 2007-08-07 Micron Technology, Inc. Methods for packaging microelectronic imagers
EP1610396A3 (en) * 2004-06-15 2009-11-18 Sharp Kabushiki Kaisha Manufacturing method of a semiconductor wafer having lid parts and manufacturing method of a semiconductor device
EP1610396A2 (en) * 2004-06-15 2005-12-28 Sharp Kabushiki Kaisha Manufacturing method of a semiconductor wafer having lid parts and manufacturing method of a semiconductor device
US20110089539A1 (en) * 2004-06-29 2011-04-21 Round Rock Research, Llc Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7329943B2 (en) 2004-06-29 2008-02-12 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US20050287783A1 (en) * 2004-06-29 2005-12-29 Kirby Kyle K Microelectronic devices and methods for forming interconnects in microelectronic devices
US20050285154A1 (en) * 2004-06-29 2005-12-29 Salman Akram Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7829976B2 (en) 2004-06-29 2010-11-09 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7294897B2 (en) 2004-06-29 2007-11-13 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20080020505A1 (en) * 2004-06-29 2008-01-24 Salman Akram Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US20080138973A1 (en) * 2004-06-29 2008-06-12 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US20060199363A1 (en) * 2004-06-29 2006-09-07 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7858429B2 (en) 2004-06-29 2010-12-28 Round Rock Research, Llc Packaged microelectronic imagers and methods of packaging microelectronic imagers
US8053857B2 (en) 2004-06-29 2011-11-08 Round Rock Research, Llc Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20060001114A1 (en) * 2004-06-30 2006-01-05 Jen-Yi Chen Apparatus and method of wafer level package
US7417294B2 (en) 2004-07-16 2008-08-26 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20070117249A1 (en) * 2004-07-16 2007-05-24 Hall Frank L Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060014313A1 (en) * 2004-07-16 2006-01-19 Hall Frank L Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7416913B2 (en) * 2004-07-16 2008-08-26 Micron Technology, Inc. Methods of manufacturing microelectronic imaging units with discrete standoffs
US7504615B2 (en) 2004-07-19 2009-03-17 Aptina Imaging Corporation Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US20090155949A1 (en) * 2004-07-19 2009-06-18 Farnworth Warren M Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US7189954B2 (en) 2004-07-19 2007-03-13 Micron Technology, Inc. Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US7709776B2 (en) 2004-07-19 2010-05-04 Aptina Imaging Corporation Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US20060243889A1 (en) * 2004-07-19 2006-11-02 Farnworth Warren M Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US20070170350A1 (en) * 2004-07-19 2007-07-26 Farnworth Warren M Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US7265330B2 (en) 2004-07-19 2007-09-04 Micron Technology, Inc. Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US7655507B2 (en) 2004-07-28 2010-02-02 Micron Technology Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20070034979A1 (en) * 2004-07-28 2007-02-15 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7858420B2 (en) 2004-07-28 2010-12-28 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7402453B2 (en) 2004-07-28 2008-07-22 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20080241985A1 (en) * 2004-07-28 2008-10-02 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060024856A1 (en) * 2004-07-28 2006-02-02 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7439598B2 (en) 2004-07-28 2008-10-21 Micron Technology, Inc. Microelectronic imaging units
US20080268563A1 (en) * 2004-07-28 2008-10-30 Derderian James M Microelectronic Imaging Units and Methods of Manufacturing Microelectronic Imaging Units
US20060023107A1 (en) * 2004-08-02 2006-02-02 Bolken Todd O Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers
US20060035402A1 (en) * 2004-08-10 2006-02-16 Street Bret K Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060216850A1 (en) * 2004-08-10 2006-09-28 Street Bret K Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7364934B2 (en) 2004-08-10 2008-04-29 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7498606B2 (en) 2004-08-10 2009-03-03 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7791184B2 (en) 2004-08-16 2010-09-07 Micron Technology, Inc. Image sensor packages and frame structure thereof
US20060192230A1 (en) * 2004-08-16 2006-08-31 Wood Alan G Image sensor packages and frame structure thereof
US7645635B2 (en) 2004-08-16 2010-01-12 Micron Technology, Inc. Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages
US7723741B2 (en) 2004-08-19 2010-05-25 Aptina Imaging Corporation Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US20060040421A1 (en) * 2004-08-19 2006-02-23 Farnworth Warren M Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US7223626B2 (en) 2004-08-19 2007-05-29 Micron Technology, Inc. Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US20060234422A1 (en) * 2004-08-19 2006-10-19 Farnworth Warren M Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US20060038183A1 (en) * 2004-08-19 2006-02-23 Oliver Steven D Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US20060275941A1 (en) * 2004-08-19 2006-12-07 Oliver Steven D Methods for manufacturing microelectronic imagers
US7397066B2 (en) 2004-08-19 2008-07-08 Micron Technology, Inc. Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US20080237443A1 (en) * 2004-08-19 2008-10-02 Oliver Steven D Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US7341881B2 (en) 2004-08-24 2008-03-11 Micron Technology, Inc. Methods of packaging and testing microelectronic imaging devices
US7993944B2 (en) 2004-08-24 2011-08-09 Micron Technology, Inc. Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US7429494B2 (en) 2004-08-24 2008-09-30 Micron Technology, Inc. Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US20060043509A1 (en) * 2004-08-24 2006-03-02 Watkins Charles M Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
US20060043512A1 (en) * 2004-08-24 2006-03-02 Oliver Steven D Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US7115961B2 (en) 2004-08-24 2006-10-03 Micron Technology, Inc. Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
US20060255418A1 (en) * 2004-08-24 2006-11-16 Watkins Charles M Packaged microelectronic imaging devices and methods of packaging microelectronic imaging device
US20060042952A1 (en) * 2004-08-24 2006-03-02 Oliver Steven D Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US20090148969A1 (en) * 2004-08-26 2009-06-11 Derderian James M Microelectronic imaging units
US7511374B2 (en) 2004-08-26 2009-03-31 Aptina Imaging Corporation Microelectronic imaging units having covered image sensors
US7276393B2 (en) 2004-08-26 2007-10-02 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7691660B2 (en) 2004-08-26 2010-04-06 Aptina Imaging Corporation Methods of manufacturing microelectronic imaging units on a microfeature workpiece
US20060223207A1 (en) * 2004-08-26 2006-10-05 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060046332A1 (en) * 2004-08-26 2006-03-02 Derderian James M Microelectronic Imaging units and methods of manufacturing microelectronic imaging units
US7786574B2 (en) 2004-08-26 2010-08-31 Aptina Imaging Corp. Microelectronic imaging units
US20060043262A1 (en) * 2004-08-30 2006-03-02 Micron Technology, Inc. Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US7547877B2 (en) 2004-08-30 2009-06-16 Micron Technology, Inc. Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US7842915B2 (en) 2004-08-30 2010-11-30 Micron Technology, Inc. Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US20080293179A1 (en) * 2004-08-30 2008-11-27 Salman Akram Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US7511262B2 (en) 2004-08-30 2009-03-31 Micron Technology, Inc. Optical device and assembly for use with imaging dies, and wafer-label imager assembly
US20060044433A1 (en) * 2004-08-31 2006-03-02 Micron Technology, Inc. Microelectronic imagers having front side contacts and methods of packaging such microelectronic imagers
US7646075B2 (en) 2004-08-31 2010-01-12 Micron Technology, Inc. Microelectronic imagers having front side contacts
US20060043599A1 (en) * 2004-09-02 2006-03-02 Salman Akram Through-wafer interconnects for photoimager and memory wafers
US7956443B2 (en) 2004-09-02 2011-06-07 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7683458B2 (en) 2004-09-02 2010-03-23 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US8502353B2 (en) 2004-09-02 2013-08-06 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US8669179B2 (en) 2004-09-02 2014-03-11 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7448910B2 (en) 2004-09-03 2008-11-11 Samsung Electronics Co., Ltd Displaying apparatus
US7569407B2 (en) 2004-09-21 2009-08-04 Cree, Inc. Methods of coating semiconductor light emitting elements by evaporating solvent from a suspension
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060148250A1 (en) * 2004-12-30 2006-07-06 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060175532A1 (en) * 2005-02-08 2006-08-10 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7303931B2 (en) 2005-02-10 2007-12-04 Micron Technology, Inc. Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US20060177959A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US20060177999A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces
US7795649B2 (en) 2005-02-10 2010-09-14 Aptina Imaging Corporation Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US20080017943A1 (en) * 2005-02-10 2008-01-24 Boettiger Ulrich C Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US20060180887A1 (en) * 2005-02-15 2006-08-17 Sharp Kabushiki Kaisha Semiconductor device and production method thereof
US20070120212A1 (en) * 2005-02-18 2007-05-31 Boettiger Ulrich C Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US7696588B2 (en) 2005-02-18 2010-04-13 Aptina Imaging Corporation Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US7390687B2 (en) 2005-02-18 2008-06-24 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US20070096235A1 (en) * 2005-02-18 2007-05-03 Boettiger Ulrich C Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US7190039B2 (en) 2005-02-18 2007-03-13 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US20060186492A1 (en) * 2005-02-18 2006-08-24 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US20060197201A1 (en) * 2005-02-23 2006-09-07 Hsin Chung H Image sensor structure
US20060289968A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20060290001A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Interconnect vias and associated methods of formation
US9293367B2 (en) 2005-06-28 2016-03-22 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US8008192B2 (en) 2005-06-28 2011-08-30 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20070148807A1 (en) * 2005-08-22 2007-06-28 Salman Akram Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
CN100413042C (en) * 2005-08-25 2008-08-20 矽格股份有限公司 Packaging method for optical sensing semiconductor assembly and its packaging structure
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7288757B2 (en) 2005-09-01 2007-10-30 Micron Technology, Inc. Microelectronic imaging devices and associated methods for attaching transmissive elements
US7915736B2 (en) 2005-09-01 2011-03-29 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US20080001068A1 (en) * 2005-09-01 2008-01-03 Farnworth Warren M Microelectronic imaging devices and associated methods for attaching transmissive elements
US7663096B2 (en) 2005-09-01 2010-02-16 Aptina Imaging Corporation Microelectronic imaging devices and associated methods for attaching transmissive elements
US20100052183A1 (en) * 2005-09-01 2010-03-04 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US20070045858A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7485899B2 (en) * 2005-10-21 2009-02-03 Advanced Semiconductor Engineering, Inc. Semiconductor package having an optical device and the method of making the same
US20070090503A1 (en) * 2005-10-21 2007-04-26 Cheng-Wei Huang Semiconductor package having an optical device and the method of making the same
US20070200944A1 (en) * 2005-10-28 2007-08-30 Yasuo Takeuchi Manufacturing method for a solid-state imaging apparatus, and the solid-state imaging apparatus
US20070139923A1 (en) * 2005-12-21 2007-06-21 Led Lighting Fixtures, Inc. Lighting device
US8337071B2 (en) 2005-12-21 2012-12-25 Cree, Inc. Lighting device
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
US20080006775A1 (en) * 2006-06-22 2008-01-10 Arno Jose I Infrared gas detection systems and methods
US7943952B2 (en) 2006-07-31 2011-05-17 Cree, Inc. Method of uniform phosphor chip coating and LED package fabricated using method
US10295147B2 (en) 2006-11-09 2019-05-21 Cree, Inc. LED array and method for fabricating same
US8232564B2 (en) 2007-01-22 2012-07-31 Cree, Inc. Wafer level phosphor coating technique for warm light emitting diodes
US9159888B2 (en) 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US20080197375A1 (en) * 2007-02-15 2008-08-21 Wen-Kung Sung Lateral-type light-emitting diode and method of manufacture thereof
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same
EP2169723A1 (en) * 2007-07-12 2010-03-31 Sumitomo Bakelite Co., Ltd. Light receiving device and method of manufacturing light receiving device
EP2169723A4 (en) * 2007-07-12 2013-03-13 Sumitomo Bakelite Co Light receiving device and method of manufacturing light receiving device
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8637883B2 (en) 2008-03-19 2014-01-28 Cree, Inc. Low index spacer layer in LED devices
US8764226B2 (en) 2008-06-25 2014-07-01 Cree, Inc. Solid state array modules for general illumination
US20090323334A1 (en) * 2008-06-25 2009-12-31 Cree, Inc. Solid state linear array modules for general illumination
US8240875B2 (en) 2008-06-25 2012-08-14 Cree, Inc. Solid state linear array modules for general illumination
US20090321861A1 (en) * 2008-06-26 2009-12-31 Micron Technology, Inc. Microelectronic imagers with stacked lens assemblies and processes for wafer-level packaging of microelectronic imagers
US8359740B2 (en) * 2008-12-19 2013-01-29 3D Plus Process for the wafer-scale fabrication of electronic modules for surface mounting
US20110247210A1 (en) * 2008-12-19 2011-10-13 3D Plus Process for the wafer-scale fabrication of electronic modules for surface mounting
US20100194465A1 (en) * 2009-02-02 2010-08-05 Ali Salih Temperature compensated current source and method therefor
US9340878B2 (en) 2009-05-29 2016-05-17 Entegris, Inc. TPIR apparatus for monitoring tungsten hexafluoride processing to detect gas phase nucleation, and method and system utilizing same
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
US20120177358A1 (en) * 2011-01-10 2012-07-12 Apple Inc. Systems and methods for coupling a cover to an enclosure
US8434951B2 (en) * 2011-01-10 2013-05-07 Apple Inc. Systems and methods for coupling a cover to an enclosure
US9281301B2 (en) 2011-05-19 2016-03-08 Osram Opto Semiconductors Gmbh Optoelectronic device and method for producing optoelectronic devices
CN103548148A (en) * 2011-05-19 2014-01-29 欧司朗光电半导体有限公司 Optoelectronic device and method for producing optoelectronic devices
WO2012155984A1 (en) * 2011-05-19 2012-11-22 Osram Opto Semiconductors Gmbh Optoelectronic device and method for producing optoelectronic devices
US20130157419A1 (en) * 2011-12-19 2013-06-20 Nitto Denko Corporation Method of manufacturing semiconductor device
CN103205087A (en) * 2012-01-16 2013-07-17 日东电工株式会社 Resin Sheet For Hollow Encapsulation And Production Method For The Sheet, And Production Method For Hollow Electronic Part Apparatus And Hollow Electronic Part Apparatus
US10171918B2 (en) 2013-05-31 2019-01-01 Heptagon Micro Optics Pte. Ltd. MEMS microphone modules and wafer-level techniques for fabricating the same
WO2014193307A1 (en) * 2013-05-31 2014-12-04 Heptagon Micro Optics Pte. Ltd. Mems microphone modules and wafer-level techniques for fabricating the same
US9826316B2 (en) 2013-05-31 2017-11-21 Heptagon Micro Optics Pte. Ltd. MEMS microphone modules and wafer-level techniques for fabricating the same
US10435185B2 (en) * 2013-10-07 2019-10-08 David A. Divine 3-D printed packaging
US20150140784A1 (en) * 2013-11-21 2015-05-21 Disco Corporation Wafer processing method
US9123797B2 (en) * 2013-11-21 2015-09-01 Disco Corporation Resin powder wafer processing utilizing a frame with a plurality of partitions
US20150147870A1 (en) * 2013-11-25 2015-05-28 Disco Corporation Wafer processing method
US9112019B2 (en) * 2013-11-25 2015-08-18 Disco Corporation Wafer processing utilizing a frame with a plurality of partitions
US20150325548A1 (en) * 2014-05-12 2015-11-12 Skyworks Solutions, Inc. Devices and methods for processing singulated radio-frequency units
US9627352B2 (en) * 2014-05-12 2017-04-18 Skyworks Solutions, Inc. Devices and methods for processing singulated radio-frequency units
US20210336104A1 (en) * 2017-08-31 2021-10-28 Beijing Boe Optoelectronics Technology Co., Ltd. Light source structure, electronic device and manufacturing method of light source structure
CN107958915A (en) * 2017-12-22 2018-04-24 成都先锋材料有限公司 A kind of cmos sensor encapsulating structure and its method for packing
CN110015635A (en) * 2018-01-08 2019-07-16 罗伯特·博世有限公司 Environmental sensor, environmental sensor intermediate products and the method for manufacturing multiple environmental sensors
US20210343915A1 (en) * 2018-10-26 2021-11-04 Barco N.V. Led package
WO2020156955A1 (en) * 2019-01-31 2020-08-06 Robert Bosch Gmbh Method for producing a plurality of sensor devices, and sensor device
US20220041436A1 (en) * 2019-01-31 2022-02-10 Robert Bosch Gmbh Method for producing a plurality of sensor devices, and sensor device
CN113140467A (en) * 2019-07-31 2021-07-20 深圳宏芯宇电子股份有限公司 Integrated circuit packaging method and semiconductor device
WO2021121608A1 (en) * 2019-12-19 2021-06-24 Ev Group E. Thallner Gmbh Individual encapsulated component and method for the production thereof
WO2022104927A1 (en) * 2020-11-17 2022-05-27 瑞声声学科技(深圳)有限公司 Method for manufacturing mems sensor

Also Published As

Publication number Publication date
US7541658B2 (en) 2009-06-02
US20050173811A1 (en) 2005-08-11

Similar Documents

Publication Publication Date Title
US7541658B2 (en) Optically interactive device package array
US8115296B2 (en) Electronic device package
US7419854B2 (en) Methods for packaging image sensitive electronic devices
US7169645B2 (en) Methods of fabrication of package assemblies for optically interactive electronic devices
JP3859318B2 (en) Electronic circuit packaging method
US7457490B2 (en) Micro-optics on optoelectronics
KR101681360B1 (en) Method for Manufacturing Electronic Component Package
KR20100016402A (en) Method for producing an opto-electronic component and opto-electronic component
CN209401614U (en) Ambient light sensor packaging body
US6873024B1 (en) Apparatus and method for wafer level packaging of optical imaging semiconductor devices
US20090239329A1 (en) Method for manufacturing package structure of optical device
US7122407B2 (en) Method for fabricating window ball grid array semiconductor package
CN111276452A (en) Chip packaging structure and packaging method thereof
CN115472640B (en) Packaging structure and method of image sensor
KR101926721B1 (en) Semiconductor package and method for manufacturing the same
JP2003115563A (en) Electric component and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KINSMAN, LARRY D.;REEL/FRAME:013247/0012

Effective date: 20020821

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION