US20040029304A1 - Packaging of multiple active optical devices - Google Patents

Packaging of multiple active optical devices Download PDF

Info

Publication number
US20040029304A1
US20040029304A1 US10/635,180 US63518003A US2004029304A1 US 20040029304 A1 US20040029304 A1 US 20040029304A1 US 63518003 A US63518003 A US 63518003A US 2004029304 A1 US2004029304 A1 US 2004029304A1
Authority
US
United States
Prior art keywords
substrate
die
gold
solder
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/635,180
Inventor
Mikhail Naydenkov
Sivasubramaniam Yegnanarayanan
Quyen Huynh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US10/635,180 priority Critical patent/US20040029304A1/en
Publication of US20040029304A1 publication Critical patent/US20040029304A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12004Combinations of two or more optical elements
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/12007Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind forming wavelength selective elements, e.g. multiplexer, demultiplexer
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/26Optical coupling means
    • G02B6/28Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals
    • G02B6/2804Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals forming multipart couplers without wavelength selective elements, e.g. "T" couplers, star couplers
    • G02B6/2808Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals forming multipart couplers without wavelength selective elements, e.g. "T" couplers, star couplers using a mixing element which evenly distributes an input signal over a number of outputs
    • G02B6/2813Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals forming multipart couplers without wavelength selective elements, e.g. "T" couplers, star couplers using a mixing element which evenly distributes an input signal over a number of outputs based on multimode interference effect, i.e. self-imaging
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24Coupling light guides
    • G02B6/42Coupling light guides with opto-electronic elements
    • G02B6/4201Packages, e.g. shape, construction, internal or external details
    • G02B6/4219Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236Fixing or mounting methods of the aligned elements
    • G02B6/4238Soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process

Definitions

  • the present invention is related to photonic devices and, in particular to hybrid integrated optoelectronic circuits and optical packaging
  • Hybrid integrated optoelectronic circuits are commonly fabricated using discrete active and passive photonic devices and electronic devices.
  • Active photonic devices commonly include edge-emitting lasers such as Fabry-Perot (FP) & distributed feedback lasers (DFB), vertical cavity surface-emitting lasers (VCSEL), electro-absorption modulated lasers (EML), photodetectors, semiconductor optical amplifiers, electro-absorption modulators, and other discrete photonic devices.
  • Active optoelectronic (photonic) devices could be combined on the same chip with electronic circuits (devices), for example laser diode and laser driver circuit, and/or photodetector and transimpedance amplifier could be integrated on one chip.
  • Passive photonic components include guided wave optical elements and optical fibers.
  • WDM wavelength division multiplexed
  • CWDM/wideband WDM coarse-wavelength division multiplexers or demultiplexers
  • variable optical attenuators variable optical attenuators.
  • passive and active photonic devices typically are formed in a chip substrate using chemical processes and/or are bonded to the substrate using solders or epoxies.
  • each photonic device is aligned with its associated optical fiber and each optical fiber is aligned with its corresponding input waveguide of guided wave device.
  • One alignment technique involves a self-alignment in which the surface tension force of melted solder pulls each optoelectronic component being bonded to common substrate (or optical bench) into alignment position and when cooled the solder provides mechanical and electrical connection of the optoelectronic component (e.g., laser) die to a bonding pad on the common substrate.
  • the optoelectronic component e.g., laser
  • micro-machined mechanical stops further refine the alignment in that they restrict the movement of the discrete components.
  • Another technique involves active alignment, which involves, for example, powering the laser so that it emits light, coupling the light into a waveguide, and monitoring optical power at the output of the waveguide to determine whether light was coupled efficiently.
  • This is a widely used technique for packaging lasers/photodetectors with optical fiber for telecom applications.
  • the optoelectronic device e.g., laser/photodetector
  • the optoelectronic device is fixed onto a ceramic substrate.
  • Micro-optic components such as isolators and lens are then placed in front of the laser.
  • the fiber is then welded into place after optimizing its position to achieve optimum (i.e., >50%) coupling of light between the optical fiber and the optoelectronic device by active alignment.
  • active alignment is a time-consuming, largely manual process that requires expensive equipment, resulting in the packaging dominating the cost of the optoelectronic module.
  • assembly of small form-factor multiple component hybrid optoelectronic devices requires flip-chip bonding of several active optoelectronic components with fine pitch and high after-bonding alignment accuracy.
  • special mechanical pedestals are micro-machined on the substrate.
  • Such techniques offer the possibility of high accuracy active optoelectronic component die bonding without using active alignment or relying on self-alignment effect.
  • heating of the substrate during bonding of subsequent components can affect the alignment of the previously bonded components. That is, the cooled (solidified) solder bond on the previously bonded component die melts when the substrate is heated to bond the next component die and the previously bonded die moves, thereby affecting its optical coupling to a passive waveguide on the substrate or coupling to/from optical fiber.
  • FIG. 1 is a cross-section view of a hybrid optical circuit prior to bonding active optoelectronic device dies to a substrate according to an embodiment of the present invention
  • FIG. 2 is a flowchart illustrating an approach to bonding active optoelectronic device dies in FIG. 1 to the substrate in FIG. 1 according to embodiments of the present invention
  • FIG. 3 is a cross-section view of a hybrid optical circuit after bonding active optoelectronic device dies to a substrate according to an embodiment of the present invention
  • FIG. 4 is a graphical representation of the phase equilibrium for a gold-tin (Au—Sn) alloy system
  • FIG. 5 is a top view of the layout of the flip-chip assembly of the hybrid optical circuit in FIG. 1 according to an embodiment of the present invention
  • FIG. 6 is a block diagram of an optical power combiner according to an embodiment of the present invention.
  • FIG. 7 is a block diagram of an optical wavelength division multiplexing (WDM) receiver according to an embodiment of the present invention.
  • FIG. 8 is a perspective view of the substrate illustrated in FIG. 1 according to embodiments of the present.
  • FIG. 9 is a perspective view of a fragment of the hybrid optical circuit illustrated in FIG. 1 according to embodiments of the present invention.
  • Embodiments of the present invention utilize unique properties of a gold-tin (Au—Sn) alloy system to electrically and mechanically bond active optoelectronic device dies to a substrate at different times without disturbing previously bonded dies.
  • Au—Sn gold-tin
  • numerous specific details, such as particular processes, materials, devices, and so forth, are presented to provide a thorough understanding of embodiments of the invention.
  • One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, etc.
  • well-known structures or operations are not shown or described in detail to avoid obscuring various embodiments of the present invention.
  • FIG. 1 is a cross-section view of a hybrid optical circuit 100 , prior to bonding components to a substrate or optical bench, according to an embodiment of the present invention.
  • the hybrid optical circuit 100 includes a set of active optoelectronic device dies ( 102 , 112 , 122 , 132 ).
  • Each die ( 102 , 112 , 122 , 132 ) includes an active optoelectronic device ( 104 , 114 , 124 , 134 , respectively) and a gold-layered (Au) die bonding pad ( 106 , 116 , 126 , 136 , respectively) disposed on the device ( 104 , 114 , 124 , 134 , respectively).
  • a gold-tin (Au—Sn) solder layer ( 108 , 118 , 128 , 138 , respectively) may be disposed on the die bonding pad ( 106 , 116 , 126 , 136 , respectively).
  • the Au—Sn solder layers ( 108 , 118 , 128 , 138 ) are eighty percent gold (Au) by weight and twenty percent tin (Sn) by weight (80% wt/20% wt Au—Sn).
  • the hybrid optical circuit 100 includes a substrate 150 , which has a gold-layered (Au) substrate bonding pads ( 160 , 164 , 168 , 172 ) disposed in a well ( 162 , 166 , 170 , 174 , respectively).
  • Au gold-layered
  • Each die ( 102 , 112 , 122 , 132 ) is aligned to alignment marks on the bottom of a substrate well ( 162 , 166 , 170 , 174 , respectively), positioned on top of a substrate well ( 162 , 166 , 170 , 174 , respectively) so that the die bonding pad ( 106 , 116 , 126 , 136 , respectively), the solder layer ( 108 , 118 , 128 , 138 , respectively), and the substrate bonding pads ( 160 , 164 , 168 , 172 , respectively) are in mechanical contact.
  • Each die ( 102 , 112 , 122 , 132 ) is bonded to the substrate 150 using a die bonding pad ( 106 , 116 , 126 , 136 , respectively), the Au—Sn solder layer ( 108 , 118 , 128 , 138 , respectively), and the substrate bonding pad ( 160 , 164 , 168 , 172 , respectively), for example, in such a manner that after-bonding alignment is better than ⁇ 2 micron.
  • the gold-tin (Au—Sn) solder layer ( 108 , 118 , 128 , 138 , respectively) may be disposed on the substrate-bonding pad ( 160 , 164 , 168 , 172 , respectively), rather than or in addition to being disposed on a die-bonding pad ( 106 , 116 , 126 , 136 , respectively).
  • the active optoelectronic devices ( 104 , 114 , 124 , 134 ) also may be aligned to waveguides (shown in FIG. 8) also disposed on the substrate 150 so that optical mode of the active optoelectronic device ( 104 , 114 , 124 , 134 ) is efficiently coupled to optical mode of the waveguide.
  • the active optoelectronic device dies may be edge-emitting laser dies, vertical cavity surface-emitting laser dies (VCSEL), photodetector dies, semiconductor optical amplifier dies, and other discrete photonic device dies with devices that generate light when stimulated, that sense light, convert light to electrical signals, or that condition light.
  • the active optoelectronic devices dies may have different operating wavelengths.
  • the substrate 150 may be a silicon substrate, a silicon-on insulator (SOI) substrate, or other suitable substrate that provides good electrical and thermal properties for the placement of the optoelectronic die.
  • SOI silicon-on insulator
  • an insulator layer of silicon oxide e.g., SiO 2 , glass
  • Si intrinsic silicon
  • An intrinsic Si layer may be formed on the insulator layer.
  • the SOI substrate may be a bond-and-etchback-silicon-on-insulator (BESOI) substrate, which is obtained by growing SiO 2 on the two Si wafers and bonding the Si wafers together by wafer fusion. The top Si wafer is subsequently thinned to the desired thickness.
  • BESOI bond-and-etchback-silicon-on-insulator
  • the SOI substrate may be separation-by-implanted-oxygen (SIMOX) SOI substrate, which is obtained by implanting oxygen at a well-defined depth (controlled by implant energy) into silicon and annealing the silicon to form a buried SiO 2 (BOX) layer.
  • SIMOX separation-by-implanted-oxygen
  • the substrate 150 may be micro-machined in accordance with well-known techniques to form the substrate wells ( 162 , 166 , 170 , 174 ).
  • the substrate 150 may be dry etched to form the substrate wells ( 162 , 166 , 170 , 174 ).
  • FIG. 2 is a flowchart illustrating an example method 200 for mechanically and electrically bonding dies to a substrate according to embodiments of the present invention.
  • the dies are bonded to the substrate with after-bonding accuracy better than ⁇ 2 microns.
  • This after-bonding alignment accuracy is sufficient to efficiently couple light into and/or out of various photonic devices when alignment tolerances between optical devices are relaxed using special input/output optical structures such mode-taper structures. In addition, this tolerance would be sufficient for low-coupling applications in short-reach optical links.
  • the dies may be bonded to the substrate using a flip-chip bonder.
  • a suitable flip-chip bonder includes a bottom chuck, a bonding arm, a heated pick-up tool, “x”-“y” positioners, and optical viewing system.
  • a suitable flip-chip bonder may be a proprietary flip-chip bonder or one available from FINETECH in Berlin, Germany.
  • a machine-readable medium with machine-readable instructions thereon may be used to cause a processor to perform the process 200 .
  • a substrate is positioned on the bottom chuck of the flip-chip bonder and the heated pick-up tool picks up a die.
  • a block 204 heats the substrate and the substrate bonding pad to a temperature less than or equal to the eutectic temperature of an Au—Sn alloy solder.
  • eutectic refers to a structure, temperature, and/or phase of an alloy system characterized by equilibrium between solid state and liquid state. Alloys of eutectic composition completely (100%) transform into liquid phase when heated above the eutectic temperature and completely (100%) transforms into solid phase when cooled below the eutectic temperature.
  • a common eutectic Au—Sn solder composition has eighty percent gold (Au) by weight and twenty percent tin (Sn) by weight (i.e., 80% wt/20% wt Au—Sn solder), but can be in the eutectic range depicted in phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system shown in FIG. 4 below.
  • a computer may control the flow of a hot inert (or forming) gas when used to reduce oxidation on the bonding interface between the substrate and the die.
  • the inert gas may be nitrogen.
  • a forming gas is a mixture of hydrogen and nitrogen and is used to render the inert atmosphere while bonding die to substrate.
  • a block 206 heats the die to a temperature greater than or equal to the eutectic temperature of eutectic Au—Sn alloy solder, which also causes the eutectic Au—Sn alloy solder to begin to melt
  • a block 208 aligns the die with alignment marks on the substrate or with a waveguide formed in or on the substrate.
  • the die is aligned using the “x”-“y” positioners and the optical viewing system.
  • Unique alignment marks/features may be implemented on the top-layer metallization in the die and the substrate to facilitate machine-vision based rapid alignment between the die and substrate. Such techniques are well known and widely used for flip-chip packaging of optoelectronic die onto substrate.
  • the heated pick-up tool brings the die-bonding pad into contact with a eutectic gold-tin (AuSn) solder layer on the substrate pad.
  • AuSn gold-tin
  • the bonding arm applies a small force to the die and holds the die in the alignment position until the gold-tin (Au—Sn) solder layer on the gold (Au) substrate-bonding pad transforms from a eutectic composition to zeta-phase (4-phase).
  • zeta-phase refers to a structure, temperature, and/or phase of an alloy system characterized by spontaneous local freezing during the bonding process. Zeta-phase transforms directly from a solid phase to a liquid phase when heated up to a temperatures above the “liquidus” line of the phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG.
  • a common zeta-phase Au—Sn solder composition has eighty-eight percent gold (Au) by weight and twelve percent tin (Sn) by weight (i.e., 88% wt/12% wt Au—Sn solder), but can be in the zeta-phase range depicted in phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG. 4 below.
  • Sn from the gold-tin (Au—Sn) solder layer will diffuse into gold (Au) on the die-bonding pad and the gold (Au) on the substrate-bonding pad, and the gold-tin (Au—Sn) solder layer begins to “consume” gold (Au) from the die-bonding pad and the substrate-bonding pad.
  • the die is positioned in the “z” direction using the micro-machined pedestals (or mechanical stops). When the solder is melted the bonding arm forces the die against its respective pedestal.
  • Au—Sn solder layer At a certain weight percentage of gold (Au) in the gold-tin (Au—Sn) solder layer (as illustrated by the phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG. 4) the gold-tin (Au—Sn) solder layer transforms into zeta-phase and solidifies completely and a bond between the die and the substrate is formed.
  • the melting point of the bond is very high (e.g., 532 degrees Centigrade) as compared to the melting point commonly used to bond dies to substrates. As a result, the bond and die alignment are not disturbed when heating the substrate to bond subsequent dies.
  • the weight percentage of gold (Au) in the gold-tin (Au—Sn) solder layer is approximately 88-90% wt, the solder layer transforms into zeta-phase and solidifies completely, and the bond between the substrate and the die is formed.
  • the die may not have a gold-tin (Au—Sn) solder layer on its die-bonding pad. Instead, the gold-tin (Au—Sn) solder layer is on the substrate-bonding pad.
  • the temperature of the substrate when heating, the temperature of the substrate is maintained below melting point of eutectic gold-tin (Au—Sn) solder to prevent a dramatic increase in diffusion of tin (Sn) into gold (Au) on the substrate-bonding pad.
  • the die is heated to a temperature above the melting point of eutectic gold-tin (Au—Sn) solder.
  • the amount of gold (Au) on the substrate-bonding pad is not enough to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase. Rather, the combined amount of gold on the die-bonding pad and the substrate-bonding pad is sufficient to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase.
  • the eutectic gold-tin (Au—Sn) solder is disposed on the die-bonding pad and the substrate-bonding pad does not have eutectic gold-tin (Au—Sn) solder.
  • the die-bonding pad when heating, is brought to a temperature that is slightly lower than the melting point of eutectic gold-tin (Au—Sn) solder and the substrate-bonding pad is brought to a temperature that is slightly higher than the melting point of eutectic gold-tin (Au—Sn) solder.
  • the amount of gold (Au) on the die-bonding pad is not sufficient to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase.
  • the amount of gold (Au) on the substrate-bonding pad is sufficient to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase.
  • the eutectic gold-tin (Au—Sn) solder is disposed on the die-bonding pad and the substrate-bonding pad.
  • either of the heating processes performed in the block 212 may be used to bond the die with the substrate.
  • the pick-up tool releases the die (e.g., the tool vacuum for the pick-up tool is turned “off”) and the flip-chip bonder ceases the flow of hot inert (or forming) gas.
  • the bond between the die and the substrate cools and the method 200 repeats itself (e.g., returns to block 202 ) for the next die(s).
  • the eutectic Au—Sn solder layer, the die-bonding pad, and/or the substrate bonding-pad are heated to the melting point of eutectic Au—Sn.
  • the previously bonded die remains bonded to the substrate and aligned because the bond between the previously bonded die and the substrate melts at a temperature that is greater than eutectic Au—Sn eutectic temperature.
  • the eutectic Au—Sn solder layer may be replaced by alternating layers of Sn and Au in predetermined weight ratios such that when melted the alternating layers of Au and Sn form a eutectic Au—Sn solder composition and when heated further form a zeta-phase composition of Au—Sn.
  • a layer of titanium and a layer of platinum may be present in the bonding-pad structure.
  • the structure of the bonding pad may be titanium over platinum over gold.
  • other materials also may be used.
  • FIG. 3 a cross-section view of a hybrid optical circuit 100 after bonding the active optoelectronic device dies ( 102 , 112 , 122 , 132 ) to the substrate 150 according to an embodiment of the present invention.
  • the eutectic Au—Sn solder layers ( 108 , 118 , 128 , 138 ) and the substrate bonding pads ( 106 , 116 , 126 , 136 ) have been inter-diffused to create other Au—Sn compositions ( 302 , 304 , 306 , 308 , respectively), such as the zeta-phase Au—Sn composition whose composition is 88-90% wt of gold (Au) and 12-10% wt of tin (Sn) respectively, and whose subsequent melting temperature is greater than 500° Centigrade (approximately 532° Centigrade).
  • the Au—Sn compositions ( 302 , 304 , 306 , 308 ) may be made from the Au from the die bonding pads ( 160 , 164 , 168 , 172 ), or Au from the die bonding pads ( 160 , 164 , 168 , 172 ) and the substrate bonding pads ( 106 , 116 , 126 , 136 ).
  • FIG. 4 is a graphical representation 400 of the phase equilibrium for a gold-tin (Au—Sn) alloy system, such as the system created by the eutectic Au—Sn solder layers ( 108 , 118 , 128 , 138 ), the die bonding pads ( 106 , 116 , 126 , 136 ), and the substrate bonding pads ( 160 , 164 , 168 , 172 ).
  • the graphical representation 400 illustrates that for a given weight ratio of Au to Sn, the Au—Sn alloy system will liquefy when it reaches a specific temperature. As the weight ratio of Au to Sn in the Au—Sn alloy system changes, the temperature at which the Au—Sn alloy system liquefies also changes.
  • the graphical representation 400 includes an “x” axis 402 , which represent temperature in degrees centigrade, and a “y” axis, which represents the percentage of Sn in an Au—Sn alloy system.
  • the graphical representation 400 also includes a (dotted line parabolic) curve 406 , the area under which represents the zeta-phase of an Au—Sn alloy system.
  • the graphical representation 400 illustrates that at a point 408 the Au—Sn alloy system is a eutectic composition, the percentage of approximately Sn is twenty and the percentage of Au is approximately eighty, and the melting temperature of the cooled compound (i.e., point of liquefaction) of such an Au—Sn system is approximately 278 degrees Centigrade.
  • the melting temperature of the cooled compound i.e., point of liquefaction
  • FIG. 5 is a top view of a hybrid optical circuit 500 according to an embodiment of the present invention, in which the substrate bonding pads ( 160 , 164 , 168 , 172 ) are coupled to wire bonding pads ( 502 , 504 , 506 , 508 , respectively) located in substrate wells ( 512 , 514 , 516 , 518 , respectively).
  • the wire bonding pads ( 502 , 504 , 506 , 508 ) may include solder bumps, which electrically connect the active optoelectronic device dies ( 102 , 112 , 122 , 132 ) to other circuitry on the substrate 150 .
  • the substrate wells 512 , 514 , 516 , 518 may be formed in a manner similar to the substrate wells 162 , 166 , 170 , 174 .
  • the wire bonding pads ( 502 , 504 , 506 , 508 ) may be routed to the side of the substrate 150 to provide access to both edges of the active optoelectronic device dies ( 102 , 112 , 122 , 132 ) so that light may be coupled from both edges of the active optoelectronic device dies ( 102 , 112 , 122 , 132 ).
  • optical waveguides are to be placed at the input and output of dies
  • optical fiber is to be placed at the input and output of dies
  • micro-optic components are to be placed at the input and output of dies (e.g., lens/isolators/diffraction gratings, etc.), and/or when other components, such as photodetector die/laser die, are to be placed at the input and output of dies.
  • each optoelectronic device dies may be an optical amplifier (SOA) or any other optoelectronic die, thereby enables placement of multiple SOA/other optoelectronic die with high-precision and close proximity on the substrate, in order to realize arrays of device.
  • SOA optical amplifier
  • Each die may be optimized to operate at a specific wavelength.
  • FIG. 6 is a block diagram of a four-by-one optical power combiner 600 according to an alternative embodiment of the present invention, in which the active optoelectronic device (e.g., laser) dies 102 , 112 , 122 , and 132 are bonded to the substrate 150 as described herein.
  • the substrate 150 includes several waveguides ( 602 , 612 , 622 , 632 ), which may be formed on the substrate 150 using reactive ion etching according to well known techniques.
  • Each active optoelectronic device die ( 102 , 112 , 122 , and 132 ) is aligned with a waveguide ( 602 , 612 , 622 , 632 , respectively) such that light from the active optoelectronic devices ( 104 , 114 , 124 , 134 , respectively) is efficiently coupled to its respective waveguide ( 602 , 612 , 622 , 632 , respectively).
  • the light emitting portion of the active optoelectronic device dies 102 , 112 , 122 , 132 may be directly coupled to the light transmitting portion of the waveguides 602 , 612 , 622 , 632 , respectively. Additionally, using the flip-chip bonder described above, placement to within one micron ( ⁇ 1 ⁇ m) accuracy may be achieved.
  • the operating wavelengths (or colors) of the active optoelectronic devices are dissimilar.
  • the waveguides ( 602 , 612 , 622 , 632 ) are coupled to a multiplexer 650 , which multiplexes the different wavelengths into a single light signal.
  • the multiplexer 650 may be a multimode interference (MMI) device or an arrayed waveguide grating (AWG) device.
  • a waveguide 652 formed on the substrate 150 in a manner equivalent to the waveguides 602 , 612 , 622 , 632 , is coupled to the multiplexer 650 to direct the multiplexed light signal to other circuitry on or outside the optical power combiner 600 .
  • FIG. 7 is a block diagram of a one-by-four WDM receiver module 700 according to an alternative embodiment of the present invention, in which the active optoelectronic device (e.g., photodetector) dies 102 , 112 , 122 , and 132 are bonded to the substrate 150 as described herein.
  • the active optoelectronic device e.g., photodetector
  • Each photodetector die ( 102 , 112 , 122 , and 132 ) is aligned with a waveguide ( 602 , 612 , 622 , 632 , respectively) formed on the substrate 150 as described herein such that light from the waveguides is efficiently coupled to its respective photodetector ( 104 , 114 , 124 , 134 , respectively).
  • Such a configuration would work optimally for an edge-illuminated photodetector.
  • other mechanical structures such as mirror/beam turner may be defined on the substrate 150 to direct the light from the optical waveguide/fiber into the photodetector aperture.
  • the light receiving portion of the photodetector dies 102 , 112 , 122 , 132 may be efficiently coupled to the light transmitting portion of the waveguides 602 , 612 , 622 , 632 , respectively.
  • the operating wavelengths (or colors) of the photodetectors ( 104 , 114 , 124 , 134 ) are dissimilar.
  • Resonantly enhanced photodetectors offer improved performance over a narrowband wavelength range.
  • typical p-i-n type photodetectors offer a wide operating wavelength range of ⁇ 100 nm or so.
  • the waveguides ( 602 , 612 , 622 , 632 ) are coupled to a demultiplexer 702 , which separates the different wavelengths out of a multiplexed light signal.
  • a waveguide 652 is coupled to the demultiplexer 702 to direct the multiplexed light signal to the demultiplexer 702 from other circuitry on or outside of the optical WDM receiver module 700 .
  • FIG. 8 is a perspective view of a fragment 800 of the substrate 150 according to embodiments of the present invention.
  • the substrate 150 includes a waveguide 802 and one of the substrate wells 162 .
  • An edge 804 defines the position of an active optoelectronic device die in the “z” direction.
  • the waveguide 802 may be formed in the second intrinsic Si layer, by dry etching to remove all but selective portions of the second intrinsic Si layer, for example.
  • FIG. 9 is a perspective view of a fragment 900 of the substrate 150 according to embodiments of the present invention.
  • FIG. 9 shows one of the active optoelectronic device dies 102 bonded to a substrate-bonding pad disposed inside the substrate well 162 and aligned to the waveguide 802 in accordance with embodiments of the present invention.
  • Embodiments of the invention can be implemented using hardware, software, or a combination of hardware and software. Such implementations include state machines and application specific integrated circuits (ASICs).
  • the software may be stored on a computer program product (such as an optical disk, a magnetic disk, a floppy disk, etc.) or a program storage device (such as an optical disk drive, a magnetic disk drive, a floppy disk drive, etc.).

Abstract

A cost effective method is provided for assembly of hybrid optoelectronic circuits requiring flip-chip bonding of multiple active optoelectronic devices onto common substrate or optical bench platform with fine pitch and high accuracy “after-bonding” alignment to the alignment features on substrate and/or to other elements of the hybrid circuit. A Flip-Chip Bonder equipped with high precision Bonding Arm and optical and mechanical system, heated substrate chuck and heated pick-up tool may be used both for alignment and thermal bonding of active component dies to corresponding bonding pads on the common substrate using gold-tin (Au—Sn) solder disposed between die bonding pad and the corresponding substrate bonding pad. During bonding of the first die, tin (Sn) diffuses from a eutectic composition of gold-tin (Au—Sn) solder to (gold (Au) on) the die-bonding pad and/or (gold (Au) on) the substrate bonding-pad resulting in transformation of the Au—Sn eutectic composition to a zeta-phase composition having much higher melting temperature as compared to that of a eutectic composition. As bonding of one or more subsequent dies is performed at temperatures equal to or slightly higher than the melting temperature of a eutectic composition and significantly lower than the melting temperature of a zeta-phase composition, the gold-tin (Au—Sn) solder at the bond of previously attached die does not melt and, consequently, the alignment is not compromised.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • The present application is related to U.S. patent application Ser. No. 10/109,166 [Attorney Docket No. 42390.P13372], filed Mar. 27, 2002 entitled “Packaging of Multiple Active Optical Devices,” with inventors Mikhail Naydenkov, Sivasubramaniam Yegnanarayanan and Quyen Huynh.[0001]
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention is related to photonic devices and, in particular to hybrid integrated optoelectronic circuits and optical packaging [0003]
  • 2. Background Information [0004]
  • Hybrid integrated optoelectronic circuits are commonly fabricated using discrete active and passive photonic devices and electronic devices. Active photonic devices commonly include edge-emitting lasers such as Fabry-Perot (FP) & distributed feedback lasers (DFB), vertical cavity surface-emitting lasers (VCSEL), electro-absorption modulated lasers (EML), photodetectors, semiconductor optical amplifiers, electro-absorption modulators, and other discrete photonic devices. Active optoelectronic (photonic) devices could be combined on the same chip with electronic circuits (devices), for example laser diode and laser driver circuit, and/or photodetector and transimpedance amplifier could be integrated on one chip. At the same time discrete photonic and electronic devices could be bonded to a common substrate, which provides electrical and optical interconnects for the devices. Passive photonic components include guided wave optical elements and optical fibers. Passive photonic components include 1×N (N=2,4,8,16) optical splitters, combiners, wavelength division multiplexed (WDM) or coarse-wavelength division multiplexers or demultiplexers (CWDM/wideband WDM), variable optical attenuators. To fabricate hybrid optoelectronic circuits, passive and active photonic devices typically are formed in a chip substrate using chemical processes and/or are bonded to the substrate using solders or epoxies. [0005]
  • In the prior art, light is coupled from separately packaged photonic devices into optical fibers and then coupled from the optical fibers to separately packaged waveguide devices. To ensure optimal coupling of light, each photonic device is aligned with its associated optical fiber and each optical fiber is aligned with its corresponding input waveguide of guided wave device. [0006]
  • One alignment technique involves a self-alignment in which the surface tension force of melted solder pulls each optoelectronic component being bonded to common substrate (or optical bench) into alignment position and when cooled the solder provides mechanical and electrical connection of the optoelectronic component (e.g., laser) die to a bonding pad on the common substrate. In some instances, micro-machined mechanical stops further refine the alignment in that they restrict the movement of the discrete components. [0007]
  • Another technique involves active alignment, which involves, for example, powering the laser so that it emits light, coupling the light into a waveguide, and monitoring optical power at the output of the waveguide to determine whether light was coupled efficiently. This is a widely used technique for packaging lasers/photodetectors with optical fiber for telecom applications. The optoelectronic device (e.g., laser/photodetector) is fixed onto a ceramic substrate. Micro-optic components such as isolators and lens are then placed in front of the laser. The fiber is then welded into place after optimizing its position to achieve optimum (i.e., >50%) coupling of light between the optical fiber and the optoelectronic device by active alignment. Typically active alignment is a time-consuming, largely manual process that requires expensive equipment, resulting in the packaging dominating the cost of the optoelectronic module. [0008]
  • With the gradual migration of optical links from long-haul transport to the enterprise and eventually the desktop, there is a growing need for highly functional optical and optoelectronic components that occupy a small form-factor, and that are inexpensive. New optical packaging approaches need to be developed in order to address this need. [0009]
  • For instance, assembly of small form-factor multiple component hybrid optoelectronic devices requires flip-chip bonding of several active optoelectronic components with fine pitch and high after-bonding alignment accuracy. Currently there are volume manufacturing ready Flip-Chip Bonders that can place an optoelectronic die onto the two-dimensional surface of the substrate with placement accuracy of ±1 μm available, with much shorter cycle times compared to active alignment. In order for edge-emitter devices to couple to each other and onto optical fiber, similar accuracy is required for die placement in the vertical (“z”) direction. To achieve alignment accuracy in the “z” direction, special mechanical pedestals are micro-machined on the substrate. [0010]
  • Such techniques offer the possibility of high accuracy active optoelectronic component die bonding without using active alignment or relying on self-alignment effect. However heating of the substrate during bonding of subsequent components (e.g., laser dies) can affect the alignment of the previously bonded components. That is, the cooled (solidified) solder bond on the previously bonded component die melts when the substrate is heated to bond the next component die and the previously bonded die moves, thereby affecting its optical coupling to a passive waveguide on the substrate or coupling to/from optical fiber. [0011]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally equivalent elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number, in which: [0012]
  • FIG. 1 is a cross-section view of a hybrid optical circuit prior to bonding active optoelectronic device dies to a substrate according to an embodiment of the present invention; [0013]
  • FIG. 2 is a flowchart illustrating an approach to bonding active optoelectronic device dies in FIG. 1 to the substrate in FIG. 1 according to embodiments of the present invention; [0014]
  • FIG. 3 is a cross-section view of a hybrid optical circuit after bonding active optoelectronic device dies to a substrate according to an embodiment of the present invention; [0015]
  • FIG. 4 is a graphical representation of the phase equilibrium for a gold-tin (Au—Sn) alloy system; [0016]
  • FIG. 5 is a top view of the layout of the flip-chip assembly of the hybrid optical circuit in FIG. 1 according to an embodiment of the present invention; [0017]
  • FIG. 6 is a block diagram of an optical power combiner according to an embodiment of the present invention; [0018]
  • FIG. 7 is a block diagram of an optical wavelength division multiplexing (WDM) receiver according to an embodiment of the present invention; [0019]
  • FIG. 8 is a perspective view of the substrate illustrated in FIG. 1 according to embodiments of the present; and [0020]
  • FIG. 9 is a perspective view of a fragment of the hybrid optical circuit illustrated in FIG. 1 according to embodiments of the present invention.[0021]
  • DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS OF THE PRESENT INVENTION
  • Embodiments of the present invention utilize unique properties of a gold-tin (Au—Sn) alloy system to electrically and mechanically bond active optoelectronic device dies to a substrate at different times without disturbing previously bonded dies. In the following description, numerous specific details, such as particular processes, materials, devices, and so forth, are presented to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, etc. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring various embodiments of the present invention. [0022]
  • Some parts of the description will be presented using terms such as waveguide, silicon, solder, active optoelectronic device, multiplexer, eutectic, and so forth. These terms are commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. [0023]
  • Various operations will be described as multiple discrete blocks performed in turn in a manner that is most helpful in understanding the invention. However, the order in which they are described should not be construed to imply that these operations are necessarily order dependent or that the operations be performed in the order in which the blocks are presented. [0024]
  • Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, process, block, or characteristic described in connection with the embodiment of the present invention is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment of the present invention” or “in an embodiment of the present invention” in various places throughout this specification are not necessarily all referring to the same embodiment of the present invention. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments of the present invention. [0025]
  • FIG. 1 is a cross-section view of a hybrid [0026] optical circuit 100, prior to bonding components to a substrate or optical bench, according to an embodiment of the present invention. In the illustrated embodiment of the present invention, the hybrid optical circuit 100 includes a set of active optoelectronic device dies (102, 112, 122, 132). Each die (102, 112, 122, 132) includes an active optoelectronic device (104, 114, 124, 134, respectively) and a gold-layered (Au) die bonding pad (106, 116, 126, 136, respectively) disposed on the device (104, 114, 124, 134, respectively).
  • In one embodiment of the present invention, A gold-tin (Au—Sn) solder layer ([0027] 108, 118, 128, 138, respectively) may be disposed on the die bonding pad (106, 116, 126, 136, respectively). In one embodiment of the present invention, the Au—Sn solder layers (108, 118, 128, 138) are eighty percent gold (Au) by weight and twenty percent tin (Sn) by weight (80% wt/20% wt Au—Sn).
  • The hybrid [0028] optical circuit 100 includes a substrate 150, which has a gold-layered (Au) substrate bonding pads (160, 164, 168, 172) disposed in a well (162, 166, 170, 174, respectively). Each die (102, 112, 122, 132) is aligned to alignment marks on the bottom of a substrate well (162, 166, 170, 174, respectively), positioned on top of a substrate well (162, 166, 170, 174, respectively) so that the die bonding pad (106, 116, 126, 136, respectively), the solder layer (108, 118, 128, 138, respectively), and the substrate bonding pads (160, 164, 168, 172, respectively) are in mechanical contact. Each die (102, 112, 122, 132) is bonded to the substrate 150 using a die bonding pad (106, 116, 126, 136, respectively), the Au—Sn solder layer (108, 118, 128, 138, respectively), and the substrate bonding pad (160, 164, 168, 172, respectively), for example, in such a manner that after-bonding alignment is better than ±2 micron.
  • In an alternative embodiment of the present invention, the gold-tin (Au—Sn) solder layer ([0029] 108, 118, 128, 138, respectively) may be disposed on the substrate-bonding pad (160, 164, 168, 172, respectively), rather than or in addition to being disposed on a die-bonding pad (106, 116, 126, 136, respectively). The active optoelectronic devices (104, 114, 124, 134) also may be aligned to waveguides (shown in FIG. 8) also disposed on the substrate 150 so that optical mode of the active optoelectronic device (104, 114, 124, 134) is efficiently coupled to optical mode of the waveguide.
  • According to an embodiment of the present invention, the active optoelectronic device dies ([0030] 102, 112, 122, 132) may be edge-emitting laser dies, vertical cavity surface-emitting laser dies (VCSEL), photodetector dies, semiconductor optical amplifier dies, and other discrete photonic device dies with devices that generate light when stimulated, that sense light, convert light to electrical signals, or that condition light. The active optoelectronic devices dies (104, 114, 124, 134) may have different operating wavelengths.
  • The substrate [0031] 150 (or optical bench) may be a silicon substrate, a silicon-on insulator (SOI) substrate, or other suitable substrate that provides good electrical and thermal properties for the placement of the optoelectronic die. For example, when the substrate is an SOI substrate an insulator layer of silicon oxide (e.g., SiO2, glass) may be formed (e.g., by growing, implanting, bonding, etc.) on an intrinsic silicon (Si) substrate in a well-known manner. An intrinsic Si layer may be formed on the insulator layer.
  • The SOI substrate may be a bond-and-etchback-silicon-on-insulator (BESOI) substrate, which is obtained by growing SiO[0032] 2 on the two Si wafers and bonding the Si wafers together by wafer fusion. The top Si wafer is subsequently thinned to the desired thickness. The SOI substrate may be separation-by-implanted-oxygen (SIMOX) SOI substrate, which is obtained by implanting oxygen at a well-defined depth (controlled by implant energy) into silicon and annealing the silicon to form a buried SiO2 (BOX) layer.
  • The [0033] substrate 150 may be micro-machined in accordance with well-known techniques to form the substrate wells (162, 166, 170, 174). For example, the substrate 150 may be dry etched to form the substrate wells (162, 166, 170, 174).
  • FIG. 2 is a flowchart illustrating an [0034] example method 200 for mechanically and electrically bonding dies to a substrate according to embodiments of the present invention. In one embodiment of the present invention, the dies are bonded to the substrate with after-bonding accuracy better than ±2 microns. This after-bonding alignment accuracy is sufficient to efficiently couple light into and/or out of various photonic devices when alignment tolerances between optical devices are relaxed using special input/output optical structures such mode-taper structures. In addition, this tolerance would be sufficient for low-coupling applications in short-reach optical links.
  • The dies may be bonded to the substrate using a flip-chip bonder. A suitable flip-chip bonder includes a bottom chuck, a bonding arm, a heated pick-up tool, “x”-“y” positioners, and optical viewing system. A suitable flip-chip bonder may be a proprietary flip-chip bonder or one available from FINETECH in Berlin, Germany. A machine-readable medium with machine-readable instructions thereon may be used to cause a processor to perform the [0035] process 200.
  • In a [0036] block 202, a substrate is positioned on the bottom chuck of the flip-chip bonder and the heated pick-up tool picks up a die.
  • A [0037] block 204 heats the substrate and the substrate bonding pad to a temperature less than or equal to the eutectic temperature of an Au—Sn alloy solder. As used herein, the term “eutectic” refers to a structure, temperature, and/or phase of an alloy system characterized by equilibrium between solid state and liquid state. Alloys of eutectic composition completely (100%) transform into liquid phase when heated above the eutectic temperature and completely (100%) transforms into solid phase when cooled below the eutectic temperature. For example, a common eutectic Au—Sn solder composition has eighty percent gold (Au) by weight and twenty percent tin (Sn) by weight (i.e., 80% wt/20% wt Au—Sn solder), but can be in the eutectic range depicted in phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system shown in FIG. 4 below.
  • When heating the substrate and the substrate-bonding pad, a computer may control the flow of a hot inert (or forming) gas when used to reduce oxidation on the bonding interface between the substrate and the die. The inert gas may be nitrogen. Generally, a forming gas is a mixture of hydrogen and nitrogen and is used to render the inert atmosphere while bonding die to substrate. [0038]
  • A [0039] block 206 heats the die to a temperature greater than or equal to the eutectic temperature of eutectic Au—Sn alloy solder, which also causes the eutectic Au—Sn alloy solder to begin to melt
  • A [0040] block 208 aligns the die with alignment marks on the substrate or with a waveguide formed in or on the substrate. In one embodiment of the present invention, the die is aligned using the “x”-“y” positioners and the optical viewing system. Unique alignment marks/features may be implemented on the top-layer metallization in the die and the substrate to facilitate machine-vision based rapid alignment between the die and substrate. Such techniques are well known and widely used for flip-chip packaging of optoelectronic die onto substrate.
  • In a [0041] block 210, the heated pick-up tool brings the die-bonding pad into contact with a eutectic gold-tin (AuSn) solder layer on the substrate pad.
  • In a block [0042] 212, the bonding arm applies a small force to the die and holds the die in the alignment position until the gold-tin (Au—Sn) solder layer on the gold (Au) substrate-bonding pad transforms from a eutectic composition to zeta-phase (4-phase). As used herein, the term “zeta-phase” refers to a structure, temperature, and/or phase of an alloy system characterized by spontaneous local freezing during the bonding process. Zeta-phase transforms directly from a solid phase to a liquid phase when heated up to a temperatures above the “liquidus” line of the phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG. 4 below and transforms directly into a solid phases when cooled down to a temperature below “solidus” line of the phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG. 4 below. For example, a common zeta-phase Au—Sn solder composition has eighty-eight percent gold (Au) by weight and twelve percent tin (Sn) by weight (i.e., 88% wt/12% wt Au—Sn solder), but can be in the zeta-phase range depicted in phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG. 4 below.
  • In the block [0043] 212, Sn from the gold-tin (Au—Sn) solder layer will diffuse into gold (Au) on the die-bonding pad and the gold (Au) on the substrate-bonding pad, and the gold-tin (Au—Sn) solder layer begins to “consume” gold (Au) from the die-bonding pad and the substrate-bonding pad. The die is positioned in the “z” direction using the micro-machined pedestals (or mechanical stops). When the solder is melted the bonding arm forces the die against its respective pedestal.
  • At a certain weight percentage of gold (Au) in the gold-tin (Au—Sn) solder layer (as illustrated by the phase equilibrium graphical representation for a gold-tin (Au—Sn) alloy system depicted in FIG. 4) the gold-tin (Au—Sn) solder layer transforms into zeta-phase and solidifies completely and a bond between the die and the substrate is formed. [0044]
  • The melting point of the bond is very high (e.g., 532 degrees Centigrade) as compared to the melting point commonly used to bond dies to substrates. As a result, the bond and die alignment are not disturbed when heating the substrate to bond subsequent dies. According to one embodiment of the present invention, when the weight percentage of gold (Au) in the gold-tin (Au—Sn) solder layer is approximately 88-90% wt, the solder layer transforms into zeta-phase and solidifies completely, and the bond between the substrate and the die is formed. [0045]
  • According to embodiments of the present invention, the die may not have a gold-tin (Au—Sn) solder layer on its die-bonding pad. Instead, the gold-tin (Au—Sn) solder layer is on the substrate-bonding pad. In this embodiment of the present invention, when heating, the temperature of the substrate is maintained below melting point of eutectic gold-tin (Au—Sn) solder to prevent a dramatic increase in diffusion of tin (Sn) into gold (Au) on the substrate-bonding pad. Thus, the die is heated to a temperature above the melting point of eutectic gold-tin (Au—Sn) solder. Additionally, the amount of gold (Au) on the substrate-bonding pad is not enough to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase. Rather, the combined amount of gold on the die-bonding pad and the substrate-bonding pad is sufficient to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase. [0046]
  • In alternative embodiments of the present invention, the eutectic gold-tin (Au—Sn) solder is disposed on the die-bonding pad and the substrate-bonding pad does not have eutectic gold-tin (Au—Sn) solder. In this embodiment of the present invention, when heating, the die-bonding pad is brought to a temperature that is slightly lower than the melting point of eutectic gold-tin (Au—Sn) solder and the substrate-bonding pad is brought to a temperature that is slightly higher than the melting point of eutectic gold-tin (Au—Sn) solder. Additionally, the amount of gold (Au) on the die-bonding pad is not sufficient to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase. However, the amount of gold (Au) on the substrate-bonding pad is sufficient to transform the eutectic gold-tin (Au—Sn) solder from eutectic to zeta-phase. [0047]
  • In other embodiments of the present invention, the eutectic gold-tin (Au—Sn) solder is disposed on the die-bonding pad and the substrate-bonding pad. In this embodiment of the present invention, either of the heating processes performed in the block [0048] 212 may be used to bond the die with the substrate.
  • In a [0049] block 214, the pick-up tool releases the die (e.g., the tool vacuum for the pick-up tool is turned “off”) and the flip-chip bonder ceases the flow of hot inert (or forming) gas.
  • In a [0050] block 216, the bond between the die and the substrate cools and the method 200 repeats itself (e.g., returns to block 202) for the next die(s). For example, the eutectic Au—Sn solder layer, the die-bonding pad, and/or the substrate bonding-pad are heated to the melting point of eutectic Au—Sn. However, unlike prior art processes, the previously bonded die remains bonded to the substrate and aligned because the bond between the previously bonded die and the substrate melts at a temperature that is greater than eutectic Au—Sn eutectic temperature.
  • Of course, there may be other layer arrangements disposed in a multiple layer stack (i.e., instead of the die bonding pad, eutectic Au—Sn solder layer, and the substrate bonding pad arrangement). For example, the eutectic Au—Sn solder layer may be replaced by alternating layers of Sn and Au in predetermined weight ratios such that when melted the alternating layers of Au and Sn form a eutectic Au—Sn solder composition and when heated further form a zeta-phase composition of Au—Sn. [0051]
  • Additionally, a layer of titanium and a layer of platinum may be present in the bonding-pad structure. In this embodiment of the present invention, the structure of the bonding pad may be titanium over platinum over gold. In other embodiments of the present invention, other materials also may be used. [0052]
  • FIG. 3 a cross-section view of a hybrid [0053] optical circuit 100 after bonding the active optoelectronic device dies (102, 112, 122, 132) to the substrate 150 according to an embodiment of the present invention. In the embodiment of the present invention shown, the eutectic Au—Sn solder layers (108, 118, 128, 138) and the substrate bonding pads (106, 116, 126, 136) have been inter-diffused to create other Au—Sn compositions (302, 304, 306, 308, respectively), such as the zeta-phase Au—Sn composition whose composition is 88-90% wt of gold (Au) and 12-10% wt of tin (Sn) respectively, and whose subsequent melting temperature is greater than 500° Centigrade (approximately 532° Centigrade). Of course, the Au—Sn compositions (302, 304, 306, 308) may be made from the Au from the die bonding pads (160, 164, 168, 172), or Au from the die bonding pads (160, 164, 168, 172) and the substrate bonding pads (106, 116, 126, 136).
  • FIG. 4 is a [0054] graphical representation 400 of the phase equilibrium for a gold-tin (Au—Sn) alloy system, such as the system created by the eutectic Au—Sn solder layers (108, 118, 128, 138), the die bonding pads (106, 116, 126, 136), and the substrate bonding pads (160, 164, 168, 172). The graphical representation 400 illustrates that for a given weight ratio of Au to Sn, the Au—Sn alloy system will liquefy when it reaches a specific temperature. As the weight ratio of Au to Sn in the Au—Sn alloy system changes, the temperature at which the Au—Sn alloy system liquefies also changes.
  • The [0055] graphical representation 400 includes an “x” axis 402, which represent temperature in degrees centigrade, and a “y” axis, which represents the percentage of Sn in an Au—Sn alloy system. The graphical representation 400 also includes a (dotted line parabolic) curve 406, the area under which represents the zeta-phase of an Au—Sn alloy system. The graphical representation 400 illustrates that at a point 408 the Au—Sn alloy system is a eutectic composition, the percentage of approximately Sn is twenty and the percentage of Au is approximately eighty, and the melting temperature of the cooled compound (i.e., point of liquefaction) of such an Au—Sn system is approximately 278 degrees Centigrade. Interpretation of the graphical representation 400 is well known.
  • FIG. 5 is a top view of a hybrid optical circuit [0056] 500 according to an embodiment of the present invention, in which the substrate bonding pads (160, 164, 168, 172) are coupled to wire bonding pads (502, 504, 506, 508, respectively) located in substrate wells (512, 514, 516, 518, respectively). The wire bonding pads (502, 504, 506, 508) may include solder bumps, which electrically connect the active optoelectronic device dies (102, 112, 122, 132) to other circuitry on the substrate 150. The substrate wells 512, 514, 516, 518 may be formed in a manner similar to the substrate wells 162, 166, 170, 174.
  • In another embodiment, the wire bonding pads ([0057] 502, 504, 506, 508) may be routed to the side of the substrate 150 to provide access to both edges of the active optoelectronic device dies (102, 112, 122, 132) so that light may be coupled from both edges of the active optoelectronic device dies (102, 112, 122, 132). This may be useful for applications in which optical waveguides are to be placed at the input and output of dies, in which optical fiber is to be placed at the input and output of dies, in which micro-optic components are to be placed at the input and output of dies (e.g., lens/isolators/diffraction gratings, etc.), and/or when other components, such as photodetector die/laser die, are to be placed at the input and output of dies.
  • According to an embodiment of the present invention, each optoelectronic device dies ([0058] 102, 112, 122, 132) may be an optical amplifier (SOA) or any other optoelectronic die, thereby enables placement of multiple SOA/other optoelectronic die with high-precision and close proximity on the substrate, in order to realize arrays of device. Each die may be optimized to operate at a specific wavelength.
  • FIG. 6 is a block diagram of a four-by-one [0059] optical power combiner 600 according to an alternative embodiment of the present invention, in which the active optoelectronic device (e.g., laser) dies 102, 112, 122, and 132 are bonded to the substrate 150 as described herein. The substrate 150 includes several waveguides (602, 612, 622, 632), which may be formed on the substrate 150 using reactive ion etching according to well known techniques. Each active optoelectronic device die (102, 112, 122, and 132) is aligned with a waveguide (602, 612, 622, 632, respectively) such that light from the active optoelectronic devices (104, 114, 124, 134, respectively) is efficiently coupled to its respective waveguide (602, 612, 622, 632, respectively).
  • Recall from above that in the prior art, light is coupled from separately packaged active optoelectronic devices into optical fibers and then coupled from the optical fibers to separately packaged waveguides on a substrate. According to an embodiment of the present invention, however, the light emitting portion of the active optoelectronic device dies [0060] 102, 112, 122, 132 may be directly coupled to the light transmitting portion of the waveguides 602, 612, 622, 632, respectively. Additionally, using the flip-chip bonder described above, placement to within one micron (±1 μm) accuracy may be achieved.
  • In one embodiment of the present invention, the operating wavelengths (or colors) of the active optoelectronic devices ([0061] 104, 114, 124, 134) are dissimilar. The waveguides (602, 612, 622, 632) are coupled to a multiplexer 650, which multiplexes the different wavelengths into a single light signal. In alternative embodiment of the present invention, the multiplexer 650 may be a multimode interference (MMI) device or an arrayed waveguide grating (AWG) device. A waveguide 652, formed on the substrate 150 in a manner equivalent to the waveguides 602, 612, 622, 632, is coupled to the multiplexer 650 to direct the multiplexed light signal to other circuitry on or outside the optical power combiner 600.
  • FIG. 7 is a block diagram of a one-by-four [0062] WDM receiver module 700 according to an alternative embodiment of the present invention, in which the active optoelectronic device (e.g., photodetector) dies 102, 112, 122, and 132 are bonded to the substrate 150 as described herein. Each photodetector die (102, 112, 122, and 132) is aligned with a waveguide (602, 612, 622, 632, respectively) formed on the substrate 150 as described herein such that light from the waveguides is efficiently coupled to its respective photodetector (104, 114, 124, 134, respectively). Such a configuration would work optimally for an edge-illuminated photodetector. For surface illuminated photodetectors, other mechanical structures such as mirror/beam turner may be defined on the substrate 150 to direct the light from the optical waveguide/fiber into the photodetector aperture.
  • Although not so depicted, instead of coupling light between the photodetector dies [0063] 102, 112, 122, 132 and the waveguides 602, 612, 622, 632, respectively, using optical fibers, the light receiving portion of the photodetector dies 102, 112, 122, 132 may be efficiently coupled to the light transmitting portion of the waveguides 602, 612, 622, 632, respectively.
  • According to an embodiment of the present invention, the operating wavelengths (or colors) of the photodetectors ([0064] 104, 114, 124, 134) are dissimilar. (Note: Resonantly enhanced photodetectors offer improved performance over a narrowband wavelength range. However, typical p-i-n type photodetectors offer a wide operating wavelength range of ˜100 nm or so). The waveguides (602, 612, 622, 632) are coupled to a demultiplexer 702, which separates the different wavelengths out of a multiplexed light signal. A waveguide 652 is coupled to the demultiplexer 702 to direct the multiplexed light signal to the demultiplexer 702 from other circuitry on or outside of the optical WDM receiver module 700.
  • FIG. 8 is a perspective view of a [0065] fragment 800 of the substrate 150 according to embodiments of the present invention. In the illustrated embodiment of the present invention, the substrate 150 includes a waveguide 802 and one of the substrate wells 162. An edge 804 defines the position of an active optoelectronic device die in the “z” direction. The waveguide 802 may be formed in the second intrinsic Si layer, by dry etching to remove all but selective portions of the second intrinsic Si layer, for example.
  • FIG. 9 is a perspective view of a [0066] fragment 900 of the substrate 150 according to embodiments of the present invention. FIG. 9 shows one of the active optoelectronic device dies 102 bonded to a substrate-bonding pad disposed inside the substrate well 162 and aligned to the waveguide 802 in accordance with embodiments of the present invention.
  • Embodiments of the invention can be implemented using hardware, software, or a combination of hardware and software. Such implementations include state machines and application specific integrated circuits (ASICs). In implementations using software, the software may be stored on a computer program product (such as an optical disk, a magnetic disk, a floppy disk, etc.) or a program storage device (such as an optical disk drive, a magnetic disk drive, a floppy disk drive, etc.). [0067]
  • The above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications can be made to the invention in light of the above detailed description. [0068]
  • The terms used in the following claims should not be construed to limit the invention to the specific embodiments of the present invention disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. [0069]

Claims (14)

What is claimed is:
1. An apparatus, comprising:
an active optoelectronic device die bonded to a substrate using a zeta-phase composition of a gold-tin (Au—Sn) solder.
2. The apparatus of claim 1, wherein the zeta-phase composition of Au—Sn solder comprises an 88-90% wt/12-10% wt Au—Sn solder composition.
3. The apparatus of claim 1, wherein the active optoelectronic device die comprises an optical modulator die.
4. The apparatus of claim 3, wherein the substrate comprises a silicon substrate.
5. An apparatus, comprising:
an active optoelectronic device die bonded to a substrate using a gold-tin (Au—Sn) solder composition whose melting temperature is greater than the eutectic temperature of eutectic Au—Sn solder, the die further comprising a gold-layered die bonding pad and a gold-layered substrate bonding pad disposed in a well of the substrate.
6. The apparatus of claim 5, wherein the solder composition whose melting temperature is greater than the eutectic temperature of eutectic Au—Sn solder comprises an Au—Sn solder composition whose melting temperature is greater than approximately two hundred seventy-eight degrees Centigrade.
7. The apparatus of claim 5, wherein the active optoelectronic device die comprises light emitting diode die.
8. The apparatus of claim 7, wherein the substrate comprises a silicon substrate having wire-bonding pads routed to either side of the substrate.
9. A system, comprising:
an active optoelectronic device die bonded to a substrate using a zeta-phase composition of a gold-tin (Au—Sn) solder; and
a waveguide disposed on the substrate and operatively aligned to the active optoelectronic device die.
10. The system of claim 9, further comprising:
a second active device die bonded to the substrate using a zeta-phase composition of a gold-tin (Au—Sn) solder; and
a second waveguide disposed on the substrate and operatively coupled to receive light from the second active optoelectronic device die.
11. The system of claim 10, further comprising a light combiner disposed on the substrate and operatively coupled to receive and combine light from the first and the second active device dies.
12. The system of claim 11, further comprising a third waveguide disposed on the substrate and operatively coupled to receive light from the light combiner.
13. The system of claim 11, wherein the first and second active optoelectronic devices comprise a first and a second laser die having a first and a second operating wavelength, respectively.
14. The system of claim 10, further comprising a demultiplexer disposed on the substrate and operatively coupled to separate and transmit light having a first wavelength to the first active optoelectronic device die and light having a second wavelength to the second active optoelectronic device die.
US10/635,180 2002-03-27 2003-08-05 Packaging of multiple active optical devices Abandoned US20040029304A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/635,180 US20040029304A1 (en) 2002-03-27 2003-08-05 Packaging of multiple active optical devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/109,166 US6660548B2 (en) 2002-03-27 2002-03-27 Packaging of multiple active optical devices
US10/635,180 US20040029304A1 (en) 2002-03-27 2003-08-05 Packaging of multiple active optical devices

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/109,166 Division US6660548B2 (en) 2002-03-27 2002-03-27 Packaging of multiple active optical devices

Publications (1)

Publication Number Publication Date
US20040029304A1 true US20040029304A1 (en) 2004-02-12

Family

ID=28453034

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/109,166 Expired - Fee Related US6660548B2 (en) 2002-03-27 2002-03-27 Packaging of multiple active optical devices
US10/635,180 Abandoned US20040029304A1 (en) 2002-03-27 2003-08-05 Packaging of multiple active optical devices

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/109,166 Expired - Fee Related US6660548B2 (en) 2002-03-27 2002-03-27 Packaging of multiple active optical devices

Country Status (4)

Country Link
US (2) US6660548B2 (en)
AU (1) AU2003228282A1 (en)
TW (1) TWI238892B (en)
WO (1) WO2003083545A2 (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011851A1 (en) * 2001-06-29 2003-01-16 John Trezza Redundant optical device array
US20050136640A1 (en) * 2002-01-07 2005-06-23 Chuan Hu Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
EP1575089A1 (en) * 2004-03-09 2005-09-14 Infineon Technologies AG Highly reliable, cost effective and thermally enhanced AuSn die-attach technology
US20060281292A1 (en) * 2005-06-14 2006-12-14 John Trezza Rigid-backed, membrane-based chip tooling
US20060281219A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip-based thermo-stack
US20060278992A1 (en) * 2005-06-14 2006-12-14 John Trezza Post & penetration interconnection
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US20060278981A1 (en) * 2005-06-14 2006-12-14 John Trezza Electronic chip contact structure
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20060278986A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip capacitive coupling
US20060278995A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip spanning connection
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US20070161235A1 (en) * 2005-06-14 2007-07-12 John Trezza Back-to-front via process
US20070281466A1 (en) * 2006-06-06 2007-12-06 John Trezza Front-end processed wafer having through-chip connections
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20070278641A1 (en) * 2005-06-14 2007-12-06 John Trezza Side Stacking Apparatus and Method
US20080153209A1 (en) * 2002-01-07 2008-06-26 Intel Corporation Thinned die integrated circuit package
US20090174079A1 (en) * 2007-02-16 2009-07-09 John Trezza Plated pillar package formation
US20090317033A1 (en) * 2008-06-20 2009-12-24 Industrial Technology Research Institute Integrated circuit and photonic board thereof
US20100140776A1 (en) * 2005-06-14 2010-06-10 John Trezza Triaxial through-chip connecton
US20100261297A1 (en) * 2005-06-14 2010-10-14 John Trezza Remote chip attachment
US8240545B1 (en) 2011-08-11 2012-08-14 Western Digital (Fremont), Llc Methods for minimizing component shift during soldering
WO2013106008A2 (en) * 2011-03-30 2013-07-18 Intel Corporation On-chip diffraction grating prepared by crystallographic wet-etch
US9042048B1 (en) 2014-09-30 2015-05-26 Western Digital (Fremont), Llc Laser-ignited reactive HAMR bonding
US9070387B1 (en) 2013-08-23 2015-06-30 Western Digital Technologies, Inc. Integrated heat-assisted magnetic recording head/laser assembly
US9257138B1 (en) 2014-10-28 2016-02-09 Western Digital (Fremont), Llc Slider assembly and method of manufacturing same

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7195941B2 (en) * 2003-03-26 2007-03-27 Intel Corporation Optical devices and methods to construct the same
TWI229911B (en) * 2003-12-16 2005-03-21 Univ Nat Central Method for controlling the bond microstructures
US7236666B2 (en) * 2004-09-30 2007-06-26 Intel Corporation On-substrate microlens to couple an off-substrate light emitter and/or receiver with an on-substrate optical device
US7283699B2 (en) * 2004-09-30 2007-10-16 Intel Corporation Optical package
US7419839B2 (en) 2004-11-12 2008-09-02 Philips Lumileds Lighting Company, Llc Bonding an optical element to a light emitting device
JP4617902B2 (en) * 2005-01-31 2011-01-26 信越半導体株式会社 Light emitting device and method for manufacturing light emitting device
US7790484B2 (en) * 2005-06-08 2010-09-07 Sharp Kabushiki Kaisha Method for manufacturing laser devices
US9084377B2 (en) * 2007-03-30 2015-07-14 Stats Chippac Ltd. Integrated circuit package system with mounting features for clearance
US8964805B2 (en) * 2009-03-12 2015-02-24 Futurewei Technologies, Inc. Thermally optimized mechanical interface for hybrid integrated wavelength division multiplexed arrayed transmitter
US20110089438A1 (en) * 2009-10-19 2011-04-21 Zarlink Semiconductor Ab Opto-electrical assemblies and associated apparatus and methods
WO2012047232A1 (en) 2010-10-08 2012-04-12 Hewlett-Packard Development Company, L.P. Optical multiplexing using laser arrays
JP5281122B2 (en) * 2011-06-16 2013-09-04 株式会社フジクラ Joining method and manufacturing method
KR101927559B1 (en) 2011-08-30 2018-12-10 에베 그룹 에. 탈너 게엠베하 Method for permanently bonding wafers by a connecting layer by means of solid-state diffusion or phase transformation
US9706670B1 (en) * 2015-12-31 2017-07-11 International Business Machines Corporation Connecting mid-board electronic devices
US10209477B1 (en) * 2017-05-25 2019-02-19 Lockheed Martin Coherent Technologies, Inc. Systems and methods for reconfigurable micro-optic assemblies
DE102017112866A1 (en) * 2017-06-12 2018-12-13 Osram Opto Semiconductors Gmbh Method for mounting a semiconductor chip on a substrate and electronic component
CN108109948A (en) * 2017-11-22 2018-06-01 贵州振华风光半导体有限公司 A kind of method of surface mount integrated circuit Vacuum Eutectic welding chip positioning
US11280968B2 (en) 2020-02-21 2022-03-22 International Business Machines Corporation High-bandwidth embedded optical connector with latching mechanism
US20210288035A1 (en) * 2020-03-12 2021-09-16 Intel Corporation Active bridge enabled co-packaged photonic transceiver
CN112363041B (en) * 2020-11-21 2021-09-28 深圳中科精工科技有限公司 Full-automatic AA equipment for semiconductor
US11860428B1 (en) * 2022-06-09 2024-01-02 Unimicron Technology Corp. Package structure and optical signal transmitter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534442A (en) * 1991-05-10 1996-07-09 Northern Telecom Limited Process of providing uniform photoresist thickness on an opto-electronic device
USH1934H1 (en) * 1992-05-01 2001-01-02 Lucent Technologies, Inc. Gold-tin solder suitable for self-aligning applications
US6489687B1 (en) * 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment
US20030095736A1 (en) * 2001-10-09 2003-05-22 Kish Fred A. Transmitter photonic integrated circuit (TxPIC) chip architectures and drive systems and wavelength stabilization for TxPICs

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280414A (en) * 1990-06-11 1994-01-18 International Business Machines Corp. Au-Sn transient liquid bonding in high performance laminates
JP3147141B2 (en) * 1995-08-30 2001-03-19 株式会社日立製作所 Light assembly
KR100198460B1 (en) * 1996-10-29 1999-06-15 이계철 Optical module and its fabrication method having lens aligned on v-groove
US6124827A (en) * 1996-12-30 2000-09-26 Green; Leon Photonic phase and time delay-steered arrays
US5990560A (en) * 1997-10-22 1999-11-23 Lucent Technologies Inc. Method and compositions for achieving a kinetically controlled solder bond
US6207950B1 (en) * 1999-01-11 2001-03-27 Lightlogic, Inc. Optical electronic assembly having a flexure for maintaining alignment between optical elements
SE513575C2 (en) * 1999-02-19 2000-10-02 Ericsson Telefon Ab L M Method and apparatus for passively aligning at least one optical fiber to at least one optical device
KR100302144B1 (en) * 1999-08-05 2001-11-01 고한준 connector-type optical transceiver using SOI optical wave-guide

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534442A (en) * 1991-05-10 1996-07-09 Northern Telecom Limited Process of providing uniform photoresist thickness on an opto-electronic device
USH1934H1 (en) * 1992-05-01 2001-01-02 Lucent Technologies, Inc. Gold-tin solder suitable for self-aligning applications
US6489687B1 (en) * 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment
US20030095736A1 (en) * 2001-10-09 2003-05-22 Kish Fred A. Transmitter photonic integrated circuit (TxPIC) chip architectures and drive systems and wavelength stabilization for TxPICs

Cited By (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7831151B2 (en) 2001-06-29 2010-11-09 John Trezza Redundant optical device array
US20030011851A1 (en) * 2001-06-29 2003-01-16 John Trezza Redundant optical device array
US20050136640A1 (en) * 2002-01-07 2005-06-23 Chuan Hu Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
US7888183B2 (en) 2002-01-07 2011-02-15 Intel Corporation Thinned die integrated circuit package
US20080153209A1 (en) * 2002-01-07 2008-06-26 Intel Corporation Thinned die integrated circuit package
US20070181987A1 (en) * 2004-03-09 2007-08-09 Sam-Hyo Hong Highly reliable, cost effective and thermally enhanced AuSn die-attach technology
EP1575089A1 (en) * 2004-03-09 2005-09-14 Infineon Technologies AG Highly reliable, cost effective and thermally enhanced AuSn die-attach technology
WO2005086220A1 (en) * 2004-03-09 2005-09-15 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced ausn die-attach technology
US7608485B2 (en) 2004-03-09 2009-10-27 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced AuSn die-attach technology
WO2006039176A1 (en) * 2004-09-30 2006-04-13 Intel Corporation Die exhibiting an effective coefficient of thermal expansion equivalent to a substrate mounted thereon, and processes of making same
US20100140776A1 (en) * 2005-06-14 2010-06-10 John Trezza Triaxial through-chip connecton
US20070167004A1 (en) * 2005-06-14 2007-07-19 John Trezza Triaxial through-chip connection
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US20060281243A1 (en) * 2005-06-14 2006-12-14 John Trezza Through chip connection
US20060278981A1 (en) * 2005-06-14 2006-12-14 John Trezza Electronic chip contact structure
US20060278966A1 (en) * 2005-06-14 2006-12-14 John Trezza Contact-based encapsulation
US20060281307A1 (en) * 2005-06-14 2006-12-14 John Trezza Post-attachment chip-to-chip connection
US20060281296A1 (en) * 2005-06-14 2006-12-14 Abhay Misra Routingless chip architecture
US20060278986A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip capacitive coupling
US20060278995A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip spanning connection
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US20070120241A1 (en) * 2005-06-14 2007-05-31 John Trezza Pin-type chip tooling
US20070138562A1 (en) * 2005-06-14 2007-06-21 Cubic Wafer, Inc. Coaxial through chip connection
US20070161235A1 (en) * 2005-06-14 2007-07-12 John Trezza Back-to-front via process
US20070158839A1 (en) * 2005-06-14 2007-07-12 John Trezza Thermally balanced via
US7785987B2 (en) 2005-06-14 2010-08-31 John Trezza Isolating chip-to-chip contact
US20070172987A1 (en) * 2005-06-14 2007-07-26 Roger Dugas Membrane-based chip tooling
US20060278980A1 (en) * 2005-06-14 2006-12-14 John Trezza Patterned contact
US20070182020A1 (en) * 2005-06-14 2007-08-09 John Trezza Chip connector
US20070197013A1 (en) * 2005-06-14 2007-08-23 Cubic Wafer, Inc. Processed Wafer Via
US20070196948A1 (en) * 2005-06-14 2007-08-23 John Trezza Stacked chip-based system and method
US20070228576A1 (en) * 2005-06-14 2007-10-04 John Trezza Isolating chip-to-chip contact
US9324629B2 (en) 2005-06-14 2016-04-26 Cufer Asset Ltd. L.L.C. Tooling for coupling multiple electronic chips
US9147635B2 (en) 2005-06-14 2015-09-29 Cufer Asset Ltd. L.L.C. Contact-based encapsulation
US20070278641A1 (en) * 2005-06-14 2007-12-06 John Trezza Side Stacking Apparatus and Method
US20060278992A1 (en) * 2005-06-14 2006-12-14 John Trezza Post & penetration interconnection
US20080171174A1 (en) * 2005-06-14 2008-07-17 John Trezza Electrically conductive interconnect system and method
US20090137116A1 (en) * 2005-06-14 2009-05-28 Cufer Asset Ltd. L.L.C. Isolating chip-to-chip contact
US8846445B2 (en) 2005-06-14 2014-09-30 Cufer Asset Ltd. L.L.C. Inverse chip connector
US20060278994A1 (en) * 2005-06-14 2006-12-14 John Trezza Inverse chip connector
US8643186B2 (en) 2005-06-14 2014-02-04 Cufer Asset Ltd. L.L.C. Processed wafer via
US7659202B2 (en) 2005-06-14 2010-02-09 John Trezza Triaxial through-chip connection
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US20060278988A1 (en) * 2005-06-14 2006-12-14 John Trezza Profiled contact
US20100148343A1 (en) * 2005-06-14 2010-06-17 John Trezza Side stacking apparatus and method
US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7785931B2 (en) 2005-06-14 2010-08-31 John Trezza Chip-based thermo-stack
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US20100197134A1 (en) * 2005-06-14 2010-08-05 John Trezza Coaxial through chip connection
US8283778B2 (en) 2005-06-14 2012-10-09 Cufer Asset Ltd. L.L.C. Thermally balanced via
US20060278993A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip connector
US7808111B2 (en) 2005-06-14 2010-10-05 John Trezza Processed wafer via
US20100261297A1 (en) * 2005-06-14 2010-10-14 John Trezza Remote chip attachment
US20060281219A1 (en) * 2005-06-14 2006-12-14 John Trezza Chip-based thermo-stack
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7847412B2 (en) 2005-06-14 2010-12-07 John Trezza Isolating chip-to-chip contact
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7884483B2 (en) 2005-06-14 2011-02-08 Cufer Asset Ltd. L.L.C. Chip connector
US20060281292A1 (en) * 2005-06-14 2006-12-14 John Trezza Rigid-backed, membrane-based chip tooling
US7919870B2 (en) 2005-06-14 2011-04-05 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US7932584B2 (en) 2005-06-14 2011-04-26 Cufer Asset Ltd. L.L.C. Stacked chip-based system and method
US7942182B2 (en) 2005-06-14 2011-05-17 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US7946331B2 (en) 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US7969015B2 (en) 2005-06-14 2011-06-28 Cufer Asset Ltd. L.L.C. Inverse chip connector
US7989958B2 (en) 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US20110212573A1 (en) * 2005-06-14 2011-09-01 John Trezza Rigid-backed, membrane-based chip tooling
US8021922B2 (en) 2005-06-14 2011-09-20 Cufer Asset Ltd. L.L.C. Remote chip attachment
US8053903B2 (en) 2005-06-14 2011-11-08 Cufer Asset Ltd. L.L.C. Chip capacitive coupling
US8067312B2 (en) 2005-06-14 2011-11-29 Cufer Asset Ltd. L.L.C. Coaxial through chip connection
US8084851B2 (en) 2005-06-14 2011-12-27 Cufer Asset Ltd. L.L.C. Side stacking apparatus and method
US8093729B2 (en) 2005-06-14 2012-01-10 Cufer Asset Ltd. L.L.C. Electrically conductive interconnect system and method
US8154131B2 (en) 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US8197626B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
US8197627B2 (en) 2005-06-14 2012-06-12 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US8232194B2 (en) 2005-06-14 2012-07-31 Cufer Asset Ltd. L.L.C. Process for chip capacitive coupling
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US20070281466A1 (en) * 2006-06-06 2007-12-06 John Trezza Front-end processed wafer having through-chip connections
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20090174079A1 (en) * 2007-02-16 2009-07-09 John Trezza Plated pillar package formation
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US20090317033A1 (en) * 2008-06-20 2009-12-24 Industrial Technology Research Institute Integrated circuit and photonic board thereof
US8970956B2 (en) 2011-03-30 2015-03-03 Intel Corporation On-chip diffraction grating prepared by crystallographic wet-etch
WO2013106008A3 (en) * 2011-03-30 2013-10-03 Intel Corporation On-chip diffraction grating prepared by crystallographic wet-etch
WO2013106008A2 (en) * 2011-03-30 2013-07-18 Intel Corporation On-chip diffraction grating prepared by crystallographic wet-etch
US9360601B2 (en) 2011-03-30 2016-06-07 Intel Corporation On-chip diffraction grating prepared by crystallographic wet-etch
US8240545B1 (en) 2011-08-11 2012-08-14 Western Digital (Fremont), Llc Methods for minimizing component shift during soldering
US9070387B1 (en) 2013-08-23 2015-06-30 Western Digital Technologies, Inc. Integrated heat-assisted magnetic recording head/laser assembly
US9042048B1 (en) 2014-09-30 2015-05-26 Western Digital (Fremont), Llc Laser-ignited reactive HAMR bonding
US9257138B1 (en) 2014-10-28 2016-02-09 Western Digital (Fremont), Llc Slider assembly and method of manufacturing same

Also Published As

Publication number Publication date
US6660548B2 (en) 2003-12-09
WO2003083545A2 (en) 2003-10-09
AU2003228282A8 (en) 2003-10-13
WO2003083545A3 (en) 2004-02-26
TW200406591A (en) 2004-05-01
AU2003228282A1 (en) 2003-10-13
TWI238892B (en) 2005-09-01
US20030186476A1 (en) 2003-10-02

Similar Documents

Publication Publication Date Title
US6660548B2 (en) Packaging of multiple active optical devices
US11163126B2 (en) Light source assembly supporting direct coupling to an integrated circuit
US9829661B2 (en) Method and system for hybrid integration of optical communication systems
Pavarelli et al. Optical and electronic packaging processes for silicon photonic systems
EP1328047B1 (en) Optical component attachment to optoelectronic packages
EP0699931A1 (en) Passive alignment and packaging of optoelectronic components to optical waveguides using flip-chip bonding technology
Hashimoto et al. Multichip optical hybrid integration technique with planar lightwave circuit platform
EP2696229A2 (en) Method and system for hybrid integration of optical communication systems
KR100302144B1 (en) connector-type optical transceiver using SOI optical wave-guide
JPH0611632A (en) Automatic-matching optical fiber link
Valk et al. Laser welding for fiber pigtailing with long-term stability and submicron accuracy
CN100355014C (en) Topside active optical device apparatus and method
Nakasuga et al. Multi-chip hybrid integration on PLC platform using passive alignment technique
JP2006072171A (en) Optical module
Kang et al. Fabrication of semiconductor optical switch module using laser welding technique
Lee et al. Optoelectronic packaging for optical interconnects
Ogawa et al. Packaging technology for ultra-small variable optical attenuator multiplexer (V-AWG) with multichip PLC integration structure using chip-scale-package PD array
JP2004186692A (en) Method of manufacturing electronic module including active component in base
JP2001007352A (en) Optical-electrical mixedly mounted module
JP2003229636A (en) Semiconductor laser element and semiconductor laser device
JP5759401B2 (en) Multi-channel optical transmission module and manufacturing method thereof
Dagenais et al. Complex needs drive optoelectronic integration
Rho et al. Multichip Integration on a PLC Platform for 16$\,\times\, $16 Optical Switch Module Using Passive Alignment Technique
Ohyama et al. Hybrid integrated multiwavelength photoreceivers consisting of photo-diodes and an arrayed-waveguide grating
CN110034486A (en) Optical module

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION