US20040019753A1 - System and method for multiple store buffer forwarding in a system with a restrictive memory model - Google Patents
System and method for multiple store buffer forwarding in a system with a restrictive memory model Download PDFInfo
- Publication number
- US20040019753A1 US20040019753A1 US10/620,555 US62055503A US2004019753A1 US 20040019753 A1 US20040019753 A1 US 20040019753A1 US 62055503 A US62055503 A US 62055503A US 2004019753 A1 US2004019753 A1 US 2004019753A1
- Authority
- US
- United States
- Prior art keywords
- memory
- store
- instruction
- data
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000013598 vector Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 230000001419 dependent effect Effects 0.000 description 4
- 238000005457 optimization Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000013479 data entry Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
Definitions
- the present invention relates to store buffer forwarding in microprocessors, and more particularly, to multiple store buffer forwarding in a microprocessor system with a restrictive memory model.
- the TSO memory model has two restrictions related to store buffer forwarding:
- a younger load operation may only receive forwarded data from a single older store buffer entry
- FIG. 1 is a flow diagram of a method for providing multiple store buffer forwarding, in accordance with an embodiment of the present invention.
- FIG. 3 is a block diagram of a computer system in which multiple store buffer forwarding can be implemented, in accordance with an embodiment of the present invention.
- the system and method provide a novel mechanism to allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the two TSO restrictions thereby increasing processor performance without violating the restrictive memory model.
- the problem can be described using some sample program executions.
- the following sample code segment demonstrates the type of store buffer forwarding that the TSO memory model specifically allows: MOV EBX, 0x1000 ; set up the base address MOV [EBX], 0x00001234 ; store 4 bytes (0x00001234) to location 0x1000 . . . ; zero or more other instructions MOV EAX, [EBX] ; load 4 bytes from location 0x1000
- store buffer forwarding hardware is permitted to bypass the store data value (0x00001234) directly to the younger load operation even before other processors observe the store data value.
- the above single store operation's data completely overlaps, that is, covers, the memory region that the load operation references.
- the same four bytes in the memory that are used by the store operation to store the data value are used by the load operation.
- This sample code segment demonstrates a type of store buffer forwarding that is not allowed in the IA-32 restrictive memory model (TSO): MOV EBX, 0x1000 ; set up the base address MOV [EBX], 0x0000 ; store 2 bytes (0x0000) to location 0x1000 MOV [EBX] +2, 0x1234 ; store 2 bytes (0x1234) to location 0x1002 . . . ; zero or more other instructions MOV EAX, [EBX] ; load 4 bytes, from location 0x1000
- processor 0 has two load operations, P0 — 4 and P0 — 5, which, according to TSO, must wait for the two older store buffer entries, P0 — 2 and P0 — 3, to become GO before the load operations can execute.
- load P0 — 5 is not consistent with the result of load P0 — 4. If load P0 — 4 saw the value 0x01020304, then load P0 — 5 should have seen either that value or 0xFFFFFF. The result that load P0 — 5 actually saw, 0xFFFF0304 makes it appear as if store P0 — 3 occurred twice.
- Embodiments of the present invention therefore, provide a mechanism to forward data from multiple store buffer entries in such a way that the invention guarantees that those store buffer entries update system memory (that is, become globally observed) at a single point in time.
- the system and method can make use of a write combining buffer (WCB).
- a WCB is a structure that usually contains buffering for several cachelines of data and control logic that allows individual store operations to “combine” into a larger unit of data, which is generally equal in size to the size of the cachelines.
- This unit of data is written back to system memory or to a processor cache, it is done so atomically and with a single transaction. This improves processor performance by conserving bus transaction and cache bandwidth, because, without a WCB, each individual store operation would have to access the system bus or cache port separately. This would use system resources less efficiently than if a number of store operations could be pre-grouped into a single transaction.
- FIG. 1 is a flow diagram of a method for providing multiple store buffer forwarding, in accordance with an embodiment of the present invention.
- multiple store instructions can be executed 110 , generally, to combine data values from the multiple store instructions into a single value.
- this single value can be combined into an entry in a processor memory, such as an entry in a WCB, which can remain invisible to all other processors in the system until all of the multiple store instructions have completed executing.
- a load instruction can be executed 120 to load data from a memory coupled to the system.
- a check can be performed to determine whether a memory region addressed by the load instruction matches any cacheline addresses stored in the WCB 130 .
- a check can be performed to determine whether all of the memory region addressed by the load instruction, is covered by data that has been stored by the multiple store instructions 140 . If all of the memory region is covered by the data from the multiple store instructions, then, a store forward is “OK” signal can be generated 150 . At this point the load instruction can complete executing by reading the data from the WCB entry.
- the method is not needed and the method can end. If all of the memory region is not covered by data from the multiple store instructions, then, the method can return to execute 120 the load instruction again. In general, the previous load instruction execution 120 and all subsequent dependent instructions are flushed from the system before the load instruction can be executed again.
- new hardware can be added to the WCB to implement the functionality required to allow store forwarding from multiple store operations without violating the spirit and intent of the IA-32 TSO memory model.
- the two requirements that are necessary to achieve this functionality include:
- the system can achieve the first requirement by adding hardware to the WCB buffer that compares, on a byte-by-byte basis, the region of memory addressed by the load operation to the available store data in the WCB. If it is acceptable to forward the data, the data is read to satisfy the load operation.
- the data can be read from any memory containing the data, for example, the WCB, a store buffer, an other buffer, a register, a memory and a cache memory.
- FIG. 2 is a schematic block diagram of a write combining buffer configuration in which multiple store buffer forwarding can be implemented, in accordance with an embodiment of the present invention.
- a cacheline address comparison component 205 can be coupled to a WCB Address and Data Buffer 210 .
- the cacheline address comparison component 205 can be configured to receive an incoming load operation 202 and compare a cacheline address in the incoming load operation 202 with the cacheline addresses of existing entries in the WCB Address and Data Buffer 210 .
- the WCB Address and Data Buffer 210 can be coupled to a WCB data valid bit vector buffer 220 , which indicates the data bytes in the WCB Address and Data Buffer 210 that have been written by the store operations.
- the data entries in both the WCB Address and Data Buffer 210 and the WCB data valid bit vector buffer 220 are generally of equal size, for example, 64 data bytes per entry.
- the WCB data valid bit vectors buffer 220 can be connected to a Multiplexer 230 , which can be configured to receive a data valid bit vector from the WCB data valid bit vector buffer 220 and configured to receive load operation address bits from the incoming load operation 202 .
- the Multiplexer 230 can be a 4:1 multiplexer, which can be configured to select a group of 16 store byte valid bits in the data valid bit vector from an 8-bit boundary specified by the load operation address bits.
- the Multiplexer 230 can be coupled to a comparison circuit 240 , which can be configured to receive the group of 16 store byte valid bits on line 232 and an incoming load operation byte mask on line 235 and generate a “store forward OK” signal if the store instruction data completely covers the WCB entry referenced by the incoming load operation.
- the heavy lines in the comparison circuit 240 indicate a 16-bit data path.
- the comparison circuit 240 can include a 16-bit inverter logic 242 which can be coupled to a first 16-bit AND-OR logic 250 .
- the inverter 242 can be configured to receive the group of 16 store byte valid bits selected by the Multiplexer 230 on line 232 and output an inverted version of the group of 16 store byte valid bits onto line 244 .
- the 16-bit AND-OR logic can be implemented with 16 AND gates, which can be configured to receive one bit from either the group of 16 store byte valid bits on line 232 or an inverted bit from the group of 16 store byte valid bits on line 244 and one bit from the incoming load operation byte mask on line 235 .
- the first 16-bit AND-OR logic 250 can be configured to receive the inverted 16 store byte valid bits on line 244 and can be coupled to a NAND gate 270 and the first 16-bit AND-OR logic 250 can be configured to receive the incoming load operation byte mask on line 235 .
- a second AND-OR 16-bit logic 260 also can be coupled to the NAND gate 270 and the second 16-bit AND-OR logic 260 can be configured to receive the group of 16 store byte valid bits selected by the Multiplexer 230 on line 232 and the incoming load operation byte mask on line 235 .
- the NAND gate 270 is configured to receive a signal from each of the first and second 16-bit AND-OR logics 260 and 250 on lines 262 and 252 , respectively, and, generate the “store forward OK” signal if the store instruction data completely covers the WCB entry referenced by the incoming load operation.
- the present invention satisfies the second requirement by taking advantage of the fact that each WCB is sized to match the system coherence granularity (that is, the cacheline size). All individual store operations that combine into a singular WCB entry become globally observed at the same time. Embodiments of the present invention make use of this fact to enable multiple store buffer forwarding in a system with a restrictive memory model, thus, improving the performance of the system.
- Embodiments of the present invention can significantly improve the performance of code that has a high occurrence of instruction sequences in which a load operation is dependent on two or more temporally close store operations.
- Existing IA-32 processors, as well as other processors with restrictive memory models traditionally stall the execution of the load operation until the offending store operations leave the store buffer and become globally observed.
- In an embodiment of the present invention improves on this method by only stalling the load operation until the store operations are accepted into the WCB, which removes the restriction that the store operations must become globally observed (a process that can take many hundreds of cycles) before the load operation can be satisfied.
- FIG. 3 is a block diagram of a computer system 100 that is suitable for implementing the present invention.
- the computer system 100 includes one or more processors 310 ( 1 )- 310 ( n ) coupled to a processor bus 320 , which can be coupled to a system logic 330 .
- Each of the one or more processors 310 ( 1 )- 310 ( n ) are N-bit processors and can include one or more N-bit registers (not shown).
- the system logic 330 can be coupled to a system memory 340 through bus 350 and coupled to a non-volatile memory 370 and one or more peripheral devices 380 ( 1 )- 380 ( m ) through a peripheral bus 360 .
- the peripheral bus 360 represents, for example, one or more Peripheral Component Interconnect (PCI) buses, PCI Special Interest Group (SIG) PCI Local Bus Specification, Revision 2.2, published Dec. 18, 1998; industry standard architecture (ISA) buses; Extended ISA (EISA) buses, BCPR Services Inc. EISA Specification, Version 3.12, 1992, published 1992; universal serial bus (USB), USB Specification, Version 1.1, published Sep. 23, 1998; and comparable peripheral buses.
- PCI Peripheral Component Interconnect
- SIG PCI Special Interest Group
- EISA Extended ISA
- USB universal serial bus
- USB USB Specification, Version 1.1, published Sep. 23, 1998
- comparable peripheral buses Non-volatile memory 370 may be a static memory device such as a read only memory (ROM) or a flash memory.
- a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.
- a machine-readable medium having stored thereon multiple executable instructions for multiple store buffer forwarding in a system with a restrictive memory model
- the multiple instructions include instructions to: execute multiple store instructions, execute a load instruction, determine that a memory region addressed by the load instruction matches a cacheline address in a memory, determine that data stored by the multiple store instructions completely covers the memory location in the memory specified by the load instruction, and transmit a store forward is OK signal.
- a processor system includes a processor, a system memory coupled to the processor, and a non-volatile memory coupled to the processor in which is stored an article of manufacture including instructions adapted to be executed by the processor, the instructions which, when executed, encode instructions in an instruction set to enable multiple store buffer forwarding in a system with a restrictive memory model.
- the article of manufacture includes instructions to: execute multiple store instructions, execute a load instruction, determine that a memory region addressed by the load instruction matches a cacheline address in a memory, determine that data stored by the multiple store instructions completely covers the memory location in the memory specified by the load instruction, and transmit a store forward is OK signal.
Abstract
The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model. In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.
Description
- The present invention relates to store buffer forwarding in microprocessors, and more particularly, to multiple store buffer forwarding in a microprocessor system with a restrictive memory model.
- Many modern microprocessors implement store buffer forwarding which is a mechanism that improves microprocessor performance by completing a younger dependent load operation by using data from an older, completely overlapping store operation. This forwarding can occur while the store operation is speculative or has passed the point of speculation and is part of the committed machine state. In either case, the load operation's execution is delayed minimally when it can read its data directly from the buffer without waiting for that data to become globally observed (GO). For multiple store operations, prior processors, such as the Intel® Pentium® III, and the related instruction set architectures (ISAs) that run on these processors have stalled the execution of the load operation until the older multiple store operations become globally observed. The Intel® Pentium® III is manufactured by Intel Corporation of Santa Clara, Calif.
- Because store buffer forwarding has implications on the order in which all processes in a multi-threaded or multi-processor system observe store operations from the other processes, a processor architecture must carefully specify the rules under which store buffer forwarding may occur. For example, the Intel® Architecture 32-bit ISA (IA-32) product family has essentially implemented the Scalable Processor Architecture (SPARC®) total store order (TSO) memory model from SPARC International Inc.™ of Santa Clara, Calif.
- The TSO memory model has two restrictions related to store buffer forwarding:
- 1. A younger load operation may only receive forwarded data from a single older store buffer entry; and
- 2. The older store buffer entry must completely cover the region of memory being read by the younger load operation.
- Many existing IA-32 code sequences produce situations in which these two TSO restrictions considerably degrade the performance of the processor. When a typical IA-32 processor executes a load operation that encounters one of the conditions listed above, the processor stalls the load operation's execution until the offending condition clears. While waiting for the contents of the store buffer entry to become GO, the load operation and all instructions that are dependent on the load operation are stalled, thus reducing processor performance.
- FIG. 1 is a flow diagram of a method for providing multiple store buffer forwarding, in accordance with an embodiment of the present invention.
- FIG. 2 is a schematic block diagram of a write combining buffer configuration in which multiple store buffer forwarding can be implemented, in accordance with an embodiment of the present invention.
- FIG. 3 is a block diagram of a computer system in which multiple store buffer forwarding can be implemented, in accordance with an embodiment of the present invention.
- In accordance with an embodiment of the present invention, the system and method provide a novel mechanism to allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the two TSO restrictions thereby increasing processor performance without violating the restrictive memory model. For greater clarity, the problem can be described using some sample program executions.
- Archetypical Store Buffer Forwarding Example
- The following sample code segment demonstrates the type of store buffer forwarding that the TSO memory model specifically allows:
MOV EBX, 0x1000 ; set up the base address MOV [EBX], 0x00001234 ; store 4 bytes (0x00001234) to location 0x1000 . . . ; zero or more other instructions MOV EAX, [EBX] ; load 4 bytes from location 0x1000 - In this example, store buffer forwarding hardware is permitted to bypass the store data value (0x00001234) directly to the younger load operation even before other processors observe the store data value. Note that the above single store operation's data completely overlaps, that is, covers, the memory region that the load operation references. In other words, in this example, the same four bytes in the memory that are used by the store operation to store the data value are used by the load operation.
- Disallowed Store Buffer Forwarding Example
- This sample code segment demonstrates a type of store buffer forwarding that is not allowed in the IA-32 restrictive memory model (TSO):
MOV EBX, 0x1000 ; set up the base address MOV [EBX], 0x0000 ; store 2 bytes (0x0000) to location 0x1000 MOV [EBX] +2, 0x1234 ; store 2 bytes (0x1234) to location 0x1002 . . . ; zero or more other instructions MOV EAX, [EBX] ; load 4 bytes, from location 0x1000 - In this example, it would be desirable to forward store data from the two store operations to the single load operation, since each store operation provides half of the data required by the load operation. Unfortunately, this multiple store buffer forwarding is specifically disallowed in the TSO memory model, and, therefore, the load operation must wait to complete until the two store operations become globally observed (GO). Multiple store buffer forwarding is disallowed by the TSO memory model to ensure a reliable and consistent order in which store operations can become globally observed by other processors in the system.
- The problem that store forwarding from multiple store buffer entries can cause is illustrated with the following code sequences, which are executed on two separate processors in a multi-processor system:
Processor 0: P0_1) MOV EBX, 0x1000 ; set up the base address P0_2) MOV [EBX], 0x0102 ; store 2 bytes (0x0102) to 0x1000 P0_3) MOV [EBX] +2, 0x0304 ; store 2 bytes (0x0304) to 0x1002 P0_4) MOV EAX, [EBX] ; load 4 bytes from location 0x10000 P0_5) MOV EAX, [EBX] ; load 4 bytes from location 0x10000 Processor 1: P1_1) MOV EBX, 0x1000 ; set up the base address P1_2) MOV [EBX], 0xFFFFFFFF ; store 4 bytes (0xFFFFFFFF) to 0x1000 -
Sample Execution 1 - In this example, processor 0 has two load operations, P0—4 and P0—5, which, according to TSO, must wait for the two older store buffer entries, P0—2 and P0—3, to become GO before the load operations can execute. In a system that implements TSO with this restriction, the following total order, that is, the order in which operations from both processors occur in time, would be possible:
Store Buffer Contents Memory Event (if a store) Result (if a load) Contents Initial conditions at memory location 0 × 1000 00 00 00 00 P0_2 01 02 xx xx 00 00 00 00 P0_2 becomes GO 01 02 00 00 P0_3 xx xx 03 04 01 02 00 00 P0_3 becomes GO 01 02 03 04 P0_4 01 02 03 04 (from 01 02 03 04 memory) P1_2 FF FF FF FF 01 02 03 04 P1_2 becomes GO FF FF FF FF P0_5 FF FF FF FF (from FF FF FF FF memory) - The results of this sample execution are consistent with the TSO memory model in that neither loads P0—4 or P0—5 receive data directly from processor 0's store buffer.
- Sample Execution 2
- The following sample execution represents another possible total order in a system that allows store buffer forwarding from multiple store buffer entries, but does not implement the present invention.
Store Buffer Contents Event (if a store) Result (if a load) Memory Contents Initial conditions at memory location 0 × 1000 00 00 00 00 P0_2 01 02 xx xx 00 00 00 00 P0_3 xx xx 03 04 00 00 00 00 P0_4 01 02 03 04 (from 00 00 00 00 store buffer) P0_2 becomes 01 02 00 00 GO P1_2 FF FF FF FF 01 02 00 00 P1_2 becomes GO FF FF FF FF P1_3 becomes GO FF FF 03 04 P0_5 FF FF 03 04 FF FF 03 04 (from memory) - Note that the result of load operation P0—5 is not consistent with the result of load P0—4. If load P0—4 saw the value 0x01020304, then load P0—5 should have seen either that value or 0xFFFFFFFF. The result that load P0—5 actually saw, 0xFFFF0304 makes it appear as if store P0—3 occurred twice.
- Sample Execution 3
- Had stores P0—2 and P0—3 become globally observed at the same point in time (that is, atomically), the situation demonstrated in Sample Execution 2 would not have occurred. In accordance with an embodiment of the present invention, the following sample execution represents a possible total order in a system that implements the present invention.
Store Buffer Contents Event (if a store) Result (if a load) Memory Contents Initial conditions at memory location 0 × 1000 00 00 00 00 P0_2 01 02 xx xx 00 00 00 00 (store is not GO) P0_3 xx xx 03 04 00 00 00 00 (store is not GO) P0_4 01 02 03 04 (from 00 00 00 00 store buffer) P1_2 FF FF FF FF 00 00 00 00 P0_2 P0_3 become 01 02 03 04 GO atomically P1_2 becomes GO FF FF FF FF P0_5 FF FF FF FF FF FF FF FF (from memory) - As shown above, load operation P0—5 now sees a result consistent with the TSO memory model. Embodiments of the present invention, therefore, provide a mechanism to forward data from multiple store buffer entries in such a way that the invention guarantees that those store buffer entries update system memory (that is, become globally observed) at a single point in time.
- In accordance with an embodiment of the present invention, the system and method can make use of a write combining buffer (WCB). A WCB is a structure that usually contains buffering for several cachelines of data and control logic that allows individual store operations to “combine” into a larger unit of data, which is generally equal in size to the size of the cachelines. When this unit of data is written back to system memory or to a processor cache, it is done so atomically and with a single transaction. This improves processor performance by conserving bus transaction and cache bandwidth, because, without a WCB, each individual store operation would have to access the system bus or cache port separately. This would use system resources less efficiently than if a number of store operations could be pre-grouped into a single transaction.
- FIG. 1 is a flow diagram of a method for providing multiple store buffer forwarding, in accordance with an embodiment of the present invention. In FIG. 1, multiple store instructions can be executed110, generally, to combine data values from the multiple store instructions into a single value. In accordance with an embodiment of the present invention, this single value can be combined into an entry in a processor memory, such as an entry in a WCB, which can remain invisible to all other processors in the system until all of the multiple store instructions have completed executing. A load instruction can be executed 120 to load data from a memory coupled to the system. A check can be performed to determine whether a memory region addressed by the load instruction matches any cacheline addresses stored in the WCB 130. If a match is found, then, a check can be performed to determine whether all of the memory region addressed by the load instruction, is covered by data that has been stored by the
multiple store instructions 140. If all of the memory region is covered by the data from the multiple store instructions, then, a store forward is “OK” signal can be generated 150. At this point the load instruction can complete executing by reading the data from the WCB entry. - If a match is not found, then, the method is not needed and the method can end. If all of the memory region is not covered by data from the multiple store instructions, then, the method can return to execute120 the load instruction again. In general, the previous
load instruction execution 120 and all subsequent dependent instructions are flushed from the system before the load instruction can be executed again. - In accordance with an embodiment of the present invention, new hardware can be added to the WCB to implement the functionality required to allow store forwarding from multiple store operations without violating the spirit and intent of the IA-32 TSO memory model. In general, the two requirements that are necessary to achieve this functionality include:
- 1. The store operation(s) must completely cover the memory region addressed by the younger load operation; and
- 2. The store operation(s) that forward data to the load operation must become globally observed at the same time (that is, atomically).
- In accordance with an embodiment of the present invention, the system can achieve the first requirement by adding hardware to the WCB buffer that compares, on a byte-by-byte basis, the region of memory addressed by the load operation to the available store data in the WCB. If it is acceptable to forward the data, the data is read to satisfy the load operation. In accordance with other embodiments of the present invention, the data can be read from any memory containing the data, for example, the WCB, a store buffer, an other buffer, a register, a memory and a cache memory. FIG. 2 is a schematic block diagram of a write combining buffer configuration in which multiple store buffer forwarding can be implemented, in accordance with an embodiment of the present invention.
- In FIG. 2, a cacheline
address comparison component 205 can be coupled to a WCB Address andData Buffer 210. The cachelineaddress comparison component 205 can be configured to receive anincoming load operation 202 and compare a cacheline address in theincoming load operation 202 with the cacheline addresses of existing entries in the WCB Address andData Buffer 210. The WCB Address andData Buffer 210 can be coupled to a WCB data validbit vector buffer 220, which indicates the data bytes in the WCB Address andData Buffer 210 that have been written by the store operations. In an embodiment of the present invention, the data entries in both the WCB Address andData Buffer 210 and the WCB data validbit vector buffer 220 are generally of equal size, for example, 64 data bytes per entry. The WCB data valid bit vectors buffer 220 can be connected to aMultiplexer 230, which can be configured to receive a data valid bit vector from the WCB data validbit vector buffer 220 and configured to receive load operation address bits from theincoming load operation 202. For example, theMultiplexer 230 can be a 4:1 multiplexer, which can be configured to select a group of 16 store byte valid bits in the data valid bit vector from an 8-bit boundary specified by the load operation address bits. TheMultiplexer 230 can be coupled to acomparison circuit 240, which can be configured to receive the group of 16 store byte valid bits online 232 and an incoming load operation byte mask online 235 and generate a “store forward OK” signal if the store instruction data completely covers the WCB entry referenced by the incoming load operation. The heavy lines in thecomparison circuit 240 indicate a 16-bit data path. Thecomparison circuit 240 can include a 16-bit inverter logic 242 which can be coupled to a first 16-bit AND-ORlogic 250. Theinverter 242 can be configured to receive the group of 16 store byte valid bits selected by theMultiplexer 230 online 232 and output an inverted version of the group of 16 store byte valid bits ontoline 244. The 16-bit AND-OR logic can be implemented with 16 AND gates, which can be configured to receive one bit from either the group of 16 store byte valid bits online 232 or an inverted bit from the group of 16 store byte valid bits online 244 and one bit from the incoming load operation byte mask online 235. The first 16-bit AND-ORlogic 250 can be configured to receive the inverted 16 store byte valid bits online 244 and can be coupled to aNAND gate 270 and the first 16-bit AND-ORlogic 250 can be configured to receive the incoming load operation byte mask online 235. A second AND-OR 16-bit logic 260 also can be coupled to theNAND gate 270 and the second 16-bit AND-ORlogic 260 can be configured to receive the group of 16 store byte valid bits selected by theMultiplexer 230 online 232 and the incoming load operation byte mask online 235. TheNAND gate 270 is configured to receive a signal from each of the first and second 16-bit AND-ORlogics lines - The present invention satisfies the second requirement by taking advantage of the fact that each WCB is sized to match the system coherence granularity (that is, the cacheline size). All individual store operations that combine into a singular WCB entry become globally observed at the same time. Embodiments of the present invention make use of this fact to enable multiple store buffer forwarding in a system with a restrictive memory model, thus, improving the performance of the system.
- Embodiments of the present invention can significantly improve the performance of code that has a high occurrence of instruction sequences in which a load operation is dependent on two or more temporally close store operations. Existing IA-32 processors, as well as other processors with restrictive memory models, traditionally stall the execution of the load operation until the offending store operations leave the store buffer and become globally observed. In an embodiment of the present invention improves on this method by only stalling the load operation until the store operations are accepted into the WCB, which removes the restriction that the store operations must become globally observed (a process that can take many hundreds of cycles) before the load operation can be satisfied.
- This is not just a theoretical performance improvement since many compilers produce situations in which the present invention is likely to be beneficial. For example, compilers can usually provide an optimization to remove as many instances of stalling the load operations as possible. Unfortunately, these optimizations usually result in a larger memory footprint for the program, as well as slower execution times, which result in the compiler optimizations not always being used. Therefore, using embodiments of the present invention, can result in faster, more efficient and compact programs.
- One apparently common situation in which the compiler cannot optimize the problem away is in multimedia code which regularly generates code sequences having two 32-bit store operations that are immediately followed by one completely overlapping 64-bit load operation. This sequence is used to move data from the integer register file to the MMX (floating point) register file. This invention has the potential to greatly improve the user's “Internet experience” and to enhance other multimedia applications as well.
- FIG. 3 is a block diagram of a computer system100 that is suitable for implementing the present invention. In FIG. 3, the computer system 100 includes one or more processors 310(1)-310(n) coupled to a
processor bus 320, which can be coupled to asystem logic 330. Each of the one or more processors 310(1)-310(n) are N-bit processors and can include one or more N-bit registers (not shown). Thesystem logic 330 can be coupled to asystem memory 340 throughbus 350 and coupled to anon-volatile memory 370 and one or more peripheral devices 380(1)-380(m) through aperipheral bus 360. Theperipheral bus 360 represents, for example, one or more Peripheral Component Interconnect (PCI) buses, PCI Special Interest Group (SIG) PCI Local Bus Specification, Revision 2.2, published Dec. 18, 1998; industry standard architecture (ISA) buses; Extended ISA (EISA) buses, BCPR Services Inc. EISA Specification, Version 3.12, 1992, published 1992; universal serial bus (USB), USB Specification, Version 1.1, published Sep. 23, 1998; and comparable peripheral buses.Non-volatile memory 370 may be a static memory device such as a read only memory (ROM) or a flash memory. Peripheral devices 380(1)-380(m) include, for example, a keyboard; a mouse or other pointing devices; mass storage devices such as hard disk drives, compact disc (CD) drives, optical disks, and digital video disc (DVD) drives; displays and the like. - In accordance with an embodiment the present invention, a method for multiple store buffer forwarding in a system with a restrictive memory model includes executing multiple store instructions, executing a load instruction, determining that a memory region addressed by the load instruction matches a cacheline address in a memory, determining that data stored by the multiple store instructions completely covers the memory region addressed by the load instruction, and transmitting a store forward is OK signal.
- In accordance with an embodiment the present invention, a machine-readable medium having stored thereon multiple executable instructions for multiple store buffer forwarding in a system with a restrictive memory model, the multiple instructions include instructions to: execute multiple store instructions, execute a load instruction, determine that a memory region addressed by the load instruction matches a cacheline address in a memory, determine that data stored by the multiple store instructions completely covers the memory location in the memory specified by the load instruction, and transmit a store forward is OK signal.
- In accordance with an embodiment the present invention, a processor system includes a processor, a system memory coupled to the processor, and a non-volatile memory coupled to the processor in which is stored an article of manufacture including instructions adapted to be executed by the processor, the instructions which, when executed, encode instructions in an instruction set to enable multiple store buffer forwarding in a system with a restrictive memory model. The article of manufacture includes instructions to: execute multiple store instructions, execute a load instruction, determine that a memory region addressed by the load instruction matches a cacheline address in a memory, determine that data stored by the multiple store instructions completely covers the memory location in the memory specified by the load instruction, and transmit a store forward is OK signal.
- It should, of course, be understood that while the present invention has been described mainly in terms of microprocessor- and multi-processor-based personal computer systems, those skilled in the art will recognize that the principles of the invention may be used advantageously with alternative embodiments involving other integrated processor chips and computer systems. Accordingly, all such implementations which fall within the spirit and scope of the appended claims will be embraced by the principles of the present invention.
Claims (30)
1. A method for multiple store buffer forwarding in a system with a restrictive memory model, the method comprising:
executing a plurality of store instructions;
executing a load instruction;
determining that a memory region addressed by the load instruction matches a cacheline address in a memory;
determining that data stored by the plurality of store instructions completely covers the memory region addressed by the load instruction; and
transmitting a store forward is OK signal.
2. The method of claim 1 , wherein executing the plurality of store instructions comprises:
performing a plurality of store operations to store a plurality of data values in contiguous memory locations in the memory, wherein the size of the contiguous memory locations equals the size of the memory region addressed by the load instruction.
3. The method of claim 2 , wherein executing a load instruction comprises: loading the data from the contiguous memory locations in the memory; and generating the store forward is OK signal.
4. The method of claim 3 , wherein loading the data from the contiguous memory locations in the memory begins after performing the plurality of store operations begins, and loading the data from the contiguous memory locations in the memory completes before the plurality of store operations become globally observed in the system.
5. The method of claim 1 , wherein executing the load instruction comprises:
loading the data from a write combining buffer; and
generating the store forward is OK signal.
6. The method of claim 1 , wherein determining that a memory region addressed by the load instruction matches a cacheline address in a memory comprises:
comparing an address of the memory region and the cacheline address; and
determining that the address of the memory region is the same address as the cacheline address.
7. The method of claim 1 , wherein determining that the data stored by the plurality of store instructions completely covers the memory region addressed by the load instruction comprises:
determining that a size of the data stored by the plurality of store instructions equals a size of the memory region addressed by the load instruction.
8. The method of claim 1 , further comprising:
terminating, if an address of the memory region and the cacheline address in the memory are different.
9. The method of claim 1 , further comprising:
re-executing the load instruction, if the memory region is incompletely covered by the data stored by the plurality of store instructions.
10. The method of claim 1 , wherein intermediate results from the plurality of store instructions are invisible to other concurrent processes.
11. The method of claim 1 , wherein the method operates within the restrictive memory model.
12. A machine-readable medium having stored thereon a plurality of executable instructions for multiple store buffer forwarding in a system with a restrictive memory model, the plurality of instructions comprising instructions to:
execute a plurality of store instructions;
execute a load instruction;
determine that a memory region addressed by the load instruction matches a cacheline address in a memory;
determine that data stored by the plurality of store instructions completely covers the memory location in the memory specified by the load instruction; and
transmit a store forward is OK signal.
13. The machine-readable medium of claim 12 , wherein the execute the plurality of store instructions instruction comprises an instruction to:
perform a plurality of store operations to store a plurality of data values in contiguous memory locations in the memory, wherein the size of the contiguous memory locations equals the size of a the memory region addressed the load instruction.
14. The machine-readable medium of claim 13 , wherein the execute a load instruction instruction comprises instructions to:
load the data from the contiguous memory locations in the memory; and
generate the store forward is OK signal.
15. The machine-readable medium of claim 14 , wherein the load data from the contiguous memory locations in the memory instruction begins executing after the perform the plurality of store operations instruction begins executing, and the load data from the contiguous memory locations in the memory instruction completes executing before the plurality of store operations become globally observed in the system.
16. The machine-readable medium of claim 12 , wherein the execute the load instruction comprises instructions to:
load the data from a write combining buffer; and
generate the store forward is OK signal.
17. The machine-readable medium of claim 12 , wherein the determine that a memory region addressed by the load instruction matches a cacheline address in a memory instruction comprises instructions to:
compare the address of the memory region and the cacheline address; and
determine that the address of the memory region is the same address as the cacheline address.
18. The machine-readable medium of claim 12 , wherein the determine that data stored by the plurality of store instructions completely covers the memory location in the memory specified by the load instruction instruction comprises an instruction to:
determine that a size of the data stored by the plurality of store instructions equals a size of the memory region addressed by the load instruction.
19. The machine-readable medium of claim 12 , further comprising an instruction to:
terminate, if an address of the memory region and the cacheline address in the memory are different.
20. The machine-readable medium of claim 12 , further comprising an instruction to:
re-execute the load instruction, if the memory region is incompletely covered by the data stored by the plurality of store instructions.
21. The machine-readable medium of claim 12 , wherein the execute the plurality of store instructions instruction comprises an instruction to:
execute the plurality of store instructions to produce intermediate results that are invisible to other concurrent processes.
22. The machine-readable medium of claim 12 , wherein the plurality of executable instructions operate within the restrictive memory model.
23. A processor system, comprising:
a processor;
a system memory coupled to the processor; and
a non-volatile memory coupled to the processor in which is stored an article of manufacture including instructions adapted to be executed by the processor, the instructions which, when executed, encode instructions in an instruction set to enable multiple store buffer forwarding in a system with a restrictive memory model, the article of manufacture comprising instructions to:
execute a plurality of store instructions;
execute a load instruction;
determine that a memory region addressed by the load instruction matches a cacheline address in a memory;
determine that data stored by the plurality of store instructions completely covers the memory location in the memory specified by the load instruction; and
transmit a store forward is OK signal.
24. The processor system of claim 23 , the processor comprising:
a write combining buffer, the write combining buffer including:
a comparator, the comparator being configured to receive and compare an incoming load operation target address with all cacheline addresses of existing write combining buffer entries;
an address and data buffer coupled to the comparator;
a data valid bits buffer coupled to the address and data buffer;
a multiplexer coupled to the data valid bits buffer; and
a comparison circuit coupled to the multiplexer.
25. The processor system of claim 24 , the multiplexer being configured to:
receive a byte valid vector from the data valid bits buffer;
receive address bits from the load operation and output valid bits;
select a group of valid bits from the byte valid vector; and
output the group of valid bits.
26. The processor system of claim 24 , the comparison circuit being configured to:
receive the group of valid bits;
receive an incoming load operation byte mask;
determine that it is acceptable to forward the data using the group of valid bits and the incoming load operation byte mask; and
produce a forward OK signal.
27. The article of manufacture of claim 23 , wherein the execute the plurality of store instructions instruction comprises an instruction to:
perform a plurality of store operations to store a plurality of data values in contiguous memory locations in the memory, wherein the size of the contiguous memory locations equals the size of a the memory region addressed the load instruction.
28. The machine-readable medium of claim 27 , wherein the execute a load instruction instruction comprises instructions to:
load the data from the contiguous memory locations in the memory; and
generate the store forward is OK signal.
29. The machine-readable medium of claim 28 , wherein the load data from the contiguous memory locations in the memory instruction begins executing after the perform the plurality of store operations instruction begins executing, and the load data from the contiguous memory locations in the memory instruction completes executing before the plurality of store operations become globally observed in the system.
30. The processor system of claim 23 , wherein said processor is implemented as a multi-processor having associated with each said multi-processor a separate set of hardware resources.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/620,555 US20040019753A1 (en) | 2000-12-21 | 2003-07-17 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/740,803 US6678807B2 (en) | 2000-12-21 | 2000-12-21 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US10/620,555 US20040019753A1 (en) | 2000-12-21 | 2003-07-17 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/740,803 Continuation US6678807B2 (en) | 2000-12-21 | 2000-12-21 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040019753A1 true US20040019753A1 (en) | 2004-01-29 |
Family
ID=24978145
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/740,803 Expired - Lifetime US6678807B2 (en) | 2000-12-21 | 2000-12-21 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US10/620,555 Abandoned US20040019753A1 (en) | 2000-12-21 | 2003-07-17 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/740,803 Expired - Lifetime US6678807B2 (en) | 2000-12-21 | 2000-12-21 | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
Country Status (7)
Country | Link |
---|---|
US (2) | US6678807B2 (en) |
KR (1) | KR100577827B1 (en) |
CN (2) | CN100530080C (en) |
AU (1) | AU2002231202A1 (en) |
HK (1) | HK1067742A1 (en) |
TW (1) | TW563021B (en) |
WO (1) | WO2002050668A2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050160326A1 (en) * | 2003-12-31 | 2005-07-21 | Boatright Bryan D. | Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM) |
US20080209183A1 (en) * | 2007-02-27 | 2008-08-28 | International Business Machines Corporation | Fast sparse list walker |
US20100042816A1 (en) * | 2008-08-15 | 2010-02-18 | Apple Inc. | Break, pre-break, and remaining instructions for processing vectors |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6678807B2 (en) * | 2000-12-21 | 2004-01-13 | Intel Corporation | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US6880154B2 (en) * | 2001-06-29 | 2005-04-12 | Intel Corporation | Alias-free test for dynamic array structures |
US6938127B2 (en) * | 2001-09-25 | 2005-08-30 | Intel Corporation | Reconfiguring memory to reduce boot time |
US7814488B1 (en) * | 2002-09-24 | 2010-10-12 | Oracle America, Inc. | Quickly reacquirable locks |
US7957428B2 (en) | 2004-05-21 | 2011-06-07 | Intel Corporation | Methods and apparatuses to effect a variable-width link |
US7376817B2 (en) | 2005-08-10 | 2008-05-20 | P.A. Semi, Inc. | Partial load/store forward prediction |
US7461238B2 (en) | 2006-06-07 | 2008-12-02 | International Business Machines Corporation | Simple load and store disambiguation and scheduling at predecode |
US20070288725A1 (en) * | 2006-06-07 | 2007-12-13 | Luick David A | A Fast and Inexpensive Store-Load Conflict Scheduling and Forwarding Mechanism |
US7721066B2 (en) * | 2007-06-05 | 2010-05-18 | Apple Inc. | Efficient encoding for detecting load dependency on store with misalignment |
US8627047B2 (en) * | 2008-02-15 | 2014-01-07 | International Business Machines Corporation | Store data forwarding with no memory model restrictions |
US20100049952A1 (en) * | 2008-08-25 | 2010-02-25 | Via Technologies, Inc. | Microprocessor that performs store forwarding based on comparison of hashed address bits |
US20100250850A1 (en) * | 2009-03-25 | 2010-09-30 | Faraday Technology Corp. | Processor and method for executing load operation and store operation thereof |
US9128725B2 (en) | 2012-05-04 | 2015-09-08 | Apple Inc. | Load-store dependency predictor content management |
US9600289B2 (en) | 2012-05-30 | 2017-03-21 | Apple Inc. | Load-store dependency predictor PC hashing |
US9361103B2 (en) * | 2012-11-02 | 2016-06-07 | Advanced Micro Devices, Inc. | Store replay policy |
US9244684B2 (en) | 2013-03-15 | 2016-01-26 | Intel Corporation | Limited range vector memory access instructions, processors, methods, and systems |
US9710268B2 (en) | 2014-04-29 | 2017-07-18 | Apple Inc. | Reducing latency for pointer chasing loads |
US10514925B1 (en) | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
US10437595B1 (en) | 2016-03-15 | 2019-10-08 | Apple Inc. | Load/store dependency predictor optimization for replayed loads |
CN106557437A (en) * | 2016-11-22 | 2017-04-05 | 上海联影医疗科技有限公司 | A kind of high speed storing method and system of raw data |
US20200401412A1 (en) * | 2019-06-24 | 2020-12-24 | Intel Corporation | Hardware support for dual-memory atomic operations |
US20220358209A1 (en) * | 2021-05-07 | 2022-11-10 | Ventana Micro Systems Inc. | Thwarting Store-to-Load Forwarding Side Channel Attacks by Pre-Forwarding Matching of Physical Address Proxies and/or Permission Checking |
US11841802B2 (en) | 2021-05-07 | 2023-12-12 | Ventana Micro Systems Inc. | Microprocessor that prevents same address load-load ordering violations |
US11836080B2 (en) | 2021-05-07 | 2023-12-05 | Ventana Micro Systems Inc. | Physical address proxy (PAP) residency determination for reduction of PAP reuse |
US11868263B2 (en) | 2021-05-07 | 2024-01-09 | Ventana Micro Systems Inc. | Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache |
US11481332B1 (en) | 2021-05-07 | 2022-10-25 | Ventana Micro Systems Inc. | Write combining using physical address proxies stored in a write combine buffer |
US11860794B2 (en) | 2021-05-07 | 2024-01-02 | Ventana Micro Systems Inc. | Generational physical address proxies |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5606670A (en) * | 1993-12-30 | 1997-02-25 | Intel Corporation | Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system |
US5671444A (en) * | 1994-02-28 | 1997-09-23 | Intel Corporaiton | Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers |
US5854914A (en) * | 1996-02-13 | 1998-12-29 | Intel Corporation | Mechanism to improved execution of misaligned loads |
US5878245A (en) * | 1993-10-29 | 1999-03-02 | Advanced Micro Devices, Inc. | High performance load/store functional unit and data cache |
US6141747A (en) * | 1998-09-22 | 2000-10-31 | Advanced Micro Devices, Inc. | System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word |
US6266744B1 (en) * | 1999-05-18 | 2001-07-24 | Advanced Micro Devices, Inc. | Store to load forwarding using a dependency link file |
US6272595B1 (en) * | 1994-08-05 | 2001-08-07 | Intel Corporation | N-way set-associative cache memory which includes a store hit buffer for improved data access |
US6334171B1 (en) * | 1999-04-15 | 2001-12-25 | Intel Corporation | Write-combining device for uncacheable stores |
US6338128B1 (en) * | 1999-05-20 | 2002-01-08 | International Business Machines Corp. | System and method for invalidating an entry in a translation unit |
US6473832B1 (en) * | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Load/store unit having pre-cache and post-cache queues for low latency load memory operations |
US6678807B2 (en) * | 2000-12-21 | 2004-01-13 | Intel Corporation | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US6922745B2 (en) * | 2002-05-02 | 2005-07-26 | Intel Corporation | Method and apparatus for handling locks |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58133696A (en) * | 1982-02-03 | 1983-08-09 | Hitachi Ltd | Storage control system |
US5265233A (en) * | 1991-05-17 | 1993-11-23 | Sun Microsystems, Inc. | Method and apparatus for providing total and partial store ordering for a memory in multi-processor system |
US6021485A (en) * | 1997-04-10 | 2000-02-01 | International Business Machines Corporation | Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching |
-
2000
- 2000-12-21 US US09/740,803 patent/US6678807B2/en not_active Expired - Lifetime
-
2001
- 2001-12-17 TW TW090131219A patent/TW563021B/en not_active IP Right Cessation
- 2001-12-18 CN CNB2005100965833A patent/CN100530080C/en not_active Expired - Fee Related
- 2001-12-18 KR KR1020037007695A patent/KR100577827B1/en not_active IP Right Cessation
- 2001-12-18 CN CNB018209548A patent/CN1307537C/en not_active Expired - Fee Related
- 2001-12-18 WO PCT/US2001/049759 patent/WO2002050668A2/en active IP Right Grant
- 2001-12-18 AU AU2002231202A patent/AU2002231202A1/en not_active Abandoned
-
2003
- 2003-07-17 US US10/620,555 patent/US20040019753A1/en not_active Abandoned
-
2005
- 2005-01-03 HK HK05100004A patent/HK1067742A1/en not_active IP Right Cessation
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6298423B1 (en) * | 1993-10-29 | 2001-10-02 | Advanced Micro Devices, Inc. | High performance load/store functional unit and data cache |
US5878245A (en) * | 1993-10-29 | 1999-03-02 | Advanced Micro Devices, Inc. | High performance load/store functional unit and data cache |
US5606670A (en) * | 1993-12-30 | 1997-02-25 | Intel Corporation | Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system |
US5671444A (en) * | 1994-02-28 | 1997-09-23 | Intel Corporaiton | Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers |
US6272595B1 (en) * | 1994-08-05 | 2001-08-07 | Intel Corporation | N-way set-associative cache memory which includes a store hit buffer for improved data access |
US5854914A (en) * | 1996-02-13 | 1998-12-29 | Intel Corporation | Mechanism to improved execution of misaligned loads |
US6141747A (en) * | 1998-09-22 | 2000-10-31 | Advanced Micro Devices, Inc. | System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word |
US6334171B1 (en) * | 1999-04-15 | 2001-12-25 | Intel Corporation | Write-combining device for uncacheable stores |
US6266744B1 (en) * | 1999-05-18 | 2001-07-24 | Advanced Micro Devices, Inc. | Store to load forwarding using a dependency link file |
US6473832B1 (en) * | 1999-05-18 | 2002-10-29 | Advanced Micro Devices, Inc. | Load/store unit having pre-cache and post-cache queues for low latency load memory operations |
US6338128B1 (en) * | 1999-05-20 | 2002-01-08 | International Business Machines Corp. | System and method for invalidating an entry in a translation unit |
US6678807B2 (en) * | 2000-12-21 | 2004-01-13 | Intel Corporation | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US6922745B2 (en) * | 2002-05-02 | 2005-07-26 | Intel Corporation | Method and apparatus for handling locks |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050160326A1 (en) * | 2003-12-31 | 2005-07-21 | Boatright Bryan D. | Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM) |
US7197670B2 (en) | 2003-12-31 | 2007-03-27 | Intel Corporation | Methods and apparatuses for reducing infant mortality in semiconductor devices utilizing static random access memory (SRAM) |
US20080209183A1 (en) * | 2007-02-27 | 2008-08-28 | International Business Machines Corporation | Fast sparse list walker |
US7743231B2 (en) * | 2007-02-27 | 2010-06-22 | International Business Machines Corporation | Fast sparse list walker |
US20100042816A1 (en) * | 2008-08-15 | 2010-02-18 | Apple Inc. | Break, pre-break, and remaining instructions for processing vectors |
US8356159B2 (en) * | 2008-08-15 | 2013-01-15 | Apple Inc. | Break, pre-break, and remaining instructions for processing vectors |
Also Published As
Publication number | Publication date |
---|---|
CN1511280A (en) | 2004-07-07 |
CN1307537C (en) | 2007-03-28 |
KR100577827B1 (en) | 2006-05-12 |
WO2002050668A3 (en) | 2002-10-31 |
HK1067742A1 (en) | 2005-04-15 |
AU2002231202A1 (en) | 2002-07-01 |
WO2002050668A2 (en) | 2002-06-27 |
TW563021B (en) | 2003-11-21 |
US20020120813A1 (en) | 2002-08-29 |
US6678807B2 (en) | 2004-01-13 |
KR20030064807A (en) | 2003-08-02 |
CN100530080C (en) | 2009-08-19 |
CN1728088A (en) | 2006-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6678807B2 (en) | System and method for multiple store buffer forwarding in a system with a restrictive memory model | |
US5826089A (en) | Instruction translation unit configured to translate from a first instruction set to a second instruction set | |
US5822602A (en) | Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity | |
US6728866B1 (en) | Partitioned issue queue and allocation strategy | |
US7299343B2 (en) | System and method for cooperative execution of multiple branching instructions in a processor | |
US6289445B2 (en) | Circuit and method for initiating exception routines using implicit exception checking | |
JP3151444B2 (en) | Method for processing load instructions and superscalar processor | |
US5778248A (en) | Fast microprocessor stage bypass logic enable | |
US20050076189A1 (en) | Method and apparatus for pipeline processing a chain of processing instructions | |
US20040064684A1 (en) | System and method for selectively updating pointers used in conditionally executed load/store with update instructions | |
US5832258A (en) | Digital signal processor and associated method for conditional data operation with no condition code update | |
US20220113966A1 (en) | Variable latency instructions | |
US5416913A (en) | Method and apparatus for dependency checking in a multi-pipelined microprocessor | |
US20240036876A1 (en) | Pipeline protection for cpus with save and restore of intermediate results | |
JP3207124B2 (en) | Method and apparatus for supporting speculative execution of a count / link register change instruction | |
US11029997B2 (en) | Entering protected pipeline mode without annulling pending instructions | |
US5802340A (en) | Method and system of executing speculative store instructions in a parallel processing computer system | |
JP3182741B2 (en) | Distributed instruction completion method and processor | |
US11048513B2 (en) | Entering protected pipeline mode with clearing | |
JPH10143366A (en) | Method and system to implement analyzing mechanism depending on early data in high performance data processing system utilizing command issuance which is not in program order | |
US20070028077A1 (en) | Pipeline processor, and method for automatically designing a pipeline processor | |
US8583897B2 (en) | Register file with circuitry for setting register entries to a predetermined value | |
JP3519047B2 (en) | Register bit update processing method, processor and data processing system | |
US6591360B1 (en) | Local stall/hazard detect in superscalar, pipelined microprocessor | |
US20060179286A1 (en) | System and method for processing limited out-of-order execution of floating point loads |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |