US20030205197A1 - Apparatus and process for precise encapsulation of flip chip interconnects - Google Patents
Apparatus and process for precise encapsulation of flip chip interconnects Download PDFInfo
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- US20030205197A1 US20030205197A1 US10/456,434 US45643403A US2003205197A1 US 20030205197 A1 US20030205197 A1 US 20030205197A1 US 45643403 A US45643403 A US 45643403A US 2003205197 A1 US2003205197 A1 US 2003205197A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A method for encapsulating flip chip interconnects includes applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip, and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate. In some embodiments, the step of applying resin to the chip includes dipping the interconnect side of the chip to a predetermined depth in a pool of resin, and then withdrawing the chip from the resin pool. In some embodiments the step of applying resin to the chip includes providing a reservoir having a bottom, providing a pool of resin in the reservoir to a shallow depth over the reservoir bottom, dipping the chip into the resin pool so that the bumps contact the reservoir bottom, and then withdrawing the chip from the resin pool. Also, apparatus for applying a precise volume of encapsulating resin to a chip, includes a reservoir having a bottom, and means for dispensing a pool of encapsulating resin to a predetermined depth over the reservoir bottom.
Description
- This application is a divisional of application Ser. No. 10/081,425 filed Feb. 22, 2002, which claims priority from Provisional Application No. 60/272,280, filed Feb. 27, 2001.
- This invention relates to semiconductor device packaging and, particularly, to flip chip packages.
- Flip chip packages include an integrated circuit chip connected to a package substrate by way of interconnect bumps which are mounted on the integrated circuit chip in arrangement corresponding to the arrangement to metal contact pads on substrate. During package assembly the chip and substrate are apposed with the corresponding bumps and pads aligned, and then the chip and substrate are brought together under conditions that promote the bonding of the bumps on the metal pads.
- Flip chip devices are conventionally encapsulated to improve the reliability of the interconnections between the chip and the substrate. Ordinarily the encapsulation is carried out using one of two approaches.
- In the first approach, commonly known as “under filling”, encapsulation is carried out following formation of the interconnections between the chip and substrate, by dispensing the encapsulating resin into the gap between the chip in the substrate near an outer edge of the chip, and then allowing the resin to move into the gap between the chip and the substrate by capillary action. This approach carries a high processing cost, because the under filling process is time-consuming and high throughput cannot be achieved. Moreover, a significant space must be provided between adjacent devices to accommodate the dispensed resin bead at the edge of each chip this requirement for extra space between adjacent devices limits of substrate utilization in high-density applications.
- In a second approach, a quantity of encapsulating resin is applied to the surface of substrate prior to assembly of the package. Then, as the chip and substrate are brought together in the assembly process, any encapsulating resin that overlies the pads is displaced by pressure of the bumps against the pads during the attachment process. This technique is susceptible to bleed-out of the resin laterally away from the chip edge as well as vertically along the sidewalls of the chip. Bleed-out away from the chip edge requires extra space between adjacent devices, limiting substrate utilization; and vertical bleed-out can result in resin reaching the backside of the chip and, in some instances, contamination of the bonding tool which is used to manipulate the die. Bleed-out is disruptive of the manufacturing process and is therefore undesirable. Moreover, a thermal excursion required to attach a device can cause partial curing of the applied resin on adjacent sites, thereby adversely affecting the quality of the inner connections on adjacent devices. Moreover, there is a practical lower limit on the thinness to which resin material can be applied by dispensing onto a surface or by screen printing, and that limit is generally greater (in some instances two or three times greater: about 100 microns for dispensing; about 50 microns for screen printing) than the bump standoff height (typically, for example, about 50-75 microns before bonding; and as little as about 25-30 microns, for example, after bonding) that is preferred in some small scale flip chip packages.
- Both of these approaches entail a dedicated unit process for application of the resin material, usually requiring dedicated equipment for the unit process and adding to both the labor costs and capital depreciation cost of the overall process.
- The invention provides an improved method for encapsulating flip chip interconnects. According to the method, a limited quantity of encapsulating resin is applied to the interconnect side of the chip, and thereafter the chip and substrate are apposed with the corresponding bumps and pads aligned, and then the chip and substrate are brought together under conditions that promote the bonding of the bumps on the metal pads. The resin may be applied to the interconnect side of the chip in any of a variety of ways. I have found, however, that a defined quantity of resin can conveniently and reliably be applied selectively to the chip by dipping the interconnect side of the chip in a pool of the resin to a predetermined depth, and then withdrawing the chip from the resin pool. A quantity of resin, precisely defined by the predetermined depth to which the chip was dipped in the resin pool, remains on the dipped portion of the chip as the chip is withdrawn from the resin pool and brought to the substrate for assembly. Most conveniently and reliably, the pool of resin is provided to a shallow depth in a reservoir, and the chip is dipped into the pool of resin in the reservoir so that the bumps contact the bottom of the reservoir. The predetermined shallow depth of the resin pool thereby determines the quantity of resin that remains on the dipped portion of the chip as the chip is withdrawn from the pool.
- Accordingly, in one general aspect the invention features a method for encapsulating flip chip interconnects, by applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip, and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate.
- In some embodiments, the step of applying resin to the chip includes dipping the interconnect side of the chip to a predetermined depth in a pool of resin, and then withdrawing the chip from the resin pool. In some embodiments the predetermined depth to which the chip is dipped in the pool approximates the standoff height between the bump surfaces and the chip surface, so that the surface of the resin pool contacts the chip surface, with result that when the chip is withdrawn from the resin pool some quantity of resin may remain on the chip surface as well as on features that standoff from the chip surface. Or, the predetermined depth to which the chip is dipped in the pool is somewhat less than the standoff height, so that the chip surface does not contact the resin pool, with the result that when the chip is withdrawn from the resin pool some quantity of resin remains only on features that standoff from the chip surface, such as the bumps or a portion of the bumps.
- In some embodiments the step of applying resin to the chip includes providing a reservoir having a bottom, providing a pool of resin in the reservoir to a shallow depth over the reservoir bottom, dipping the chip into the resin pool so that the bumps contact the reservoir bottom, and then withdrawing the chip from the resin pool. In some such embodiments, the shallow depth of the pool over the reservoir bottom approximates the standoff height between the bumps surfaces and the chip surface, or is somewhat less than the standoff height.
- In another general aspect the invention features apparatus for applying a precise volume of encapsulating resin to a chip, including a reservoir having a bottom, and means for dispensing a pool of encapsulating resin to a predetermined depth over the reservoir bottom. In some embodiments the reservoir is at least deep enough to accommodate a pool having a predetermined depth that approximates a bump standoff height on the chip. In some embodiments the means for dispensing the resin pool includes means for dispensing a measured volume of resin into the reservoir. In some embodiments the means for dispensing the resin pool includes means for dispensing an excess of resin into the reservoir, and means such as a doctor for removing the excess; in such embodiments the predetermined depth of the pool is established by the depth of the reservoir itself.
- An advantage of the method of the invention is that the resin pattern is self-aligned to the chip, so that there is no requirement according to the invention for alignment of the dispense pattern with the flip chip footprint pattern on the substrate. Moreover the resin is applied according to the invention preferentially to the portions of the interconnect side of the chip on which application of resin is most particularly desired, that is, on hand in the vicinity of the bumps.
- The resin reservoir is readily integrated with existing chip attachment equipment, so that there is no need for specialized or dedicated equipment or process steps for applying resin according to the invention.
- FIGS.1-5 are a diagrammatic sketches in a partially sectional view illustrating stages in an embodiment of the method of the invention.
- The invention will now be described in further detail by reference to the drawings, which illustrate an embodiment of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating stages in the method of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs.
- Turning now to FIG. 1, there is shown generally at20 a reservoir formed in a
support 22 and generally at 10 an integrated circuit chip being held by aconventional tool 12. Thereservoir 28 is defined by areservoir bottom 24 andsides 26. The reservoir depth is indicated at 27, and the reservoir is here shown filled nearly to its full depth with encapsulation resin forming aresin pool 30. Theintegrated circuit chip 10 includes asemiconductor die 18 havinginterconnect bumps 16 attached to interconnect sites (not shown in the FIGs.) in achip surface 17. The bump standoff height is indicated at 15. Thechip surface 17 and theinterconnect bumps 16 together with other features not shown in the FIGs. constitute aninterconnect side 14 of the chip. In FIG. 1, thetool 12 is poised to move toward the reservoir 20 (as shown by the arrow 11 in FIG. 2) to dip theinterconnect side 14 of the chip into theresin pool 30. - FIG. 2 shows the
chip 10 being dipped into theresin pool 30. Thebumps 16 have been brought into contact with thereservoir bottom 28, so that the pool depth defines the depth to which the interconnect side of the chip is dipped into the pool. In FIGS. 1 and 2 the pool depth is shown as being slightly less than the reservoir depth 27, and pool depth is also shown as being somewhat less than thebump standoff height 15. As a consequence, in the example shown here, thesurface 32 of the resin pool does not come into contact with thechip surface 17 and, accordingly, resin would be expected to remain on only the bumps when the chip is withdrawn from the pool. - FIG. 3 shows a
chip 10 that has been withdrawn from a resin pool. Evidently, the interconnect side of the chip shown in FIG. 3 was dipped to a greater depth in a resin pool than is shown in FIG. 2, inasmuch as in FIG. 3 theresin mass 34 is shown as being carried not only on thebumps 16 but also on thesurface 17 of the semiconductor die. As will be appreciated, the quantity of resin in a resin mass carried by the chip after the chip is withdrawn from the resin pool will depend not only upon the extent of contact to the chip with the resin in the pool, but also upon surface characteristics (for example, wettability by the resin) of the various features on the chip and upon characteristics (for example, viscosity) of the resin itself. A desired predetermined depth to which a particular chip should be dipped in a particular resin composition, to result in a particular desired encapsulation form, can readily be determined without undue experimentation. FIG. 3 also shows apackage substrate 40 havingmetal interconnect pads 42 in an arrangement complementary to the arrangement of the bumps on the chip, and thetool 12 is holding the chip in apposition to the substrate with the corresponding bumps and pads aligned. The tool is poised in FIG. 3 to bring the chip and substrate together as shown for example in FIG. 4. - In FIG. 4 the
resin mass 36 is shown having been compressed between the chip in the substrate, and displaced by the various features on the interconnect sides of the chip and of the substrate, to form a desired “fillet” 37, at the margins of the gap between the die and substrate, without excessive bleed out. Thetool 12 is then released from the die, and encapsulating resin is cured to form a completedencapsulation 38 of thepackage 50 as shown in FIG. 5. Some deformation of the bumps during the attachment operation can be expected, resulting in a reduction of the standoff height. This can further compress the resin and force it into asperities formed by the circuit pattern on the substrate surface as well as by features on the interconnect side of the chip, resulting in improved encapsulation integrity. - Other embodiments are within the following claims.
Claims (4)
1. Apparatus for applying a precise volume of encapsulating resin to an integrated circuit chip, comprising a reservoir having a bottom and means for dispensing a pool of encapsulating resin to a predetermined depth over the reservoir bottom.
2. Apparatus of claim 1 per wherein the reservoir is at least deep enough to accommodate a pool having a predetermined depth that approximates a bump standoff height on the chip.
3. Apparatus of claim 1 wherein the means for dispensing the resin pool comprises means for dispensing a measured volume of resin into the reservoir.
4. Apparatus of claim 1 wherein the means for dispensing the resin pool comprises means for dispensing an excess of resin into the reservoir, and means for removing the excess.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/456,434 US20030205197A1 (en) | 2001-02-27 | 2003-06-06 | Apparatus and process for precise encapsulation of flip chip interconnects |
US12/018,441 US20080134484A1 (en) | 2001-02-27 | 2008-01-23 | Apparatus and process for precise encapsulation of flip chip interconnects |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US27228001P | 2001-02-27 | 2001-02-27 | |
US10/081,425 US6780682B2 (en) | 2001-02-27 | 2002-02-22 | Process for precise encapsulation of flip chip interconnects |
US10/456,434 US20030205197A1 (en) | 2001-02-27 | 2003-06-06 | Apparatus and process for precise encapsulation of flip chip interconnects |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/081,425 Division US6780682B2 (en) | 2001-02-27 | 2002-02-22 | Process for precise encapsulation of flip chip interconnects |
Related Child Applications (1)
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US12/018,441 Continuation US20080134484A1 (en) | 2001-02-27 | 2008-01-23 | Apparatus and process for precise encapsulation of flip chip interconnects |
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US20030205197A1 true US20030205197A1 (en) | 2003-11-06 |
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Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US10/081,425 Expired - Lifetime US6780682B2 (en) | 2001-02-27 | 2002-02-22 | Process for precise encapsulation of flip chip interconnects |
US10/456,434 Abandoned US20030205197A1 (en) | 2001-02-27 | 2003-06-06 | Apparatus and process for precise encapsulation of flip chip interconnects |
US12/018,441 Abandoned US20080134484A1 (en) | 2001-02-27 | 2008-01-23 | Apparatus and process for precise encapsulation of flip chip interconnects |
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US10/081,425 Expired - Lifetime US6780682B2 (en) | 2001-02-27 | 2002-02-22 | Process for precise encapsulation of flip chip interconnects |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US12/018,441 Abandoned US20080134484A1 (en) | 2001-02-27 | 2008-01-23 | Apparatus and process for precise encapsulation of flip chip interconnects |
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Country | Link |
---|---|
US (3) | US6780682B2 (en) |
EP (1) | EP1461823A4 (en) |
JP (1) | JP4243487B2 (en) |
KR (1) | KR20030092001A (en) |
TW (1) | TWI251317B (en) |
WO (1) | WO2002069377A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102476089A (en) * | 2010-11-26 | 2012-05-30 | 普罗科技有限公司 | Dispensing apparatus for chip welding machine |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030137039A1 (en) * | 2001-11-16 | 2003-07-24 | Tdk Corporation | Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device |
JP2005064362A (en) * | 2003-08-19 | 2005-03-10 | Nec Electronics Corp | Manufacturing method of electronic device and electronic device thereof, and manufacturing method of semiconductor apparatus |
TWI378516B (en) | 2003-11-10 | 2012-12-01 | Chippac Inc | Bump-on-lead flip chip interconnection |
US7659633B2 (en) | 2004-11-10 | 2010-02-09 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US20070105277A1 (en) | 2004-11-10 | 2007-05-10 | Stats Chippac Ltd. | Solder joint flip chip interconnection |
US8026128B2 (en) | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
KR20070107154A (en) | 2005-03-25 | 2007-11-06 | 스태츠 칩팩, 엘티디. | Flip chip interconnection having narrow interconnection sites on the substrate |
US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
DE102006051607B4 (en) * | 2006-11-02 | 2008-11-20 | Mühlbauer Ag | Method and device for the standard application and mounting of electronic components on substrates |
US8193034B2 (en) | 2006-11-10 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertical interconnect structure using stud bumps |
US8174119B2 (en) | 2006-11-10 | 2012-05-08 | Stats Chippac, Ltd. | Semiconductor package with embedded die |
US8133762B2 (en) | 2009-03-17 | 2012-03-13 | Stats Chippac, Ltd. | Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core |
US9786629B2 (en) * | 2013-08-02 | 2017-10-10 | Alpha Assembly Solutions Inc. | Dual-side reinforcement flux for encapsulation |
CN109560034A (en) * | 2018-11-05 | 2019-04-02 | 紫光宏茂微电子(上海)有限公司 | The technique of chip attachment |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633535A (en) * | 1995-01-27 | 1997-05-27 | Chao; Clinton C. | Spacing control in electronic device assemblies |
US5828128A (en) * | 1995-08-01 | 1998-10-27 | Fujitsu, Ltd. | Semiconductor device having a bump which is inspected from outside and a circuit board used with such a semiconductor device |
US6184062B1 (en) * | 1999-01-19 | 2001-02-06 | International Business Machines Corporation | Process for forming cone shaped solder for chip interconnection |
US6420213B1 (en) * | 2000-02-23 | 2002-07-16 | Fujitsu Limited | Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive |
US6576495B1 (en) * | 2000-08-30 | 2003-06-10 | Micron Technology, Inc. | Microelectronic assembly with pre-disposed fill material and associated method of manufacture |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54105774A (en) | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Method of forming pattern on thin film hybrid integrated circuit |
JP2520411B2 (en) * | 1987-02-18 | 1996-07-31 | シチズン時計株式会社 | How to bond IC to LCD panel |
JPH0355860A (en) | 1989-07-25 | 1991-03-11 | Sharp Corp | Fixing method of semiconductor integrated circuit having protruding electrodes to circuit board |
JPH0429338A (en) | 1990-05-24 | 1992-01-31 | Nippon Mektron Ltd | Method circuit board for mounting ic and its mounting |
US5865365A (en) | 1991-02-19 | 1999-02-02 | Hitachi, Ltd. | Method of fabricating an electronic circuit device |
US5686317A (en) | 1991-06-04 | 1997-11-11 | Micron Technology, Inc. | Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die |
JP3225062B2 (en) | 1991-08-05 | 2001-11-05 | ローム株式会社 | Thermosetting resin sheet and semiconductor element mounting method using the same |
US5143745A (en) * | 1991-08-16 | 1992-09-01 | Maganas Thomas C | Intermittent film deposition method and system |
GB2261181B (en) * | 1991-11-08 | 1994-10-19 | Murata Manufacturing Co | Electrode forming apparatus |
US5346857A (en) | 1992-09-28 | 1994-09-13 | Motorola, Inc. | Method for forming a flip-chip bond from a gold-tin eutectic |
US5439162A (en) * | 1993-06-28 | 1995-08-08 | Motorola, Inc. | Direct chip attachment structure and method |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5592736A (en) | 1993-09-03 | 1997-01-14 | Micron Technology, Inc. | Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JP2664878B2 (en) | 1994-01-31 | 1997-10-22 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Semiconductor chip package and method of manufacturing the same |
DE19524739A1 (en) | 1994-11-17 | 1996-05-23 | Fraunhofer Ges Forschung | Inhomogeneous composition bump contact for surface mounted device flip-chip technology |
JP3209875B2 (en) | 1995-03-23 | 2001-09-17 | 株式会社日立製作所 | Substrate manufacturing method and substrate |
JP2796070B2 (en) | 1995-04-28 | 1998-09-10 | 松下電器産業株式会社 | Method of manufacturing probe card |
US5874780A (en) | 1995-07-27 | 1999-02-23 | Nec Corporation | Method of mounting a semiconductor device to a substrate and a mounted structure |
DE19527661C2 (en) | 1995-07-28 | 1998-02-19 | Optrex Europ Gmbh | Carrier comprising electrical conductors with an electronic component and method for contacting conductors of a substrate with contact warts of an electronic component |
JP3376203B2 (en) * | 1996-02-28 | 2003-02-10 | 株式会社東芝 | Semiconductor device, method of manufacturing the same, mounting structure using the semiconductor device, and method of manufacturing the same |
JP2828021B2 (en) | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | Bare chip mounting structure and manufacturing method |
US5681757A (en) * | 1996-04-29 | 1997-10-28 | Microfab Technologies, Inc. | Process for dispensing semiconductor die-bond adhesive using a printhead having a microjet array and the product produced by the process |
JP3309709B2 (en) * | 1996-05-24 | 2002-07-29 | 松下電器産業株式会社 | Mounting method of chip with bump |
JP2924830B2 (en) | 1996-11-15 | 1999-07-26 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5931371A (en) | 1997-01-16 | 1999-08-03 | Ford Motor Company | Standoff controlled interconnection |
JPH10209214A (en) * | 1997-01-22 | 1998-08-07 | Sony Corp | Method and device for mounting |
US6097098A (en) * | 1997-02-14 | 2000-08-01 | Micron Technology, Inc. | Die interconnections using intermediate connection elements secured to the die face |
JP3070514B2 (en) | 1997-04-28 | 2000-07-31 | 日本電気株式会社 | Semiconductor device having protruding electrode, method of mounting semiconductor device, and mounting structure thereof |
JPH10335383A (en) * | 1997-05-28 | 1998-12-18 | Matsushita Electric Ind Co Ltd | Producing method for semiconductor device |
US6337522B1 (en) | 1997-07-10 | 2002-01-08 | International Business Machines Corporation | Structure employing electrically conductive adhesives |
JP2001510944A (en) * | 1997-07-21 | 2001-08-07 | アギラ テクノロジーズ インコーポレイテッド | Semiconductor flip chip package and method of manufacturing the same |
US6013535A (en) * | 1997-08-05 | 2000-01-11 | Micron Technology, Inc. | Method for applying adhesives to a lead frame |
US6367150B1 (en) * | 1997-09-05 | 2002-04-09 | Northrop Grumman Corporation | Solder flux compatible with flip-chip underfill material |
US6083773A (en) | 1997-09-16 | 2000-07-04 | Micron Technology, Inc. | Methods of forming flip chip bumps and related flip chip bump constructions |
US6324069B1 (en) | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
SG71734A1 (en) | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
US6037192A (en) | 1998-01-22 | 2000-03-14 | Nortel Networks Corporation | Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure |
US5953814A (en) | 1998-02-27 | 1999-09-21 | Delco Electronics Corp. | Process for producing flip chip circuit board assembly exhibiting enhanced reliability |
US6323062B1 (en) * | 1998-04-27 | 2001-11-27 | Alpha Metals, Inc. | Wafer coating method for flip chips |
US6376352B1 (en) | 1998-11-05 | 2002-04-23 | Texas Instruments Incorporated | Stud-cone bump for probe tips used in known good die carriers |
SG88747A1 (en) | 1999-03-01 | 2002-05-21 | Motorola Inc | A method and machine for underfilling an assembly to form a semiconductor package |
US6194788B1 (en) | 1999-03-10 | 2001-02-27 | Alpha Metals, Inc. | Flip chip with integrated flux and underfill |
US6173887B1 (en) | 1999-06-24 | 2001-01-16 | International Business Machines Corporation | Method of making electrically conductive contacts on substrates |
-
2002
- 2002-02-22 US US10/081,425 patent/US6780682B2/en not_active Expired - Lifetime
- 2002-02-25 WO PCT/US2002/005634 patent/WO2002069377A1/en active Application Filing
- 2002-02-25 JP JP2002568405A patent/JP4243487B2/en not_active Expired - Lifetime
- 2002-02-25 KR KR10-2003-7011169A patent/KR20030092001A/en not_active Application Discontinuation
- 2002-02-25 EP EP02703379A patent/EP1461823A4/en not_active Withdrawn
- 2002-02-27 TW TW091103587A patent/TWI251317B/en not_active IP Right Cessation
-
2003
- 2003-06-06 US US10/456,434 patent/US20030205197A1/en not_active Abandoned
-
2008
- 2008-01-23 US US12/018,441 patent/US20080134484A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5633535A (en) * | 1995-01-27 | 1997-05-27 | Chao; Clinton C. | Spacing control in electronic device assemblies |
US5828128A (en) * | 1995-08-01 | 1998-10-27 | Fujitsu, Ltd. | Semiconductor device having a bump which is inspected from outside and a circuit board used with such a semiconductor device |
US6184062B1 (en) * | 1999-01-19 | 2001-02-06 | International Business Machines Corporation | Process for forming cone shaped solder for chip interconnection |
US6420213B1 (en) * | 2000-02-23 | 2002-07-16 | Fujitsu Limited | Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive |
US6576495B1 (en) * | 2000-08-30 | 2003-06-10 | Micron Technology, Inc. | Microelectronic assembly with pre-disposed fill material and associated method of manufacture |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102476089A (en) * | 2010-11-26 | 2012-05-30 | 普罗科技有限公司 | Dispensing apparatus for chip welding machine |
Also Published As
Publication number | Publication date |
---|---|
US20080134484A1 (en) | 2008-06-12 |
US20020123173A1 (en) | 2002-09-05 |
US6780682B2 (en) | 2004-08-24 |
JP4243487B2 (en) | 2009-03-25 |
TWI251317B (en) | 2006-03-11 |
EP1461823A1 (en) | 2004-09-29 |
KR20030092001A (en) | 2003-12-03 |
EP1461823A4 (en) | 2009-09-23 |
WO2002069377A1 (en) | 2002-09-06 |
JP2004525512A (en) | 2004-08-19 |
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