US20030153150A1 - Floating gate nitridation - Google Patents
Floating gate nitridation Download PDFInfo
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- US20030153150A1 US20030153150A1 US10/184,661 US18466102A US2003153150A1 US 20030153150 A1 US20030153150 A1 US 20030153150A1 US 18466102 A US18466102 A US 18466102A US 2003153150 A1 US2003153150 A1 US 2003153150A1
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- nonvolatile memory
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- 238000007667 floating Methods 0.000 title claims abstract description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 89
- 230000015654 memory Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 26
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 description 27
- 235000012239 silicon dioxide Nutrition 0.000 description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 239000000758 substrate Substances 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 108091006146 Channels Proteins 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910017464 nitrogen compound Inorganic materials 0.000 description 3
- 150000002830 nitrogen compounds Chemical class 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- -1 110 Chemical compound 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Abstract
The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.
Description
- The present invention relates to integrated circuits, and more particularly to nonvolatile integrated memories.
- FIG. 1 shows a cross section of a stacked gate nonvolatile memory cell such as used in flash and non-flash electrically erasable programmable read only memories (EEPROM). Conductive
floating gate 110, made of doped polysilicon, overliesmonocrystalline silicon substrate 120.Silicon dioxide 130 insulates the floating gate from the substrate. N type source/drain regions 140 insubstrate 120 are separated by Ptype channel region 150. Channelregion 150 is directly below the floating gate. Dielectric 160 separates the floating gate fromcontrol gate 170 made of doped polysilicon. - The memory cell is read by applying a voltage between the
regions 140, applying a voltage between one of theregions 140 andcontrol gate 170, and detecting a current through the other one of theregions 140. The memory cell is written (programmed or erased) by modifying a charge onfloating gate 110. Floatinggate 110 is completely insulated on all sides. The modify the charge on the floating gate, electrons are transferred between the floating gate andsubstrate 150 throughoxide 130. The electrons can be transferred by Fowler-Nordheim tunneling or hot electron injection. See “Nonvolatile Semiconductor Memory Technology” (1998) edited by W. D. Brown and J. E. Brewer, pages 10-25, incorporated herein by reference. The electron transfer requires a voltage to be established between the floating gate and a substrate region (the substrate region can bechannel 150 or a source/drain region 140). This voltage is established by creating a voltage between the substrate region and the control gate. The control gate voltage is coupled to the floating gate. To reduce the voltage required to be created between the substrate region and the control gate, a high capacitive coupling is needed between the floating and control gates. A high specific capacitance (capacitance per unit area) can be obtained between the floating and control gates by reducing the thickness of dielectric 160. However, dielectric 160 functions as a barrier to a charge leakage from the floating gate to the control gate. Therefore, dielectric 160 has to be a high quality, thin, uniform dielectric in order to provide good data retention (low leakage) and ensure a predictable high capacitive coupling between the floating and control gates. - Dielectric160 can be silicon dioxide. Also, ONO (silicon dioxide, silicon nitride, silicon dioxide) has been used. See U.S. Pat. No. 4,613,956 issued Sep. 23, 1986 to Peterson et al. Another option is a combination of silicon dioxide and oxynitride layers. Thus, according to U.S. Pat. No. 6,274,902, a silicon dioxide layer is thermally grown on floating gate polysilicon, and an oxynitride layer is deposited by LPCVD (low pressure chemical vapor deposition) on the silicon dioxide.
- This section summarizes some features of the invention. The invention is defined by the appended claims that are incorporated into this section by reference.
- In some embodiments of the present invention, before the dielectric160 is formed, the top surface of
floating gate 110 is nitrided to incorporate nitrogen atoms. The nitridation may involve ion implantation of pure nitrogen or nitrogen compounds intolayer 110. Alternatively, the nitridation can be accomplished by exposing the surface oflayer 110 to a nitrogen containing plasma. Other techniques, known or to be invented, are also possible. - After the nitridation process, silicon dioxide is thermally grown on the nitrided surface of
layer 110. The nitrogen atoms inlayer 110 slow down the oxidation process, so a more uniform silicon dioxide layer with fewer defects can be formed. Optionally, other dielectric layers (e.g. silicon nitride, silicon dioxide, oxynitride) are formed on the thermally grown silicon dioxide layer. - In some embodiments, dielectric160 includes a top layer of silicon dioxide. The top silicon dioxide layer is nitrided to incorporate nitrogen atoms. The nitrogen atoms may be pure nitrogen or part of nitrogen compounds. The nitrogen atoms reduce the leakage current, thus improving the data retention. Some of the nitrogen may bind with silicon atoms of the silicon oxide layer to form silicon nitride. The silicon nitride has a higher dielectric constant than silicon dioxide, thus increasing the capacitive coupling between the floating and control gates.
- Some embodiments combine the features described above, i.e. the nitridation of
floating gate 110 and the nitridation of the top silicon dioxide surface of dielectric 160. - The invention is applicable to split gate memories and other flash and non-flash floating gate memories, known or to be invented. Other features of the invention are described below. The invention is defined by the appended claims.
- FIG. 1 shows a cross section of a prior art nonvolatile memory cell.
- FIGS.2-7 show cross sections of nonvolatile memory cells in the process of fabrication according to some embodiments of the present invention.
- FIG. 2 illustrates a cross section of a nonvolatile memory cell at an early stage of fabrication. Semiconductor substrate120 (monocrystalline silicon or some other material) is processed to form a suitably doped channel region 150 (type P in FIG. 2, but an N type channel can also be used). Dielectric 130 is formed on
substrate 120 overchannel 150. Dielectric 130 may be thermally grown silicon dioxide or some other type of dielectric. Thenpolysilicon layer 110 is deposited and doped during or after deposition. See for example U.S. patent application Ser. No. 09/640,139 filed Aug. 15, 2000 and incorporated herein by reference. - The top surface of
polysilicon 110 is nitrided to incorporate nitrogen atoms. The nitrogen atoms may be pure nitrogen or part of nitrogen compounds. In one embodiment, nitrogen is implanted by ion implantation to a doze of 1013 to 1015 atoms/cm2 at an energy 1-30 keV. Optionally, the structure is thermally annealed. In one embodiment, the anneal is performed at 850-1000° C. for 10 to 60 seconds. - In another embodiment, nitridation is performed with plasma. For example, remote plasma nitridation (RPN) can be used. RPN involves exposing the
layer 110 to high density nitrogen plasma generated outside of a chamber containing the wafer. See U.S. Pat. No. 6,268,296 and U.S. patent publication Ser. No. 20010021588, both incorporated herein by reference. - In one embodiment, RPN is performed in a system of type Centura® available from Applied Materials, Inc. of Santa Clara, Calif. Suitable process parameters are:
Wafer temperature 300-500° C. Pressure 1-100 torr Nitrogen (N2) 0.5 slm (standard liters per minute) to 5 slm Helium (He) 1-6 slm Time 10-600 seconds - Other parameters can also be used.
- Optionally, a thermal anneal is conducted. For example, the structure can be held at 900-1100° C. at a pressure of 1 to 500 torr in the atmosphere of any of N2, He, NO, O2, N2O, or a combination of theses gases. An exemplary anneal time is 10-150 seconds.
- Another suitable plasma nitridation process is decoupled plasma nitridation (DPN) performed in a machine of type Gate Stack™ Centura® available from Applied Materials, Inc. of Santa Crara, Calif. A similar machine, a Decoupled Plasma Source of type Centura®, is described in U.S. Pat. No. 6,074,954 issued on Jun. 13, 2000 to Lill et al. and incorporated herein by reference. Exemplary process parameters are:
Power on the coil outside the processing chamber 100-500 W Pressure 10 mTorr to 10 Torr N2 flow 50 sccm to 2 slm Time 10-100 seconds - Optionally, the structure is annealed. The anneal parameters described above for the RPN process are suitable.
- After the nitridation step, the exemplary surface concentration of nitrogen atoms is 1-20 atomic percent in some embodiments. The exemplary thickness of the nitrided layer110.1 at the top of
layer 110 is below 3 nm. These parameters are not limiting. - As shown in FIG. 2, the nitridation can be performed before the
layer 110 is patterned. Alternatively, the nitridation can be performed after this layer is patterned. The nitridation can be a blanket process, or a mask can be used to block nitrogen from some wafer regions. In the floating gate regions, both silicon and nitrogen atoms are present at the top surface oflayer 110. - Then silicon dioxide310 (FIG. 3) is formed by thermal oxidation or chemical vapor deposition (CVD) on the nitrided surface of
layer 110. Thermal oxidation can be performed at 800-1050° C. in an oxygen or oxygen/hydrogen atmosphere. In some embodiments, the thermal oxide growth rate is up to 10 times less than for a non-nitrided silicon surface. An exemplary thickness oflayer 310 is 3 to 8 nm. Other thicknesses, processes, and process parameters may also be used. FIG. 3 shows thelayer 310 to be on top of nitrided layer 110.1. In fact, some or all of the silicon atoms in layer 110.1 can be consumed by the oxidation process. A layer of silicon dioxide with SixNy molecules can form as a result. - Known techniques can be used to complete the memory fabrication. In the example of FIG. 4,
silicon nitride layer 410 is formed by low pressure CVD (LPCVD) onlayer 310.Silicon dioxide 420 is deposited by CVD, or thermally grown, onlayer 410.Layers Doped polysilicon 170, or some other conductive material, is deposited to provide the control gates (possibly wordlines each of which provides the control gates for a row of memory cells). Thelayers drain regions 140 are formed by doping. Additional layers (not shown) may be formed to provide select gates, erase gates, or other features. See the aforementioned U.S. patent application Ser. No. 09/640,139 for an exemplary memory fabrication process that can be modified to incorporate the floating gate nitridation described above. - In FIG. 5, the nitridation of floating
gate polysilicon 110 is omitted.Silicon dioxide 310 is formed onpolysilicon 110 using conventional techniques (e.g. thermal oxidation or CVD). Thensilicon nitride 410 is deposited.Silicon dioxide 420 is deposited by CVD or grown thermally onnitride 410. An exemplary thickness oflayer 420 is 3-8 nm.Layers - The top surface of
oxide 420 is nitrided to improve the data retention. The capacitance is also increased as nitrogen binds with silicon to form silicon nitride. The nitridation can be performed, for example, by ion implantation, RPN or DPN, using the processes described above for nitridation ofpolysilicon 110. A thermal anneal can be performed at the end of the nitridation as described above forlayer 110. - In some embodiments, the surface concentration of nitrogen atoms is 1-20 atomic percent, and the thickness of the nitrided layer420.1 at the top of
layer 420 is below 3 nm. - Conductive layer170 (FIG. 6), for example, doped polysilicon, is formed on the nitrided surface of
oxide 420 as described above in connection with FIG. 4. This layer will provide the control gate. The structure is patterned and the fabrication is completed as described above in connection with FIG. 5. - In FIG. 7, the techniques of FIGS.2-6 are combined. Floating
gate polysilicon 110 is nitrided as described above in connection with FIG. 2. Then one or more dielectric layers are deposited (e.g. oxide 310,nitride 410, and oxide 420), with the top layer being silicon dioxide. The topsilicon dioxide layer 420 is nitrided as described above in connection with FIG. 5. Thenconductive layer 170 is formed and the fabrication is completed as described above. - Nitridation of floating
gate polysilicon 110 and/orsilicon dioxide 420 does not lead to a significant change in the total physical thickness ofdielectric 160. However, the specific capacitance between the floating and control gates increases by 5 to 20% in some embodiments depending on the nitridation conditions. Other capacitance parameters can also be obtained. - The memory cells of FIGS. 4, 6,7 can be operated like the memory cell of FIG. 1. The memory can be programmed by Fowler-Nordheim tunneling of electrons from
channel 150 or source/drain region 140 to floatinggate 110. The memory can be erased by Fowler-Nordheim tunneling of electrons from the floating gate to channel 150 or a source/drain region 140. In other embodiments, the memory is programmed by hot electron injection, and erased by Fowler-Nordheim tunneling. In still other embodiments, the memory is erased by tunneling of electrons from the floating gate to a separate erase gate (not shown). Other memory structures, including split gate structures with select gates, and other programming and erase mechanisms, known or to be invented, can also be used. - The invention is not limited to the embodiments described above. The invention is not limited to the particular nitridation techniques or process parameters, layer thicknesses, or other details. The invention is not limited to the particular shape of the floating and control gates or their positioning relative to each other. The invention is not limited to particular materials. For example,
polysilicon 110 can be replaced with amorphous silicon, monocrystalline silicon, or their combinations. Silicon dioxide (SO2) can be replaced, or mixed with, silicon monoxide (we will use the term “silicon oxide” to refer both to silicon dioxide and silicon monoxide). Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Claims (9)
1. A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:
forming a first layer comprising silicon, the first layer being to provide one or more floating gates for the nonvolatile memory;
nitriding a surface of the first layer to incorporate nitrogen atoms into said surface;
forming a first dielectric at the nitrided surface, wherein forming the first dielectric comprises forming silicon oxide at the nitrided surface;
forming a conductive layer separated from the nitrided surface by the first dielectric, the conductive layer providing one or more control gates for the nonvolatile memory.
2. The method of claim 1 wherein forming the silicon oxide at the nitrided surface comprises forming the silicon oxide by thermal oxidation.
3. The method of claim 1 wherein the surface of the first layer is a polysilicon surface.
4. An integrated circuit manufactured by the method of claim 1 .
5. An integrated circuit comprising a nonvolatile memory cell:
a channel region;
a first dielectric on a surface of the channel region;
a conductive floating gate on the first dielectric, the floating gate having a surface which has silicon and nitrogen atoms therein;
silicon oxide formed at said surface of the floating gate;
a conductive control gate opposite to said surface of the floating gate.
6. The integrated circuit of claim 5 further comprising a second dielectric between said surface of the floating gate and the control gate.
7. A method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:
forming a first layer to provide one or more floating gates for the nonvolatile memory;
forming a first dielectric on a surface of the first layer, wherein the first dielectric comprises a first surface comprising silicon oxide;
nitriding the first surface of the first dielectric to incorporate nitrogen atoms into the first surface;
forming a conductive layer on-the nitrided first surface of the first dielectric, the conductive layer providing one or more control gates for the nonvolatile memory.
8. An integrated circuit manufactured by the method of claim 7 .
9. An integrated circuit comprising a nonvolatile memory cell comprising:
a channel region;
a first dielectric on a surface of the channel region;
a conductive floating gate on the first dielectric;
a second dielectric on a surface of the floating gate; and
a conductive control gate separated from the floating gate by the second dielectric;
wherein the second dielectric comprises a layer of silicon oxide having a surface having nitrogen atoms embedded therein; and
the control gate contacts said silicon oxide surface with nitrogen atoms.
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US10/184,661 US20030153150A1 (en) | 2002-02-08 | 2002-06-26 | Floating gate nitridation |
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US10/071,689 US20030153149A1 (en) | 2002-02-08 | 2002-02-08 | Floating gate nitridation |
US10/184,661 US20030153150A1 (en) | 2002-02-08 | 2002-06-26 | Floating gate nitridation |
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US10/769,025 Expired - Lifetime US7001810B2 (en) | 2002-02-08 | 2004-01-30 | Floating gate nitridation |
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Also Published As
Publication number | Publication date |
---|---|
US20030153149A1 (en) | 2003-08-14 |
US7001810B2 (en) | 2006-02-21 |
US20040185647A1 (en) | 2004-09-23 |
TWI300961B (en) | 2008-09-11 |
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