US20030146478A1 - MOS device with dual gate insulators and method of forming the same - Google Patents

MOS device with dual gate insulators and method of forming the same Download PDF

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US20030146478A1
US20030146478A1 US10/382,842 US38284203A US2003146478A1 US 20030146478 A1 US20030146478 A1 US 20030146478A1 US 38284203 A US38284203 A US 38284203A US 2003146478 A1 US2003146478 A1 US 2003146478A1
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insulator
gate
electrode layer
gate electrode
mos device
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US10/382,842
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Wen Yen
Yun Chen
Hung-Cheng Weng
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Silicon Integrated Systems Corp
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Silicon Integrated Systems Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present invention relates to a metal-oxide-semiconductor (MOS) device process and, more particularly, to a MOS device with dual gate insulators and a method of forming the same.
  • MOS metal-oxide-semiconductor
  • HV MOS devices high-voltage MOS devices and low-voltage (LV) MOS devices are formed within the active areas and HV I/O devices are formed in the peripheral circuit areas. Since the HV MOS device has a longer channel length and a thicker gate insulator in comparison with the LV MOS device, how to provide two gate insulators of different thickness becomes an important problem to be solved.
  • FIGS. 1A to 1 E are sectional diagrams showing a method of forming HV MOS devices and LV MOS devices according to the prior art.
  • a semiconductor substrate 10 has a plurality of shallow trench isolation regions 12 for separating adjacent active areas, such as a HV MOS device region I and a LV MOS device region II.
  • a first oxide layer 14 is formed on the entire surface of the substrate 10 , and then photolithography and etching are employed to remove the first gate oxide layer 14 within the LV MOS device region II, thus the first oxide layer 14 only remains on the HV MOS device region I.
  • a second oxide layer 16 is formed on the entire surface of the substrate 10 to cover the first oxide layer 14 and the exposed area of the substrate 10 . Therefore, the stacked structure consisting of the first oxide layer 14 and the second oxide layer 16 within the HV MOS device region I serves as a thick gate oxide insulator of the HV MOS device. Also, the second oxide layer 16 within the LV MOS device region II serves as a thin gate oxide insulator of the LV MOS device. Thereafter, as shown in FIG.
  • photolithography and etching are employed to pattern the polysilicon layer as a first gate electrode layer 18 in the HV MOS device region I and a second gate electrode layer 20 in the LV MOS device region II.
  • LDD Lightly doped drains
  • the present invention provides a MOS device with dual gate insulators and a method of forming the same to solve the problems mentioned in the prior art.
  • the MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator.
  • the second gate insulator is thicker than the first gate insulator.
  • a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.
  • Yet another object of the invention is to improve the vertical electric field near the drain junction.
  • Still another object of the invention is to overcome hot-carrier effect without fabricating an LDD structure.
  • Another object of the invention is to reduce process time and costs.
  • FIGS. 1A to 1 E are sectional diagrams showing a method of forming HV MOS devices and LV MOS devices according to the prior art.
  • FIG. 2 is a sectional diagram showing a MOS device with dual gate insulators according to the present invention.
  • FIGS. 3A to 3 H are sectional diagrams showing a method of forming a MOS DEVICE with dual gate insulators according to the present invention.
  • FIG. 2 is a sectional diagram showing a MOS device with dual gate insulators according to the present invention.
  • a semiconductor substrate 30 comprises a thick gate insulator 32 , a thin gate insulator 34 , a gate electrode layer 36 patterned on the gate insulators 32 and 34 , and a source/drain electrode region 38 formed in the substrate 30 and surrounding the gate electrode layer 36 .
  • the thin gate insulator 34 has a width L and covers a predetermined area of the substrate 30 .
  • the thick gate insulator 32 surrounds the thin gate insulator 34 to cover the non-predetermined area of the substrate 30 .
  • the gate electrode layer 36 may be formed as a trapezoid profile with inclined sidewalls, or a square profile with vertical sidewalls as shown by the dotted line. It is noticed that the bottom center of the gate electrode layer 36 covers the thin gate insulator 34 for the distance L, and the bottom edge of the gate electrode layer 36 extends to cover a part of the thick gate insulator 32 for the distance d. Therefore, the lateral distance between the source/drain electrode regions 38 is L+2d. This increases the channel length of the MOS device and improves the lateral electric field near the drain junction.
  • the MOS device can overcome hot-carrier effect without fabricating an LDD structure. Therefore, lightly doped ion implantation and sidewall spacer processes comprising deposit, photolithography and etching can be omitted to reduce process time and costs. Furthermore, the MOS device with dual gate insulators can be applied to LV MOD devices, HV MOS devices and I/O devices for improving the electric field distribution near the edge of the gate electrode and preventing hot-carrier effect from a reduced channel length.
  • FIGS. 3A to 3 H are sectional diagrams showing a method of forming a MOS DEVICE with dual gate insulators according to the present invention.
  • a semiconductor substrate 40 comprises a plurality of shallow trench isolation regions 42 for separating adjacent active areas, such as a HV MOS device region I, a LV MOS device region II and a peripheral circuit region III.
  • FIG. 3A a semiconductor substrate 40 comprises a plurality of shallow trench isolation regions 42 for separating adjacent active areas, such as a HV MOS device region I, a LV MOS device region II and a peripheral circuit region III.
  • thermal oxidation or general deposition may be employed to form a first oxide layer 44 on the substrate 40 .
  • a first photoresist layer 46 with an opening 47 is patterned on the first oxide layer 44 , in which the opening 47 is used to define a thin gate insulator of a width L within the LV MOS device region II in subsequent processes.
  • the first oxide layer 44 exposed in the opening 47 is etched to exposed a predetermined area of the substrate 40 , and then the first photoresist layer 46 is removed.
  • a second oxide layer 48 is formed on the entire surface of the substrate 40 to cover the first oxide layer 44 and the exposed substrate 40 .
  • the stacked structure consisting of the first oxide layer 44 and the second oxide layer 48 serves as a gate insulator.
  • the second oxide layer 48 serves as a thin gate insulator, and the stacked structure of the first oxide layer 44 and the second oxide layer 48 serves as a thick gate insulator.
  • a polysilicon layer 50 and a second photoresist layer 52 with a predetermined pattern are successively formed on the entire surface of the substrate 40 .
  • photolithography and etching are used to pattern the polysilicon layer 50 as gate electrode layers, and then the second photoresist layer 52 is removed.
  • FIGS. 3G and 3H shows the results in the LV MOS device region II.
  • the second gate electrode layer 502 may be formed as a square profile with vertical sidewalls as shown in FIG. 3G, or a trapezoid profile with inclined sidewalls by tuning etching parameters as shown in FIG. 3H. Also, using ion implantation as the second gate electrode layer 502 as the mask, source/drain regions 52 are formed in the substrate 40 and surround the second gate electrode layer 502 .
  • the bottom edge of the second gate electrode layer 502 extends to cover the thick gate insulator, the lateral distance between the source/drain regions 52 , the channel length of the LV MOS device, is increased to solve the problem of hot-carrier effect. Furthermore, lightly doped ion implantation and sidewall spacer processes comprising deposit, photolithography and etching are omitted to reduce process time and costs.

Abstract

A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a metal-oxide-semiconductor (MOS) device process and, more particularly, to a MOS device with dual gate insulators and a method of forming the same. [0002]
  • 2. Description of the Related Art [0003]
  • In highly integrated VLSI or ULSI processing, high-voltage (HV) MOS devices and low-voltage (LV) MOS devices are formed within the active areas and HV I/O devices are formed in the peripheral circuit areas. Since the HV MOS device has a longer channel length and a thicker gate insulator in comparison with the LV MOS device, how to provide two gate insulators of different thickness becomes an important problem to be solved. [0004]
  • FIGS. 1A to [0005] 1E are sectional diagrams showing a method of forming HV MOS devices and LV MOS devices according to the prior art. As shown in FIG. 1A, a semiconductor substrate 10 has a plurality of shallow trench isolation regions 12 for separating adjacent active areas, such as a HV MOS device region I and a LV MOS device region II. As shown in FIG. 1B, a first oxide layer 14 is formed on the entire surface of the substrate 10, and then photolithography and etching are employed to remove the first gate oxide layer 14 within the LV MOS device region II, thus the first oxide layer 14 only remains on the HV MOS device region I. Next, a second oxide layer 16 is formed on the entire surface of the substrate 10 to cover the first oxide layer 14 and the exposed area of the substrate 10. Therefore, the stacked structure consisting of the first oxide layer 14 and the second oxide layer 16 within the HV MOS device region I serves as a thick gate oxide insulator of the HV MOS device. Also, the second oxide layer 16 within the LV MOS device region II serves as a thin gate oxide insulator of the LV MOS device. Thereafter, as shown in FIG. 1C, after depositing a polysilicon layer on the substrate 10, photolithography and etching are employed to pattern the polysilicon layer as a first gate electrode layer 18 in the HV MOS device region I and a second gate electrode layer 20 in the LV MOS device region II.
  • As the channel length is scaling down, hot-carrier effect has indeed become a significant problem in NMOS devices, especially when the channel length is smaller than 1.5 μm. Lightly doped drains (LDD) structure is one way to solve this problem. As shown in FIG. 1D, using lightly-doped ion implantation with the [0006] gate electrode layers 18 and 20 as the mask, a lightly-doped region 22 is formed in the substrate 10 and surrounds the gate electrode layers 18 and 20. Then, as shown in FIG. 1E, using deposit, photolithography and anisotropic etching, a sidewall spacer 24 is formed on the sidewalls of the gate electrode layers 18 and 20. Next, using heavily-doped ion implantation with the gate electrode layers 18 and 20 and the sidewall spacer 24 as the mask, a heavily doped region 26 is formed in the exposed area of the lightly doped region 22 to serve as a source/drain electrode region. The remaining lightly doped region 22 serves as an LDD structure. Thus, the HV MOS device completed within the HV MOS device region I has a channel length dI longer than a channel length dII of the LV MOS device completed within the LV MOS device region II.
    • SUMMARY OF THE INVENTION
  • The present invention provides a MOS device with dual gate insulators and a method of forming the same to solve the problems mentioned in the prior art. [0007]
  • The MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator. [0008]
  • Accordingly, it is a principal object of the invention to increases the channel length of the MOS device. [0009]
  • It is another object of the invention to improve the lateral electric field near the drain junction. [0010]
  • Yet another object of the invention is to improve the vertical electric field near the drain junction. [0011]
  • It is a further object of the invention to diminish a parasitic capacitance at the bottom corner of the gate electrode. [0012]
  • Still another object of the invention is to overcome hot-carrier effect without fabricating an LDD structure. [0013]
  • Another object of the invention is to reduce process time and costs. [0014]
  • These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.[0015]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to [0016] 1E are sectional diagrams showing a method of forming HV MOS devices and LV MOS devices according to the prior art.
  • FIG. 2 is a sectional diagram showing a MOS device with dual gate insulators according to the present invention. [0017]
  • FIGS. 3A to [0018] 3H are sectional diagrams showing a method of forming a MOS DEVICE with dual gate insulators according to the present invention.
  • Similar reference characters denote corresponding features consistently throughout the attached drawings. [0019]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 2 is a sectional diagram showing a MOS device with dual gate insulators according to the present invention. A [0020] semiconductor substrate 30 comprises a thick gate insulator 32, a thin gate insulator 34, a gate electrode layer 36 patterned on the gate insulators 32 and 34, and a source/drain electrode region 38 formed in the substrate 30 and surrounding the gate electrode layer 36. The thin gate insulator 34 has a width L and covers a predetermined area of the substrate 30. The thick gate insulator 32 surrounds the thin gate insulator 34 to cover the non-predetermined area of the substrate 30. The gate electrode layer 36 may be formed as a trapezoid profile with inclined sidewalls, or a square profile with vertical sidewalls as shown by the dotted line. It is noticed that the bottom center of the gate electrode layer 36 covers the thin gate insulator 34 for the distance L, and the bottom edge of the gate electrode layer 36 extends to cover a part of the thick gate insulator 32 for the distance d. Therefore, the lateral distance between the source/drain electrode regions 38 is L+2d. This increases the channel length of the MOS device and improves the lateral electric field near the drain junction. Also, this increases the distance between the edge of the gate electrode layer 36 and the source/drain electrode region 38 to improve the vertical electric field near the drain junction, thus diminishes a parasitic capacitance at the bottom corner of the gate electrode layer 36. Accordingly, the MOS device can overcome hot-carrier effect without fabricating an LDD structure. Therefore, lightly doped ion implantation and sidewall spacer processes comprising deposit, photolithography and etching can be omitted to reduce process time and costs. Furthermore, the MOS device with dual gate insulators can be applied to LV MOD devices, HV MOS devices and I/O devices for improving the electric field distribution near the edge of the gate electrode and preventing hot-carrier effect from a reduced channel length.
  • The above-described MOS device with dual gate insulators is preferably applied to a LV MOS device. Hereinafter, the present invention provides a method of integrating the formation of the above-described MOS device with dual gate insulators into the general HV MOS process. FIGS. 3A to [0021] 3H are sectional diagrams showing a method of forming a MOS DEVICE with dual gate insulators according to the present invention. As shown in FIG. 3A, a semiconductor substrate 40 comprises a plurality of shallow trench isolation regions 42 for separating adjacent active areas, such as a HV MOS device region I, a LV MOS device region II and a peripheral circuit region III. As shown in FIG. 3B, thermal oxidation or general deposition may be employed to form a first oxide layer 44 on the substrate 40. Then, a first photoresist layer 46 with an opening 47 is patterned on the first oxide layer 44, in which the opening 47 is used to define a thin gate insulator of a width L within the LV MOS device region II in subsequent processes. Then, as shown in FIG. 3C, the first oxide layer 44 exposed in the opening 47 is etched to exposed a predetermined area of the substrate 40, and then the first photoresist layer 46 is removed.
  • Next, as shown in FIG. 3D, a [0022] second oxide layer 48 is formed on the entire surface of the substrate 40 to cover the first oxide layer 44 and the exposed substrate 40. Thus, in the HV MOS device region I and the peripheral circuit region III, the stacked structure consisting of the first oxide layer 44 and the second oxide layer 48 serves as a gate insulator. Also, in the LV MOS device region II, the second oxide layer 48 serves as a thin gate insulator, and the stacked structure of the first oxide layer 44 and the second oxide layer 48 serves as a thick gate insulator.
  • Thereafter, as shown in FIG. 3E, a [0023] polysilicon layer 50 and a second photoresist layer 52 with a predetermined pattern are successively formed on the entire surface of the substrate 40. Next, as shown in FIG. 3F, photolithography and etching are used to pattern the polysilicon layer 50 as gate electrode layers, and then the second photoresist layer 52 is removed. This completes a first gate electrode layer 501 in the HV MOS device region I, a second gate electrode layer 502 in the LV MOS device region II, and a third gate electrode layer 503 in the peripheral circuit region III. It is noticed that the bottom center of the second gate electrode layer 502 covers the thin gate insulator, and the bottom edges of the second gate electrode layer 502 extend to cover the thick gate insulator.
  • In the subsequent processes, the formation of sidewall spacers, LDD structures and source/drain electrode regions can proceed in the HV MOS device region I and the peripheral circuit region III depending on the concerns of electrical properties and process requirements. FIGS. 3G and 3H shows the results in the LV MOS device region II. The second [0024] gate electrode layer 502 may be formed as a square profile with vertical sidewalls as shown in FIG. 3G, or a trapezoid profile with inclined sidewalls by tuning etching parameters as shown in FIG. 3H. Also, using ion implantation as the second gate electrode layer 502 as the mask, source/drain regions 52 are formed in the substrate 40 and surround the second gate electrode layer 502. Since the bottom edge of the second gate electrode layer 502 extends to cover the thick gate insulator, the lateral distance between the source/drain regions 52, the channel length of the LV MOS device, is increased to solve the problem of hot-carrier effect. Furthermore, lightly doped ion implantation and sidewall spacer processes comprising deposit, photolithography and etching are omitted to reduce process time and costs.
  • It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims. [0025]

Claims (13)

What is claimed is:
1. A MOS device with dual gate insulators, comprising:
a semiconductor substrate;
a first gate insulator formed on a predetermined area of the semiconductor substrate;
a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator, wherein the second gate insulator is thicker than the first gate insulator; and
a gate electrode layer, wherein the bottom center of the gate electrode layer covers the first gate insulator and the bottom edge of the gate electrode layer extends to cover the second gate insulator.
2. The MOS device with dual gate insulators according to claim 1, wherein the gate electrode layer has a square profile with vertical sidewalls.
3. The MOS device with dual gate insulators according to claim 1, wherein the gate electrode layer has a trapezoid profile with tapered sidewalls
4. The MOS device with dual gate insulators according to claim 1, further comprising a source/drain electrode region formed in the semiconductor substrate and surrounds the gate electrode layer.
5. The MOS device with dual gate insulators according to claim 1, wherein the first gate insulator and the second gate insulator are silicon oxide.
6. The MOS device with dual gate insulators according to claim 1, wherein the gate electrode layer is polysilicon.
7. A method of forming a MOS device with dual gate insulators, comprising steps of:
providing a semiconductor substrate having a predetermined region;
forming a first insulator on the predetermined area of the semiconductor substrate;
forming a second insulator to cover the first insulator and the exposed semiconductor substrate, wherein the second insulator on the predetermined region serves as a thin gate insulator and the stacked structure of the second insulator and the first insulator outside the predetermined region serves as a thick gate insulator; and
forming a gate electrode layer on the second insulator, wherein the bottom center of the gate electrode layer covers the thin gate insulator and the bottom edge of the gate electrode layer extends to cover the thick gate insulator.
8. The method according to claim 7, wherein the gate electrode layer has a square profile with vertical sidewalls.
9. The method according to claim 7, wherein the gate electrode layer has a trapezoid profile with tapered sidewalls
10. The method according to claim 7, further comprising a step of forming a source/drain electrode region in the semiconductor substrate and surrounds the gate electrode layer.
11. The method according to claim 7, wherein the formation of first gate insulator comprises steps of:
forming the first insulator on the semiconductor substrate;
forming a first photoresist layer with an opening on the first insulator, wherein the opening expose the first insulator within the predetermined region; and
removing the first insulator exposed in the opening.
12. The method according to claim 7, wherein the first insulator and the second insulator are silicon oxide.
13. The method according to claim 7, wherein the gate electrode layer is polysilicon.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070069259A1 (en) * 2005-09-28 2007-03-29 Dongbu Electronics Co., Ltd. CMOS image sensor and method of manufacturing the same
US20070164366A1 (en) * 2006-01-13 2007-07-19 Texas Instruments Incorporated Mitigation of gate oxide thinning in dual gate CMOS process technology
US20080067616A1 (en) * 2006-09-20 2008-03-20 Young-Suk Ko Semiconductor device
CN103456631A (en) * 2012-05-30 2013-12-18 上海华虹Nec电子有限公司 Manufacturing method of low-voltage LDMOS (laterally diffused metal oxide semiconductor) devices

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794281B2 (en) * 2002-05-20 2004-09-21 Freescale Semiconductor, Inc. Dual metal gate transistors for CMOS process
TW583724B (en) * 2003-03-13 2004-04-11 Promos Technologies Inc Method to form nitride layer with different thicknesses
KR100935988B1 (en) * 2003-12-08 2010-01-08 인터내셔널 비지네스 머신즈 코포레이션 Semiconductor memory device with increased node capacitance
US9978849B2 (en) 2015-12-29 2018-05-22 Globalfoundries Inc. SOI-MOSFET gate insulation layer with different thickness

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642881A (en) * 1984-05-17 1987-02-17 Kabushiki Kaisha Toshiba Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate
US5275960A (en) * 1990-04-03 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength
US5811340A (en) * 1996-10-25 1998-09-22 Lg Semicon Co., Ltd. Metal oxide semiconductor field effect transistor and method of manufacturing the same
US5888869A (en) * 1996-06-27 1999-03-30 Hyundai Electronics Industries, Co., Ltd. Method of fabricating a flash memory device
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US5960289A (en) * 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
US6165851A (en) * 1997-03-07 2000-12-26 Citizen Watch Co., Ltd. Semiconductor nonvolatile storage and method of fabricating the same
US6180473B1 (en) * 1999-06-21 2001-01-30 Hyundai Electroncis Industries Co., Ltd. Method for manufacturing semiconductor device
US6200834B1 (en) * 1999-07-22 2001-03-13 International Business Machines Corporation Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization
US6228708B1 (en) * 1998-12-10 2001-05-08 United Microelectronics Corp. Method of manufacturing high voltage mixed-mode device
US6284597B1 (en) * 1999-01-30 2001-09-04 United Microelectronics, Corp. Method of fabricating flash memory
US6284637B1 (en) * 1999-03-29 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Method to fabricate a floating gate with a sloping sidewall for a flash memory
US6333541B1 (en) * 1998-12-22 2001-12-25 Kabushiki Kaisha Toshiba MOSFET gate insulating films with oxynitride and oxide
US6333222B1 (en) * 1999-03-17 2001-12-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6441431B1 (en) * 1998-12-04 2002-08-27 Texas Instruments Incorporated Lateral double diffused metal oxide semiconductor device
US6620656B2 (en) * 2001-12-19 2003-09-16 Motorola, Inc. Method of forming body-tied silicon on insulator semiconductor device

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642881A (en) * 1984-05-17 1987-02-17 Kabushiki Kaisha Toshiba Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate
US5275960A (en) * 1990-04-03 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength
US5888869A (en) * 1996-06-27 1999-03-30 Hyundai Electronics Industries, Co., Ltd. Method of fabricating a flash memory device
US5811340A (en) * 1996-10-25 1998-09-22 Lg Semicon Co., Ltd. Metal oxide semiconductor field effect transistor and method of manufacturing the same
US6165851A (en) * 1997-03-07 2000-12-26 Citizen Watch Co., Ltd. Semiconductor nonvolatile storage and method of fabricating the same
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US5960289A (en) * 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
US6441431B1 (en) * 1998-12-04 2002-08-27 Texas Instruments Incorporated Lateral double diffused metal oxide semiconductor device
US6228708B1 (en) * 1998-12-10 2001-05-08 United Microelectronics Corp. Method of manufacturing high voltage mixed-mode device
US6333541B1 (en) * 1998-12-22 2001-12-25 Kabushiki Kaisha Toshiba MOSFET gate insulating films with oxynitride and oxide
US6284597B1 (en) * 1999-01-30 2001-09-04 United Microelectronics, Corp. Method of fabricating flash memory
US6333222B1 (en) * 1999-03-17 2001-12-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6284637B1 (en) * 1999-03-29 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Method to fabricate a floating gate with a sloping sidewall for a flash memory
US6180473B1 (en) * 1999-06-21 2001-01-30 Hyundai Electroncis Industries Co., Ltd. Method for manufacturing semiconductor device
US6200834B1 (en) * 1999-07-22 2001-03-13 International Business Machines Corporation Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization
US6620656B2 (en) * 2001-12-19 2003-09-16 Motorola, Inc. Method of forming body-tied silicon on insulator semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070069259A1 (en) * 2005-09-28 2007-03-29 Dongbu Electronics Co., Ltd. CMOS image sensor and method of manufacturing the same
US20070164366A1 (en) * 2006-01-13 2007-07-19 Texas Instruments Incorporated Mitigation of gate oxide thinning in dual gate CMOS process technology
US20080067616A1 (en) * 2006-09-20 2008-03-20 Young-Suk Ko Semiconductor device
US7863692B2 (en) * 2006-09-20 2011-01-04 Dongbu Hitek Co., Ltd. Semiconductor device
CN103456631A (en) * 2012-05-30 2013-12-18 上海华虹Nec电子有限公司 Manufacturing method of low-voltage LDMOS (laterally diffused metal oxide semiconductor) devices

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