|Publication number||US20030146102 A1|
|Application number||US 10/358,561|
|Publication date||7 Aug 2003|
|Filing date||5 Feb 2003|
|Priority date||5 Feb 2002|
|Publication number||10358561, 358561, US 2003/0146102 A1, US 2003/146102 A1, US 20030146102 A1, US 20030146102A1, US 2003146102 A1, US 2003146102A1, US-A1-20030146102, US-A1-2003146102, US2003/0146102A1, US2003/146102A1, US20030146102 A1, US20030146102A1, US2003146102 A1, US2003146102A1|
|Inventors||Sivakami Ramanathan, Srinivas Gandikota, Deenesh Padhi, Chris McGuirk, Girish Dixit, Robin Cheung|
|Original Assignee||Applied Materials, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (2), Classifications (17), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 This application claims benefit of U.S. provisional patent application serial No. 60/355,419 filed Feb. 5, 2002, which is herein incorporated by reference.
 1. Field of the Invention
 Embodiments of the invention generally relate to a method for depositing a copper film on a substrate by an electrochemical plating technique.
 1. Description of the Related Art
 Reliably producing sub-quarter micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die. Interconnects and multilevel interconnects are generally formed using sequential material deposition and material removal techniques of conducting, semiconducting, and dielectric materials, on a substrate surface to form features thereon.
 One material of choice for use in forming ULSI interconnects that provides the conductive pathway in integrated circuits and other electronic devices is copper. Copper is a material having advantageous properties, such as lower resistance and better electromigration performance, compared to traditional materials, such as aluminum. Currently, copper and its alloys have become the metals of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current carrying capacity, and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
 Electrochemical plating is generally accepted today as a preferred method of depositing copper for interconnect applications in the 0.13 μm generation of integrated circuits, and is being evaluated for extension to future generations of devices. Typically, electroplating solutions consist of: copper sulfate solutions, sulfuric acid to change the acidity (or pH) of the plating solution, copper chloride for nucleation of suppressor molecules, and additives to aid in depositing copper on the surface of a substrate and in filling sub micron sized features, e.g., vias and interconnects. The additives may include any combination of, but not limited to, levelers, brighteners or accelerators, inhibitors, suppressors, enhancers, and surfactants. The additives are often organic molecules that adsorb onto the surface of the substrate. Suppressors inhibit or reduce copper deposition in the adsorbed areas, while accelerators enhance growth in the adsorbed areas. Levelers improve deposition thickness uniformity.
 While the overall yield with copper interconnects depends on several key items, such as the type of barrier/seed, quality of the fill, or other upstream and downstream processes, the intrinsic properties of the plated film contribute largely to the reliability of the interconnect structure. Electromigration-induced failure is one of the most important modes of reliability failure in metal lines in VLSI circuits. Electromigration leads to a transport and accumulation of metal in the direction of electron flow, resulting in discontinuities in the metal lines. The directional mobility of atoms is enhanced by the presence of grain boundaries and impurity in metal films. Electromigration is affected by the metal grain size, film stress and trapped contamination (point defects). Larger grain size generally resists electromigration, while trapped contaminants facilitate electromigration failure. The mismatch of film stress between copper and dielectric films, underneath and above, could result in stress voiding. Film stress, grain size and trapped contamination, are modulated by plating parameters, such as plating current density, substrate rotation speed, electrolyte (or plating solution) flow rates and the type of plating waveform.
 Despite its significantly higher electromigration resistance compared to aluminum, there is an ongoing need to provide methods for improving electromigration resistance in copper interconnects. Consequently, there is a need for methods of electrochemical deposition of copper films on substrate surfaces and in substrate structures with reduced or minimal electromigration and improved electrical and mechanical properties.
 The invention described herein generally relates to a method of electrochemical plating metal, such as copper, onto substrates by controlling depositing parameters, such as plating current density and substrate rotation speed. Controlling the deposition parameters of the deposited material allows control of the intrinsic properties and reliability characteristics of deposited layers.
 Embodiments of the invention provide a method of plating a copper film on a substrate in an electrochemical plating apparatus. The method includes positioning a substrate in an electrolyte solution, applying a current between the substrate and an anode to generate a current density of between about 10 mA/cm2 and about 40 mA/cm2 on the substrate surface, rotating the substrate at a rotational speed of between about 20 rpm and about 50 rpm, and plating a copper film having a sheet resistance of less than about 16.5×10−2 Ohms/cm2. Embodiments of the invention further provide a copper film plated onto a semiconductor substrate, wherein the film has improved electromigration and stress characteristics
 Embodiments of the invention may further provide a copper film having a sheet resistance of between about 10.5×10−2 Ohms/cm2 and about 16.5×10−2 Ohms/cm2 formed onto a semiconductor substrate via an electrochemical deposition process, wherein the process includes applying a current density to the substrate surface of between about 15 mA/cm2 and about 30 mA/cm2 during the process and rotating the substrate at between about 10 rpm and about 25 rpm during the process.
 Embodiments of the invention further provide a copper layer formed on a semiconductor substrate, wherein the copper layer has a sheet resistance of between about 15.5×10−2 Ohms/cm2 and about 16.5×10−2 Ohms/cm2, a pre-anneal stress of less than about 90 Mpa, and a post anneal: pre-anneal stress ratio of less than about 6.
 So that the manner in which the features of the invention described herein are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
FIG. 1 is a schematic cross sectional view of an apparatus capable of performing the processes described herein.
FIG. 2 is a schematic cross sectional view of a copper wire.
FIG. 3 is a plot of Sheet resistance (Rs) dependence on substrate rotation speed and current density for samples anneal at 235° C. for one minute.
FIGS. 4A and 4B are plots of Film Stress dependence on substrate rotation speed and current density before (4A) and after (4B) anneal at 250° C. for 30 seconds.
 FIGS. 5A-5E are plots of dependence of Impurity (carbon, sulfur, nitrogen, oxygen and chlorine) concentration in plated copper film on substrate rotation speed and current density.
FIG. 6 is an electromigration activation energy plot for two-components and three-components chemistries.
FIG. 7 is a plot of Resistance rise for electromigration test samples, processed by two-components and three-components chemistries, stressed at 300° C.
FIG. 8 is a SEM cross sectional diagram of via fill on features of size 0.14 μm×1 μm.
 Aspects of the invention described herein generally relate to depositing material on a substrate surface by an electrochemical plating technique. The words and phrases used herein should be given their ordinary and customary meaning in the art by one skilled in the art, unless otherwise further defined. Embodiments of the invention may be practiced using a variety of apparatuses suitable for forming electroplated copper layers. One example of an electroplating apparatus is an Electra™ ECP system, which is available either as a stand-alone electroplating system or as part of an integrated processing system known as iECP™, both of which are available from Applied Materials, Inc., of Santa Clara, Calif. Details of an integrated processing system have been disclosed in commonly assigned U.S. Pat. No. 6,136,163, entitled “Apparatus for Electrochemical Deposition with Thermal Anneal chamber”, issued on Oct. 24, 2000, and U.S. Pat. No. 6,261,433, entitled “Electro-Chemical Deposition System and Method of Electroplating on Substrate”, issued on Jul.17, 2001. Both of the aforementioned patents are incorporated herein by reference in their entireties. Although the invention is described with respect to an Electra™ ECP processing chamber, any chamber, cell, or apparatus capable of electrochemically plating a material on a substrate can be used to advantage.
FIG. 1 illustrates a cross sectional view of an exemplary electroplating cell 100 of the present invention. The exemplary processing cell 100 generally includes a head assembly 110, a process kit 120, and an electrolyte (or electroplating solution) basin 140. The basin 140 may be secured onto the body 142 of the mainframe 114 over an opening 143 that defines a location for placement of the process kit 120. The basin 140 generally includes an inner wall 146, an outer wall 148, and a bottom 147 connecting the respective walls. A fluid inlet 210 maybe disposed through the bottom of the basin 140 so that the electrolyte may enter the electroplating cell. An electrolyte drain 149 is positioned to receive overflow from a weir of the basin 140 and is connected to the electrolyte replenishing system (not shown).
 The head assembly 110 is mounted onto a head assembly frame 152. A mounting post 154 is mounted onto the body 142, and the cantilever arm 156 extends laterally from an upper portion of the mounting post 154. Preferably, the mounting post 154 provides rotational movement with respect to a vertical axis along the mounting post to allow rotation of the head assembly 110. The head assembly 110 generally includes a substrate holder assembly 150 and a substrate assembly actuator 158. The substrate holder assembly 150 generally includes a substrate holder 164 and a cathode contact ring 166. The head assembly 110 is generally adapted to rotate the substrate at between about 5 and about 500 rpm in an electrolyte solution disposed in the cell.
 The substrate holder assembly 150 is positioned above the process kit 120. The process kit 120 generally includes a bowl 130, a container body 172, and an anode assembly 174. The container body 172 is preferably sized and adapted to conform to the substrate surface and the shape of a substrate being processed through the system, typically circular or rectangular in shape. The anode assembly 174 includes a soluble metal 196, disposed in an anode enclosure 194, and an anode contact 198. The anode contact 198 is inserted through the anode enclosure 194 to provide electrical connection to the soluble metal 196 from a power supply. The anode electrical contact 198 extends through the bowl 130 and is connected to an electrical power supply. A power source is coupled to the process cell to provide power between the substrate and anode to generate a current density between the substrate and the anode between about 1 mA/cm2 and about 100 mA/cm2 over the substrate surface.
 Embodiments of the invention may be practiced using different copper plating baths. In general, aside from a copper-containing electrolyte, a copper-electroplating bath also generally contains additives, such as suppressors, accelerators, and levelers. Examples of copper plating baths include two-component chemistries and three-component chemistries. Two-component chemistries refer to copper-electroplating baths that contain suppressors and accelerators (no levelers) as additives. Its' chemistry and process are described in commonly assigned and pending U.S. patent application Ser. No. 09/810,677, entitled “Method of Forming Copper Interconnects”, filed on Mar. 15, 2001, which is incorporated herein by reference in its entirety. The plating current for two-component chemistries can either be direct or pulsed. Three-component chemistries refer to baths that contain suppressors, accelerators, and levelers. Its' chemistry and process are described in commonly assigned and pending U.S. patent application Ser. No. 10/109,560, entitled “Process Window for Gap-Fill on Very High Aspect Ratio Structures Using Additives in Low Acid copper Baths”, filed on Mar. 26, 2002, which is incorporated herein by reference in its entirety. The plating current for three-component chemistries is typically direct (or non-pulsed).
 Copper interconnect processing includes etching a feature definition in a dielectric material, depositing a barrier layer in the feature definition, depositing an optional seed layer, and depositing a conductive material by an electroplating process to fill the feature definition. Feature definitions are generally formed in the dielectric material by conventional photolithographic and etching techniques. Examples of feature definitions include damascene and dual damascene structures. FIG. 2 shows a schematic cross section of a copper wire. The dielectric material may include any of various dielectric materials that may be employed in the manufacture of semiconductor devices. The barrier layer is used to prevent interlayer diffusion between the conductive material and the underlying dielectric material. The barrier layer is preferably deposited to a thickness between about 250 Å and about 1500 Å. An optional nucleation or “seed” layer may be deposited on the barrier layer to improve nucleation of subsequent materials, such as the deposition of the conductive layer in the feature definitions. The seed layer is typically made of a conductive material, such a copper seed layer for a copper material deposition.
 In one exemplary embodiment of the invention, a substrate with or without a patterned dielectric layer of Si/SiO2 thereon, receives a conformal TaN/Ta barrier layer having a thickness about 250 Å (or less depending upon the implementation) and a copper seed layer having a thickness of up to about 1500 Å (generally between about 200 Å and about 700 Å) deposited on the substrate using a PVD Self Ionized Plasma (SIP) technique. Plating may be, for example, carried out on the Applied Materials iECP tool. The temperature of the electrochemical plating bath may be maintained constant at 20° C. throughout the plating process. The current density may be varied between about 1.0 mA/cm2 and about 40.0 mA/cm2 and the plating rotation speed may be varied between 1 rpm, and about 50 rpm. Further, for all of the embodiments of the invention presented herein, the current density may be between about 10 mA/cm2 or between about 10 mA/cm2 and about 25 mA/cm2, for example. The rotation rates for the embodiments of the invention presented here may be between about 1 and about 50 rpm, or more particularly, between about 20 and about 50 rpm.
 A typical plating cell includes an anode assembly and a substrate rotation assembly. Electrolyte is introduced from the bottom of the cell and travels around or through the anode. This flow of electrolyte is modulated into a laminar flow toward the substrate to be plated. Upon immersion of the substrate, a boundary layer is formed at the interface of the substrate and the electrolyte. The boundary layer thickness can be expressed as δ=1.61ω−1/2γ1/6D1/3 where, δ is the thickness of the boundary layer, ω is the rotational speed, γ is the coefficient of viscosity, and D is the coefficient of diffusion. This relationship indicates that the boundary layer, which provides the source of plating material to the substrate, can be modulated by the substrate rotation speed, plating bath temperature (diffusion coefficient), and the constituents of the bath that effect viscosity. Once the bath constituents are optimized for gap filling, the species incorporated into the plated copper film generally depend on current density, rotation speed, and the electrolyte flow rate.
FIG. 3 illustrates the sheet resistance, measured by a four-point probe, as it depends upon current density and substrate rotation speeds, with an one-minute post anneal at 235° C. for 1 μm plated copper film deposited by a three-component chemistry. The result indicates lower sheet resistance for films deposited at lower substrate rotation speeds. The results indicate that lower substrate rotation speeds (less agitation) produce films with larger grain size. The results also indicate that films deposited at higher current densities have lower sheet resistance and larger grain size.
FIGS. 4A and 4B illustrate the variation of film stress of as-deposited (FIG. 4A) and post-anneal (FIG. 4B) 1 μm copper films with various current densities and various substrate rotation speeds. The annealing was performed at 250° C. for 30 seconds. The lower rotation as-deposited and annealed films exhibit lower stress than those deposited at higher rotation speeds. Films deposited at lower current densities exhibit significantly lower stress than films deposited at higher current densities. Annealed films deposited at lower rotation speeds exhibit lower stress, and current density does not show significant influence on after anneal film stress characteristics. The ratio of post-anneal film stress to pre-anneal film stress reflects stress relaxation as a result of grain growth. The low ratio reflects less grain growth and large as-deposited grain size. The ratios are lowest for high current density and low rotation speed, which means that high current density and low rotation speed provide copper films with larger grains. This finding is consistent with the conclusion drawn from sheet resistance study demonstrated in FIG. 3. Generally the sheet resistance of the films of the invention will be between less than about 16.5×10−2 Ohms/cm2, and more particularly the sheet resistance may be between about 15.25×10−2 Ohms/cm2 and about 16.25×10−2 Ohms/cm2, or between about 10.5×10−2 Ohms/cm2 and about 16.25×10−2 Ohms/cm2. ,Further, the ratio of pre-anneal stress to post anneal stress will generally be less than 12, and more particularly, less than about 6. The pre-anneal stress of the films of the invention is generally less than 90 Mpa.
 Table 1 shows the stress relaxation of 1 μm plated copper films with two and three component chemistries. The ratio of post-anneal film stress to pre-anneal film stress indicates a change by a factor of eleven for films deposited with pulse plating and by a factor of eight for DC plated films with two-component chemistries. Pulse plated films appears to provide smaller grain size compared to DC plated films. The post-anneal stress of films deposited with three-component chemistries exhibits a change by a factor of five, which indicates a larger grain size for three-component chemistries compared to two-component chemistries. In general, it's desirable to have a low ratio of post-anneal film stress to pre-anneal film stress, such as a ratio <12, since the low ratio reflects less grain growth and large as-deposited grain size.
TABLE 1 Stress measurements of plated Cu film (1 μm) under various electroplating conditions. Two- Two- components components Pulse Plating DC Three-components (MPa) Plating (MPa) DC Plating (MPa) As deposited 28.31 36.14 61.6 Post Anneal 331.5 296.4 322 (250° C., 30 sec)
 The sheet resistance and resistivity of the metal depends on grain size, impurity incorporation, etc., which in turn influences stress relaxation mechanisms. FIGS. 5A, 5B, 5C, 5D and 5E illustrate the current density and substrate rotation speed dependence on incorporation of various elements, such as carbon (FIG. 5A), sulfur (FIG. 5B), nitrogen (FIG. 5C), oxygen (FIG. 5D) and chlorine (FIG. 5D), in three-component chemistry plated copper films as estimated from SIMS. It has been observed that, in general, increasing current density or decreasing rotation speed decreases the concentration of these elements in the films. However, the effects of rotation speed and current density on nitrogen concentration are not as straightforward. Incorporation in films is controlled by the changes in adsorption or desorption of the breakdown/oxidized species of the additives. In general additive breakdown at the cathode and the respective byproducts do not exhibit similar adsorption as parent species, and are therefore, fed back into the plating baths. This may lead to an increase in the total organic concentration (TOC) level of the bath, but generally does not lead to a significant variation in the concentration of the impurities in the films with bath aging. The TOC levels are typically controlled by a bleed/feed mechanism, so as not to have any impact on gap-fill. The SIMS data presented was measured at the same depths in the bulk of the film. In general, it's desirable to have low impurity concentration, such as carbon <50×1018 atoms/cm3, sulfur <8×1018 atoms/cm3, nitrogen <25×1018 atoms/cm3, oxygen <9×1018 atoms/cm3, chlorine <20×1018 atoms/cm3, since impurities (point defects) tend to move under EM stress and increase EM failure.
FIG. 6 shows the activation energy plot of electromigration median time to failure (T50) for 0.22 μm Via-M2-Via structures, with a failure criterion of 2% change in via resistance, as a function of temperature. The test temperatures were in the range of 250-350° C. with an electromigration stress current density of 1E6 A/cm2 in via. The result indicates activation energy of about 0.9 eV for both two-component and three-component chemistries. Three-component chemistries give higher T50 (median time to fail) than two-component chemistries. Another EM test, resistance rise, is illustrated in FIG. 7. The resistance rise is very small for copper plated by three-component chemistries, which indicates a very low rate of void formation and/or microstructural changes and good electromigration resistance of the copper film. Using 2% rise as the failure criteria catches resistance spikes that may heal by a void-repair mechanism. This test magnified time to fail and allows gathering electromigration results in shorter time frame and in larger number of samples. The intrinsic stress, as a result of different impurity concentration in the film as well as the grain structure of the films account for the difference in electromigration resistance rise performance. An electromigration resistant copper film is defined as a copper film having a mean time to failure of greater than 10 for the electromigration stress on a 0.22 μm Via-M2-Via structure with a failure criteria of 2% change in the via resistance. Further, an electromigration resistant film may generally be characterized by the fact that median decay time is at least ten years when operating at a standard operating temperature (generally approximately 100° C.) at a current density of about 1 MA/cm2 to about 4 MA/cm2. Two-component chemistries films showed a higher stress relaxation than the three-component chemistries plated films. The higher stress change, with resultant relief through strain, may lead to micro-void formation and results in poorer electromigration performance noted here.
 Void free gap-fill depends on the build-up of an optimum concentration gradient of organic species inside the features, the current density at which the plating is carried out, and the plating cell electrolyte flow dynamics in the proximity of the substrate. With the electroplating bath prepared at optimum concentrations of organic and inorganic additives (three-component chemistries), a complete fill on vias of feature size 0.14 μm×1 μm was achieved, as shown in FIG. 8, using current density less than about 15 mA/cm2 and rotation speed between about 1 rpm and about 50 rpm. It has been observed that at current densities greater than about 15 mA/cm2, copper deposits rapidly, not allowing establishment of a concentration gradient of organic molecules. This leads to void formation, and therefore, to achieve gap fill at high aspect ratio, the current density should be kept below about 15 mA/cm2.
 With the current trends of shrinking device dimensions, lower plating current densities (≦about 15 mA/cm2) are preferred for void free filling of the features. Stress and impurity concentrations together with the reliability data show that to achieve better reliability, the preferred process regime should be a combination of lower current densities with low rotation speeds. The best result is achieved for copper film deposited at a combination of current density between about 1 mA/cm2 and about 10 mA/cm2 with rotation speed between about 1 rpm and about 10 rpm.
 While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
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|CH283612A *||Title not available|
|FR1392029A *||Title not available|
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6753251 *||28 Mar 2002||22 Jun 2004||Semitool, Inc.||Method for filling recessed micro-structures with metallization in the production of a microelectronic device|
|US8518817 *||22 Sep 2010||27 Aug 2013||International Business Machines Corporation||Method of electrolytic plating and semiconductor device fabrication|
|U.S. Classification||205/291, 428/606, 257/E21.585, 257/E21.175|
|International Classification||H01L21/288, C25D3/38, C25D7/12, H01L21/768|
|Cooperative Classification||Y10T428/12431, H01L21/2885, H01L21/76877, C25D3/38, C25D7/123|
|European Classification||H01L21/288E, C25D3/38, H01L21/768C4, C25D7/12|
|5 Feb 2003||AS||Assignment|
Owner name: APPLIED MATERIALS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RAMANATHAN, SIVAKAMI;GANDIKOTA, SRINIVAS;PADHI, DEENESH;AND OTHERS;REEL/FRAME:013747/0443
Effective date: 20030204