US20030090932A1 - Asymmetric mram cell and bit design for improving bit yield - Google Patents
Asymmetric mram cell and bit design for improving bit yield Download PDFInfo
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- US20030090932A1 US20030090932A1 US10/094,971 US9497102A US2003090932A1 US 20030090932 A1 US20030090932 A1 US 20030090932A1 US 9497102 A US9497102 A US 9497102A US 2003090932 A1 US2003090932 A1 US 2003090932A1
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/155—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements with cylindrical configuration
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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Definitions
- the present invention relates generally to memory devices and, more particularly, to an asymmetric cell and bit design for improving the bit yield of a magnetoresistive random access memory (MRAM) device.
- MRAM magnetoresistive random access memory
- An MRAM device typically includes an array of magnetic memory cells.
- a typical magnetic memory cell has a structure which includes magnetic layers separated by a non-magnetic layer. Magnetic vectors in one magnetic layer, typically referred to as the pinned layer, are magnetically fixed or pinned in one direction. The magnetic vectors of the other magnetic layer, often referred to as the storage or sense layer, are not fixed so that its magnetization direction is free to switch between “parallel” and “anti-parallel” states relative to the pinned layer. In response to the parallel state, the magnetic memory cell will have a low resistance state. Conversely and in response to the anti-parallel state, the magnetic memory cell will have a high resistance state. The MRAM device associates these two resistance states with either a logical “1” or a “0” bit value.
- a logical “1” or “0” is usually written into the magnetic memory cell by applying external magnetic fields (via an electrical current) that rotate the magnetization direction in the storage layer.
- the orientation of magnetization in the storage layer aligns along an axis known as the easy-axis.
- the external magnetic fields are applied to flip the orientation of magnetization in the storage layer along its easy-axis to either the parallel or anti-parallel orientation with respect to the orientation of magnetization in the pinned layer depending on the desired logic state.
- MRAM devices usually include an array of row lines and column lines that are used to apply the external magnetic fields to the magnetic memory cells during writing.
- the magnetic memory cells are usually located at intersections of the row lines and column lines.
- a selected magnetic memory cell is usually written by applying electrical currents to the particular row and column lines that intersect at the selected magnetic memory cell.
- FIG. 1 illustrates a portion of an array 10 of magnetic memory cells 11 found in the typical MRAM device.
- the cells 11 are arranged into rows and columns with each row having an associated row line 12 and each column having an associated column line 14 .
- the cells 11 are arranged with their long axis extending parallel to the row lines 12 and their transverse axis extending parallel to the column lines 14 .
- each cell 11 has an easy-axis 19 of magnetization directed parallel with the long axis (length) of the cell and a hard-axis 20 of magnetization directed parallel with the short axis (width) of the cell.
- Each cell 11 has a column line 14 that generates an easy-axis magnetic field when current is applied through it and a row line 12 that generates a hard-axis magnetic field when current is applied through it.
- the manner in which currents generate magnetic fields in magnetic memory devices is well known in the art and is not discussed herein.
- the magnetic field aligned to the easy-axis is referred to herein as the easy-axis write field while the other field is referred to as the hard-axis write field. It is desired that only the selected magnetic memory cell receives both the easy-axis and hard-axis write fields.
- Each write field is commonly referred to as a half-select field because individually they cannot switch the contents of cell.
- the hard-axis write field is usually referred to as the half-select field
- the easy-axis write field is referred to as the switching field.
- the bit stored in the selected memory cell is referred to herein as a “selected bit.” All of the remaining memory cells coupled to the column line or row line, which are not the desired selected cell are referred to herein as “unselected cells” and their corresponding bits are “unselected bits.”
- the unselected cells coupled to the particular column line usually receive only the easy-axis write field.
- the unselected cells coupled to the particular row line usually receive only the hard-axis write field.
- the magnitudes of the easy-axis and hard-axis write fields are usually chosen to be high enough so that the stored bit in the selected magnetic memory cell switches its logic state, but are low enough so that the stored bits in the unselected memory cells, that are subject to only one of the write fields, do not switch.
- An undesirable switching of a stored bit in an unselected magnetic memory cell is commonly referred to as half-select switching.
- a serious problem that needs to be overcome in order to build reliable MRAM devices is the distribution of the switching fields that occur in the selected and unselected bits.
- a distribution of selected or unselected write fields strongly degrades bit yield. This is due to an overlap in the distribution of the write currents between the selected and unselected bits. It has been determined that this problem is attributable in part to the shape of the memory cells.
- the typical memory cell 11 has multiple layers of magnetoresistive material.
- the illustrated cell 11 includes a first magnetic layer 16 and a second magnetic layer 17 , which are separated by a first conducting or insulating spacer layer 18 .
- the stack of magnetic and non-magnetic layers are often patterned into symmetrical shape such as an ellipse, rectangle or hexagon.
- FIG. 2 a illustrates a memory cell 11 with a rectangular shape.
- the layers 16 and 17 have a magnetization vector 21 that is positioned substantially along the length or easy-axis of the cell 11 .
- the vector 21 is depicted with an arrowhead at each end to represent the two different magnetization directions within the cell 11 .
- the magnetization in one of the layers 16 / 17 is generally pinned while the magnetization of the other layer 17 / 16 is free to rotate into either of the two positions represented by the vector 21 .
- the problem with the shape of the current magnetic memory cell is that they are perfectly symmetrical. Any slight deviation from the perfectly symmetrical shape due to, for example, manufacturing process variations can cause a significant change in the magnetic fields and currents required to write a bit into the cells increasing the distribution of write currents within the array. This decreases write margin (i.e., the difference between the write currents of selected and unselected bits), which reduces bit yield.
- the present invention provides a design for memory cells of an MRAM device that increases the write margin and bit yield of the MRAM device.
- the above and other features and advantages are achieved by providing an asymmetric cell and bit design, rather than a symmetric design, for an MRAM device.
- the design is asymmetric when reflected about the easy-axis and has a centroid that is displaced from the bit center along the hard-axis. This asymmetry is large enough so that manufacturing process variations do not substantially change the switching fields of the stored bits.
- the asymmetry causes the ends of the bits to align in opposite directions in small half-select fields and parallel to each other at large half-select fields, which increases the difference in the switching fields between selected and unselected bits.
- the combined effect of these two characteristics results in increased bit yield (relative to similarly sized symmetric cells and bits) due to a smaller overlap between selected and unselected bit switching distributions.
- FIG. 1 illustrates a portion of an array of magnetic memory cells in an MRAM device
- FIG. 2 a illustrates a simplified view of a memory cell in the array illustrated in FIG. 1;
- FIG. 2 b illustrates a bit center and coordinate system for defining bit symmetry/asymmetry
- FIGS. 3 a - 3 c illustrate exemplary bit shapes that can be used in an MRAM device
- FIGS. 4 a - 4 d illustrate different magnetization patterns for a bit shape that is asymmetrical and has a centroid displaced from the bit center along the hard-axis;
- FIGS. 5 a - 5 d illustrate different magnetization patterns for a bit shape that is rotated with respect to the row line
- FIGS. 6 a - 6 d illustrate different magnetization patterns for a symmetrical bit shape
- FIG. 8 is a simulation of the switching astroids of the bit shapes shown in FIGS. 7 a - 7 d;
- FIGS. 9 a - 9 c illustrate an example reversal mode for an asymmetric bit shape with a centroid that is displaced from bit center along the hard-axis with a small hard-axis bias;
- FIGS. 10 a - 10 c illustrate an example reversal mode for an asymmetric bit shape with a centroid displaced along the hard-axis from the bit center with a large hard-axis bias
- FIG. 11 illustrates a processor system incorporating an MRAM memory circuit constructed in accordance with an exemplary embodiment of the invention.
- the magnetization reversal mode can be defined as the sequence of magnetization patterns during the magnetization reversal process (i.e., the switching of the magnetization direction of vector 21 illustrated in FIG. 2 a ). These magnetization patterns can be selected by bit shape and by different combinations of the write fields.
- bit shape is used throughout the remainder of this specification, but it should be appreciated that bit shape results from the shape of the memory cell storing the bit. Thus, for example, a reference to a symmetrical bit shape should also be deemed as referring to a symmetrical memory cell.
- bit shape and write fields used to write the bit can be used to increase the distance between the mean of the selected and unselected write field distributions (i.e., increase the write margin) and to decrease the width of the write field distributions by locking in a preferred reversal mode.
- Bit shape and corresponding symmetry/asymmetry can be quantified using the bit centroid and rotation with respect to the coordinate system illustrated in FIG. 2 b.
- the x-axis is parallel to the row line and the y-axis is parallel to the column line.
- the length of the bit is measured along the x-axis and the width is measured along the y-axis.
- the coordinate system used for defining bit symmetry/asymmetry is centered at 22 as shown in FIG. 2 b.
- bit rotation is defined as:
- bit symmetry/asymmetry is defined as follow:
- FIG. 3 a illustrates a symmetrical ellipse-shaped bit corresponding to equation (4).
- FIG. 3 b illustrates a rotated parallelogram-shaped bit corresponding to equation (5).
- FIG. 3 c illustrates a bit shape that is asymmetrical with a centroid that is displaced from the bit center along the hard-axis (y) that corresponds to equation (6).
- the x-axis is the easy-axis while the y-axis is the hard-axis.
- FIGS. 4 a - 4 d illustrate different magnetization patterns for a bit 30 that is asymmetrical and has a centroid displaced along the hard-axis from the bit's center (i.e., ⁇ y> ⁇ 0).
- FIGS. 4 a, 4 b illustrate the patterns for low hard-axis write fields. With low hard-axis write fields, the magnetization patterns in the ends 32 , 34 of the asymmetrical bit 30 align in opposite directions (i.e., vector 32 is point up while vector 34 is pointing down). In FIG. 4 a, the magnetization vector 21 is pointing to the right and in FIG.
- FIGS. 4 c, 4 d illustrate the patterns for high hard-axis write fields. With high hard-axis write fields, the patterns in the ends 32 , 34 of the asymmetrical bit 30 align in the same direction. In FIG. 4 c, the magnetization vector 21 is pointing to the right and in FIG. 4 d, the vector 21 has been switched or reversed such that it is now pointing to the left. The field required to switch the direction of the magnetization vector 21 is greater when the patterns in the ends 32 , 34 are aligned in opposite directions than when they are aligned in the same direction.
- FIGS. 5 a - 5 d illustrate different magnetization patterns for a bit 35 having a shape that is rotated with respect to the x-axis ( ⁇ > ⁇ 0).
- FIGS. 5 a, 5 b illustrate the patterns for low hard-axis write fields. With low hard-axis bias fields, the magnetization patterns in the ends 36 , 36 of the bit 35 align in the up direction when the magnetization vector 21 is pointing to the right and in the down direction when the vector 21 has been reversed such that it is pointing to the left.
- FIGS. 5 c, 5 d illustrate the patterns for high hard-axis bias fields. With high hard-axis bias fields, the patterns in the ends 36 , 38 of the bit 35 align in the same direction and always up. As the hard-axis magnetic write field increases it becomes easier to magnetize the vector 21 to the right than to the left.
- FIGS. 6 a - 6 d illustrate different magnetization patterns for a symmetrical bit 40 .
- FIGS. 6 a, 6 b illustrate the patterns for low hard-axis bias fields. With low hard-axis bias fields and perfect symmetry, the magnetization patterns in the ends 42 , 44 of the bit 40 split (point up and down) so that they align parallel to the bit edge. Slight deviation in bit symmetry, which could result from process variations, will cause the bit to magnetize as illustrated in FIGS. 4 and 5. This will cause a large scatter in the write fields required to reverse the direction of the magnetization vector 21 .
- FIGS. 6 c, 6 d illustrate the patterns for high hard-axis bias fields. With high hard-axis bias fields, the patterns in the ends 42 , 44 of the bit 40 align in the same direction and parallel to the hard-axis bias field.
- bit symmetry/asymmetry strongly determines magnetization patterns.
- bit shapes were simulated to determine their magnetization patterns. The shapes are illustrated in FIGS. 7 a - 7 d and are defined as follows:
- FIG. 7 a illustrates the symmetrical ellipse 40 corresponding to equation (7).
- FIG. 7 b illustrates a first asymmetrical bit 30 a that has a centroid that is displaced from the center along the hard-axis (i.e., y-axis) and corresponds to equation (8).
- FIG. 7 c illustrates a second asymmetrical bit 30 b that has a centroid displaced along its hard-axis (i.e., y-axis) from the bit center and corresponds to equation (9).
- FIG. 7 d illustrates a third ellipse that is rotated with respect to its easy-axis (i.e., x-axis) and corresponds to equation (10).
- FIG. 8 shows the effects of changes in bit symmetry on the mean magnetic field required to write a bit.
- the curve for the ellipse corresponds to the first and second lines 50 a, 50 b
- the curve for asym#2 corresponds to the third and fourth lines 60 a, 60 b
- the curve for asym#3 corresponds to the fifth and sixth lines 70 a, 70 b
- the curve for asym#4 corresponds to the seventh and eighth lines 80 a, 80 b.
- the axes for the graph are the hard-axis write field (Hy) and the easy-axis write fields (Hx). That is, Hy is the half-select field, and Hx is the switching field.
- the units for the fields in the graph are oersted (Oe).
- the curves represented by lines 50 a, 50 b, 60 a, 60 b, 70 a, 70 b, 80 a, 80 b are usually referred to as switching astroids.
- the memory cell operating points are represented by Hx, Hy pairs. If the operating point is between the two lines of the curve (i.e., inside the astroid), a bit cannot be written into the cell. If, however, the operating point is on the outer left or right of the two lines of the curve (e.g., outside the astroid), the bit can be written into the cell.
- FIGS. 7 a - 7 d cause significant variations in the switching field at fixed values of the half-select field, as indicated by the different curves shown in FIG. 8. From FIG. 8, it is apparent that when a bit has an asymmetry characterized by a centroid displaced along the y-axis (illustrated by the asym#2 and asym#3 curves), it shows a stronger drop in Hx with increasing Hy and would thus be preferred in terms of improving bit yield.
- the present invention uses asymmetric bit shapes that have a centroid displaced from the bit center along the hard-axis to overcome one of the major problems with the prior art MRAM cells.
- the present invention also encompasses the effects of material parameter variation as well as dimensional variation.
- material parameter variation and/or dimensional variation been introduced into the above example, the switching field distribution at fixed values of Hy would be larger than those shown in FIG. 8.
- increasing the difference in Hx between the unselected and selected states improves bit yield.
- the bit shape characterized by equation (6) would have this effect.
- FIGS. 9 a - 9 c and 10 a - 10 c Two exemplary switching modes are illustrated in FIGS. 9 a - 9 c and 10 a - 10 c.
- FIGS. 9 a - 9 c illustrate the switching mode that tends to occur in asymmetric bits characterized by ⁇ y> ⁇ 0 (i.e., the centroid is displaced from center along the hard-axis) and at values of Hy below a threshold value.
- FIG. 9 a illustrates a first magnetization pattern 100 in which it main magnetization 102 is pointing to the left.
- An end region 104 has a magnetization direction pointing down while a second end region 106 has a magnetization direction pointing up.
- FIG. 9 a illustrates a first magnetization pattern 100 in which it main magnetization 102 is pointing to the left.
- An end region 104 has a magnetization direction pointing down while a second end region 106 has a magnetization direction pointing up.
- FIG. 9 b illustrates an intermediate magnetization pattern 110 that consists of a main magnetization portion 112 with its direction pointing to the left.
- the first end region 114 has a magnetization direction pointing down while a second end region 116 has a magnetization direction pointing up.
- FIG. 9 c illustrates a magnetization pattern 120 after the reversal.
- the pattern 120 comprises a portion 122 with a magnetization direction pointing to the right, an end region 124 has a magnetization direction pointing up while a second end region 126 has a magnetization direction pointing down.
- This switching mode occurs because it is energetically favorable for the ends of these bits to align in opposite directions and thus, they tend to form a domain wall (e.g., regions 114 , 116 ) as the Hx is increased (FIG. 9 b ).
- FIGS. 10 a - 10 c illustrate the mode that occurs in asymmetric bits characterized by ⁇ y> ⁇ 0 (i.e., centroid displaced from bit center along the hard-axis) but at high bias values of Hy (i.e., above a certain threshold value).
- FIG. 10 a illustrates a magnetization pattern 140 in which it main magnetization 142 is pointing to the left while its end regions 144 , 146 have a magnetization that are pointing down and up, respectively.
- FIG. 10 b illustrates an intermediate magnetization pattern 150 after both Hx and Hy have been turned on that consists of a main magnetization portion 152 with its direction pointing up, and left and right end regions 154 , 156 also pointing up.
- FIG. 10 a illustrates a magnetization pattern 140 in which it main magnetization 142 is pointing to the left while its end regions 144 , 146 have a magnetization that are pointing down and up, respectively.
- FIG. 10 b illustrates an intermediate magnetization pattern 150
- FIGS. 10 c illustrates a magnetization pattern 160 after the reversal and after Hy is set to zero.
- the pattern 160 comprises a main magnetization region 162 pointing to the right, and end regions 164 , 166 having magnetization directions pointing up and down, respectively.
- a shape such as ⁇ y> ⁇ 0 asymmetry that exhibits this mode change with increasing Hy is highly desirable since it increases write margin due to the difference in switching fields between the reversal modes illustrated in FIGS. 9 and 10.
- the cells with the asymmetric bit shapes such that the centroid is displaced from the bit center along the hard-axis can be manufactured by any processing method or technique and that the invention is not to be limited to any such method.
- the layers e.g., layers 16 - 18 illustrated in FIG. 2 a
- the layers 16 - 18 illustrated in FIG. 2 a are not limited to any specific material or layers of materials. All that is required is the ability to form cells with the desired shape.
- the layers 16 - 18 illustrated in FIG. 2 a are suitable to practice the invention as long as they are patterned into the asymmetrical shape with the centroid displaced from the bit center along the hard-axis.
- the storage layer 17 needs to have a shape with its centroid displaced from the bit center along the hard-axis to practice the invention. That is, if it is desirable to have a symmetrical pinned layer 16 and non-magnetic layer 18 , then the invention could still be practiced solely by shaping the storage layer 17 with its centroid displaced from the bit center along the hard-axis.
- FIG. 11 illustrates a processor system 200 incorporating an MRAM memory circuit 212 constructed in accordance with an embodiment of the invention. That is, the MRAM memory circuit 212 comprises an array of magnetic memory cells that are asymmetrical and have a centroid displaced from bit center along the hard-axis and thus, have improved bit yield as explained above with respect to FIGS. 3 b, 4 a - 4 d, 8 and 9 a - 9 c.
- the system 200 may be a computer system, a process control system or any other system employing a processor and associated memory.
- the system 200 includes a central processing unit (CPU) 202 , e.g., a microprocessor, that communicates with the memory circuit 212 and an I/O device 208 over a bus 220 .
- CPU central processing unit
- I/O device 208 communicates with the memory circuit 212 and an I/O device 208 over a bus 220 .
- the bus 220 may be a series of buses and bridges commonly used in a processor system, but for convenience purposes only, the bus 220 has been illustrated as a single bus.
- a second I/O device 210 is illustrated, but is not necessary to practice the invention.
- the system 200 may also include additional memory devices such as a read-only memory (ROM) device 214 , and peripheral devices such as a floppy disk drive 204 and a compact disk (CD) ROM drive 206 that also communicates with the CPU 202 over the bus 220 as is well known in the art. It should be noted that the memory 212 may be embedded on the same chip as the CPU 202 if so desired.
- ROM read-only memory
- CD compact disk
Abstract
Description
- This application claims the benefit of U.S. Provisional Patent Application No. 60/331,421, filed on Nov. 15, 2001, the entire contents of which are incorporated herein by reference.
- The present invention relates generally to memory devices and, more particularly, to an asymmetric cell and bit design for improving the bit yield of a magnetoresistive random access memory (MRAM) device.
- Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. MRAM technology has been increasingly viewed as offering all these advantages.
- An MRAM device typically includes an array of magnetic memory cells. A typical magnetic memory cell has a structure which includes magnetic layers separated by a non-magnetic layer. Magnetic vectors in one magnetic layer, typically referred to as the pinned layer, are magnetically fixed or pinned in one direction. The magnetic vectors of the other magnetic layer, often referred to as the storage or sense layer, are not fixed so that its magnetization direction is free to switch between “parallel” and “anti-parallel” states relative to the pinned layer. In response to the parallel state, the magnetic memory cell will have a low resistance state. Conversely and in response to the anti-parallel state, the magnetic memory cell will have a high resistance state. The MRAM device associates these two resistance states with either a logical “1” or a “0” bit value.
- A logical “1” or “0” is usually written into the magnetic memory cell by applying external magnetic fields (via an electrical current) that rotate the magnetization direction in the storage layer. Typically, the orientation of magnetization in the storage layer aligns along an axis known as the easy-axis. The external magnetic fields are applied to flip the orientation of magnetization in the storage layer along its easy-axis to either the parallel or anti-parallel orientation with respect to the orientation of magnetization in the pinned layer depending on the desired logic state.
- MRAM devices usually include an array of row lines and column lines that are used to apply the external magnetic fields to the magnetic memory cells during writing. The magnetic memory cells are usually located at intersections of the row lines and column lines. A selected magnetic memory cell is usually written by applying electrical currents to the particular row and column lines that intersect at the selected magnetic memory cell.
- FIG. 1 illustrates a portion of an
array 10 ofmagnetic memory cells 11 found in the typical MRAM device. Thecells 11 are arranged into rows and columns with each row having anassociated row line 12 and each column having an associatedcolumn line 14. In addition, thecells 11 are arranged with their long axis extending parallel to therow lines 12 and their transverse axis extending parallel to thecolumn lines 14. Referring to FIGS. 1 and 2a, eachcell 11 has an easy-axis 19 of magnetization directed parallel with the long axis (length) of the cell and a hard-axis 20 of magnetization directed parallel with the short axis (width) of the cell. Eachcell 11 has acolumn line 14 that generates an easy-axis magnetic field when current is applied through it and arow line 12 that generates a hard-axis magnetic field when current is applied through it. The manner in which currents generate magnetic fields in magnetic memory devices is well known in the art and is not discussed herein. - The magnetic field aligned to the easy-axis is referred to herein as the easy-axis write field while the other field is referred to as the hard-axis write field. It is desired that only the selected magnetic memory cell receives both the easy-axis and hard-axis write fields. Each write field is commonly referred to as a half-select field because individually they cannot switch the contents of cell. In practice, however, the hard-axis write field is usually referred to as the half-select field, while the easy-axis write field is referred to as the switching field.
- The bit stored in the selected memory cell is referred to herein as a “selected bit.” All of the remaining memory cells coupled to the column line or row line, which are not the desired selected cell are referred to herein as “unselected cells” and their corresponding bits are “unselected bits.” The unselected cells coupled to the particular column line usually receive only the easy-axis write field. Similarly, the unselected cells coupled to the particular row line usually receive only the hard-axis write field. The magnitudes of the easy-axis and hard-axis write fields are usually chosen to be high enough so that the stored bit in the selected magnetic memory cell switches its logic state, but are low enough so that the stored bits in the unselected memory cells, that are subject to only one of the write fields, do not switch. An undesirable switching of a stored bit in an unselected magnetic memory cell (i.e., one that receives only one of the write fields) is commonly referred to as half-select switching.
- A serious problem that needs to be overcome in order to build reliable MRAM devices is the distribution of the switching fields that occur in the selected and unselected bits. A distribution of selected or unselected write fields strongly degrades bit yield. This is due to an overlap in the distribution of the write currents between the selected and unselected bits. It has been determined that this problem is attributable in part to the shape of the memory cells.
- Referring again to FIG. 2a and as discussed above, the
typical memory cell 11 has multiple layers of magnetoresistive material. For example, the illustratedcell 11 includes a firstmagnetic layer 16 and a secondmagnetic layer 17, which are separated by a first conducting or insulatingspacer layer 18. The stack of magnetic and non-magnetic layers are often patterned into symmetrical shape such as an ellipse, rectangle or hexagon. FIG. 2a illustrates amemory cell 11 with a rectangular shape. In the illustratedrectangular cell 11, thelayers magnetization vector 21 that is positioned substantially along the length or easy-axis of thecell 11. Thevector 21 is depicted with an arrowhead at each end to represent the two different magnetization directions within thecell 11. As discussed above, the magnetization in one of thelayers 16/17 is generally pinned while the magnetization of theother layer 17/16 is free to rotate into either of the two positions represented by thevector 21. - The problem with the shape of the current magnetic memory cell (i.e., ellipse, rectangle, hexagon) is that they are perfectly symmetrical. Any slight deviation from the perfectly symmetrical shape due to, for example, manufacturing process variations can cause a significant change in the magnetic fields and currents required to write a bit into the cells increasing the distribution of write currents within the array. This decreases write margin (i.e., the difference between the write currents of selected and unselected bits), which reduces bit yield.
- Accordingly, there is a desire and need for a cell and bit design that increases the write margin and bit yield in an MRAM device.
- The present invention provides a design for memory cells of an MRAM device that increases the write margin and bit yield of the MRAM device.
- The above and other features and advantages are achieved by providing an asymmetric cell and bit design, rather than a symmetric design, for an MRAM device. The design is asymmetric when reflected about the easy-axis and has a centroid that is displaced from the bit center along the hard-axis. This asymmetry is large enough so that manufacturing process variations do not substantially change the switching fields of the stored bits. In addition, the asymmetry causes the ends of the bits to align in opposite directions in small half-select fields and parallel to each other at large half-select fields, which increases the difference in the switching fields between selected and unselected bits. The combined effect of these two characteristics results in increased bit yield (relative to similarly sized symmetric cells and bits) due to a smaller overlap between selected and unselected bit switching distributions.
- The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:
- FIG. 1 illustrates a portion of an array of magnetic memory cells in an MRAM device;
- FIG. 2a illustrates a simplified view of a memory cell in the array illustrated in FIG. 1;
- FIG. 2b illustrates a bit center and coordinate system for defining bit symmetry/asymmetry;
- FIGS. 3a-3 c illustrate exemplary bit shapes that can be used in an MRAM device;
- FIGS. 4a-4 d illustrate different magnetization patterns for a bit shape that is asymmetrical and has a centroid displaced from the bit center along the hard-axis;
- FIGS. 5a-5 d illustrate different magnetization patterns for a bit shape that is rotated with respect to the row line;
- FIGS. 6a-6 d illustrate different magnetization patterns for a symmetrical bit shape;
-
- FIG. 8 is a simulation of the switching astroids of the bit shapes shown in FIGS. 7a-7 d;
- FIGS. 9a-9 c. illustrate an example reversal mode for an asymmetric bit shape with a centroid that is displaced from bit center along the hard-axis with a small hard-axis bias;
- FIGS. 10a-10 c. illustrate an example reversal mode for an asymmetric bit shape with a centroid displaced along the hard-axis from the bit center with a large hard-axis bias; and
- FIG. 11 illustrates a processor system incorporating an MRAM memory circuit constructed in accordance with an exemplary embodiment of the invention.
- In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention.
- As noted above, a fundamental problem that needs to be overcome in any MRAM device is the distribution of switching fields that results in poor bit yield due to an overlap between the write current distributions of selected and unselected bits. It has been determined that there are various parameters intrinsic to the MRAM cell/bit that could affect the selected and unselected bit distribution overlap. These include, but are not limited to random variations in bit shape from bit to bit, random variations in material parameters from bit to bit, the sequence of fields by which the bit is written, the value of the fields used to write a bit, and magnetic noise.
- A major contributor to the width of the switching field distributions relates to the magnetization reversal mode. The magnetization reversal mode can be defined as the sequence of magnetization patterns during the magnetization reversal process (i.e., the switching of the magnetization direction of
vector 21 illustrated in FIG. 2a). These magnetization patterns can be selected by bit shape and by different combinations of the write fields. The term “bit shape” is used throughout the remainder of this specification, but it should be appreciated that bit shape results from the shape of the memory cell storing the bit. Thus, for example, a reference to a symmetrical bit shape should also be deemed as referring to a symmetrical memory cell. - It has been determined that if properly selected, the bit shape and write fields used to write the bit can be used to increase the distance between the mean of the selected and unselected write field distributions (i.e., increase the write margin) and to decrease the width of the write field distributions by locking in a preferred reversal mode.
- Bit shape and corresponding symmetry/asymmetry can be quantified using the bit centroid and rotation with respect to the coordinate system illustrated in FIG. 2b. The x-axis is parallel to the row line and the y-axis is parallel to the column line. The length of the bit is measured along the x-axis and the width is measured along the y-axis. The coordinate system used for defining bit symmetry/asymmetry is centered at 22 as shown in FIG. 2b.
- The x and y coordinates of a bit's centroid are defined as follows:
- (1) <x>=∫∫xdxdy/∫∫dxdy; and
- (2) <y>=∫∫ydxdy/∫∫dxdy.
- The bit rotation is defined as:
- (3) <θ>=∫∫θ(x,y)dxdy/∫∫dxdy.
- Using these definitions, bit symmetry/asymmetry is defined as follow:
-
-
-
- FIG. 3a illustrates a symmetrical ellipse-shaped bit corresponding to equation (4). FIG. 3b illustrates a rotated parallelogram-shaped bit corresponding to equation (5). FIG. 3c illustrates a bit shape that is asymmetrical with a centroid that is displaced from the bit center along the hard-axis (y) that corresponds to equation (6). In FIGS. 3a-3 c, the x-axis is the easy-axis while the y-axis is the hard-axis.
- Bit symmetry/asymmetry strongly determines magnetization patterns, since the magnetization prefers to align parallel to the edges of the bit. FIGS. 4a-4 d illustrate different magnetization patterns for a
bit 30 that is asymmetrical and has a centroid displaced along the hard-axis from the bit's center (i.e., <y>≠0). FIGS. 4a, 4 b illustrate the patterns for low hard-axis write fields. With low hard-axis write fields, the magnetization patterns in theends asymmetrical bit 30 align in opposite directions (i.e.,vector 32 is point up whilevector 34 is pointing down). In FIG. 4a, themagnetization vector 21 is pointing to the right and in FIG. 4b, thevector 21 has been switched or reversed such that it is now pointing to the left. FIGS. 4c, 4 d illustrate the patterns for high hard-axis write fields. With high hard-axis write fields, the patterns in theends asymmetrical bit 30 align in the same direction. In FIG. 4c, themagnetization vector 21 is pointing to the right and in FIG. 4d, thevector 21 has been switched or reversed such that it is now pointing to the left. The field required to switch the direction of themagnetization vector 21 is greater when the patterns in theends - FIGS. 5a-5 d illustrate different magnetization patterns for a
bit 35 having a shape that is rotated with respect to the x-axis (<θ>≠0). FIGS. 5a, 5 b illustrate the patterns for low hard-axis write fields. With low hard-axis bias fields, the magnetization patterns in theends bit 35 align in the up direction when themagnetization vector 21 is pointing to the right and in the down direction when thevector 21 has been reversed such that it is pointing to the left. FIGS. 5c, 5 d illustrate the patterns for high hard-axis bias fields. With high hard-axis bias fields, the patterns in theends bit 35 align in the same direction and always up. As the hard-axis magnetic write field increases it becomes easier to magnetize thevector 21 to the right than to the left. - FIGS. 6a-6 d illustrate different magnetization patterns for a
symmetrical bit 40. FIGS. 6a, 6 b illustrate the patterns for low hard-axis bias fields. With low hard-axis bias fields and perfect symmetry, the magnetization patterns in theends bit 40 split (point up and down) so that they align parallel to the bit edge. Slight deviation in bit symmetry, which could result from process variations, will cause the bit to magnetize as illustrated in FIGS. 4 and 5. This will cause a large scatter in the write fields required to reverse the direction of themagnetization vector 21. FIGS. 6c, 6 d illustrate the patterns for high hard-axis bias fields. With high hard-axis bias fields, the patterns in theends bit 40 align in the same direction and parallel to the hard-axis bias field. - As shown above with respect to FIGS. 3a-6 d, bit symmetry/asymmetry strongly determines magnetization patterns. Four different bit shapes were simulated to determine their magnetization patterns. The shapes are illustrated in FIGS. 7a-7 d and are defined as follows:
- (7) ellipse=<x>=0 nm; <y>=0 nm; <θ>=0 degrees;
- (8)
asym# 2=<x>=0 nm; <y>=−8 nm; <θ>=0 degrees; - (9)
asym# 3=<x>=0 nm; <y>=−4 nm; <θ>=0 degrees; and - (10)
asym# 4=<x>=0 nm; <y>=0 nm; <θ>=−15 degrees. - All bits in the simulation are nominally 270 nm long, by 180 nm wide and 4 nm thick ellipses. FIG. 7a illustrates the
symmetrical ellipse 40 corresponding to equation (7). FIG. 7b illustrates a firstasymmetrical bit 30 a that has a centroid that is displaced from the center along the hard-axis (i.e., y-axis) and corresponds to equation (8). FIG. 7c illustrates a secondasymmetrical bit 30 b that has a centroid displaced along its hard-axis (i.e., y-axis) from the bit center and corresponds to equation (9). FIG. 7d illustrates a third ellipse that is rotated with respect to its easy-axis (i.e., x-axis) and corresponds to equation (10). - FIG. 8 shows the effects of changes in bit symmetry on the mean magnetic field required to write a bit. There are four curves with each curve comprised of two lines on the graph. Each curve represents the bits illustrated in FIGS. 7a-7 d. The curve for the ellipse corresponds to the first and
second lines asym# 2 corresponds to the third andfourth lines asym# 3 corresponds to the fifth andsixth lines asym# 4 corresponds to the seventh andeighth lines - The axes for the graph are the hard-axis write field (Hy) and the easy-axis write fields (Hx). That is, Hy is the half-select field, and Hx is the switching field. The units for the fields in the graph are oersted (Oe). The curves represented by
lines - The subtle differences in bit shape illustrated in FIGS. 7a-7 d cause significant variations in the switching field at fixed values of the half-select field, as indicated by the different curves shown in FIG. 8. From FIG. 8, it is apparent that when a bit has an asymmetry characterized by a centroid displaced along the y-axis (illustrated by the
asym# 2 andasym# 3 curves), it shows a stronger drop in Hx with increasing Hy and would thus be preferred in terms of improving bit yield. Thus, the present invention uses asymmetric bit shapes that have a centroid displaced from the bit center along the hard-axis to overcome one of the major problems with the prior art MRAM cells. - It should be noted that the present invention also encompasses the effects of material parameter variation as well as dimensional variation. Had material parameter variation and/or dimensional variation been introduced into the above example, the switching field distribution at fixed values of Hy would be larger than those shown in FIG. 8. As noted above, increasing the difference in Hx between the unselected and selected states (Hy=0 and Hy≠0) improves bit yield. The bit shape characterized by equation (6) would have this effect.
- Two exemplary switching modes are illustrated in FIGS. 9a-9 c and 10 a-10 c. FIGS. 9a-9 c illustrate the switching mode that tends to occur in asymmetric bits characterized by <y>≠0 (i.e., the centroid is displaced from center along the hard-axis) and at values of Hy below a threshold value. FIG. 9a illustrates a
first magnetization pattern 100 in which itmain magnetization 102 is pointing to the left. Anend region 104 has a magnetization direction pointing down while asecond end region 106 has a magnetization direction pointing up. FIG. 9b illustrates anintermediate magnetization pattern 110 that consists of amain magnetization portion 112 with its direction pointing to the left. Thefirst end region 114 has a magnetization direction pointing down while asecond end region 116 has a magnetization direction pointing up. FIG. 9c illustrates amagnetization pattern 120 after the reversal. Thepattern 120 comprises aportion 122 with a magnetization direction pointing to the right, anend region 124 has a magnetization direction pointing up while asecond end region 126 has a magnetization direction pointing down. This switching mode occurs because it is energetically favorable for the ends of these bits to align in opposite directions and thus, they tend to form a domain wall (e.g.,regions 114, 116) as the Hx is increased (FIG. 9b). - FIGS. 10a-10 c illustrate the mode that occurs in asymmetric bits characterized by <y>≠0 (i.e., centroid displaced from bit center along the hard-axis) but at high bias values of Hy (i.e., above a certain threshold value). FIG. 10a illustrates a
magnetization pattern 140 in which itmain magnetization 142 is pointing to the left while itsend regions intermediate magnetization pattern 150 after both Hx and Hy have been turned on that consists of amain magnetization portion 152 with its direction pointing up, and left andright end regions magnetization pattern 160 after the reversal and after Hy is set to zero. Thepattern 160 comprises amain magnetization region 162 pointing to the right, and endregions - Thus, simulations of the lopsided asymmetrical bits (
asym# 2 andasym# 3 illustrated in FIGS. 7b, 7 c) tend to show that it is possible to design a bit that changes its magnetization reversal mode upon application of Hy and thus shows an improved write margin over that of a symmetric bit. Secondly, it is possible to design the <y>≠0 asymmetry so that it is just large enough to overwhelm any changes in symmetry that may result due to processing variation. This would lock in a reversal mode and narrow the distribution of switching fields by eliminating modes with different switching astroids. FIG. 8 illustrates that although bits asym#2 andasym# 3 have slightly different shapes, their astroids nearly identical. - It should be noted that the cells with the asymmetric bit shapes such that the centroid is displaced from the bit center along the hard-axis can be manufactured by any processing method or technique and that the invention is not to be limited to any such method. Moreover, the layers (e.g., layers16-18 illustrated in FIG. 2a) that make up the cells are not limited to any specific material or layers of materials. All that is required is the ability to form cells with the desired shape. The layers 16-18 illustrated in FIG. 2a are suitable to practice the invention as long as they are patterned into the asymmetrical shape with the centroid displaced from the bit center along the hard-axis. It should also be appreciated that only the
storage layer 17 needs to have a shape with its centroid displaced from the bit center along the hard-axis to practice the invention. That is, if it is desirable to have a symmetrical pinnedlayer 16 andnon-magnetic layer 18, then the invention could still be practiced solely by shaping thestorage layer 17 with its centroid displaced from the bit center along the hard-axis. - FIG. 11 illustrates a
processor system 200 incorporating anMRAM memory circuit 212 constructed in accordance with an embodiment of the invention. That is, theMRAM memory circuit 212 comprises an array of magnetic memory cells that are asymmetrical and have a centroid displaced from bit center along the hard-axis and thus, have improved bit yield as explained above with respect to FIGS. 3b, 4 a-4 d, 8 and 9 a-9 c. Thesystem 200 may be a computer system, a process control system or any other system employing a processor and associated memory. - The
system 200 includes a central processing unit (CPU) 202, e.g., a microprocessor, that communicates with thememory circuit 212 and an I/O device 208 over abus 220. It must be noted that thebus 220 may be a series of buses and bridges commonly used in a processor system, but for convenience purposes only, thebus 220 has been illustrated as a single bus. A second I/O device 210 is illustrated, but is not necessary to practice the invention. Thesystem 200 may also include additional memory devices such as a read-only memory (ROM)device 214, and peripheral devices such as afloppy disk drive 204 and a compact disk (CD)ROM drive 206 that also communicates with theCPU 202 over thebus 220 as is well known in the art. It should be noted that thememory 212 may be embedded on the same chip as theCPU 202 if so desired. - While the invention has been described and illustrated with reference to exemplary embodiments, many variations can be made and equivalents substituted without departing from the spirit or scope of the invention. Accordingly, the invention is not to be understood as being limited by the foregoing description, but is only limited by the scope of the appended claims.
- What is claimed as new and desired to be protected by Letters Patent of the United States is:
Claims (25)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
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US10/094,971 US6570783B1 (en) | 2001-11-15 | 2002-03-12 | Asymmetric MRAM cell and bit design for improving bit yield |
PCT/US2002/036464 WO2003044800A2 (en) | 2001-11-15 | 2002-11-14 | Asymmetric mram cell and bit design for improving bit yield |
AU2002366074A AU2002366074A1 (en) | 2001-11-15 | 2002-11-14 | Asymmetric mram cell and bit design for improving bit yield |
JP2003546351A JP2005510077A (en) | 2001-11-15 | 2002-11-14 | Asymmetric MRAM cell and bit design to improve bit yield |
CNB028270436A CN100557703C (en) | 2001-11-15 | 2002-11-14 | Be used to improve the asymmetric MRAM cell and the bit design of bit yield rate |
EP02803618A EP1454321B1 (en) | 2001-11-15 | 2002-11-14 | Asymmetric mram cell and bit design for improving bit yield |
AT02803618T ATE408881T1 (en) | 2001-11-15 | 2002-11-14 | ASYMMETRIC MRAM CELL AND BIT DESIGN TO IMPROVE BIT YIELD |
DE60228992T DE60228992D1 (en) | 2001-11-15 | 2002-11-14 | ASYMMETRIC MRAM CELL AND BIT DESIGN TO IMPROVE BITAUSBEUTE |
KR1020047007471A KR100870320B1 (en) | 2001-11-15 | 2002-11-14 | Asymmetric mram cell and bit design for improving bit yield |
Applications Claiming Priority (2)
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---|---|---|---|
US33142101P | 2001-11-15 | 2001-11-15 | |
US10/094,971 US6570783B1 (en) | 2001-11-15 | 2002-03-12 | Asymmetric MRAM cell and bit design for improving bit yield |
Publications (2)
Publication Number | Publication Date |
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US20030090932A1 true US20030090932A1 (en) | 2003-05-15 |
US6570783B1 US6570783B1 (en) | 2003-05-27 |
Family
ID=26789406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/094,971 Expired - Lifetime US6570783B1 (en) | 2001-11-15 | 2002-03-12 | Asymmetric MRAM cell and bit design for improving bit yield |
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Country | Link |
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US (1) | US6570783B1 (en) |
EP (1) | EP1454321B1 (en) |
JP (1) | JP2005510077A (en) |
KR (1) | KR100870320B1 (en) |
CN (1) | CN100557703C (en) |
AT (1) | ATE408881T1 (en) |
AU (1) | AU2002366074A1 (en) |
DE (1) | DE60228992D1 (en) |
WO (1) | WO2003044800A2 (en) |
Cited By (4)
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US20050030786A1 (en) * | 2002-05-02 | 2005-02-10 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
US7002228B2 (en) | 2003-02-18 | 2006-02-21 | Micron Technology, Inc. | Diffusion barrier for improving the thermal stability of MRAM devices |
US20070194359A1 (en) * | 2006-02-23 | 2007-08-23 | Samsung Electronics Co., Ltd. | Magnetic memory devices using magnetic domain dragging |
US20100151276A1 (en) * | 2008-12-15 | 2010-06-17 | Renesas Technology Corp. | Magnetic storage device |
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US6803616B2 (en) * | 2002-06-17 | 2004-10-12 | Hewlett-Packard Development Company, L.P. | Magnetic memory element having controlled nucleation site in data layer |
US6936903B2 (en) * | 2001-09-25 | 2005-08-30 | Hewlett-Packard Development Company, L.P. | Magnetic memory cell having a soft reference layer |
US6665201B1 (en) * | 2002-07-24 | 2003-12-16 | Hewlett-Packard Development Company, L.P. | Direct connect solid-state storage device |
TW578149B (en) * | 2002-09-09 | 2004-03-01 | Ind Tech Res Inst | High density magnetic random access memory |
US7195927B2 (en) * | 2003-10-22 | 2007-03-27 | Hewlett-Packard Development Company, L.P. | Process for making magnetic memory structures having different-sized memory cell layers |
KR100541558B1 (en) | 2004-04-19 | 2006-01-11 | 삼성전자주식회사 | Magnetic tunnel junction structures having bended tips at both ends thereof, magnetic random access memory cells employing the same and photo masks used in formation thereof |
JP4667763B2 (en) * | 2004-04-20 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | Magnetic memory element and semiconductor device |
JP4594694B2 (en) * | 2004-10-08 | 2010-12-08 | 株式会社東芝 | Magnetoresistive effect element |
US7715224B2 (en) * | 2007-04-16 | 2010-05-11 | Magic Technologies, Inc. | MRAM with enhanced programming margin |
US7868404B2 (en) * | 2007-11-01 | 2011-01-11 | Nve Corporation | Vortex spin momentum transfer magnetoresistive device |
JP2009252878A (en) * | 2008-04-03 | 2009-10-29 | Renesas Technology Corp | Magnetic memory device |
JP5470602B2 (en) * | 2009-04-01 | 2014-04-16 | ルネサスエレクトロニクス株式会社 | Magnetic storage |
JP2011210830A (en) | 2010-03-29 | 2011-10-20 | Renesas Electronics Corp | Magnetic storage element and magnetic storage apparatus |
JP2012209358A (en) * | 2011-03-29 | 2012-10-25 | Renesas Electronics Corp | Magnetic storage element and magnetic storage device |
KR102641744B1 (en) | 2017-01-20 | 2024-03-04 | 삼성전자주식회사 | Variable resistance memory device |
KR102611433B1 (en) | 2018-11-14 | 2023-12-08 | 삼성전자주식회사 | Magnetic memory devices |
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US5835314A (en) * | 1996-04-17 | 1998-11-10 | Massachusetts Institute Of Technology | Tunnel junction device for storage and switching of signals |
US5748524A (en) * | 1996-09-23 | 1998-05-05 | Motorola, Inc. | MRAM with pinned ends |
US5982658A (en) | 1997-10-31 | 1999-11-09 | Honeywell Inc. | MRAM design to reduce dissimilar nearest neighbor effects |
US6104633A (en) | 1998-02-10 | 2000-08-15 | International Business Machines Corporation | Intentional asymmetry imposed during fabrication and/or access of magnetic tunnel junction devices |
US6072718A (en) * | 1998-02-10 | 2000-06-06 | International Business Machines Corporation | Magnetic memory devices having multiple magnetic tunnel junctions therein |
US6081445A (en) | 1998-07-27 | 2000-06-27 | Motorola, Inc. | Method to write/read MRAM arrays |
US6072717A (en) | 1998-09-04 | 2000-06-06 | Hewlett Packard | Stabilized magnetic memory cell |
US6005800A (en) | 1998-11-23 | 1999-12-21 | International Business Machines Corporation | Magnetic memory array with paired asymmetric memory cells for improved write margin |
US6097626A (en) | 1999-07-28 | 2000-08-01 | Hewlett-Packard Company | MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells |
US6134139A (en) | 1999-07-28 | 2000-10-17 | Hewlett-Packard | Magnetic memory structure with improved half-select margin |
US6252795B1 (en) * | 2000-09-29 | 2001-06-26 | Motorola Inc. | Programmable resistive circuit using magnetoresistive memory technology |
US6385082B1 (en) * | 2000-11-08 | 2002-05-07 | International Business Machines Corp. | Thermally-assisted magnetic random access memory (MRAM) |
-
2002
- 2002-03-12 US US10/094,971 patent/US6570783B1/en not_active Expired - Lifetime
- 2002-11-14 JP JP2003546351A patent/JP2005510077A/en active Pending
- 2002-11-14 AT AT02803618T patent/ATE408881T1/en not_active IP Right Cessation
- 2002-11-14 DE DE60228992T patent/DE60228992D1/en not_active Expired - Lifetime
- 2002-11-14 EP EP02803618A patent/EP1454321B1/en not_active Expired - Lifetime
- 2002-11-14 CN CNB028270436A patent/CN100557703C/en not_active Expired - Lifetime
- 2002-11-14 AU AU2002366074A patent/AU2002366074A1/en not_active Abandoned
- 2002-11-14 KR KR1020047007471A patent/KR100870320B1/en active IP Right Grant
- 2002-11-14 WO PCT/US2002/036464 patent/WO2003044800A2/en active Application Filing
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US20050030786A1 (en) * | 2002-05-02 | 2005-02-10 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
US7009874B2 (en) | 2002-05-02 | 2006-03-07 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
US7002228B2 (en) | 2003-02-18 | 2006-02-21 | Micron Technology, Inc. | Diffusion barrier for improving the thermal stability of MRAM devices |
US20070194359A1 (en) * | 2006-02-23 | 2007-08-23 | Samsung Electronics Co., Ltd. | Magnetic memory devices using magnetic domain dragging |
US7902579B2 (en) * | 2006-02-23 | 2011-03-08 | Samsung Electronics Co., Ltd. | Magnetic memory devices using magnetic domain dragging |
US20100151276A1 (en) * | 2008-12-15 | 2010-06-17 | Renesas Technology Corp. | Magnetic storage device |
US8518562B2 (en) * | 2008-12-15 | 2013-08-27 | Renesas Electronics Corporation | Magnetic storage device |
Also Published As
Publication number | Publication date |
---|---|
ATE408881T1 (en) | 2008-10-15 |
KR100870320B1 (en) | 2008-11-25 |
AU2002366074A8 (en) | 2003-06-10 |
US6570783B1 (en) | 2003-05-27 |
DE60228992D1 (en) | 2008-10-30 |
CN1613117A (en) | 2005-05-04 |
EP1454321B1 (en) | 2008-09-17 |
WO2003044800A2 (en) | 2003-05-30 |
KR20040058294A (en) | 2004-07-03 |
CN100557703C (en) | 2009-11-04 |
JP2005510077A (en) | 2005-04-14 |
WO2003044800A3 (en) | 2003-12-31 |
AU2002366074A1 (en) | 2003-06-10 |
EP1454321A2 (en) | 2004-09-08 |
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