US20030046520A1 - Selective writing of data elements from packed data based upon a mask using predication - Google Patents
Selective writing of data elements from packed data based upon a mask using predication Download PDFInfo
- Publication number
- US20030046520A1 US20030046520A1 US10/279,553 US27955302A US2003046520A1 US 20030046520 A1 US20030046520 A1 US 20030046520A1 US 27955302 A US27955302 A US 27955302A US 2003046520 A1 US2003046520 A1 US 2003046520A1
- Authority
- US
- United States
- Prior art keywords
- data
- instructions
- mask
- data element
- packed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 claims abstract description 25
- 230000004044 response Effects 0.000 claims abstract description 5
- 238000012360 testing method Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000013459 approach Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 101000912503 Homo sapiens Tyrosine-protein kinase Fgr Proteins 0.000 description 1
- 102100026150 Tyrosine-protein kinase Fgr Human genes 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
Definitions
- the invention relates to the field of computer systems. More specifically, the invention relates to the selective writing of data element from packed data based on a Mask using predication.
- One common operation required by such applications is the writing of selected data items from a collection of data items to memory. Whether a given data item is to be written to memory is based upon a mask.
- An approach to moving select bytes of data uses a test, branch, and write series of instructions. In accordance with this approach, one or more of the mask bits for each corresponding data item is tested and a branch is used to either write or bypass writing the byte to memory.
- this approach suffers a performance penalty for branch mispredictions.
- FIG. 1 is a block diagram illustrating specialized parallel circuitry for implementing a SIMD Byte Mask Write instruction in a SIMD architecture.
- FIG. 1 illustrates the SIMD byte masked quadword move instruction (MASKMOVQ) which moves up to 64-bits representing integer data from a first SIMD register, labeled MM 1 and denoted by the first operand SRC 1 100 , to a memory location 106 implicitly specified by a register, using the byte packed data mask located in a second SIMD register, labeled MM 2 and denoted by the second operand SRC 2 102 .
- Bytes 110 and 114 of the register MM 1 100 are write-enabled by bytes 108 and 112 of the mask stored in the register MM 2 102 .
- this SIMD Byte Mask Write instruction requires specialized circuitry in the processor to process each byte of a packed data item in parallel. Although the parallel nature of this specialized circuitry achieves relatively good processor throughput, this specialized circuitry requires valuable die area and is only utilized for graphical and similar type processing.
- a method and apparatus for selectively writing data elements from packed data based upon a mask using predication are described.
- the following is performed in response to a plurality of instructions: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.
- FIG. 1 is a block diagram illustrating specialized parallel circuitry for implementing a SIMD Byte Mask Write instruction in a SIMD architecture.
- FIG. 2 is a block diagram illustrating a computer system in accordance with one embodiment of the invention.
- FIG. 3 is a flow diagram according to one embodiment of the invention.
- FIG. 4 is a diagram illustrating a selected portion of a computer system in accordance with one embodiment of the invention.
- FIG. 2 is a block diagram illustrating one embodiment of a computer system 200 in accordance with one embodiment of the invention.
- the computer system 200 comprises a processor 210 , a storage device 220 , and a bus 215 .
- the processor 210 is coupled to the storage device 220 by the bus 215 .
- a number of user input/output devices 240 e.g., keyboard, mouse
- the processor 210 represents a central processing unit of any type of architecture, such as CISC, RISC, VLIW, or hybrid architecture.
- the processor 210 could be implemented on one or more chips.
- the bus 215 represents one or more buses (e.g., AGP, PCI, ISA, X-Bus, VESA, etc.) and bridges. While this embodiment is described in relation to a single processor computer system, the invention could be implemented in a multi-processor computer system.
- buses e.g., AGP, PCI, ISA, X-Bus, VESA, etc.
- a network controller 255 In addition to other devices, one or more of a network controller 255 , a TV broadcast signal receiver 260 , a fax/modem 245 , a video capture card 235 , and an audio card 250 may optionally be coupled to bus 215 .
- the network controller 255 represents one or more network connections (e.g., an ethernet connection).
- the storage device 220 and media on which traffic from the network is received by the network controller 255 represents one or more machine-readable media.
- a machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer).
- machine-readable media include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.
- the TV broadcast signal receiver 260 represents a device for receiving TV broadcast signals
- the fax/modem 245 represents a fax and/or modem for receiving and/or transmitting analog signals representing data.
- the image capture card 235 represents one or more devices for digitizing images (i.e., a scanner, camera, etc.).
- the audio card 250 represents one or more devices for inputting and/or outputting sound (e.g., microphones, speakers, magnetic storage devices, optical storage devices, etc.).
- a graphics controller card 230 is also coupled to the bus 215 .
- the graphics controller 230 represents one or more devices for generating images (e.g., graphics card).
- FIG. 2 also illustrates that the storage device 220 has stored therein data 224 and program code 222 .
- Data 224 represents data stored in one or more formats (e.g., a packed data format).
- Program code 222 represents the necessary code for performing any and/or all of the techniques of the invention.
- the program code 222 contains instruction(s) that cause the processor 210 to perform efficient selective writing of data elements from packed data based upon a mask (e.g., emulation of a SIMD byte mask write instruction) using predication and parallel data processing.
- the storage device 220 preferably contains additional software (not shown), which is not necessary to understanding the invention.
- FIG. 2 additionally illustrates that the processor 210 includes a decoder 216 , a set of registers 214 , an execution unit 212 , an internal bus 211 , and predication circuitry 213 .
- the processor 210 contains additional circuitry, which is not necessary to understanding the invention.
- the decoder 216 , registers 214 , execution unit 212 , and predication circuitry 213 are coupled together by the internal bus 211 .
- the decoder 216 is used for decoding instructions received by processor 210 into control signals and/or a microcode entry points. In response to these control signals and/or microcode entry points, the execution unit 212 performs the appropriate operations.
- the decoder 216 may be implemented using any number of different mechanisms (e.g., a look-up table, a hardware implementation, a PLA, etc.).
- the decoder 216 is shown including decode circuitry 218 to support instruction(s) to cause the processor 210 to perform selective writing of data elements from packed data based upon a mask.
- the processor 210 is a superscalar pipelined processor capable of completing one or more of these instruction(s) per clock cycle (ignoring any data dependencies and pipeline freezes).
- the processor 210 can be capable of executing new instructions and/or instructions similar to or the same as those found in existing general-purpose processors.
- the processor 210 supports an instruction set which is compatible with the Intel Architecture instruction set used by existing processors, such as the Pentium® III processor manufactured by Intel Corporation of Santa Clara, Calif.
- the execution unit 212 contains multiple parallel processing units 219 A- 219 N, which can process multiple instructions in parallel (e.g., parallel processing units).
- the execution unit 212 also contains a combining buffer 270 for storing data until a 64-bit write could be performed.
- This combining buffer 270 allows the maximum utilization of the bus 215 by allowing the bus 215 to be used for other purposes while the buffer accumulates data to be stored.
- a combining buffer 270 or a bus 215 is within the scope of the present invention, and that these would engender corresponding differences in certain details of the processing units.
- the registers 214 represent a storage area on processor 210 for storing information, including control/status information, integer data, floating point data, packed data (integer and/or floating point), and predicate data. It is understood that aspects of the invention are the described instruction(s) for operating on packed data, as well as how those instruction(s) are used. According to these aspects of the invention, the storage area used for storing the predicate data is not critical.
- the term data processing system is used herein to refer to any machine for processing data, including the computer systems(s) described with reference to FIG. 2.
- the predication circuitry 213 is generalized predication circuitry that can be used for any instructions of the instruction set supported by the processor 216 .
- Predication enables conditional execution of all instructions. This technique therefore allows for the removal of branches themselves, and thereby removes the misprediction penalty. See Demystifying the EPIC and IA -64 by Peter Song in Microprocessor Report, Jan. 26, 1998 issue and ARM Architecture Offers High Code Density by Brian Case in Microprocessor Report, Dec. 18, 1991 issue.
- a generalized predication model is used
- alternative embodiments could support predication on only certain instructions (e.g.,conditional move-type instructions).
- the masks used for enabling which data elements are written are of the same size as the data elements, in alternative embodiments the masks could be of different sizes (including each mask being composed of a single bit).
- FIG. 3 is a flow diagram according to one embodiment of the invention.
- an initialization value is determined that identifies the potential storage location for the currently selected data element of the packed data operand to be selectively written. From block 305 , the process flows to block 310 .
- the value of a predicate for the currently selected data element is determined.
- the value of the predicate is determined using a test bit (“tbit”) instruction.
- the tbit instruction is used to test a bit of the packed mask data element corresponding to the currently selected data element of the packed data operand to be selectively written.
- This predicate value could be stored in a variety of storage mediums (e.g., a dedicated predicate register, a general-purpose register, etc).
- the currently selected data element of the packed data operand is stored (with respect to FIG. 2, the currently selected data element may be store in the combining buffer).
- the process flows to block 350 .
- the value associated with the storage location is incremented. For one embodiment of the present invention, this value is located in general-purpose register. However, the value associated with the storage location could be located in a variety of storage mediums.
- the packed data operand is shifted by the width of one data element (e.g., assuming the most significant data element of the packed data operand is the currently selected data item, the packed data operand is left shifted such that the next lower data element becomes the most significant data element, and thus the currently selected data element). The process flow then proceeds from 370 back to block 310 and the process is repeated until the last data element is processed.
- FIG. 3 could be interpreted to illustrate sequential processing, it is understood that the operations can be done in different orders (e.g., compile scheduling, loop unrolling, hardware out-of-order execution etc.), various operations can be done in parallel, and/or various other operations may be intersperseded in the flow.
- One embodiment of the invention may be conceptually viewed as follows:
- R 2 Address Register
- R 4 Mask Register with corresponding mask elements (x 0 , x 1 , . . . ,x 7 )
- Register R 2 contains the value associated with the storage location.
- Register R 3 contains the 64-bits of packed data, divided up, in this example, into eight data elements.
- Register R 4 contains the packed mask operand, with eight mask elements, x 0 -x 7 , corresponding to the eight data elements of R 3 .
- the code sequence determines the predicate value using the tbit instruction.
- the tbit tests the most significant bit of the packed mask element x 0 . If the bit is 1 , then the predicate p 1 will be set to true, else the predicate p 1 will be set to false.
- An alternative embodiment could set predicate p 1 equal to true is the bit value was 0 and, conversely, set p 1 equal to false if the bit value was 1. It should be understood that the tbit instruction could test any bit of the corresponding packed mask element.
- the previously stored predication value is used to conditionally store, in this example, one byte to the storage location associated with the value in R 4 .
- R 2 is incremented, R 3 is shifted eight bits to the right, and the predicate p 1 is reset in the same manner as the first group of instructions except the packed mask element x 1 is used instead x 0 .
- Multiple parallel processing units allows for the parallel processing of all 4 instructions in the second group of instructions in the same clock cycle(s).
- the third through the seventh group of instructions continue in the same manner as the second group of instructions, except that each group of instructions uses a different packed mask element.
- the ninth group of instructions uses predication to conditionally store the last byte to the storage location associated with the value in R 4 .
- the sequence takes 9 clock cycles.
- the amount of clock cycles can vary with the implementation of the processor and/or the number of data elements of the packed data operand.
- the invention does not require the use of specialized SIMD Byte Mask Write circuitry. Rather, the use of predication allows for the avoidance of conditional branches, and therefore performance loss due to branch misprediction.
- the multiple parallel processing units allow for improved processor throughput (e.g., one embodiment of the invention has the required number of parallel processing units to process the instructions of each group above in parallel).
- This parallelism and predication allows the invention to have comparable performance to a specialized SIMD circuitry implementation of the Byte Mask Write.
- the instructions in Table 1, and thus the circuitry in the processor to support them are used for many purposes, as compared to the specialized/dedicated byte mask write instruction circuitry which has a much narrower field of use (e.g., graphics processing).
- the invention may be implemented at various levels in the processing system. For example, based on the processor architecture, the above code sequence could be manually coded and provided to the processor, generated by a compiler compiling a single instruction, generated by a decoder in the processor responsive to receiving a single instruction, etc.
- FIG. 4 is a diagram illustrating a selected portion of a computer system in accordance with one embodiment of the invention.
- the select portion of the computer system comprises the processor 410 , the storage device 420 , and the bus 415 .
- the processor 410 in FIG. 4 contains additional circuitry, which is not necessary to understanding the invention.
- the processor 410 is designed to execute two different instruction sets (e.g., a 64-bit instruction set and a 32-bit instruction set).
- the term macroinstruction is used herein to refer to an instruction externally received by the processor.
- the decoder 416 is used for decoding instructions from a first of the instruction sets 410 into control signals and/or microcode entry points.
- the instructions from the first instruction set 410 when externally received by the processor 410 , are macroinstructions.
- the microcode converter 417 is used for converting instructions from the second instruction set 420 (e.g., IA32 Intel Architecture instructions) into the instructions from the first instruction set 410 , which are then processed by the decoder 416 .
- the macroinstructions from the second instruction set 420 are converted into a first level microcode made up of instructions from the first instruction set 410 .
- the instructions from the first instruction set 410 when generated internally to the processor 410 , are microinstructions.
- the conversion is accomplished using a microcode ROM.
- a single SIMD Byte Mask Write macroinstruction may be provided to the microcode converter 417 where it is converted to the appropriate instructions from the first instruction set 410 (here acting as microinstructions) for selectively writing data elements from packed data based upon a mask using predication.
- the same instructions from the first instruction set 410 for selectively writing data elements could be received as macroinstructions directly by the decoder 416 .
Abstract
A method and apparatus for selectively writing data elements from packed data based upon a mask using predication. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in response to a plurality of instructions: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.
Description
- The present patent application is a Continuation of prior application Ser. No. 09/399,612, filed Sep. 20, 1999, entitled SELECTIVE WRITING OF DA TA ELEMENTS FROM PACKED DATA BASED UPONA MASK USING PREDICATION, which is also incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to the field of computer systems. More specifically, the invention relates to the selective writing of data element from packed data based on a Mask using predication.
- 2. Background Information
- Computer technology continues to evolve at an ever-increasing rate. Gone are the days when the computer was merely a business tool primarily used for word-processing and spreadsheet applications. Today, with the evolution of multimedia applications, computer systems have become a common home electronic appliance, much like the television and home stereo system. Indeed, the line between computer system and other consumer electronic appliance has become blurred as multimedia applications executing on an appropriately configured computer system will function as a television set, a radio, a video playback device, and the like. Consequently, the market popularity of computer systems is often decided by the amount of memory they contain and the speed at which they can execute such multimedia applications.
- Those skilled in the art will appreciate that multimedia and communications applications require the manipulation of large amounts of data represented in a small number of bits to provide the true-to-life renderings of audio and video we have come to expect. For example, to render a 3D graphic, a relatively large collection of individual data items (e.g., eight-bit data) must be similarly processed.
- One common operation required by such applications is the writing of selected data items from a collection of data items to memory. Whether a given data item is to be written to memory is based upon a mask. An approach to moving select bytes of data uses a test, branch, and write series of instructions. In accordance with this approach, one or more of the mask bits for each corresponding data item is tested and a branch is used to either write or bypass writing the byte to memory. However, this approach suffers a performance penalty for branch mispredictions.
- To avoid this branch misprediction penalty, a Single Instruction, Multiple Data (SIMD) processor architecture is used to support a SIMD “Byte Mask Write” instruction to write packed data from one storage location to another (see U.S. patent application Ser. No. 09/052,802; filed Feb. 31, 1998. FIG. 1 is a block diagram illustrating specialized parallel circuitry for implementing a SIMD Byte Mask Write instruction in a SIMD architecture. FIG. 1 illustrates the SIMD byte masked quadword move instruction (MASKMOVQ) which moves up to 64-bits representing integer data from a first SIMD register, labeled MM1 and denoted by the first operand
SRC1 100, to amemory location 106 implicitly specified by a register, using the byte packed data mask located in a second SIMD register, labeled MM2 and denoted by the second operandSRC2 102. Bytes 110 and 114 of theregister MM1 100 are write-enabled bybytes register MM2 102. - As illustrated in FIG. 1 this SIMD Byte Mask Write instruction requires specialized circuitry in the processor to process each byte of a packed data item in parallel. Although the parallel nature of this specialized circuitry achieves relatively good processor throughput, this specialized circuitry requires valuable die area and is only utilized for graphical and similar type processing.
- A method and apparatus for selectively writing data elements from packed data based upon a mask using predication are described. In one embodiment of the invention, for each data element of a packed data operand, the following is performed in response to a plurality of instructions: determining a predicate value for the data element from one or more bits of a corresponding packed data mask element indicating whether the data element is selected for writing to a corresponding storage location, and storing in the corresponding storage location the data element based on the predicate value.
- The features and advantages of the invention will become apparent from the following detailed description of the invention in which:
- FIG. 1 is a block diagram illustrating specialized parallel circuitry for implementing a SIMD Byte Mask Write instruction in a SIMD architecture.
- FIG. 2 is a block diagram illustrating a computer system in accordance with one embodiment of the invention.
- FIG. 3 is a flow diagram according to one embodiment of the invention.
- FIG. 4 is a diagram illustrating a selected portion of a computer system in accordance with one embodiment of the invention.
- In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the invention.
- FIG. 2 is a block diagram illustrating one embodiment of a
computer system 200 in accordance with one embodiment of the invention. Thecomputer system 200 comprises aprocessor 210, astorage device 220, and abus 215. Theprocessor 210 is coupled to thestorage device 220 by thebus 215. In addition, a number of user input/output devices 240 (e.g., keyboard, mouse) are also coupled to thebus 215. Theprocessor 210 represents a central processing unit of any type of architecture, such as CISC, RISC, VLIW, or hybrid architecture. Furthermore, theprocessor 210 could be implemented on one or more chips. Thebus 215 represents one or more buses (e.g., AGP, PCI, ISA, X-Bus, VESA, etc.) and bridges. While this embodiment is described in relation to a single processor computer system, the invention could be implemented in a multi-processor computer system. - In addition to other devices, one or more of a
network controller 255, a TV broadcast signal receiver 260, a fax/modem 245, avideo capture card 235, and anaudio card 250 may optionally be coupled tobus 215. Thenetwork controller 255 represents one or more network connections (e.g., an ethernet connection). Thestorage device 220 and media on which traffic from the network is received by thenetwork controller 255 represents one or more machine-readable media. Thus, a machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc. - While the TV broadcast signal receiver260 represents a device for receiving TV broadcast signals, the fax/
modem 245 represents a fax and/or modem for receiving and/or transmitting analog signals representing data. Theimage capture card 235 represents one or more devices for digitizing images (i.e., a scanner, camera, etc.). Theaudio card 250 represents one or more devices for inputting and/or outputting sound (e.g., microphones, speakers, magnetic storage devices, optical storage devices, etc.). Agraphics controller card 230 is also coupled to thebus 215. Thegraphics controller 230 represents one or more devices for generating images (e.g., graphics card). - FIG. 2 also illustrates that the
storage device 220 has stored thereindata 224 andprogram code 222.Data 224 represents data stored in one or more formats (e.g., a packed data format).Program code 222 represents the necessary code for performing any and/or all of the techniques of the invention. In particular, theprogram code 222 contains instruction(s) that cause theprocessor 210 to perform efficient selective writing of data elements from packed data based upon a mask (e.g., emulation of a SIMD byte mask write instruction) using predication and parallel data processing. Of course, thestorage device 220 preferably contains additional software (not shown), which is not necessary to understanding the invention. - FIG. 2 additionally illustrates that the
processor 210 includes adecoder 216, a set ofregisters 214, anexecution unit 212, an internal bus 211, andpredication circuitry 213. Of course, theprocessor 210 contains additional circuitry, which is not necessary to understanding the invention. Thedecoder 216, registers 214,execution unit 212, andpredication circuitry 213 are coupled together by the internal bus 211. Thedecoder 216 is used for decoding instructions received byprocessor 210 into control signals and/or a microcode entry points. In response to these control signals and/or microcode entry points, theexecution unit 212 performs the appropriate operations. Thedecoder 216 may be implemented using any number of different mechanisms (e.g., a look-up table, a hardware implementation, a PLA, etc.). - The
decoder 216 is shown includingdecode circuitry 218 to support instruction(s) to cause theprocessor 210 to perform selective writing of data elements from packed data based upon a mask. Furthermore, in one embodiment, theprocessor 210 is a superscalar pipelined processor capable of completing one or more of these instruction(s) per clock cycle (ignoring any data dependencies and pipeline freezes). In addition to these instructions, theprocessor 210 can be capable of executing new instructions and/or instructions similar to or the same as those found in existing general-purpose processors. For example, in one embodiment theprocessor 210 supports an instruction set which is compatible with the Intel Architecture instruction set used by existing processors, such as the Pentium® III processor manufactured by Intel Corporation of Santa Clara, Calif. - The
execution unit 212 contains multipleparallel processing units 219A-219N, which can process multiple instructions in parallel (e.g., parallel processing units). In one embodiment of the invention, theexecution unit 212 also contains a combining buffer 270 for storing data until a 64-bit write could be performed. This combining buffer 270 allows the maximum utilization of thebus 215 by allowing thebus 215 to be used for other purposes while the buffer accumulates data to be stored. However, it will be understood that a combining buffer 270 or abus 215, either with a width different than 64-bits, is within the scope of the present invention, and that these would engender corresponding differences in certain details of the processing units. - The
registers 214 represent a storage area onprocessor 210 for storing information, including control/status information, integer data, floating point data, packed data (integer and/or floating point), and predicate data. It is understood that aspects of the invention are the described instruction(s) for operating on packed data, as well as how those instruction(s) are used. According to these aspects of the invention, the storage area used for storing the predicate data is not critical. The term data processing system is used herein to refer to any machine for processing data, including the computer systems(s) described with reference to FIG. 2. - In one embodiment of the invention, the
predication circuitry 213 is generalized predication circuitry that can be used for any instructions of the instruction set supported by theprocessor 216. Predication enables conditional execution of all instructions. This technique therefore allows for the removal of branches themselves, and thereby removes the misprediction penalty. See Demystifying the EPIC and IA-64 by Peter Song in Microprocessor Report, Jan. 26, 1998 issue and ARM Architecture Offers High Code Density by Brian Case in Microprocessor Report, Dec. 18, 1991 issue. While one embodiment is described where a generalized predication model is used, alternative embodiments could support predication on only certain instructions (e.g.,conditional move-type instructions). In addition, while one embodiment is described wherein the masks used for enabling which data elements are written are of the same size as the data elements, in alternative embodiments the masks could be of different sizes (including each mask being composed of a single bit). - FIG. 3 is a flow diagram according to one embodiment of the invention. At block305 an initialization value is determined that identifies the potential storage location for the currently selected data element of the packed data operand to be selectively written. From block 305, the process flows to block 310.
- At
block 310 the value of a predicate for the currently selected data element is determined. In one embodiment of the present invention, the value of the predicate is determined using a test bit (“tbit”) instruction. According to this embodiment, the tbit instruction is used to test a bit of the packed mask data element corresponding to the currently selected data element of the packed data operand to be selectively written. This predicate value could be stored in a variety of storage mediums (e.g., a dedicated predicate register, a general-purpose register, etc). - At
block 320 of FIG. 3, a decision is made regarding the value of the predicate determined inblock 310. According to block 320, if the value of the predicate is true, then the process flow proceeds to block 330. Otherwise, process flow proceeds to block 350. - At
block 330, the currently selected data element of the packed data operand is stored (with respect to FIG. 2, the currently selected data element may be store in the combining buffer). Afterblock 330, the process flows to block 350. - at
block 350, of FIG. 3, another decision is made regarding whether the currently selected data element is the last data element of the packed data operand to be processed. If the currently selected data element is the last data element to be processed, then the process flow proceeds to exit the method. Otherwise, the process flow proceeds fromblock 350 to block 360. - At
block 360 of FIG. 3, the value associated with the storage location is incremented. For one embodiment of the present invention, this value is located in general-purpose register. However, the value associated with the storage location could be located in a variety of storage mediums. Next, atblock 370 of FIG. 3, the packed data operand is shifted by the width of one data element (e.g., assuming the most significant data element of the packed data operand is the currently selected data item, the packed data operand is left shifted such that the next lower data element becomes the most significant data element, and thus the currently selected data element). The process flow then proceeds from 370 back to block 310 and the process is repeated until the last data element is processed. - While one embodiment is described in which shifting is used to select the currently selected data element of the packed data operand, alternative embodiments could used other techniques (e.g., a pointer, support instructions that allows for a designation (see tbit instruction below), etc.) In addition, while FIG. 3 could be interpreted to illustrate sequential processing, it is understood that the operations can be done in different orders (e.g., compile scheduling, loop unrolling, hardware out-of-order execution etc.), various operations can be done in parallel, and/or various other operations may be intersperseded in the flow.
- One embodiment of the invention may be conceptually viewed as follows:
- R2=Address Register
- R3=64 bit data Register
- R4=Mask Register with corresponding mask elements (x0, x1, . . . ,x7)
- Code Sequence to selectively write byte size data elements from the packed data operand stored in R3:
Instruction Group 1) p1,p2 = tbit r4,x0 2) <p1> store1 r2 = r3 r2 = r2 + 1 shifir r3 = r<<8 p1,p2 = tbit r4,×1 3) <p1> store1 r2 = r3 r2 = r2 + 1 shifir r3 = r<<8 p1,p2 = tbit r4,×2 4) <p1> store1 r2 = r3 r2 = r2 + 1 shiftr r3 = r<<8 p1,p2 = tbit r4,×3 5) <p1> store1 r2 = r3 r2 = r2 + 1 shiftr r3 = r<<8 p1,p2 = tbit r4,×4 6) <p1> store1 r2 = r3 r2 = r2 + 1 shiftr r3 = r<<8 p1,p2 = tbit r4,×5 7) <p1> store1 r2 = r3 r2 = r2 + 1 shiftr r3 = r<<8 p1,p2 = tbit r4,×6 8) <p1> store1 r2 = r3 r2 = r2 + 1 shiftr r3 = r<<8 p1,p2 = tbit r4,×7 9) <p1> store1 r2 = r3 - Register R2 contains the value associated with the storage location. Register R3 contains the 64-bits of packed data, divided up, in this example, into eight data elements. Register R4 contains the packed mask operand, with eight mask elements, x0-x7, corresponding to the eight data elements of R3.
- In the first group of instructions, the code sequence determines the predicate value using the tbit instruction. In this embodiment, the tbit tests the most significant bit of the packed mask element x0. If the bit is 1, then the predicate p1 will be set to true, else the predicate p1 will be set to false. An alternative embodiment could set predicate p1 equal to true is the bit value was 0 and, conversely, set p1 equal to false if the bit value was 1. It should be understood that the tbit instruction could test any bit of the corresponding packed mask element.
- In the second group of instructions, the previously stored predication value is used to conditionally store, in this example, one byte to the storage location associated with the value in R4. Also during the second group of instructions, R2 is incremented, R3 is shifted eight bits to the right, and the predicate p1 is reset in the same manner as the first group of instructions except the packed mask element x1 is used instead x0. Multiple parallel processing units allows for the parallel processing of all 4 instructions in the second group of instructions in the same clock cycle(s). The third through the seventh group of instructions continue in the same manner as the second group of instructions, except that each group of instructions uses a different packed mask element. The ninth group of instructions uses predication to conditionally store the last byte to the storage location associated with the value in R4. In this example, the sequence takes 9 clock cycles. However, the amount of clock cycles can vary with the implementation of the processor and/or the number of data elements of the packed data operand.
- Accordingly, the invention does not require the use of specialized SIMD Byte Mask Write circuitry. Rather, the use of predication allows for the avoidance of conditional branches, and therefore performance loss due to branch misprediction. The multiple parallel processing units allow for improved processor throughput (e.g., one embodiment of the invention has the required number of parallel processing units to process the instructions of each group above in parallel). This parallelism and predication allows the invention to have comparable performance to a specialized SIMD circuitry implementation of the Byte Mask Write. Moreover, the instructions in Table 1, and thus the circuitry in the processor to support them, are used for many purposes, as compared to the specialized/dedicated byte mask write instruction circuitry which has a much narrower field of use (e.g., graphics processing).
- The invention may be implemented at various levels in the processing system. For example, based on the processor architecture, the above code sequence could be manually coded and provided to the processor, generated by a compiler compiling a single instruction, generated by a decoder in the processor responsive to receiving a single instruction, etc.
- FIG. 4 is a diagram illustrating a selected portion of a computer system in accordance with one embodiment of the invention. The select portion of the computer system comprises the
processor 410, thestorage device 420, and the bus 415. Theprocessor 410 in FIG. 4 contains additional circuitry, which is not necessary to understanding the invention. - The
processor 410 is designed to execute two different instruction sets (e.g., a 64-bit instruction set and a 32-bit instruction set). The term macroinstruction is used herein to refer to an instruction externally received by the processor. In one particular embodiment, thedecoder 416 is used for decoding instructions from a first of theinstruction sets 410 into control signals and/or microcode entry points. In this case, the instructions from thefirst instruction set 410, when externally received by theprocessor 410, are macroinstructions. In addition, themicrocode converter 417 is used for converting instructions from the second instruction set 420 (e.g., IA32 Intel Architecture instructions) into the instructions from thefirst instruction set 410, which are then processed by thedecoder 416. In other words, at least certain of the macroinstructions from thesecond instruction set 420 are converted into a first level microcode made up of instructions from thefirst instruction set 410. In this case, the instructions from thefirst instruction set 410, when generated internally to theprocessor 410, are microinstructions. In one embodiment, the conversion is accomplished using a microcode ROM. For example, in one embodiment, a single SIMD Byte Mask Write macroinstruction may be provided to themicrocode converter 417 where it is converted to the appropriate instructions from the first instruction set 410 (here acting as microinstructions) for selectively writing data elements from packed data based upon a mask using predication. In addition, the same instructions from thefirst instruction set 410 for selectively writing data elements could be received as macroinstructions directly by thedecoder 416. - This invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident to persons having the benefit of this disclosure that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (8)
1. A computer-implemented method for selectively writing each data element from a packed data operand into a corresponding storage location comprising:
in response to a plurality of instructions, performing the following for each data element of said packed data operand,
determining a predicate value for said data element from one or more bits of a corresponding packed data mask element indicating whether said data element is selected for writing to said corresponding storage location; and
storing in said corresponding storage location the selected data element based on said predicate value.
2. The method of claim 1 , wherein the following is also performed for each data element of said packed data operand:
shifting said packed data operand by one data element.
3. The method of claim 1 , wherein said predicate value is determined by using a test bit instruction.
4. The method of claim 1 , wherein the acts are performed in response to a single macroinstruction from which said plurality of instructions have been produced.
5. The method of claim 4 , wherein said macroinstruction is part of a first instruction set separate and different from a second instruction set including said plurality of instructions, wherein instructions from said second instruction set can be received directly by said processor.
6. The method of claim 1 , wherein said plurality of instructions are microinstructions.
7. The method of claim 1 , wherein said plurality of instructions are macroinstructions.
8. The method of claim 1 preliminarily comprising:
translating a single instruction into said plurality of instructions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/279,553 US20030046520A1 (en) | 1999-09-20 | 2002-10-23 | Selective writing of data elements from packed data based upon a mask using predication |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/399,612 US6484255B1 (en) | 1999-09-20 | 1999-09-20 | Selective writing of data elements from packed data based upon a mask using predication |
US10/279,553 US20030046520A1 (en) | 1999-09-20 | 2002-10-23 | Selective writing of data elements from packed data based upon a mask using predication |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/399,612 Continuation US6484255B1 (en) | 1999-09-20 | 1999-09-20 | Selective writing of data elements from packed data based upon a mask using predication |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030046520A1 true US20030046520A1 (en) | 2003-03-06 |
Family
ID=23580223
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/399,612 Expired - Lifetime US6484255B1 (en) | 1999-09-20 | 1999-09-20 | Selective writing of data elements from packed data based upon a mask using predication |
US10/279,553 Abandoned US20030046520A1 (en) | 1999-09-20 | 2002-10-23 | Selective writing of data elements from packed data based upon a mask using predication |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/399,612 Expired - Lifetime US6484255B1 (en) | 1999-09-20 | 1999-09-20 | Selective writing of data elements from packed data based upon a mask using predication |
Country Status (8)
Country | Link |
---|---|
US (2) | US6484255B1 (en) |
JP (1) | JP4921665B2 (en) |
CN (1) | CN100440138C (en) |
AU (1) | AU6945400A (en) |
DE (1) | DE10085391T1 (en) |
GB (1) | GB2371135B (en) |
HK (1) | HK1044202B (en) |
WO (1) | WO2001022216A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080222444A1 (en) * | 2007-03-09 | 2008-09-11 | Analog Devices, Inc. | Variable instruction width software programmable data pattern generator |
US11537398B2 (en) | 2006-09-22 | 2022-12-27 | Intel Corporation | Instruction and logic for processing text strings |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6484255B1 (en) * | 1999-09-20 | 2002-11-19 | Intel Corporation | Selective writing of data elements from packed data based upon a mask using predication |
JP3964593B2 (en) * | 2000-02-24 | 2007-08-22 | 富士通株式会社 | Semiconductor memory device |
US7155601B2 (en) * | 2001-02-14 | 2006-12-26 | Intel Corporation | Multi-element operand sub-portion shuffle instruction execution |
US7861071B2 (en) * | 2001-06-11 | 2010-12-28 | Broadcom Corporation | Conditional branch instruction capable of testing a plurality of indicators in a predicate register |
US20040054877A1 (en) | 2001-10-29 | 2004-03-18 | Macy William W. | Method and apparatus for shuffling data |
US7624138B2 (en) | 2001-10-29 | 2009-11-24 | Intel Corporation | Method and apparatus for efficient integer transform |
US7631025B2 (en) * | 2001-10-29 | 2009-12-08 | Intel Corporation | Method and apparatus for rearranging data between multiple registers |
US7818356B2 (en) | 2001-10-29 | 2010-10-19 | Intel Corporation | Bitstream buffer manipulation with a SIMD merge instruction |
US7685212B2 (en) * | 2001-10-29 | 2010-03-23 | Intel Corporation | Fast full search motion estimation with SIMD merge instruction |
US7725521B2 (en) * | 2001-10-29 | 2010-05-25 | Intel Corporation | Method and apparatus for computing matrix transformations |
US7739319B2 (en) * | 2001-10-29 | 2010-06-15 | Intel Corporation | Method and apparatus for parallel table lookup using SIMD instructions |
JP3773195B2 (en) * | 2002-10-25 | 2006-05-10 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Memory module, information processing apparatus, initial setting method for memory module, and program |
US7275149B1 (en) * | 2003-03-25 | 2007-09-25 | Verisilicon Holdings (Cayman Islands) Co. Ltd. | System and method for evaluating and efficiently executing conditional instructions |
US7395531B2 (en) | 2004-06-07 | 2008-07-01 | International Business Machines Corporation | Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements |
US7475392B2 (en) * | 2004-06-07 | 2009-01-06 | International Business Machines Corporation | SIMD code generation for loops with mixed data lengths |
US8549501B2 (en) | 2004-06-07 | 2013-10-01 | International Business Machines Corporation | Framework for generating mixed-mode operations in loop-level simdization |
US7478377B2 (en) * | 2004-06-07 | 2009-01-13 | International Business Machines Corporation | SIMD code generation in the presence of optimized misaligned data reorganization |
US7367026B2 (en) * | 2004-06-07 | 2008-04-29 | International Business Machines Corporation | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization |
US7386842B2 (en) * | 2004-06-07 | 2008-06-10 | International Business Machines Corporation | Efficient data reorganization to satisfy data alignment constraints |
US7480787B1 (en) * | 2006-01-27 | 2009-01-20 | Sun Microsystems, Inc. | Method and structure for pipelining of SIMD conditional moves |
US8156310B2 (en) * | 2006-09-11 | 2012-04-10 | International Business Machines Corporation | Method and apparatus for data stream alignment support |
US20080071851A1 (en) * | 2006-09-20 | 2008-03-20 | Ronen Zohar | Instruction and logic for performing a dot-product operation |
US20080077772A1 (en) * | 2006-09-22 | 2008-03-27 | Ronen Zohar | Method and apparatus for performing select operations |
US9529592B2 (en) | 2007-12-27 | 2016-12-27 | Intel Corporation | Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation |
US8078836B2 (en) | 2007-12-30 | 2011-12-13 | Intel Corporation | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits |
BR112014004603A2 (en) * | 2011-09-26 | 2017-06-13 | Intel Corp | instruction and logic for providing step-masking functionality and vector loads and stores |
WO2013077884A1 (en) * | 2011-11-25 | 2013-05-30 | Intel Corporation | Instruction and logic to provide conversions between a mask register and a general purpose register or memory |
US9336000B2 (en) * | 2011-12-23 | 2016-05-10 | Intel Corporation | Instruction execution unit that broadcasts data values at different levels of granularity |
WO2013095618A1 (en) | 2011-12-23 | 2013-06-27 | Intel Corporation | Instruction execution that broadcasts and masks data values at different levels of granularity |
WO2013095604A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing mask bit compression |
CN107967149B (en) * | 2011-12-23 | 2021-12-10 | 英特尔公司 | System, apparatus and method for setting an output mask in a destination writemask register from a source writemask register |
WO2013095599A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a double blocked sum of absolute differences |
CN104011652B (en) * | 2011-12-30 | 2017-10-27 | 英特尔公司 | packing selection processor, method, system and instruction |
US9304771B2 (en) * | 2013-02-13 | 2016-04-05 | International Business Machines Corporation | Indirect instruction predication |
US9990202B2 (en) * | 2013-06-28 | 2018-06-05 | Intel Corporation | Packed data element predication processors, methods, systems, and instructions |
US9612840B2 (en) * | 2014-03-28 | 2017-04-04 | Intel Corporation | Method and apparatus for implementing a dynamic out-of-order processor pipeline |
US10133570B2 (en) * | 2014-09-19 | 2018-11-20 | Intel Corporation | Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4141005A (en) * | 1976-11-11 | 1979-02-20 | International Business Machines Corporation | Data format converting apparatus for use in a digital data processor |
US4217638A (en) * | 1977-05-19 | 1980-08-12 | Tokyo Shibaura Electric Co., Ltd. | Data-processing apparatus and method |
US4656581A (en) * | 1983-10-20 | 1987-04-07 | Nec Corporation | Vector mask control system |
US5249266A (en) * | 1985-10-22 | 1993-09-28 | Texas Instruments Incorporated | Data processing apparatus with self-emulation capability |
US5383154A (en) * | 1992-03-04 | 1995-01-17 | Nec Corporation | Memory circuit capable of executing a bit manipulation at a high speed |
US5423010A (en) * | 1992-01-24 | 1995-06-06 | C-Cube Microsystems | Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words |
US5467413A (en) * | 1993-05-20 | 1995-11-14 | Radius Inc. | Method and apparatus for vector quantization for real-time playback on low cost personal computers |
US5630075A (en) * | 1993-12-30 | 1997-05-13 | Intel Corporation | Write combining buffer for sequentially addressed partial line operations originating from a single instruction |
US5751982A (en) * | 1995-03-31 | 1998-05-12 | Apple Computer, Inc. | Software emulation system with dynamic translation of emulated instructions for increased processing speed |
US5784607A (en) * | 1996-03-29 | 1998-07-21 | Integrated Device Technology, Inc. | Apparatus and method for exception handling during micro code string instructions |
US5991531A (en) * | 1997-02-24 | 1999-11-23 | Samsung Electronics Co., Ltd. | Scalable width vector processor architecture for efficient emulation |
US5996066A (en) * | 1996-10-10 | 1999-11-30 | Sun Microsystems, Inc. | Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions |
US6052769A (en) * | 1998-03-31 | 2000-04-18 | Intel Corporation | Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction |
US6173393B1 (en) * | 1998-03-31 | 2001-01-09 | Intel Corporation | System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data |
US20020002666A1 (en) * | 1998-10-12 | 2002-01-03 | Carole Dulong | Conditional operand selection using mask operations |
US6484255B1 (en) * | 1999-09-20 | 2002-11-19 | Intel Corporation | Selective writing of data elements from packed data based upon a mask using predication |
US7480787B1 (en) * | 2006-01-27 | 2009-01-20 | Sun Microsystems, Inc. | Method and structure for pipelining of SIMD conditional moves |
US20090172365A1 (en) * | 2007-12-27 | 2009-07-02 | Doron Orenstien | Instructions and logic to perform mask load and store operations |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59135548A (en) | 1983-01-22 | 1984-08-03 | Toshiba Corp | Arithmetic device |
JPS6059469A (en) * | 1983-09-09 | 1985-04-05 | Nec Corp | Vector processor |
JPH0812660B2 (en) * | 1989-02-02 | 1996-02-07 | 日本電気株式会社 | Vector data processor |
US5680332A (en) | 1995-10-30 | 1997-10-21 | Motorola, Inc. | Measurement of digital circuit simulation test coverage utilizing BDDs and state bins |
JP2806346B2 (en) * | 1996-01-22 | 1998-09-30 | 日本電気株式会社 | Arithmetic processing unit |
JPH1153189A (en) * | 1997-07-31 | 1999-02-26 | Toshiba Corp | Operation unit, operation method and recording medium readable by computer |
US6067617A (en) | 1998-04-07 | 2000-05-23 | International Business Machines Corporation | Specialized millicode instructions for packed decimal division |
US6098087A (en) * | 1998-04-23 | 2000-08-01 | Infineon Technologies North America Corp. | Method and apparatus for performing shift operations on packed data |
DE69930893T2 (en) | 1998-06-25 | 2006-11-16 | Texas Instruments Inc., Dallas | Digital signal processor for data with large bit length |
-
1999
- 1999-09-20 US US09/399,612 patent/US6484255B1/en not_active Expired - Lifetime
-
2000
- 2000-08-29 JP JP2001525517A patent/JP4921665B2/en not_active Expired - Lifetime
- 2000-08-29 CN CNB008159319A patent/CN100440138C/en not_active Expired - Lifetime
- 2000-08-29 DE DE10085391T patent/DE10085391T1/en not_active Ceased
- 2000-08-29 WO PCT/US2000/023721 patent/WO2001022216A1/en active Application Filing
- 2000-08-29 AU AU69454/00A patent/AU6945400A/en not_active Abandoned
- 2000-08-29 GB GB0208629A patent/GB2371135B/en not_active Expired - Lifetime
-
2002
- 2002-07-27 HK HK02105537.7A patent/HK1044202B/en not_active IP Right Cessation
- 2002-10-23 US US10/279,553 patent/US20030046520A1/en not_active Abandoned
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4141005A (en) * | 1976-11-11 | 1979-02-20 | International Business Machines Corporation | Data format converting apparatus for use in a digital data processor |
US4217638A (en) * | 1977-05-19 | 1980-08-12 | Tokyo Shibaura Electric Co., Ltd. | Data-processing apparatus and method |
US4656581A (en) * | 1983-10-20 | 1987-04-07 | Nec Corporation | Vector mask control system |
US5249266A (en) * | 1985-10-22 | 1993-09-28 | Texas Instruments Incorporated | Data processing apparatus with self-emulation capability |
US5423010A (en) * | 1992-01-24 | 1995-06-06 | C-Cube Microsystems | Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words |
US5383154A (en) * | 1992-03-04 | 1995-01-17 | Nec Corporation | Memory circuit capable of executing a bit manipulation at a high speed |
US5467413A (en) * | 1993-05-20 | 1995-11-14 | Radius Inc. | Method and apparatus for vector quantization for real-time playback on low cost personal computers |
US5630075A (en) * | 1993-12-30 | 1997-05-13 | Intel Corporation | Write combining buffer for sequentially addressed partial line operations originating from a single instruction |
US5751982A (en) * | 1995-03-31 | 1998-05-12 | Apple Computer, Inc. | Software emulation system with dynamic translation of emulated instructions for increased processing speed |
US5784607A (en) * | 1996-03-29 | 1998-07-21 | Integrated Device Technology, Inc. | Apparatus and method for exception handling during micro code string instructions |
US5996066A (en) * | 1996-10-10 | 1999-11-30 | Sun Microsystems, Inc. | Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions |
US5991531A (en) * | 1997-02-24 | 1999-11-23 | Samsung Electronics Co., Ltd. | Scalable width vector processor architecture for efficient emulation |
US6052769A (en) * | 1998-03-31 | 2000-04-18 | Intel Corporation | Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction |
US6173393B1 (en) * | 1998-03-31 | 2001-01-09 | Intel Corporation | System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data |
US20020002666A1 (en) * | 1998-10-12 | 2002-01-03 | Carole Dulong | Conditional operand selection using mask operations |
US6484255B1 (en) * | 1999-09-20 | 2002-11-19 | Intel Corporation | Selective writing of data elements from packed data based upon a mask using predication |
US7480787B1 (en) * | 2006-01-27 | 2009-01-20 | Sun Microsystems, Inc. | Method and structure for pipelining of SIMD conditional moves |
US20090172365A1 (en) * | 2007-12-27 | 2009-07-02 | Doron Orenstien | Instructions and logic to perform mask load and store operations |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11537398B2 (en) | 2006-09-22 | 2022-12-27 | Intel Corporation | Instruction and logic for processing text strings |
US20080222444A1 (en) * | 2007-03-09 | 2008-09-11 | Analog Devices, Inc. | Variable instruction width software programmable data pattern generator |
US8732440B2 (en) * | 2007-03-09 | 2014-05-20 | Analog Devices, Inc. | Data pattern generator with selectable programmable outputs |
Also Published As
Publication number | Publication date |
---|---|
CN100440138C (en) | 2008-12-03 |
GB2371135B (en) | 2004-03-31 |
WO2001022216A1 (en) | 2001-03-29 |
DE10085391T1 (en) | 2002-12-12 |
HK1044202A1 (en) | 2002-10-11 |
GB2371135A (en) | 2002-07-17 |
JP2003510682A (en) | 2003-03-18 |
CN1391668A (en) | 2003-01-15 |
US6484255B1 (en) | 2002-11-19 |
AU6945400A (en) | 2001-04-24 |
HK1044202B (en) | 2004-12-03 |
GB0208629D0 (en) | 2002-05-22 |
JP4921665B2 (en) | 2012-04-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6484255B1 (en) | Selective writing of data elements from packed data based upon a mask using predication | |
US6356994B1 (en) | Methods and apparatus for instruction addressing in indirect VLIW processors | |
US7584343B2 (en) | Data reordering processor and method for use in an active memory device | |
JP4986431B2 (en) | Processor | |
US6401190B1 (en) | Parallel computing units having special registers storing large bit widths | |
JP2019032859A (en) | Systems, apparatuses and methods for blending two source operands into single destination using writemask | |
EP0426393A2 (en) | Instructing method and execution system | |
US5561808A (en) | Asymmetric vector multiprocessor composed of a vector unit and a plurality of scalar units each having a different architecture | |
US20110307687A1 (en) | In-lane vector shuffle instructions | |
US20020002666A1 (en) | Conditional operand selection using mask operations | |
US7574583B2 (en) | Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor | |
US5119324A (en) | Apparatus and method for performing arithmetic functions in a computer system | |
US7133040B1 (en) | System and method for performing an insert-extract instruction | |
US6542989B2 (en) | Single instruction having op code and stack control field | |
US6026486A (en) | General purpose processor having a variable bitwidth | |
US7047396B1 (en) | Fixed length memory to memory arithmetic and architecture for a communications embedded processor system | |
US7093107B2 (en) | Bypass circuitry for use in a pipelined processor | |
KR100309861B1 (en) | Microprocessor, operation process execution method and recording medium | |
US7757066B2 (en) | System and method for executing variable latency load operations in a date processor | |
US7024540B2 (en) | Methods and apparatus for establishing port priority functions in a VLIW processor | |
JP2004510248A (en) | FIFO write / LIFO read trace buffer with software and hardware loop compression | |
US6922773B2 (en) | System and method for encoding constant operands in a wide issue processor | |
US6307553B1 (en) | System and method for performing a MOVHPS-MOVLPS instruction | |
US8395630B2 (en) | Format conversion apparatus from band interleave format to band separate format | |
JP3844465B2 (en) | Overriding the event vector table |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |