US20030030078A1 - MOS transistor having aluminum nitrade gate structure and method of manufacturing same - Google Patents
MOS transistor having aluminum nitrade gate structure and method of manufacturing same Download PDFInfo
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- US20030030078A1 US20030030078A1 US10/265,867 US26586702A US2003030078A1 US 20030030078 A1 US20030030078 A1 US 20030030078A1 US 26586702 A US26586702 A US 26586702A US 2003030078 A1 US2003030078 A1 US 2003030078A1
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- aluminum nitride
- substrate
- mos transistor
- silicon substrate
- gate
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- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910052782 aluminium Inorganic materials 0.000 title description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 77
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 74
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 37
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 239000000377 silicon dioxide Substances 0.000 description 9
- 230000008901 benefit Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 210000004180 plasmocyte Anatomy 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000002524 electron diffraction data Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Definitions
- the present invention relates to metal-oxide-silicon (MOS) transistors, and more particularly, to improved materials for use as gate structures of MOS transistors.
- MOS metal-oxide-silicon
- FIG. 1 illustrates a conventional MOS transistor 10 comprising a silicon substrate 12 , a source 14 , a drain 18 , and a gate 22 .
- the MOS transistor 10 further comprises a substrate electrode 26 , a source electrode 16 , a drain electrode 20 , and a gate electrode 24 formed on the substrate 12 , the source 14 , the drain 18 , and the gate 22 , respectively.
- Electrical connection to the substrate electrode 26 , the source electrode 16 , the drain electrode 20 , and the gate electrode 20 is via a substrate terminal B, a source terminal S, a drain terminal D, and a gate terminal G, respectively.
- the silicon substrate 12 can be either p-type (as shown) or n-type, and the source 14 and drain 18 can be n + -type (as shown) or p + -type depending on the conductivity of the substrate 12 .
- carriers enter the MOS transistor 10 through the source terminal S, leave through the drain terminal D, and are subject to the control of the action of signals applied to the gate electrode G.
- the voltage applied to the gate terminal G relative to ground is V G while the voltage applied to the drain electrode D relative to ground is V D .
- the material used for the gate 22 is silicon dioxide (SiO 2 ).
- SiO 2 silicon dioxide
- MOS transistors incorporating such thin gate structures will suffer from excess leakage, which could result in device failure.
- the present invention is directed to a gate dielectric material for an MOS transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
- the invention provides an MOS transistor comprising a substrate, a source, a drain, and a gate, wherein the gate comprises aluminum nitride.
- the invention also provider a method of making an MOS transistor comprising forming a source and drain in a substrate and forming a gate on the substrate, wherein the gate comprises aluminum nitride.
- the invention also provides a method of forming an aluminum nitride film on a silicon substrate comprising epitaxially growing aluminum nitride on the silicon substrate at a substrate temperature of about 600° C., and subsequently annealing the substrate and epitaxially grown aluminum nitride at a substrate temperature of about 950° C.
- FIG. 1 is a cross-sectional view of a conventional MOS transistor
- FIG. 2 is a cross-sectional view of an MOS transistor according to the present invention.
- FIG. 2 An MOS transistor according to the present invention is shown in FIG. 2 and is designated generally by reference numeral 100 .
- the MOS transistor 100 comprise a silicon substrate 110 , a source 120 , a drain 140 , and a gate 160 .
- the MOS transistor 100 further comprises a substrate electrode 110 , a source electrode 130 , a drain electrode 150 , and a gate electrode 170 formed on the substrate 110 , the source 120 , the drain 140 , and the gate 160 , respectively. Electrical connection to the substrate electrode 110 , the source electrode 130 , the drain electrode 150 , and the gate electrode 170 is via a substrate terminal B, a source terminal S, a drain terminal D, and a gate terminal G, respectively.
- the MOS transistor 100 is similar to the MOS transistor 10 of FIG. 1 except that the material used for the gate 160 is aluminum nitride (AlN).
- AlN has certain advantages over the use of SiO 2 for the gate material of the MOS transistor 10 .
- AlN has a higher dielectric constant than SiO 2 (AlN has a dielectric constant of about 9, while SiO 2 has a dielectric constant of only about 4)
- the gate 160 can be made proportionally thicker than the gate 22 in the same applications.
- the use of AlN for the gate 160 allows for a physically thicker film to act as a tunnel barrier, yet provides the same effective thickness from the point of view of capacitance.
- the AlN gate 160 serves as a better diffusion barrier for substrate dopants (e.g., doped polysilicon, metal silicide, or metal), especially when the AlN gate 160 is grown epitaxially as described below.
- substrate dopants e.g., doped polysilicon, metal silicide, or metal
- the larger bandgap of the AlN gate 160 offers the benefit of lower leakage current through the gate 160 .
- the gate 160 of MOS transistor 100 is fabricated using an epitaxial growth technique, such as molecular beam epitaxy (MBE).
- MBE molecular beam epitaxy
- One advantage of fabricating the gate 160 using epitaxial growth is that a high quality, single crystalline AlN film can be obtained and the thickness of the gate 160 can be accurately controlled.
- epitaxial growth results in the gate 160 having a low defect density.
- epitaxial growth produces a good lattice match between the gate 160 and the substrate 110 resulting in a reduction of interfacial traps (also referred to as surface states or interface states) at the gate 160 /substrate 110 interfaces.
- interfacial traps in Si/dielectric structures are the result of dangling bonds at the interface between the atoms of the Si and the dielectric.
- the interface is between crystalline Si and amorphous SiO 2 . This could theoretically lead to one dangling bond per atom, or 6 ⁇ 10 14 cm ⁇ 2 interfacial traps.
- interfacial trap levels of 10 10 cm ⁇ 2 are found experimentally for what is considered by those skilled in the art to be “good” thermal SiO 2 on Si.
- AlN/Si structures both materials are crystalline and further they share an epitaxial relationship.
- the only opportunities for dangling bonds are those due to the 1 to 1.18 lattice mismatch between the AlN and Si. Accordingly, the theoretically maximum number of interfacial traps is reduced by at least a factor of about 5 2 or 25. This reduction of interfacial traps allows for lower and better control of the threshold voltages applied to the MOS transistor 100 .
- the substrate was first prepared by cleaning in HF and blown dry with N 2 gas and then loaded into the load lock of the MBE machine.
- the substrate was next baked at 450° C. in a vacuum and transferred to the MBE machine growth chamber where it was heated to 900° C. to evaporate residual surface contaminants and oxides. Evaporation of the residual surface contaminants and oxides was verified by examining the reflected electron diffraction pattern produced by a 15 keV electron beam incident to the substrate surface at about a 1° grating angle.
- the substrate temperature was allowed to lower until it reached about 600° C., whereupon the shutter from the aluminum effusion cell was opened. Two seconds later, the shutter from the nitrogen rf plasma cell was opened.
- the aluminum effusion cell was comprised of a conventional tantalum furnace that heated a pyrolytic boron nitride crucible containing molten aluminum. The temperature was calibrated in previous experiments to produce a flux of aluminum atoms sufficient to provide an AlN growth rate of about 0.1 monolayer per second.
- the rf plasma cell model had a N 2 gas flow rate of 0.75 sccm/minute and was operated in the bright-optical mode with 450 watts of net absorbed rf power at 13.5 MHz.
- the base pressure of the growth chamber was about 10 ⁇ 10 torr
- the aluminum flux had a beam equivalent pressure of about 1 ⁇ 10 ⁇ 8 torr
- the nitrogen rf plasma flux had a beam equivalent pressure of about 5 ⁇ 10 ⁇ 5 torr.
- the deposition process was stopped and the substrate temperature was raised to about 950° C. for about a 10-minute anneal. It was found that the deposition at low temperature (about 600° C.) suppressed any tendency for the AlN to form islands, thus insuring a smooth, uniform and continuous film on the substrate. Further, it was found that the 950° C. anneal after growth allowed the aluminum and nitrogen atoms to diffuse over short distances to improve the epitaxial stacking.
- the AlN films were ⁇ -phase hexagonal AlN epitaxially grown with a nominal 18% lattice mismatch to the (111) silicon substrates.
- the ⁇ -phase crystalline form of cubic or zincblend AlN can be grown on silicon if a (100) or (110) silicon substrate is substituted for the (111) silicon substrate in the above examples.
- the cubic AlN to silicon lattice mismatch would at 18%, but possible problems with polarization induced electric fields would be suppressed by the cubic symmetry.
Abstract
Description
- This application claims priority to U.S. Provisional Patent Application No.60/______, filed Jan.__, 1999, which provisional application is incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates to metal-oxide-silicon (MOS) transistors, and more particularly, to improved materials for use as gate structures of MOS transistors.
- 2. Description of the Related Art
- MOS transistors have been a dominant technology in the silicon industry. FIG. 1 illustrates a
conventional MOS transistor 10 comprising asilicon substrate 12, asource 14, adrain 18, and agate 22. TheMOS transistor 10 further comprises asubstrate electrode 26, asource electrode 16, adrain electrode 20, and agate electrode 24 formed on thesubstrate 12, thesource 14, thedrain 18, and thegate 22, respectively. Electrical connection to thesubstrate electrode 26, thesource electrode 16, thedrain electrode 20, and thegate electrode 20 is via a substrate terminal B, a source terminal S, a drain terminal D, and a gate terminal G, respectively. - As is known to those skilled in the art, the
silicon substrate 12 can be either p-type (as shown) or n-type, and thesource 14 anddrain 18 can be n+-type (as shown) or p+-type depending on the conductivity of thesubstrate 12. As is also known to those skilled in the art, carriers enter theMOS transistor 10 through the source terminal S, leave through the drain terminal D, and are subject to the control of the action of signals applied to the gate electrode G. The voltage applied to the gate terminal G relative to ground is VG while the voltage applied to the drain electrode D relative to ground is VD. It should be understood that many variations of the foregoing structure are well know to those skilled in the art and the foregoing structure is meant to be illustrative and not limiting. - As shown in FIG. 1, the material used for the
gate 22 is silicon dioxide (SiO2). There are certain disadvantages, however, associated with using such a gate material. In particular, in response to various market demands, the level of integration of MOS transistor based integrated circuit devices continues to increase. As a result, the size of MOS transistors in those devices decreases. In addition, in order to lower the power density consumed by the devices, the gate voltage VG is lowered accordingly. This leads to a need for thinner gate structures. It is contemplated that in order to meet future performance demands, conventional MOS transistors will be required to have gate thickness that are well below the tunneling limit of SiO2. MOS transistors incorporating such thin gate structures will suffer from excess leakage, which could result in device failure. - Accordingly, the present invention is directed to a gate dielectric material for an MOS transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
- Additional features and advantages of the invention will be set forth in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the gate dielectric material particularly pointed out in the written description and claims hereof as well as the appended drawings.
- To achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described, the invention provides an MOS transistor comprising a substrate, a source, a drain, and a gate, wherein the gate comprises aluminum nitride.
- To further achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described, the invention also provider a method of making an MOS transistor comprising forming a source and drain in a substrate and forming a gate on the substrate, wherein the gate comprises aluminum nitride.
- To still further achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described, the invention also provides a method of forming an aluminum nitride film on a silicon substrate comprising epitaxially growing aluminum nitride on the silicon substrate at a substrate temperature of about 600° C., and subsequently annealing the substrate and epitaxially grown aluminum nitride at a substrate temperature of about 950° C.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and, together with the written description, serve to explain the principles of the invention. In the drawings:
- FIG. 1 is a cross-sectional view of a conventional MOS transistor; and
- FIG. 2 is a cross-sectional view of an MOS transistor according to the present invention.
- Reference will now be made in detail to the presently preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings.
- An MOS transistor according to the present invention is shown in FIG. 2 and is designated generally by
reference numeral 100. As embodied herein, theMOS transistor 100 comprise asilicon substrate 110, asource 120, adrain 140, and agate 160. TheMOS transistor 100 further comprises asubstrate electrode 110, asource electrode 130, adrain electrode 150, and agate electrode 170 formed on thesubstrate 110, thesource 120, thedrain 140, and thegate 160, respectively. Electrical connection to thesubstrate electrode 110, thesource electrode 130, thedrain electrode 150, and thegate electrode 170 is via a substrate terminal B, a source terminal S, a drain terminal D, and a gate terminal G, respectively. It should be appreciated that theMOS transistor 100 is similar to theMOS transistor 10 of FIG. 1 except that the material used for thegate 160 is aluminum nitride (AlN). - It should be appreciated that the use of AlN for the gate material of the
MOS transistor 100 has certain advantages over the use of SiO2 for the gate material of theMOS transistor 10. First, because AlN has a higher dielectric constant than SiO2 (AlN has a dielectric constant of about 9, while SiO2 has a dielectric constant of only about 4), thegate 160 can be made proportionally thicker than thegate 22 in the same applications. Thus, the use of AlN for thegate 160 allows for a physically thicker film to act as a tunnel barrier, yet provides the same effective thickness from the point of view of capacitance. Second, when compared to the SiO2 gate of theMOS transistor 10, theAlN gate 160 serves as a better diffusion barrier for substrate dopants (e.g., doped polysilicon, metal silicide, or metal), especially when theAlN gate 160 is grown epitaxially as described below. Third, when compared to the SiO2gate 22, the larger bandgap of the AlN gate 160 (the bandgap of AlN is about 6 eV, while the bandgap for AlN is about 11 eV) offers the benefit of lower leakage current through thegate 160. - Preferably, the
gate 160 ofMOS transistor 100 is fabricated using an epitaxial growth technique, such as molecular beam epitaxy (MBE). One advantage of fabricating thegate 160 using epitaxial growth is that a high quality, single crystalline AlN film can be obtained and the thickness of thegate 160 can be accurately controlled. With regard to the quality of thegate 160, epitaxial growth results in thegate 160 having a low defect density. Furthermore, epitaxial growth produces a good lattice match between thegate 160 and thesubstrate 110 resulting in a reduction of interfacial traps (also referred to as surface states or interface states) at thegate 160/substrate 110 interfaces. As is know to those skilled in the art, interfacial traps in Si/dielectric structures are the result of dangling bonds at the interface between the atoms of the Si and the dielectric. In the case of Si/SiO2 structures, the interface is between crystalline Si and amorphous SiO2. This could theoretically lead to one dangling bond per atom, or 6×1014 cm−2 interfacial traps. Indeed, interfacial trap levels of 1010 cm−2 are found experimentally for what is considered by those skilled in the art to be “good” thermal SiO2 on Si. In the case of AlN/Si structures, however, both materials are crystalline and further they share an epitaxial relationship. Thus, the only opportunities for dangling bonds are those due to the 1 to 1.18 lattice mismatch between the AlN and Si. Accordingly, the theoretically maximum number of interfacial traps is reduced by at least a factor of about 52 or 25. This reduction of interfacial traps allows for lower and better control of the threshold voltages applied to theMOS transistor 100. - Using a Gem II MBE machine made by EPI Products Co., Eden Prairie, Minn., 10-100 Å thick AlN films were grown on (111) silicon substrates, each under the following conditions.
- The substrate was first prepared by cleaning in HF and blown dry with N2 gas and then loaded into the load lock of the MBE machine. The substrate was next baked at 450° C. in a vacuum and transferred to the MBE machine growth chamber where it was heated to 900° C. to evaporate residual surface contaminants and oxides. Evaporation of the residual surface contaminants and oxides was verified by examining the reflected electron diffraction pattern produced by a 15 keV electron beam incident to the substrate surface at about a 1° grating angle.
- Inside the growth chamber, the substrate temperature was allowed to lower until it reached about 600° C., whereupon the shutter from the aluminum effusion cell was opened. Two seconds later, the shutter from the nitrogen rf plasma cell was opened. The aluminum effusion cell was comprised of a conventional tantalum furnace that heated a pyrolytic boron nitride crucible containing molten aluminum. The temperature was calibrated in previous experiments to produce a flux of aluminum atoms sufficient to provide an AlN growth rate of about 0.1 monolayer per second. The rf plasma cell model had a N2 gas flow rate of 0.75 sccm/minute and was operated in the bright-optical mode with 450 watts of net absorbed rf power at 13.5 MHz. The base pressure of the growth chamber was about 10−10 torr, the aluminum flux had a beam equivalent pressure of about 1×10−8 torr, and the nitrogen rf plasma flux had a beam equivalent pressure of about 5×10−5 torr.
- After an appropriate amount of AlN was deposited on the substrate to form a film of desired thickness (i.e., 10-100 Å), the deposition process was stopped and the substrate temperature was raised to about 950° C. for about a 10-minute anneal. It was found that the deposition at low temperature (about 600° C.) suppressed any tendency for the AlN to form islands, thus insuring a smooth, uniform and continuous film on the substrate. Further, it was found that the 950° C. anneal after growth allowed the aluminum and nitrogen atoms to diffuse over short distances to improve the epitaxial stacking.
- In the foregoing examples, the AlN films were α-phase hexagonal AlN epitaxially grown with a nominal 18% lattice mismatch to the (111) silicon substrates. However, the β-phase crystalline form of cubic or zincblend AlN can be grown on silicon if a (100) or (110) silicon substrate is substituted for the (111) silicon substrate in the above examples. In the case of the cubic form, the cubic AlN to silicon lattice mismatch would at 18%, but possible problems with polarization induced electric fields would be suppressed by the cubic symmetry.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the MOS transistor and method of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claim and their equivalents.
Claims (46)
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US10/265,867 US20030030078A1 (en) | 1999-01-26 | 2002-10-07 | MOS transistor having aluminum nitrade gate structure and method of manufacturing same |
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US11718699P | 1999-01-26 | 1999-01-26 | |
US09/472,331 US6495409B1 (en) | 1999-01-26 | 1999-12-23 | MOS transistor having aluminum nitride gate structure and method of manufacturing same |
US10/265,867 US20030030078A1 (en) | 1999-01-26 | 2002-10-07 | MOS transistor having aluminum nitrade gate structure and method of manufacturing same |
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US20040224459A1 (en) * | 1999-07-07 | 2004-11-11 | Matsushita Electric Industrial Co., Ltd. | Layered structure, method for manufacturing the same, and semiconductor element |
US20050146672A1 (en) * | 2003-12-23 | 2005-07-07 | Samsung Electronics Co., Ltd. | Method and apparatus for aligning ferroelectric liquid crystal device |
US20050272210A1 (en) * | 2004-06-08 | 2005-12-08 | Hynix Semiconductor Inc. | Method for manufacturing gate electrode of semiconductor device using aluminium nitride film |
US20060163569A1 (en) * | 2005-01-13 | 2006-07-27 | Samsung Electronics Co., Ltd. | Test structure of semiconductor device |
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