US20020180062A1 - Flip chip package of monolithic microwave integrated circuit - Google Patents
Flip chip package of monolithic microwave integrated circuit Download PDFInfo
- Publication number
- US20020180062A1 US20020180062A1 US09/927,564 US92756401A US2002180062A1 US 20020180062 A1 US20020180062 A1 US 20020180062A1 US 92756401 A US92756401 A US 92756401A US 2002180062 A1 US2002180062 A1 US 2002180062A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- metal strips
- mmic
- chip
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/8547—Zirconium (Zr) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the invention relates to a flip chip package of monolithic microwave integrated circuit (MMIC), and more particularly, to a flip chip package of MMIC that has optimum heat-dissipative characteristic, and that can reduce the effects of parasitic inductance and parasitic capacitance, for the application in micro-wave, millimeter-wave and radio-frequency.
- MMIC monolithic microwave integrated circuit
- FIG. 1 is a structural disposition of a microwave integrated circuit package according to a prior art.
- the microwave integrated circuit package structure disclosed in patent No. 69,402 of Taiwan, Republic of China includes a grounded potential metal surface 112 , an IC chip bonding part 113 , a slot-type via hole signal line 115 penetrating through the substrate, a coplanar waveguide input/output port (I/O port) 121 , and a plurality of circular via holes connecting the top and bottom metal surfaces of the substrate.
- the microwave integrated circuit package provides a grounded potential metal surface to perform signal transmission between each of the I/O ports and IC circuit.
- the material employed for the metal surface is any ones that can be performed wire bonding and are chemically stable.
- the metal surface is fabricated by making use of thick film or thin film or a common IC board's etching methods, and its attenuation is smaller than that of a micro-strip since it employs coplanar waveguide.
- FIG. 2 is a cross-sectional view of a microwave integrated circuit package according to another prior art.
- the prior art shown in FIG. 2 is a “small outline integrated circuit (SOIC) package” which is the most popular IC package technology nowadays.
- SOIC small outline integrated circuit
- FIG. 2 the steps for forming the SOIC package is described as follows. First of all, a chip 281 is adhered to the paddle 221 of the lead frame 282 by the surface mounting method. Afterwards, the wires 283 are bonded, and adhesive material 284 is applied to fix the package in position. The package is finally formed by mold injection with encapsulant 285 to protect against the intrusion of the moisture and the dust that might affect the electrical characteristic in order to improve the package reliability.
- encapsulant 285 to protect against the intrusion of the moisture and the dust that might affect the electrical characteristic in order to improve the package reliability.
- FIG. 3( a ) is a cross-sectional view of a microwave integrated circuit package according to one other prior art.
- the microwave integrated circuit package is disclosed in patent No. 93,511 of Taiwan, Republic of China.
- the microwave integrated circuit package includes an IC chip 363 and a substrate 361 .
- Wires 331 , 332 are employed to connect the I/O ports 341 , 342 of the IC to the I/O ports 321 , 322 of the substrate's top surface. They are further connected to the I/O ports 323 , 324 of the substrate's bottom surface through the via holes 315 , 316 at the left and right edges of the substrate.
- underfill material 390 is employed to cover the IC chip 363 and bonding wires 331 , 332 to fix the IC chip in position. Finally, the package is formed on the top of the underfill material 390 by mold injection with encapsulant 391 .
- FIG. 3( b ) is an isometric top view of a microwave integrated circuit package according to the one other prior art shown in FIG. 3( a ).
- the IC chip 416 is flipped over to have the surface, having signal and ground terminals, facing downward.
- metal strip 411 , 412 are widen such that the input signal terminal of the IC chip 416 can contact the metal strip 411 , the output signal terminal can contact the metal strip 412 , and the all the grounded terminals can contact the metal strip 415 .
- the portion covered by the IC chip 416 is performed etching to prevent the surface of the IC chip 416 from being short-circuited.
- an object of the invention is to have a package that can make use of the common surface-mounted technology (SMT) to undertake mass production so as to lower the production cost.
- the MMIC package of the invention includes a substrate, having an top surface and a bottom surface, and each of the surfaces is divided respectively into a periphery area and a central area; an integrated circuit chip (IC chip), having a first surface and a second surface, and each of the surfaces being divided respectively into a periphery area and a central area, and the MMIC package being made by flipping the IC chip to have its first surface covering on the top surface of the substrate, and the central area of the first surface having one or several active devices; a plurality of metal strips, positioned on the IC chip's first surface and disposed in the periphery area of the IC chip's first surface, and these metal strips being electrically connected to the active devices on the first surface of the IC chip; a plurality of solder bumps, implanted respectively on and being electrically connected to the first surface's metal strips of the pluralit
- a penetration hole is provided in the central areas of the top and bottom surfaces of the substrate for those high power packages that require optimum heat-dissipative effect. Moreover, the material removed by penetrating the penetration hole is replaced by filling a heat-dissipative material with relatively low dielectric constant and relatively low dielectric loss.
- FIG. 1 is a structural disposition of a microwave integrated circuit package according to a prior art.
- FIG. 2 is a cross-sectional view of a microwave integrated circuit package according to another prior art.
- FIG. 3( a ) is a cross-sectional view of a microwave integrated circuit package according to one other prior art.
- FIG. 3( b ) is an isometric top view of a microwave integrated circuit package according to the one other prior art shown in FIG. 3( a ).
- FIG. 4 is a flow chart showing the technical content and the fabrication process of the flip chip package of a monolithic microwave integrated circuit (MMIC) of the invention.
- MMIC monolithic microwave integrated circuit
- FIG. 5( a ) is an isometric top view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 5( b ) is a top view of the substrate's top surface of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 5( c ) is a bottom view of the substrate's bottom surface of an MMIC of the first embodiment of the invention.
- FIG. 5( d ) is a top view of the IC chip's bottom surface of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 6 is an isometric bottom view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 7 is a cross-sectional view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 8 is an isometric bottom view of a flip chip package of an MMIC of the second embodiment of the invention.
- FIG. 9 is a cross-sectional view of a flip chip package of an MMIC of the second embodiment of the invention.
- the flip chip packages of the monolithic microwave integrated circuit are classified into low power packages and high power packages depending on the required power in their field of application.
- the low power packages have their power less that one milli-Watt (mW) while the high power packages have their power greater that one milli-Watt (mW).
- high power packages require much better heat-dissipative package structure in order to improve the reliability since the high power packages contain MMIC that generates relatively high quantity of heat.
- the first embodiment of the invention is a low power package while the second embodiment of the invention is a high power package.
- FIG. 5( a ) is an isometric top view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 5( b ) is a top view of the substrate's top surface of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 5( c ) is a bottom view of the substrate's bottom surface of an MMIC of the first embodiment of the invention.
- FIG. 5( d ) is a top view of the IC chip's bottom surface of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 6 is an isometric bottom view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 7 is a cross-sectional view of a flip chip package of an MMIC of the first embodiment of the invention.
- the flip chip package of a monolithic microwave integrated circuit of the invention 4 includes a substrate 5 , an integrated circuit chip (IC chip) 6 .
- the substrate 5 has a top surface 501 and a bottom surface 502
- the IC chip 6 has a first surface 601 and a second surface 602 .
- the flip chip package of a monolithic microwave integrated circuit 4 also includes a plurality of first surface metal strips 641 , 642 , 643 , 644 , 645 , 646 , 647 , 648 , 649 , 650 , 671 , 672 , 673 of the IC chip 6 , and a plurality of solder bumps 531 , 532 , 533 , 534 , 535 , 536 , 537 , 538 , 539 , 540 , 561 , 562 , 563 implanting on the plurality of first surface metal strips of the IC chip 6 , a plurality of substrate's top surface metal strips 511 , 512 , 513 , 518 , 519 , 520 , 514 , 515 , 516 , 517 , 541 , 542 , 543 , a plurality of substrate's bottom surface metal strips 571 , 572 , 573 , 574 ,
- the top surface 501 of the substrate 5 includes a first side 581 , a second surface 582 , a third side 583 , and a fourth side 584 . Moreover the whole top surface 501 of the substrate 5 is divided into a periphery area 585 and a central area 586 .
- the bottom surface 502 of the substrate 5 includes a first side 591 , a second surface 592 , a third side 593 , and a fourth side 594 . Moreover, the whole bottom surface 502 of the substrate 5 is divided into a periphery area 595 and a central area 596 .
- the first surface 601 of the IC chip 6 includes a first side 611 , a second side 612 , a third side 613 , and a fourth side 614 . Moreover, the whole first surface 601 of the IC chip 6 is divided into a periphery area 615 and a central area 616 .
- FIG. 4 is a flow chart showing the technical content and the fabrication process of the flip chip package of a monolithic microwave integrated circuit (MMIC) of the invention.
- MMIC monolithic microwave integrated circuit
- the package structure and the technical content of the flip chip package of a monolithic microwave integrated circuit can be understood in accordance with the flow chart shown in FIG. 4.
- I/O ports input/output ports (I/O ports) (not shown), having been connected to external circuit, are disposed on the top surface 501 of the substrate 5 .
- I/O ports include direct current (DC) source terminals, signal terminals, and ground terminals.
- step 403 as shown in FIG.
- a plurality of metal strips (acting as I/O ports) and via holes connected thereof respectively are provided in the periphery area 585 on the top surface 501 of the substrate 5 .
- They are metal strips 511 , 512 , 513 and their corresponding via holes 521 , 522 , 523 on the first side 581 , metal strips 518 , 519 , 520 and their corresponding via holes 528 , 529 , 530 on the second side 582 , metal strips 514 , 515 , 516 , 517 and their corresponding via holes 527 on the third side 583 , as well as metal strips 541 , 542 , 543 and their corresponding via holes 524 , 525 , 526 on the fourth side 584 .
- Etching method can be employed for providing these metal strips on the substrate 5 , and the materials employed for these metal strips on both the top surface 501 and the bottom surface 502 of the substrate 5 can be gold (Au), copper (Cu), or aluminum (Al). As for the material for the metal strips on the IC chip 6 , gold (Au), copper (Cu), or aluminum (Al) can also be employed.
- a plurality of metal strips and via holes connected thereof respectively are provided in the periphery area 595 on the bottom surface 502 of the substrate 5 .
- They are metal strips 571 , 572 , 573 and their corresponding via holes 521 , 522 , 523 on the first side 591 , metal strips 578 , 579 , 580 and their corresponding via holes 528 , 529 , 530 on the second side 592 , metal strip 577 and its corresponding via hole 527 on the third side 593 , as well as metal strips 574 , 575 , 576 and their corresponding via holes 524 , 525 , 526 on the fourth side 594 .
- the metal strips provided on the bottom surface 502 of the substrate 5 and acting as I/O ports are electrically connected to the metal strips, also acting as I/O ports, provided on the top surface 501 of the substrate 5 through these via holes.
- a plurality of metal strips are provided in the periphery area 615 on the first surface 601 of the IC chip 6 . They are metal strips 641 , 642 , 643 on the first side 611 , metal strips 648 , 649 , 650 on the second side 612 , metal strips 644 , 645 , 646 , 647 on the third side 613 , as well as metal strips 671 , 672 , 673 on the fourth side 614 .
- solder bumps are implanted on the plurality of metal strips provided in the periphery area 615 on the first surface 601 of the above-mentioned IC chip 6 . They are solder bumps 531 , 532 , 533 on the metal strips 641 , 642 , 643 on the first side 611 of the first surface 601 of the IC chip 6 ; solder bumps 538 , 539 , 540 on the metal strip 648 , 649 , 650 on the second side 612 ; solder bumps 534 , 535 , 536 , 537 on the metal strips 644 , 645 , 646 , 647 on the third side 613 ; as well as solder bumps 561 , 562 , 563 on the metal strip 671 , 672 , 673 on the fourth side 614 .
- the metal strips provided on the first surface 601 of the IC chip 6 and acting as I/O ports are electrically connected to the metal strips, also acting as I/O ports, provided on the top surface 501 of the substrate 5 through these solder bumps.
- the solder bumps are employed to directly transmit the radio-frequency signals from the G-S-G or S-G I/O port structure on the MMIC to the G-S-G or S-G I/O port structure on the substrate where the G-S-D and S-G denote ground-signal-ground and signal-ground respectively.
- This method of the invention does not deteriorate the electrical characteristics of the MMIC while the conventional chip-and-wire method does.
- step 406 the IC chip 6 is flipped over and having its active surface (the first surface) covered on the substrate 5 .
- solder bumps are implanted by placing method and a reflow process is performed to accomplish the forming of the solder bumps.
- the methods of deposition, electroplating, and stencil printing can also be employed for forming the solder bumps
- the material for the solder bumps can be a metal or alloy such as gold (Au), gold-tin (Au—Sn), gold-silicon (Au—Si), gold-germanium (Au—Ge), tin-lead (Sn—Pb), tin-silver (Sn—Ag), tin-lead-silver (Sn—Pb—Ag), indium (In), indium-tin (In—Sn), or indium-lead (In—Pb).
- the plurality of solder bumps formed in the periphery area 615 on the first surface 601 of the IC chip 6 can also be implanted on the top surface 501 of the substrate 5 .
- the first surface 601 is the active area provided with electronic device
- the MMIC package 4 is to have the IC chip 6 flipped over and having its first surface 601 covering on the top surface 501 of the substrate 5 .
- the circuit on the electronic device is electrically connected to the metal strips on the first surface 601 through the traces (not shown) extended from the circuit.
- the active area becomes the main source of heat generation since the active area can generate heat as the active device is operating.
- the material of the IC chip can be selected from gallium arsenide (GaAs) of III-V group compound or silicon (Si).
- underfill 7 is employed to fill around the solder bumps and the plurality of the metal strips which are connected to the solder bumps and are positioned on the IC chip's first surface.
- the underfill 7 is also employed to fill all the chinks around the top surface's metal strips of the substrate 5 , and to cover the whole IC chip up to a height that is slightly higher than the thickness of the MMIC chip.
- step 409 a singulating process is performed to the substrate 5 , and the packaging process is accomplished (step 410 ).
- FIG. 8 is an isometric bottom view of a flip chip package of an MMIC of the second embodiment of the invention
- FIG. 9 is a cross-sectional view of a flip chip package of an MMIC of the second embodiment of the invention. Repeated illustration on the package structure of the flip chip package of an MMIC of the second embodiment of the invention shown in FIG. 8 and FIG. 9 is not necessary since the package structure is almost the same as that of the first embodiment of the invention.
- a penetration hole 503 provided through the central area 586 of the top surface 501 and the central area 596 of the bottom surface 502 of the substrate 5 .
- the material removed by penetrating the penetration hole is replaced by filling a heat-dissipative material which can be selected from boron nitride (BN), aluminum nitride (Al N), berylium oxide (BeO), aluminum oxide (Al 2 O 3 ), or silicon carbide (Si C).
- the number and disposition of the metal strips, solder bumps, and via holes depends on the structure and dimension of the IC chip.
- the flip chip package of an MMIC of the invention has the advantage of low cost, high operation frequency, fast in heat dissipation.
- this MMIC package of the invention can undertake mass production since the package size become smaller after the packaging process. What is more, the operation frequency can be improved since the package of the invention has less parasitic capacitance and parasitic inductance as the package of the prior art that has the chip-and-wire package. Therefore, the invention has the advantages what the package of the conventional MMIC can not achieve.
Abstract
A flip chip package of monolithic microwave integrated circuit (MMIC) is disclosed. The MMIC includes a substrate having an top surface and a bottom surface; a MMIC chip, having an active surface and having the chip flipped over and covered on the substrate with the active surface as the contacting surface wherein a central area of the active surface has one or several active devices; a plurality of metal strips, provided in a periphery area of the active surface of the MMIC chip and electrically connected to the active device; a plurality of solder bumps implanted respectively on the metal strips on the active surface of the MMIC chip and electrically connected to the metal strips on the MMIC chip; a plurality of substrate's top surface metal strips, provided in a periphery area of the top surface of the substrate and electrically connected to the solder bumps; a plurality of substrate's bottom surface metal strips, provided in the periphery area of the bottom surface of the substrate; a plurality of via holes, penetrating through the substrate in the periphery area of the upper and bottom surfaces of the substrate and electrically connected to the metal strips on the upper and bottom surfaces of the substrate, and electrically connected to these metal strips thereof; as well as an underfill, filling all the chinks around the solder bumps and the plurality of the metal strips connected to the solder bumps on the substrate's surface, and covering up to a height that is slightly higher than the thickness of the MMIC chip. Moreover, the MMIC package for the high power application has a penetration hole through the substrate in the central area of the upper and bottom surfaces of the substrate and filled with a heat-dissipative material in order to obtain a package structure with optimum heat-dissipative effect.
Description
- The invention relates to a flip chip package of monolithic microwave integrated circuit (MMIC), and more particularly, to a flip chip package of MMIC that has optimum heat-dissipative characteristic, and that can reduce the effects of parasitic inductance and parasitic capacitance, for the application in micro-wave, millimeter-wave and radio-frequency.
- In our modern society, internet has become an indispensable part of our daily life. As the quality demands on the transmitting speed of the audio, video and data are getting higher and higher, wide-band network emerges in response to the needs of the times.
- FIG. 1 is a structural disposition of a microwave integrated circuit package according to a prior art. As shown in FIG. 1, the microwave integrated circuit package structure disclosed in patent No. 69,402 of Taiwan, Republic of China includes a grounded
potential metal surface 112, an ICchip bonding part 113, a slot-type viahole signal line 115 penetrating through the substrate, a coplanar waveguide input/output port (I/O port) 121, and a plurality of circular via holes connecting the top and bottom metal surfaces of the substrate. The microwave integrated circuit package provides a grounded potential metal surface to perform signal transmission between each of the I/O ports and IC circuit. As far as the disposition of the metal surface on the substrate's top surface is concerned, the material employed for the metal surface is any ones that can be performed wire bonding and are chemically stable. And the metal surface is fabricated by making use of thick film or thin film or a common IC board's etching methods, and its attenuation is smaller than that of a micro-strip since it employs coplanar waveguide. - FIG. 2 is a cross-sectional view of a microwave integrated circuit package according to another prior art. The prior art shown in FIG. 2 is a “small outline integrated circuit (SOIC) package” which is the most popular IC package technology nowadays. As shown in FIG. 2, the steps for forming the SOIC package is described as follows. First of all, a
chip 281 is adhered to thepaddle 221 of thelead frame 282 by the surface mounting method. Afterwards, thewires 283 are bonded, andadhesive material 284 is applied to fix the package in position. The package is finally formed by mold injection withencapsulant 285 to protect against the intrusion of the moisture and the dust that might affect the electrical characteristic in order to improve the package reliability. - FIG. 3(a) is a cross-sectional view of a microwave integrated circuit package according to one other prior art. The microwave integrated circuit package is disclosed in patent No. 93,511 of Taiwan, Republic of China. As shown in FIG. 3(a), the microwave integrated circuit package includes an
IC chip 363 and asubstrate 361.Wires O ports O ports O ports via holes underfill material 390 is employed to cover theIC chip 363 andbonding wires underfill material 390 by mold injection withencapsulant 391. - FIG. 3(b) is an isometric top view of a microwave integrated circuit package according to the one other prior art shown in FIG. 3(a). As shown in FIG. 3(b), the
IC chip 416 is flipped over to have the surface, having signal and ground terminals, facing downward. In the meantime,metal strip IC chip 416 can contact themetal strip 411, the output signal terminal can contact themetal strip 412, and the all the grounded terminals can contact themetal strip 415. Moreover, the portion covered by theIC chip 416 is performed etching to prevent the surface of theIC chip 416 from being short-circuited. - Most of the above-mentioned package technology makes use of bonding wires to connect the IC chip to the I/O ports of the substrate. Since the bonding wires of this kind of chip-and-wire IC package will cause significant parasitic inductance effect and parasitic capacitance effect in the frequency range of micro-wave and milli-meter wave, the chip-and-wire IC package will affect the electrical characteristic in the high frequency range and deteriorate the reliability of the electronic devices. Moreover, among the MMIC packages, the manufacturing cost of this kind of chip-and-wire is rather high nowadays, and its mass production is not feasible. Further, the size of the MMIC made by chip-and-wire is rather large that does not meet the trend of compact design in package.
- Currently, in respect of the frequency range of micro-wave and milli-wave application, although the micro-wave integrated circuit (MIC) formed by employing bare chip and wire bonding is widely used, the fabrication process is time consuming and the cost of manpower is very high, thereby, the price of the MIC package remains very high. Besides, since the bonding wires currently employed by the microwave chip package results in parasitic inductance effect and parasitic capacitance effect, the electrical performance is deteriorated, consequently, the application of the wire bonding in milli-wave package is not even feasible.
- On the other hand, a comparison of the invention with the prior art shown in FIG. 3(b) is made as follows. Since the invention employs metal strips to connect the IC chip to the substrate, and since the area of the substrate is only slightly greater than that of the IC chip, the size of the device after finishing the packaging process is rather small. Therefore, the MMIC package of the invention is in accordance with the trend of the compact design of the package. In addition, since the IC chip is electrically connected to the substrate through the metal strip instead of being directly contacted the substrate, the short circuit phenomenon on the surface of the IC chip can be avoided, thereby, the yield of the package of the electronic device is improved.
- In the light of the above-mentioned disadvantages, and in order to resolve the problems on the package used in radio frequency (RF), microwave, and milli-wave devices, an object of the invention is to have a package that can make use of the common surface-mounted technology (SMT) to undertake mass production so as to lower the production cost. The above-mentioned problems are summarized as follows:
- 1. The undesired impedance matching and the self-resonant problems resulted from the parasitic capacitance and parasitic inductance generated by the bonding wires.
- 2. The inability problem to undertake automation on the production of the chip-and-wire package.
- 3. The inertly heat-dissipative problem of the chip of gallium arsenide (GaAs) commonly used by the RF, microwave, and milli-wave.
- 4. The inability to have a compact package since the size of the package becomes large after the packaging process.
- To attain the object of resolving these problems, the invention provides a flip chip package of monolithic microwave integrated circuit (MMIC). The MMIC package of the invention includes a substrate, having an top surface and a bottom surface, and each of the surfaces is divided respectively into a periphery area and a central area; an integrated circuit chip (IC chip), having a first surface and a second surface, and each of the surfaces being divided respectively into a periphery area and a central area, and the MMIC package being made by flipping the IC chip to have its first surface covering on the top surface of the substrate, and the central area of the first surface having one or several active devices; a plurality of metal strips, positioned on the IC chip's first surface and disposed in the periphery area of the IC chip's first surface, and these metal strips being electrically connected to the active devices on the first surface of the IC chip; a plurality of solder bumps, implanted respectively on and being electrically connected to the first surface's metal strips of the plurality of IC chips; a plurality of metal strips of the substrate's top surface, disposed in the periphery area of the substrate's top surface, and these metal strips being electrically connected to the plurality of solder bumps; a plurality of metal strips of the substrate's bottom surface, disposed in the periphery area of the substrate's bottom surface; a plurality of via holes, penetrating through the substrate and being electrically connected to the plurality of metal strips of the substrate's top surface and to the plurality of metal strips of the substrate's bottom surface respectively; and an underfill, filling the solder bumps and the plurality of the metal strips which are connected to the solder bumps and are positioned on the IC chip's first surface, also filling all the chinks around the top surface's metal strips of the substrate, and covering the whole IC chip up to a height that is slightly higher than the thickness of the MMIC chip. A penetration hole is provided in the central areas of the top and bottom surfaces of the substrate for those high power packages that require optimum heat-dissipative effect. Moreover, the material removed by penetrating the penetration hole is replaced by filling a heat-dissipative material with relatively low dielectric constant and relatively low dielectric loss.
- FIG. 1 is a structural disposition of a microwave integrated circuit package according to a prior art.
- FIG. 2 is a cross-sectional view of a microwave integrated circuit package according to another prior art.
- FIG. 3(a) is a cross-sectional view of a microwave integrated circuit package according to one other prior art.
- FIG. 3(b) is an isometric top view of a microwave integrated circuit package according to the one other prior art shown in FIG. 3(a).
- FIG. 4 is a flow chart showing the technical content and the fabrication process of the flip chip package of a monolithic microwave integrated circuit (MMIC) of the invention.
- FIG. 5(a) is an isometric top view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 5(b) is a top view of the substrate's top surface of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 5(c) is a bottom view of the substrate's bottom surface of an MMIC of the first embodiment of the invention.
- FIG. 5(d) is a top view of the IC chip's bottom surface of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 6 is an isometric bottom view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 7 is a cross-sectional view of a flip chip package of an MMIC of the first embodiment of the invention.
- FIG. 8 is an isometric bottom view of a flip chip package of an MMIC of the second embodiment of the invention.
- FIG. 9 is a cross-sectional view of a flip chip package of an MMIC of the second embodiment of the invention.
- The flip chip packages of the monolithic microwave integrated circuit are classified into low power packages and high power packages depending on the required power in their field of application. The low power packages have their power less that one milli-Watt (mW) while the high power packages have their power greater that one milli-Watt (mW). As compared with low power packages, high power packages require much better heat-dissipative package structure in order to improve the reliability since the high power packages contain MMIC that generates relatively high quantity of heat. The first embodiment of the invention is a low power package while the second embodiment of the invention is a high power package.
- The flip chip package of a monolithic microwave integrated circuit of the first embodiment of the invention is illustrated in FIG. 5(a), 5(b), 5(c), 5(d), FIG. 6, and FIG. 7. FIG. 5(a) is an isometric top view of a flip chip package of an MMIC of the first embodiment of the invention. FIG. 5(b) is a top view of the substrate's top surface of a flip chip package of an MMIC of the first embodiment of the invention. FIG. 5(c) is a bottom view of the substrate's bottom surface of an MMIC of the first embodiment of the invention. FIG. 5(d) is a top view of the IC chip's bottom surface of a flip chip package of an MMIC of the first embodiment of the invention. FIG. 6 is an isometric bottom view of a flip chip package of an MMIC of the first embodiment of the invention. FIG. 7 is a cross-sectional view of a flip chip package of an MMIC of the first embodiment of the invention.
- As shown in FIG. 5(a), 5(b), 5(c), 5(d), FIG. 6, FIG. 7, the flip chip package of a monolithic microwave integrated circuit of the
invention 4 includes asubstrate 5, an integrated circuit chip (IC chip) 6. Thesubstrate 5 has atop surface 501 and abottom surface 502, and theIC chip 6 has afirst surface 601 and asecond surface 602. The flip chip package of a monolithic microwave integratedcircuit 4 also includes a plurality of first surface metal strips 641, 642, 643, 644, 645, 646, 647, 648, 649, 650, 671, 672, 673 of theIC chip 6, and a plurality of solder bumps 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 561, 562, 563 implanting on the plurality of first surface metal strips of theIC chip 6, a plurality of substrate's top surface metal strips 511, 512, 513, 518, 519, 520, 514, 515, 516, 517, 541, 542, 543, a plurality of substrate's bottom surface metal strips 571, 572, 573, 574,575, 576, 577, 578, 579, 580, and a plurality of viaholes - Among them, the
top surface 501 of thesubstrate 5 includes afirst side 581, asecond surface 582, athird side 583, and afourth side 584. Moreover the wholetop surface 501 of thesubstrate 5 is divided into aperiphery area 585 and acentral area 586. In the similar way, thebottom surface 502 of thesubstrate 5 includes afirst side 591, asecond surface 592, athird side 593, and afourth side 594. Moreover, the wholebottom surface 502 of thesubstrate 5 is divided into aperiphery area 595 and acentral area 596. - What is more, the
first surface 601 of theIC chip 6 includes afirst side 611, asecond side 612, athird side 613, and afourth side 614. Moreover, the wholefirst surface 601 of theIC chip 6 is divided into aperiphery area 615 and acentral area 616. - FIG. 4 is a flow chart showing the technical content and the fabrication process of the flip chip package of a monolithic microwave integrated circuit (MMIC) of the invention. The package structure and the technical content of the flip chip package of a monolithic microwave integrated circuit can be understood in accordance with the flow chart shown in FIG. 4. As shown in FIG. 4, first of all (step401, 402), input/output ports (I/O ports) (not shown), having been connected to external circuit, are disposed on the
top surface 501 of thesubstrate 5. These I/O ports include direct current (DC) source terminals, signal terminals, and ground terminals. Next (step 403), as shown in FIG. 5(b), a plurality of metal strips (acting as I/O ports) and via holes connected thereof respectively are provided in theperiphery area 585 on thetop surface 501 of thesubstrate 5. They aremetal strips 511, 512, 513 and their corresponding viaholes 521, 522, 523 on thefirst side 581, metal strips 518, 519, 520 and their corresponding viaholes second side 582, metal strips 514, 515, 516, 517 and their corresponding viaholes 527 on thethird side 583, as well as metal strips 541, 542, 543 and their corresponding viaholes fourth side 584. Etching method can be employed for providing these metal strips on thesubstrate 5, and the materials employed for these metal strips on both thetop surface 501 and thebottom surface 502 of thesubstrate 5 can be gold (Au), copper (Cu), or aluminum (Al). As for the material for the metal strips on theIC chip 6, gold (Au), copper (Cu), or aluminum (Al) can also be employed. - Thereafter, similarly as shown in FIG. 5(c), a plurality of metal strips and via holes connected thereof respectively are provided in the
periphery area 595 on thebottom surface 502 of thesubstrate 5. They aremetal strips 571, 572, 573 and their corresponding viaholes 521, 522, 523 on thefirst side 591, metal strips 578, 579, 580 and their corresponding viaholes second side 592,metal strip 577 and its corresponding viahole 527 on thethird side 593, as well as metal strips 574, 575, 576 and their corresponding viaholes fourth side 594. The metal strips provided on thebottom surface 502 of thesubstrate 5 and acting as I/O ports are electrically connected to the metal strips, also acting as I/O ports, provided on thetop surface 501 of thesubstrate 5 through these via holes. - Subsequently, same way is undertaken as shown in FIG. 5(d). a plurality of metal strips are provided in the
periphery area 615 on thefirst surface 601 of theIC chip 6. They aremetal strips first side 611, metal strips 648, 649, 650 on thesecond side 612, metal strips 644, 645, 646, 647 on thethird side 613, as well as metal strips 671, 672, 673 on thefourth side 614. Afterwards (step 405), solder bumps are implanted on the plurality of metal strips provided in theperiphery area 615 on thefirst surface 601 of the above-mentionedIC chip 6. They aresolder bumps first side 611 of thefirst surface 601 of theIC chip 6; solder bumps 538, 539, 540 on themetal strip second side 612; solder bumps 534, 535, 536, 537 on the metal strips 644, 645, 646, 647 on thethird side 613; as well as solder bumps 561, 562, 563 on themetal strip fourth side 614. The metal strips provided on thefirst surface 601 of theIC chip 6 and acting as I/O ports are electrically connected to the metal strips, also acting as I/O ports, provided on thetop surface 501 of thesubstrate 5 through these solder bumps. The solder bumps are employed to directly transmit the radio-frequency signals from the G-S-G or S-G I/O port structure on the MMIC to the G-S-G or S-G I/O port structure on the substrate where the G-S-D and S-G denote ground-signal-ground and signal-ground respectively. This method of the invention does not deteriorate the electrical characteristics of the MMIC while the conventional chip-and-wire method does. Then (step 406), theIC chip 6 is flipped over and having its active surface (the first surface) covered on thesubstrate 5. Thereafter (step 407), solder bumps are implanted by placing method and a reflow process is performed to accomplish the forming of the solder bumps. In addition to the placing method, the methods of deposition, electroplating, and stencil printing can also be employed for forming the solder bumps, and the material for the solder bumps can be a metal or alloy such as gold (Au), gold-tin (Au—Sn), gold-silicon (Au—Si), gold-germanium (Au—Ge), tin-lead (Sn—Pb), tin-silver (Sn—Ag), tin-lead-silver (Sn—Pb—Ag), indium (In), indium-tin (In—Sn), or indium-lead (In—Pb). It is worthwhile to mention that the plurality of solder bumps formed in theperiphery area 615 on thefirst surface 601 of theIC chip 6 can also be implanted on thetop surface 501 of thesubstrate 5. - In the
IC chip 6 of the flip chip package of a monolithic microwave integrated circuit of the invention, thefirst surface 601 is the active area provided with electronic device, and theMMIC package 4 is to have theIC chip 6 flipped over and having itsfirst surface 601 covering on thetop surface 501 of thesubstrate 5. The circuit on the electronic device is electrically connected to the metal strips on thefirst surface 601 through the traces (not shown) extended from the circuit. The active area becomes the main source of heat generation since the active area can generate heat as the active device is operating. The material of the IC chip can be selected from gallium arsenide (GaAs) of III-V group compound or silicon (Si). - From hereon (step408),
underfill 7 is employed to fill around the solder bumps and the plurality of the metal strips which are connected to the solder bumps and are positioned on the IC chip's first surface. Theunderfill 7 is also employed to fill all the chinks around the top surface's metal strips of thesubstrate 5, and to cover the whole IC chip up to a height that is slightly higher than the thickness of the MMIC chip. Finally (step 409), a singulating process is performed to thesubstrate 5, and the packaging process is accomplished (step 410). - In the flip chip package of a monolithic microwave integrated circuit of the invention, the one applicable to the high power device is the “high power package” of the second embodiment of the invention. FIG. 8 is an isometric bottom view of a flip chip package of an MMIC of the second embodiment of the invention, and FIG. 9 is a cross-sectional view of a flip chip package of an MMIC of the second embodiment of the invention. Repeated illustration on the package structure of the flip chip package of an MMIC of the second embodiment of the invention shown in FIG. 8 and FIG. 9 is not necessary since the package structure is almost the same as that of the first embodiment of the invention. The only difference is a
penetration hole 503 provided through thecentral area 586 of thetop surface 501 and thecentral area 596 of thebottom surface 502 of thesubstrate 5. The material removed by penetrating the penetration hole is replaced by filling a heat-dissipative material which can be selected from boron nitride (BN), aluminum nitride (Al N), berylium oxide (BeO), aluminum oxide (Al2O3), or silicon carbide (Si C). - Among the first and second embodiments of the flip chip package of a monolithic microwave integrated circuit of the invention, the number and disposition of the metal strips, solder bumps, and via holes depends on the structure and dimension of the IC chip.
- The flip chip package of an MMIC of the invention has the advantage of low cost, high operation frequency, fast in heat dissipation. In addition, this MMIC package of the invention can undertake mass production since the package size become smaller after the packaging process. What is more, the operation frequency can be improved since the package of the invention has less parasitic capacitance and parasitic inductance as the package of the prior art that has the chip-and-wire package. Therefore, the invention has the advantages what the package of the conventional MMIC can not achieve.
- While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.
Claims (14)
1. A flip chip package of monolithic microwave integrated circuit (MMIC) comprising:
a substrate, having an top surface and a bottom surface, and each of the surfaces is divided respectively into a periphery area and a central area;
an integrated circuit chip (IC chip), having a first surface and a second surface, and each of the surfaces being divided respectively into a periphery area and a central area, and the MMIC package being made by flipping the IC chip to have its first surface covering on the top surface of the substrate, and the central area of the first surface having one or several active devices;
a plurality of metal strips, positioned on the IC chip's first surface and disposed in the periphery area of the IC chip's first surface, and these metal strips being electrically connected to the active devices on the first surface of the IC chip;
a plurality of solder bumps, implanted respectively on and being electrically connected to the first surface's metal strips of the plurality of IC chips;
a plurality of metal strips of the substrate's top surface, disposed in the periphery area of the substrate's top surface, and these metal strips being electrically connected to the plurality of solder bumps;
a plurality of metal strips of the substrate's bottom surface, disposed in the periphery area of the substrate's bottom surface
a plurality of via holes, penetrating through the substrate and being electrically connected to the plurality of metal strips on the substrate's top surface and to the plurality of metal strips on the substrate's bottom surface respectively; and
an underfill, filling the solder bumps and the plurality of the metal strips which are connected to the solder bumps and are positioned on the IC chip's first surface, also filling all the chinks around the top surface's metal strips of the substrate, and covering the whole IC chip up to a height that is slightly higher than the thickness of the MMIC chip.
2. The flip chip package of MMIC of claim 1 , wherein the plurality of solder bumps are implanted on and electrically connected to the top surface's metal strips of the substrate, and also being electrically connected to the first surface's metal strips of the IC chip.
3. The flip chip package of MMIC of claim 1 , wherein the plurality of the first surface's metal strips of the IC chip are input/output (I/O) ports and ground terminals of the IC chip.
4. The flip chip package of MMIC of claim 1 , wherein the material of the plurality of the first surface's metal strips of the IC chip is selected from the group of metal consisting of gold, copper, and aluminum.
5. The flip chip package of MMIC of claim 1 , wherein the material of the plurality of the top surface's metal strips and the plurality of the bottom surface's metal strips of the substrate is selected from the group of metal consisting of gold, copper, and aluminum.
6. The flip chip package of MMIC of claim 1 , wherein the material of the IC chip is selected from the group consisting of gallium arsenide (GaAs) of III-V group compound or silicon (Si).
7. The flip chip package of MMIC of claim 1 , wherein the material of the solder bumps is selected from the group of metal or alloy consisting of gold (Au), gold-tin (Au—Sn), gold-silicon (Au—Si), gold-germanium (Au—Ge), tin-lead (Sn—Pb), tin-silver (Sn—Ag), tin-lead-silver (Sn—Pb—Ag), indium (In), indium-tin (In—Sn), indium-lead (In—Pb).
8. The flip chip package of MMIC of claim 1 , wherein the method for forming the solder bumps is selected from the group consisting of deposition, electroplating, stencil printing, wire bonding, solder ball implanting.
9. The flip chip package of MMIC of claim 1 , wherein the material of the via holes is selected from the group of metal consisting of gold, silver, copper, and aluminum.
10. The flip chip package of MMIC of claim 1 , wherein the forming method of metal strips on the top and bottom surfaces of the substrate and on the first surface of the IC chip is etching.
11. The flip chip package of MMIC of claim 1 , wherein the number and disposition of all the metal strips and via holes depend on the structure and size of the IC chip.
12. The flip chip package of MMIC of claim 1 , wherein a penetration hole is provided in the central areas of the top and bottom surfaces of the substrate and the material removed by penetrating the penetration hole is replaced by filling a heat-dissipative material.
13. The flip chip package of MMIC of claim 12 , wherein the heat-dissipative material is selected from the group consisting of boron nitride (BN), aluminum nitride (Al N), berylium oxide (Be O), aluminum oxide (Al2O3), silicon carbide (Si C).
14. The flip chip package of MMIC of claim 1 , wherein the material of the underfill is thermosetting resin.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW90713148A | 2001-05-30 | ||
TW090113148A TW536795B (en) | 2001-05-30 | 2001-05-30 | Flip chip package of monolithic microwave integrated circuit |
TW90113148 | 2001-05-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020180062A1 true US20020180062A1 (en) | 2002-12-05 |
US6495915B1 US6495915B1 (en) | 2002-12-17 |
Family
ID=21678389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/927,564 Expired - Fee Related US6495915B1 (en) | 2001-05-30 | 2001-08-09 | Flip chip package of monolithic microwave integrated circuit |
Country Status (3)
Country | Link |
---|---|
US (1) | US6495915B1 (en) |
JP (1) | JP2002368157A (en) |
TW (1) | TW536795B (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030127734A1 (en) * | 2002-01-07 | 2003-07-10 | Jin-Yuan Lee | Cylindrical bonding structure and method of manufacture |
US20030205808A1 (en) * | 2002-04-03 | 2003-11-06 | Makoto Terui | Semiconductor device |
US20040089953A1 (en) * | 2002-11-08 | 2004-05-13 | Mccormick John P. | Via construction |
US20080180924A1 (en) * | 2007-01-18 | 2008-07-31 | Shaikh Naseer A | Microwave surface mount hermetically sealed package and method of forming the same |
US20110212614A1 (en) * | 2007-03-09 | 2011-09-01 | Micron Technology, Inc. | Microelectronic workpieces and method for manufacturing microelectronic devices using such workpieces |
CN103069936A (en) * | 2010-11-30 | 2013-04-24 | 乐健线路板(珠海)有限公司 | Printed circuit board with insulated micro radiator |
US8546927B2 (en) * | 2010-09-03 | 2013-10-01 | Murata Manufacturing Co., Ltd. | RFIC chip mounting structure |
US8664756B2 (en) * | 2012-07-24 | 2014-03-04 | Medtronic, Inc. | Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability |
CN105789163A (en) * | 2016-03-23 | 2016-07-20 | 宜确半导体(苏州)有限公司 | Radio frequency front-end chip integration module and radio frequency front-end chip integration method |
EP3148298A1 (en) | 2015-09-22 | 2017-03-29 | Rayben Technologies (HK) Limited | Manufacturing method of printing circuit board with micro-radiators |
US10312176B2 (en) * | 2016-04-05 | 2019-06-04 | Gpower Semiconductor, Inc. | Semiconductor device |
US10433414B2 (en) | 2010-12-24 | 2019-10-01 | Rayben Technologies (HK) Limited | Manufacturing method of printing circuit board with micro-radiators |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040080033A1 (en) * | 2002-04-09 | 2004-04-29 | Advanced Semiconductor Engineering Inc. | Flip chip assembly and method for producing the same |
US6977435B2 (en) * | 2003-09-09 | 2005-12-20 | Intel Corporation | Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
WO2005024912A2 (en) * | 2003-09-09 | 2005-03-17 | Intel Corporation | Methods of processing thick ild layers using spray coating or lamination for c4 wafer level thick metal integrated flow |
US20060035413A1 (en) * | 2004-01-13 | 2006-02-16 | Cookson Electronics, Inc. | Thermal protection for electronic components during processing |
US20050151555A1 (en) * | 2004-01-13 | 2005-07-14 | Cookson Electronics, Inc. | Cooling devices and methods of using them |
JP4972306B2 (en) * | 2004-12-21 | 2012-07-11 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and circuit device |
US7723759B2 (en) * | 2005-10-24 | 2010-05-25 | Intel Corporation | Stacked wafer or die packaging with enhanced thermal and device performance |
US7622793B2 (en) * | 2006-12-21 | 2009-11-24 | Anderson Richard A | Flip chip shielded RF I/O land grid array package |
US20110198609A1 (en) * | 2010-02-12 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-Emitting Devices with Through-Substrate Via Connections |
CN102026496A (en) * | 2010-12-24 | 2011-04-20 | 乐健线路板(珠海)有限公司 | Method for preparing printed circuit board with insulated micro radiator |
US8581406B1 (en) * | 2012-04-20 | 2013-11-12 | Raytheon Company | Flip chip mounted monolithic microwave integrated circuit (MMIC) structure |
US10355193B2 (en) | 2017-11-28 | 2019-07-16 | International Business Machines Corporation | Flip chip integration on qubit chips |
US10340438B2 (en) | 2017-11-28 | 2019-07-02 | International Business Machines Corporation | Laser annealing qubits for optimized frequency allocation |
US11895931B2 (en) | 2017-11-28 | 2024-02-06 | International Business Machines Corporation | Frequency tuning of multi-qubit systems |
US10418540B2 (en) | 2017-11-28 | 2019-09-17 | International Business Machines Corporation | Adjustment of qubit frequency through annealing |
US10170681B1 (en) | 2017-11-28 | 2019-01-01 | International Business Machines Corporation | Laser annealing of qubits with structured illumination |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10308478A (en) * | 1997-03-05 | 1998-11-17 | Toshiba Corp | Semiconductor module |
JP4015746B2 (en) * | 1997-10-30 | 2007-11-28 | 松下電器産業株式会社 | Semiconductor device |
-
2001
- 2001-05-30 TW TW090113148A patent/TW536795B/en active
- 2001-08-09 US US09/927,564 patent/US6495915B1/en not_active Expired - Fee Related
- 2001-11-01 JP JP2001336582A patent/JP2002368157A/en active Pending
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8461679B2 (en) | 2002-01-07 | 2013-06-11 | Megica Corporation | Method for fabricating circuit component |
US7960270B2 (en) | 2002-01-07 | 2011-06-14 | Megica Corporation | Method for fabricating circuit component |
US20030127734A1 (en) * | 2002-01-07 | 2003-07-10 | Jin-Yuan Lee | Cylindrical bonding structure and method of manufacture |
US8890336B2 (en) | 2002-01-07 | 2014-11-18 | Qualcomm Incorporated | Cylindrical bonding structure and method of manufacture |
US20030205808A1 (en) * | 2002-04-03 | 2003-11-06 | Makoto Terui | Semiconductor device |
US7157794B2 (en) * | 2002-04-03 | 2007-01-02 | Oki Electric Industry Co., Ltd. | Semiconductor device that suppresses variations in high frequency characteristics of circuit elements |
US20070021089A1 (en) * | 2002-04-03 | 2007-01-25 | Makoto Terui | Semiconductor device that suppresses variations in high frequency characteristics of circuit elements |
US7545036B2 (en) | 2002-04-03 | 2009-06-09 | Oki Semiconductor Co., Ltd. | Semiconductor device that suppresses variations in high frequency characteristics of circuit elements |
US20040089953A1 (en) * | 2002-11-08 | 2004-05-13 | Mccormick John P. | Via construction |
US6943446B2 (en) * | 2002-11-08 | 2005-09-13 | Lsi Logic Corporation | Via construction for structural support |
US20080180924A1 (en) * | 2007-01-18 | 2008-07-31 | Shaikh Naseer A | Microwave surface mount hermetically sealed package and method of forming the same |
US7557431B2 (en) * | 2007-01-18 | 2009-07-07 | Miteq, Inc. | Microwave surface mount hermetically sealed package and method of forming the same |
US20110212614A1 (en) * | 2007-03-09 | 2011-09-01 | Micron Technology, Inc. | Microelectronic workpieces and method for manufacturing microelectronic devices using such workpieces |
US8492198B2 (en) * | 2007-03-09 | 2013-07-23 | Micron Technology, Inc. | Microelectronic workpieces with stand-off projections and methods for manufacturing microelectronic devices using such workpieces |
US8987874B2 (en) | 2007-03-09 | 2015-03-24 | Micron Technology, Inc. | Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces |
US8546927B2 (en) * | 2010-09-03 | 2013-10-01 | Murata Manufacturing Co., Ltd. | RFIC chip mounting structure |
CN103069936A (en) * | 2010-11-30 | 2013-04-24 | 乐健线路板(珠海)有限公司 | Printed circuit board with insulated micro radiator |
US10433414B2 (en) | 2010-12-24 | 2019-10-01 | Rayben Technologies (HK) Limited | Manufacturing method of printing circuit board with micro-radiators |
US8664756B2 (en) * | 2012-07-24 | 2014-03-04 | Medtronic, Inc. | Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability |
EP3148298A1 (en) | 2015-09-22 | 2017-03-29 | Rayben Technologies (HK) Limited | Manufacturing method of printing circuit board with micro-radiators |
CN105789163A (en) * | 2016-03-23 | 2016-07-20 | 宜确半导体(苏州)有限公司 | Radio frequency front-end chip integration module and radio frequency front-end chip integration method |
US10312176B2 (en) * | 2016-04-05 | 2019-06-04 | Gpower Semiconductor, Inc. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TW536795B (en) | 2003-06-11 |
JP2002368157A (en) | 2002-12-20 |
US6495915B1 (en) | 2002-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6495915B1 (en) | Flip chip package of monolithic microwave integrated circuit | |
KR100980139B1 (en) | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices | |
US7268426B2 (en) | High-frequency chip packages | |
US6191487B1 (en) | Semiconductor and flip chip packages and method having a back-side connection | |
US5557144A (en) | Plastic packages for microwave frequency applications | |
US7514771B2 (en) | Leadless lead-frame | |
JPH08167630A (en) | Chip connection structure | |
US6753599B2 (en) | Semiconductor package and mounting structure on substrate thereof and stack structure thereof | |
US6177719B1 (en) | Chip scale package of semiconductor | |
US5426319A (en) | High-frequency semiconductor device including microstrip transmission line | |
US7015591B2 (en) | Exposed pad module integrating a passive device therein | |
CN111199957A (en) | Three-dimensional packaging structure integrating chip and antenna and preparation method thereof | |
US6046501A (en) | RF-driven semiconductor device | |
US7211887B2 (en) | connection arrangement for micro lead frame plastic packages | |
KR100248035B1 (en) | Semiconductor package | |
JP2574510B2 (en) | High frequency semiconductor device | |
JP2538072B2 (en) | Semiconductor device | |
JP3933601B2 (en) | High frequency integrated circuit package and electronic device | |
US20050082658A1 (en) | Simplified stacked chip assemblies | |
CN211208440U (en) | Three-dimensional packaging structure integrating chip and antenna | |
US20230317567A1 (en) | Leadframe | |
US20230154891A1 (en) | Substrate-based package semiconductor device with side wettable flanks | |
JP2543894B2 (en) | Semiconductor integrated circuit device | |
JP3586867B2 (en) | Semiconductor device, method of manufacturing the same, method of mounting the same, and circuit board mounting the same | |
JPS6348129Y2 (en) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: APACK COMMUNICATIONS INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIEH, TSUNG-YING;HSU, CHIN-LIN;HSU, WEN-RUI;REEL/FRAME:012076/0137 Effective date: 20010502 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20061217 |