US20020179996A1 - Semiconductor device having a nitride barrier for preventing formation of structural defects - Google Patents
Semiconductor device having a nitride barrier for preventing formation of structural defects Download PDFInfo
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- US20020179996A1 US20020179996A1 US10/193,176 US19317602A US2002179996A1 US 20020179996 A1 US20020179996 A1 US 20020179996A1 US 19317602 A US19317602 A US 19317602A US 2002179996 A1 US2002179996 A1 US 2002179996A1
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 230000004888 barrier function Effects 0.000 title 1
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- 238000007254 oxidation reaction Methods 0.000 claims abstract description 44
- 238000005121 nitriding Methods 0.000 claims abstract description 35
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- 238000005530 etching Methods 0.000 claims abstract description 11
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 37
- 229910052710 silicon Inorganic materials 0.000 abstract description 37
- 239000010703 silicon Substances 0.000 abstract description 37
- 238000002955 isolation Methods 0.000 abstract description 18
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 35
- 229910052814 silicon oxide Inorganic materials 0.000 description 33
- -1 boron ions Chemical class 0.000 description 13
- 230000007547 defect Effects 0.000 description 10
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- YZYDPPZYDIRSJT-UHFFFAOYSA-K boron phosphate Chemical compound [B+3].[O-]P([O-])([O-])=O YZYDPPZYDIRSJT-UHFFFAOYSA-K 0.000 description 7
- 229910000149 boron phosphate Inorganic materials 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 239000005365 phosphate glass Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
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- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 239000012298 atmosphere Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
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- 150000004706 metal oxides Chemical class 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Definitions
- the present invention relates to a semiconductor device, and a method of producing the same. More particularly, it relates to a trench isolation structure for electrically isolating semiconductor elements.
- Trench isolation structure formed between semiconductor elements such as transistors has been becoming increasingly important as semiconductor devices are packaged with higher density and higher performance.
- FIGS. 12 through 21 are cross sectional views showing first through tenth steps of the method of producing a trench isolation structure of the prior art.
- a silicon oxide film 2 having thickness of 100 ⁇ is grown on a principal plane of a P-type silicon substrate 1 by thermal oxidation process, followed by the deposition of a silicon nitride film 3 having thickness of 500 ⁇ by low pressure CVD (Chemical Vapor Deposition) process and application of a resist to form a desired resist pattern 4 by photolithography technology.
- CVD Chemical Vapor Deposition
- the silicon substrate 1 is etched thereby to form a groove 5 having a depth of 4000 ⁇ from the surface, and the resist pattern 4 is removed, as shown in FIG. 13.
- the groove 5 is filled up by depositing a silicon oxide filling 7 to a depth of 6000 ⁇ by CVD process.
- Surface of the silicon oxide filling 7 is smoothed by CMP (Chemical Mechanical Polishing) process.
- FIG. 16 where the silicon nitride film 3 is selectively removed by using thermal phosphoric acid, thus forming a trench isolation structure 30 comprising the groove 5 , the silicon oxide film 6 and the silicon oxide filling 7 .
- boron ions are implanted with a density of 3 ⁇ 10 12 /cm 2 and an energy of 200 KeV by ion implantation process, thereby to form a channel stopper layer 35 .
- FIG. 19 where a silicon oxide film having thickness of 50 ⁇ which would become a gate oxidation film 8 of a transistor is formed by thermal oxidation process, and phosphorus-doped polycrystal silicon is deposited to a thickness of about 3000 ⁇ by low pressure CVD process. After forming a desired resist pattern 10 by the photolithography technology, the phosphorus-doped polycrystal silicon is etched with the resist pattern 10 used as a mask, thereby forming a gate electrode 9 .
- arsenic ions are implanted with a density of 4 ⁇ 10 15 /cm 2 at an energy of 50 KeV by ion implantation process, thereby to form an impurity-doped layer 11 of a conductivity type different from that of the silicon substrate 1 .
- heat treatment is applied in nitrogen atmosphere at 800° C. for about 30 minutes, thereby to form an N-type diffusion layer 11 which is an impurity-doped layer by activating the arsenic ions.
- MOS Metal Oxide Semiconductor
- a boron phosphate glass 13 is deposited by the CVD process.
- a resist pattern (not shown) is formed by photolithography technology. The resist pattern is used as a mask in etching the boron phosphate glass 13 and the silicon oxide film 12 to make contact holes (not shown), followed by deposition of an aluminum-silicon-copper (Al—Si—Cu) alloy film by a sputtering technique.
- a resist (not shown) is applied in a desired pattern by the photolithography technology, and the resist pattern is used as a mask for etching the aluminum-silicon-copper alloy film, thereby to form an aluminum-silicon-copper wiring 14 .
- the semiconductor device of the prior art is constructed as described above, while semiconductor elements such as transistor are electrically isolated from each other by the trench isolation structure.
- FIG. 22 is a diagram for explaining a mechanism wherein leak current flowing through an NP junction between an N-type diffusion layer (drain) 11 a and a P ⁇ type silicon substrate 1 increases due to the generation of crystalline defects in the silicon located near the groove 5 .
- an N type diffusion layer (source) 11 b and the P ⁇ type silicon substrate 1 are grounded with a voltage of 3.3 V applied to the gate electrode 9 and 3.3 V applied to the drain 11 a to operate the MOS transistor, a depletion layer 19 is generated in the vicinity of the interface between the drain 11 a and the P ⁇ type silicon substrate 1 .
- the depletion layer 19 may involve the crystalline defect 20 where electron-hole ( 21 - 22 ) pairs are generated, thereby increasing the leak current flowing through the NP junction between the drain 11 a and the P ⁇ type silicon substrate 1 .
- the present invention has been attained to solve the problem described above, and an object of the present invention is to provide a semiconductor device wherein the current consumption is reduced by controlling the generation of crystalline defects, and another object of the present invention is to provide a method of producing the semiconductor device.
- a semiconductor device of the first invention is a semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein the plurality of transistors are isolated from each other by filling a groove formed by etching the semiconductor substrate with an insulating material, while a nitride layer is provided by nitriding the semiconductor in the inner surface of the groove.
- a semiconductor device of the second invention is that wherein the nitride layer is formed by a nitriding treatment using a nitrogen monoxide gas.
- a semiconductor device of the third invention is a semiconductor device, wherein the nitriding treatment is carried out at a temperature of not less than 800° C.
- a semiconductor device of the fourth invention is a semiconductor device, wherein the nitriding treatment is carried out by using an ammonia gas.
- a semiconductor device of the fifth invention is a semiconductor device, wherein the nitriding treatment carried out at a temperature of not less than 700° C.
- a method of producing the semiconductor device according to the sixth invention is a method of producing the semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein a step of isolating the plurality of transistors from each other comprises a step of forming a groove by etching the semiconductor substrate, a step of nitriding the semiconductor of the inner surface of the groove thereby to form a nitride layer, and a step of filling the groove with an insulating material.
- a method of producing the semiconductor device according to the seventh invention is a method, wherein the step of forming the nitride layer comprises a step of carrying out the nitriding treatment using a nitrogen monoxide gas.
- a method of producing the semiconductor device according to the eighth invention is a method, wherein the nitriding treatment is carried out at a temperature of not less than 800° C.
- a method of producing the semiconductor device according to the ninth invention is a method, wherein the step of forming the nitride layer comprises a step of nitriding treatment carried out by using an ammonia gas.
- a method of producing the semiconductor device according to the tenth invention is a method, wherein the nitriding treatment is carried out at a temperature of not less than 700° C.
- the plurality of transistors are isolated from each other and the nitride layer is formed on the inner surface of the groove which constitutes the trench isolation structure, expansion of the oxide film due to the oxidation treatment after filling the groove is suppressed thereby preventing crystalline defects from being generated due to the compressive stress generated in the semiconductor substrate, thus minimizing the leak current caused by crystalline defect and improving the characteristics of the junction, and therefore it is made possible to produce the semiconductor device of low power consumption and stable operation.
- the nitriding treatment can also be effectively performed from above the insulating material in which case nitrogen gas concentrates to the interface between the semiconductor substrate,and the insulating material due to diffusion, thus forming a strong oxidation control layer.
- the nitride layer having sufficient oxidation control effect can be formed by applying the nitriding treatment with the nitrogen monoxide gas at a temperature of 800° C. or higher.
- ammonia gas can be applied from above the insulating material for the nitriding treatment in which case nitrogen concentrates to the interface between the semiconductor substrate and the insulating material due to diffusion, thus forming a strong oxidation control layer.
- the nitride layer having sufficient oxidation control effect can be formed by applying the nitriding treatment using ammonia gas at a temperature of 700° C. or higher.
- FIG. 1 is a cross sectional view showing the semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a cross sectional view showing a first step of the method of producing the semiconductor device according to the first embodiment of the present invention
- FIG. 3 is a cross sectional view showing a second step of the method of producing the semiconductor device according to the first embodiment of the present invention
- FIG. 4 is a cross sectional view showing a third step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 5 is a cross sectional view showing a fourth step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 6 is a cross sectional view showing a fifth step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 7 is a cross sectional view showing a sixth step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 8 is a cross sectional view showing a seventh step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 9 is a cross sectional view showing an eighth step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 10 is a cross sectional view showing a ninth step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 11 is a cross sectional view showing a tenth step of the method of producing the semiconductor device according to the first embodiment of the present invention.
- FIG. 12 is a cross sectional view showing a first step of the method of producing the semiconductor device of the prior art
- FIG. 13 is a cross sectional view showing a second step of the method of producing the semiconductor device of the prior art
- FIG. 14 is a cross sectional view showing a third step of the method of producing the semiconductor device of the prior art
- FIG. 15 is a cross sectional view showing a fourth step of the method of producing the semiconductor device of the prior art
- FIG. 16 is a cross sectional view showing a fifth step of the method of producing the semiconductor device of the prior art
- FIG. 17 is a cross sectional view showing a sixth step of the method of producing the semiconductor device of the prior art
- FIG. 18 is a cross sectional view showing a seventh step of the method of producing the semiconductor device of the prior art
- FIG. 19 is a cross sectional view showing an eighth step of the method of producing the semiconductor device of the prior art.
- FIG. 20 is a cross sectional view showing a ninth step of the method of producing the semiconductor device of the prior art
- FIG. 21 is a cross sectional view showing a tenth step of the method of producing the semiconductor device of the prior art.
- FIG. 22 is a diagram for explaining the increasing leak current through transistor junction due to crystalline defect induced by the conventional trench isolation employed in the semiconductor device of the prior art.
- FIG. 1 is a cross sectional view showing the semiconductor device according to the first embodiment of the present invention.
- numeral 1 denotes a P type silicon substrate which is a semiconductor substrate
- 5 denotes a groove
- 6 and 7 denote silicon oxide films
- 8 denotes a silicon oxidation film which is a gate oxidation film
- 9 denotes a gate electrode
- 11 denotes an impurity-doped layer
- 12 denotes a silicon oxide film
- 13 denotes a boron phosphate glass
- 14 denotes an aluminum-silicon-copper wiring
- 35 denotes a channel stopper layer
- 40 denotes an MOS transistor
- 60 denotes a nitride layer
- 80 denotes an isolation trench.
- FIGS. 2 through 11 show first through tenth step for making the trench isolation structure used in the semiconductor device shown in FIG. 1.
- the silicon oxide film 2 having a thickness of 100 ⁇ is grown on the surface of the P type silicon substrate 1 which is a semiconductor substrate by thermal oxidation step, followed by deposition of the silicon nitride film 3 having a thickness of 500 ⁇ by low pressure CVD process, and then a desired pattern of resist 4 is formed by the photolithography technology.
- the resist pattern 4 is used as a mask in etching of the silicon nitride film 3 and the silicon oxide film 2 , surface of the silicon substrate is etched to form the groove 5 having a depth of 4000 ⁇ and the resist pattern 4 is removed.
- thermal oxidation is applied to the inner surface of the groove 5 in the silicon substrate thereby to form the silicon oxide film 6 having a thickness of 500 ⁇ .
- the silicon oxide film 6 is annealed at a temperature of 800° C. or higher in nitrogen monoxide (NO) gas atmosphere which has nitriding effect, thereby to nitride the inner surface of the groove 5 in the silicon substrate 1 and form the nitride layer 60 made by nitriding of silicon included in the inner surface of the silicon substrate 1 .
- NO nitrogen monoxide
- Nitriding can be effectively performed even when applied from above the silicon oxide film 6 since nitrogen concentrates to the interface between the silicon substrate 1 and the silicon oxide film 6 due to diffusion.
- the same nitriding effect can also be achieved without the silicon oxide film 6 , and therefore nitriding process can be applied to a structure without the silicon oxide film 6 .
- the nitriding treatment may not necessarily be done by using nitrogen monoxide gas, and ammonia gas or the like which has an action to nitride the silicon surface may be employed.
- the groove 5 is filled up by depositing a silicon oxide filling 7 to a depth of 6000 ⁇ by the CVD process.
- Surface of the silicon oxide filling 7 is then smoothed by the CMP process.
- the silicon nitride film 3 is selectively removed using thermal phosphoric acid, thus forming a trench isolation structure 80 according to the first embodiment comprising the groove 5 , the silicon oxide film 6 , the silicon oxide filling 7 and the nitride layer 60 .
- boron ions are implanted with a density of 3 ⁇ 10 12 /cm 2 and an energy of 200 KeV by ion implantation process, thereby to form the channel stopper layer 35 .
- the silicon oxide film 2 is removed by using hydrofluoric acid solution.
- a silicon oxide film having a thickness of 50 ⁇ which would become the gate oxidation film 8 of a transistor is grown by the thermal oxidation process, a phosphorus-doped polycrystal silicon is deposited to a thickness of about 3000 ⁇ by the low pressure CVD process and, after forming a desired resist pattern 10 by the photolithography technology, the phosphorus-doped polycrystal silicon is etched with the resist pattern 10 used as a mask, thereby forming the gate electrode 9 .
- arsenic ions are implanted with a density of 4 ⁇ 10 15 /cm 2 and an energy of 50 KeV by the ion implantation process, thereby to form the impurity-doped layer 11 of a conductivity type different from that of the silicon substrate 1 .
- heat treatment is applied in nitrogen atmosphere at 800° C. for about 30 minutes, thereby to form the N-type diffusion layer 11 which is an impurity-doped layer by activating the arsenic ions.
- a MOS transistor 40 comprising the gate oxidation film 8 , the gate electrode 9 and the impurity-doped layer 11 is formed.
- a boron phosphate glass 13 is deposited by the CVD process. After reflowing the boron phosphate glass 13 through heat treatment applied in nitrogen atmosphere at 850° C. for 30 minutes, a resist pattern (not shown) is formed by the photolithography technology. The resist pattern is used as a mask in etching the boron phosphate glass 13 and the silicon oxide film 12 to make contact holes (not shown), followed by deposition of an aluminum-silicon-copper alloy film by sputtering technique.
- a resist (not shown) is applied in a desired pattern by the photolithography technology, the resist pattern is used as a mask for etching the aluminum-silicon-copper alloy film, thereby to form an aluminum-silicon-copper wiring 14 and forming the semiconductor device shown in FIG. 1.
- the nitride layer having an effect of controlling the oxidation is formed on the inner surface of the groove by nitriding the silicon included therein after etching of the trench, volumetric expansion inside the trench can be controlled during oxidation such as gate oxidation after forming the trench, thereby making it possible to minimize the compressive stress generated by the volumetric expansion in the active region.
- Minimization of the stress in turn enables it to prevent crystalline defects from being generated in the silicon substrate, thus suppressing leak current caused by crystalline defect flowing through the NP junction.
- the nitride layer can be formed on the inner surface of the trench.
- the semiconductor device capable of controlling the volumetric expansion in the trench can be produced also by oxidation such as gate oxidation after forming the trench isolation structure.
Abstract
Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation process after forming the trench isolation structure is controlled thereby making it possible to prevent deterioration of the electrical characteristics of the semiconductor device.
A nitriding treatment is applied to the trench surface of the silicon substrate after forming the trench by etching, thereby to form a thin nitride layer having a better effect of preventing oxidation in the interface of silicon.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device, and a method of producing the same. More particularly, it relates to a trench isolation structure for electrically isolating semiconductor elements.
- 2. Description of the Related Art
- Trench isolation structure formed between semiconductor elements such as transistors has been becoming increasingly important as semiconductor devices are packaged with higher density and higher performance.
- A method of producing trench isolation structure of the prior art used in the conventional semiconductor device will be described below with reference to FIGS. 12 through 21.
- FIGS. 12 through 21 are cross sectional views showing first through tenth steps of the method of producing a trench isolation structure of the prior art.
- First, referring to FIG. 12, a
silicon oxide film 2 having thickness of 100 Å is grown on a principal plane of a P-type silicon substrate 1 by thermal oxidation process, followed by the deposition of asilicon nitride film 3 having thickness of 500 Å by low pressure CVD (Chemical Vapor Deposition) process and application of a resist to form a desiredresist pattern 4 by photolithography technology. - After etching the
silicon nitride film 3 and thesilicon oxide film 2 with theresist pattern 4 used as a mask, thesilicon substrate 1 is etched thereby to form agroove 5 having a depth of 4000 Å from the surface, and theresist pattern 4 is removed, as shown in FIG. 13. - Now referring to FIG. 14, where thermal oxidation is applied to the inner surface of the
groove 5 formed in thesilicon substrate 1, thereby to form asilicon oxide film 6 having thickness of 500 Å. - Then as shown in FIG. 15, the
groove 5 is filled up by depositing a silicon oxide filling 7 to a depth of 6000 Å by CVD process. Surface of thesilicon oxide filling 7 is smoothed by CMP (Chemical Mechanical Polishing) process. - Now referring to FIG. 16, where the
silicon nitride film 3 is selectively removed by using thermal phosphoric acid, thus forming atrench isolation structure 30 comprising thegroove 5, thesilicon oxide film 6 and thesilicon oxide filling 7. - After the
isolation trench 30 has been formed as shown in FIG. 17, boron ions are implanted with a density of 3×1012/cm2 and an energy of 200 KeV by ion implantation process, thereby to form achannel stopper layer 35. - Now referring to FIG. 18, where the
silicon oxide film 2 is removed by using hydrofluoric acid (HF) solution. - Now referring to FIG. 19, where a silicon oxide film having thickness of 50 Å which would become a
gate oxidation film 8 of a transistor is formed by thermal oxidation process, and phosphorus-doped polycrystal silicon is deposited to a thickness of about 3000 Å by low pressure CVD process. After forming a desiredresist pattern 10 by the photolithography technology, the phosphorus-doped polycrystal silicon is etched with theresist pattern 10 used as a mask, thereby forming agate electrode 9. - Then as shown in FIG. 20, after removing the
resist pattern 10, arsenic ions are implanted with a density of 4×1015/cm2 at an energy of 50 KeV by ion implantation process, thereby to form an impurity-dopedlayer 11 of a conductivity type different from that of thesilicon substrate 1. Then heat treatment is applied in nitrogen atmosphere at 800° C. for about 30 minutes, thereby to form an N-type diffusion layer 11 which is an impurity-doped layer by activating the arsenic ions. Thus an MOS (Metal Oxide Semiconductor)transistor 40 comprising thegate oxidation film 8, thegate electrode 9 and the impurity-dopedlayer 11 is formed. - Then as shown in FIG. 21, after depositing a
silicon oxide film 12 having thickness of about 1000 Å by the CVD process, aboron phosphate glass 13 is deposited by the CVD process. After reflowing theboron phosphate glass 13 through heat treatment applied in nitrogen atmosphere at 850° C. for 30 minutes, a resist pattern (not shown) is formed by photolithography technology. The resist pattern is used as a mask in etching theboron phosphate glass 13 and thesilicon oxide film 12 to make contact holes (not shown), followed by deposition of an aluminum-silicon-copper (Al—Si—Cu) alloy film by a sputtering technique. Then a resist (not shown) is applied in a desired pattern by the photolithography technology, and the resist pattern is used as a mask for etching the aluminum-silicon-copper alloy film, thereby to form an aluminum-silicon-copper wiring 14. - The semiconductor device of the prior art is constructed as described above, while semiconductor elements such as transistor are electrically isolated from each other by the trench isolation structure.
- In the semiconductor device of the prior art described above, while the
gate oxidation film 8 of the transistor is formed by thermal oxidation process after forming thetrench isolation structure 30 as shown in FIG. 19, an oxidation agent tends to diffuse into thesilicon oxide filling 7 which is embedded in thegroove 5 and react with the silicon included in the inner wall of thegroove 5, resulting in the oxidation of the silicon included in the inner wall of thegroove 5. That is, oxidation of silicon in the reaction of Si+O2→SiO2 causes silicon to turn into a silicon oxide film, while the volume increases with the ratio of silicon to silicon oxide being 1:2. In the present case, since thegroove 5 is filled with the silicon oxide filling 7, the increased volume causes a compressive stress in the silicon located near thegroove 5. The compressive stress causes crystalline defects to be generated in the silicon located near thegroove 5. - FIG. 22 is a diagram for explaining a mechanism wherein leak current flowing through an NP junction between an N-type diffusion layer (drain)11 a and a P−
type silicon substrate 1 increases due to the generation of crystalline defects in the silicon located near thegroove 5. In FIG. 22, when an N type diffusion layer (source) 11 b and the P−type silicon substrate 1 are grounded with a voltage of 3.3 V applied to thegate electrode 9 and 3.3 V applied to the drain 11 a to operate the MOS transistor, adepletion layer 19 is generated in the vicinity of the interface between the drain 11 a and the P−type silicon substrate 1. At this time, in case there iscrystalline defect 20 caused by the stress due to formation of thegroove 5 in thesilicon substrate 1, thedepletion layer 19 may involve thecrystalline defect 20 where electron-hole (21-22) pairs are generated, thereby increasing the leak current flowing through the NP junction between the drain 11 a and the P−type silicon substrate 1. - In the semiconductor device which employs the trench isolation structure of the prior art, as described above, there has been such a problem that the stress, caused by volume expansion through the oxidation of the silicon after forming the trench isolation structure, thereby increasing junction leak current and consequently causing an increased current consumption in the semiconductor device.
- The present invention has been attained to solve the problem described above, and an object of the present invention is to provide a semiconductor device wherein the current consumption is reduced by controlling the generation of crystalline defects, and another object of the present invention is to provide a method of producing the semiconductor device.
- A semiconductor device of the first invention is a semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein the plurality of transistors are isolated from each other by filling a groove formed by etching the semiconductor substrate with an insulating material, while a nitride layer is provided by nitriding the semiconductor in the inner surface of the groove.
- A semiconductor device of the second invention is that wherein the nitride layer is formed by a nitriding treatment using a nitrogen monoxide gas.
- A semiconductor device of the third invention is a semiconductor device, wherein the nitriding treatment is carried out at a temperature of not less than 800° C.
- A semiconductor device of the fourth invention is a semiconductor device, wherein the nitriding treatment is carried out by using an ammonia gas.
- A semiconductor device of the fifth invention is a semiconductor device, wherein the nitriding treatment carried out at a temperature of not less than 700° C.
- A method of producing the semiconductor device according to the sixth invention is a method of producing the semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein a step of isolating the plurality of transistors from each other comprises a step of forming a groove by etching the semiconductor substrate, a step of nitriding the semiconductor of the inner surface of the groove thereby to form a nitride layer, and a step of filling the groove with an insulating material.
- A method of producing the semiconductor device according to the seventh invention is a method, wherein the step of forming the nitride layer comprises a step of carrying out the nitriding treatment using a nitrogen monoxide gas.
- A method of producing the semiconductor device according to the eighth invention is a method, wherein the nitriding treatment is carried out at a temperature of not less than 800° C.
- A method of producing the semiconductor device according to the ninth invention is a method, wherein the step of forming the nitride layer comprises a step of nitriding treatment carried out by using an ammonia gas.
- A method of producing the semiconductor device according to the tenth invention is a method, wherein the nitriding treatment is carried out at a temperature of not less than 700° C.
- The present invention, having the configuration described above, provides the following effects.
- According to the first and the sixth inventions, since the plurality of transistors are isolated from each other and the nitride layer is formed on the inner surface of the groove which constitutes the trench isolation structure, expansion of the oxide film due to the oxidation treatment after filling the groove is suppressed thereby preventing crystalline defects from being generated due to the compressive stress generated in the semiconductor substrate, thus minimizing the leak current caused by crystalline defect and improving the characteristics of the junction, and therefore it is made possible to produce the semiconductor device of low power consumption and stable operation.
- Further according to the second and the seventh inventions, the nitriding treatment can also be effectively performed from above the insulating material in which case nitrogen gas concentrates to the interface between the semiconductor substrate,and the insulating material due to diffusion, thus forming a strong oxidation control layer.
- Also according to the third and the eighth inventions, the nitride layer having sufficient oxidation control effect can be formed by applying the nitriding treatment with the nitrogen monoxide gas at a temperature of 800° C. or higher.
- Further according to the fourth and the ninth inventions, ammonia gas can be applied from above the insulating material for the nitriding treatment in which case nitrogen concentrates to the interface between the semiconductor substrate and the insulating material due to diffusion, thus forming a strong oxidation control layer.
- Also according to the fifth and the tenth inventions, the nitride layer having sufficient oxidation control effect can be formed by applying the nitriding treatment using ammonia gas at a temperature of 700° C. or higher.
- FIG. 1 is a cross sectional view showing the semiconductor device according to the first embodiment of the present invention;
- FIG. 2 is a cross sectional view showing a first step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 3 is a cross sectional view showing a second step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 4 is a cross sectional view showing a third step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 5 is a cross sectional view showing a fourth step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 6 is a cross sectional view showing a fifth step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 7 is a cross sectional view showing a sixth step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 8 is a cross sectional view showing a seventh step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 9 is a cross sectional view showing an eighth step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 10 is a cross sectional view showing a ninth step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 11 is a cross sectional view showing a tenth step of the method of producing the semiconductor device according to the first embodiment of the present invention;
- FIG. 12 is a cross sectional view showing a first step of the method of producing the semiconductor device of the prior art;
- FIG. 13 is a cross sectional view showing a second step of the method of producing the semiconductor device of the prior art;
- FIG. 14 is a cross sectional view showing a third step of the method of producing the semiconductor device of the prior art;
- FIG. 15 is a cross sectional view showing a fourth step of the method of producing the semiconductor device of the prior art;
- FIG. 16 is a cross sectional view showing a fifth step of the method of producing the semiconductor device of the prior art;
- FIG. 17 is a cross sectional view showing a sixth step of the method of producing the semiconductor device of the prior art;
- FIG. 18 is a cross sectional view showing a seventh step of the method of producing the semiconductor device of the prior art;
- FIG. 19 is a cross sectional view showing an eighth step of the method of producing the semiconductor device of the prior art;
- FIG. 20 is a cross sectional view showing a ninth step of the method of producing the semiconductor device of the prior art;
- FIG. 21 is a cross sectional view showing a tenth step of the method of producing the semiconductor device of the prior art; and
- FIG. 22 is a diagram for explaining the increasing leak current through transistor junction due to crystalline defect induced by the conventional trench isolation employed in the semiconductor device of the prior art.
-
Embodiment 1 - Now the first embodiment of the present invention will be described below with reference to FIGS. 1 through 11.
- FIG. 1 is a cross sectional view showing the semiconductor device according to the first embodiment of the present invention. In FIG. 1,
numeral 1 denotes a P type silicon substrate which is a semiconductor substrate, 5 denotes a groove, 6 and 7 denote silicon oxide films, 8 denotes a silicon oxidation film which is a gate oxidation film, 9 denotes a gate electrode, 11 denotes an impurity-doped layer, 12 denotes a silicon oxide film, 13 denotes a boron phosphate glass, 14 denotes an aluminum-silicon-copper wiring, 35 denotes a channel stopper layer, 40 denotes an MOS transistor, 60 denotes a nitride layer and 80 denotes an isolation trench. - Now a method of producing the semiconductor device will be described below with reference to FIGS.2 through
- FIGS. 2 through 11 show first through tenth step for making the trench isolation structure used in the semiconductor device shown in FIG. 1.
- First, with reference to FIG. 2, the
silicon oxide film 2 having a thickness of 100 Å is grown on the surface of the Ptype silicon substrate 1 which is a semiconductor substrate by thermal oxidation step, followed by deposition of thesilicon nitride film 3 having a thickness of 500 Å by low pressure CVD process, and then a desired pattern of resist 4 is formed by the photolithography technology. - Then as shown in FIG. 3, the resist
pattern 4 is used as a mask in etching of thesilicon nitride film 3 and thesilicon oxide film 2, surface of the silicon substrate is etched to form thegroove 5 having a depth of 4000 Å and the resistpattern 4 is removed. - Then as shown in FIG. 4, thermal oxidation is applied to the inner surface of the
groove 5 in the silicon substrate thereby to form thesilicon oxide film 6 having a thickness of 500 Å. - Now with reference to FIG. 5, the
silicon oxide film 6 is annealed at a temperature of 800° C. or higher in nitrogen monoxide (NO) gas atmosphere which has nitriding effect, thereby to nitride the inner surface of thegroove 5 in thesilicon substrate 1 and form thenitride layer 60 made by nitriding of silicon included in the inner surface of thesilicon substrate 1. Nitriding can be effectively performed even when applied from above thesilicon oxide film 6 since nitrogen concentrates to the interface between thesilicon substrate 1 and thesilicon oxide film 6 due to diffusion. The same nitriding effect can also be achieved without thesilicon oxide film 6, and therefore nitriding process can be applied to a structure without thesilicon oxide film 6. Also the nitriding treatment may not necessarily be done by using nitrogen monoxide gas, and ammonia gas or the like which has an action to nitride the silicon surface may be employed. - Then as shown in FIG. 6, the
groove 5 is filled up by depositing a silicon oxide filling 7 to a depth of 6000 Å by the CVD process. Surface of the silicon oxide filling 7 is then smoothed by the CMP process. - Then as shown in FIG. 7, the
silicon nitride film 3 is selectively removed using thermal phosphoric acid, thus forming atrench isolation structure 80 according to the first embodiment comprising thegroove 5, thesilicon oxide film 6, the silicon oxide filling 7 and thenitride layer 60. - Now taking reference to FIG. 8, boron ions are implanted with a density of 3×1012/cm2 and an energy of 200 KeV by ion implantation process, thereby to form the
channel stopper layer 35. - Then as shown in FIG. 9, the
silicon oxide film 2 is removed by using hydrofluoric acid solution. - Then as shown in FIG. 10, a silicon oxide film having a thickness of 50 Å which would become the
gate oxidation film 8 of a transistor is grown by the thermal oxidation process, a phosphorus-doped polycrystal silicon is deposited to a thickness of about 3000 Å by the low pressure CVD process and, after forming a desired resistpattern 10 by the photolithography technology, the phosphorus-doped polycrystal silicon is etched with the resistpattern 10 used as a mask, thereby forming thegate electrode 9. - Then as shown in FIG. 11, after removing the resist
pattern 10, arsenic ions are implanted with a density of 4 ×1015/cm2 and an energy of 50 KeV by the ion implantation process, thereby to form the impurity-dopedlayer 11 of a conductivity type different from that of thesilicon substrate 1. Then heat treatment is applied in nitrogen atmosphere at 800° C. for about 30 minutes, thereby to form the N-type diffusion layer 11 which is an impurity-doped layer by activating the arsenic ions. Thus aMOS transistor 40 comprising thegate oxidation film 8, thegate electrode 9 and the impurity-dopedlayer 11 is formed. - Then after depositing the
silicon oxide film 12 having a thickness of about 1000 Å by the CVD process, aboron phosphate glass 13 is deposited by the CVD process. After reflowing theboron phosphate glass 13 through heat treatment applied in nitrogen atmosphere at 850° C. for 30 minutes, a resist pattern (not shown) is formed by the photolithography technology. The resist pattern is used as a mask in etching theboron phosphate glass 13 and thesilicon oxide film 12 to make contact holes (not shown), followed by deposition of an aluminum-silicon-copper alloy film by sputtering technique. Then a resist (not shown) is applied in a desired pattern by the photolithography technology, the resist pattern is used as a mask for etching the aluminum-silicon-copper alloy film, thereby to form an aluminum-silicon-copper wiring 14 and forming the semiconductor device shown in FIG. 1. - According to the first embodiment of the semiconductor device and the method of producing the semiconductor device, as described above, since the nitride layer having an effect of controlling the oxidation is formed on the inner surface of the groove by nitriding the silicon included therein after etching of the trench, volumetric expansion inside the trench can be controlled during oxidation such as gate oxidation after forming the trench, thereby making it possible to minimize the compressive stress generated by the volumetric expansion in the active region.
- Minimization of the stress in turn enables it to prevent crystalline defects from being generated in the silicon substrate, thus suppressing leak current caused by crystalline defect flowing through the NP junction. Further, since nitriding treatment is applied after the trench has been etched out and before the trench is filled up by the CVD oxidation or the like, the nitride layer can be formed on the inner surface of the trench. As the nitriding layer has a strong effect of suppressing oxidation, the semiconductor device capable of controlling the volumetric expansion in the trench can be produced also by oxidation such as gate oxidation after forming the trench isolation structure.
Claims (12)
1. A semiconductor, comprising:
(a) a substrate having a surface, said surface being formed with a groove to define a first region on one side of said groove and a second region on the opposite side of said groove;
(b) first and second transistors provided in said first and second region, respectively,
each of said first and second transistors having a gate oxidation film provide on said surface, a gate electrode provided on said gate oxidation film, and impurity-doped layers positioned on either sides of said gate electrode and between said substrate and gate oxidation film;
(c) an insulator filled in said groove; and
(d) a nitride layer positioned on a surface of said groove to separate said insulator from a surface of said groove.
2. The semiconductor device according to claim 1 , wherein said nitride layer is formed on the full surface of said groove.
3. The semiconductor device according to claim 1 , further comprising an oxidation film formed on the surface of the groove, wherein said nitride layer is provided by nitriding said surface of the groove through an oxidation film.
4. The semiconductor device according to claim 1 , wherein said insulator is an oxidation film formed by CVD method.
5. The semiconductor device according to claim 1 , wherein said nitride layer is formed to prevent said surface of the groove from being oxidized.
6. A method of producing the semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein a step of isolating the plurality of transistors from each other comprising the steps of:
(a) forming a groove by etching the semiconductor substrate;
(b) nitriding the surface of the groove to form a nitride layer; and
(c) filling the groove with an insulator.
7. The method according to claim 6 , further comprising the step of:
forming an oxidation film on the surface of the groove, wherein the step of nitriding the surface of the groove comprises a step of nitriding treatment carried out by nitriding the surface of the groove through the oxidation film thereby to form a nitride layer on the surface of the groove.
8. The method according to claim 6 , wherein the step of nitriding the surface of the groove comprises a step of nitriding treatment of the surface of the groove carried out by using a nitrogen monoxide gas.
9. The method according to claim 8 , wherein the nitriding treatment is carried out at a temperature of not less than 800° C.
10. The method according to claim 6 , wherein the step of nitriding the surface of the groove comprises a step of nitriding treatment of the surface of the groove carried out by using an ammonia gas.
11. The method according to claim 10 , wherein the nitriding treatment is carried out at a temperature of not less than 700° C.
12. The method according to claim 6 , wherein the step of filling the groove with an insulator is comprises a step of filling the groove with an oxidation film formed by CVD method.
Priority Applications (1)
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US10/193,176 US20020179996A1 (en) | 1998-10-22 | 2002-07-12 | Semiconductor device having a nitride barrier for preventing formation of structural defects |
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JPP10-301010 | 1998-10-22 | ||
JP10301010A JP2000133700A (en) | 1998-10-22 | 1998-10-22 | Semiconductor device and manufacture thereof |
US09/352,401 US6441444B1 (en) | 1998-10-22 | 1999-07-14 | Semiconductor device having a nitride barrier for preventing formation of structural defects |
US10/193,176 US20020179996A1 (en) | 1998-10-22 | 2002-07-12 | Semiconductor device having a nitride barrier for preventing formation of structural defects |
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US09/352,401 Division US6441444B1 (en) | 1998-10-22 | 1999-07-14 | Semiconductor device having a nitride barrier for preventing formation of structural defects |
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US09/352,401 Expired - Fee Related US6441444B1 (en) | 1998-10-22 | 1999-07-14 | Semiconductor device having a nitride barrier for preventing formation of structural defects |
US10/193,176 Abandoned US20020179996A1 (en) | 1998-10-22 | 2002-07-12 | Semiconductor device having a nitride barrier for preventing formation of structural defects |
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US20130056830A1 (en) * | 2011-09-02 | 2013-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Structure and Method |
US8877614B2 (en) | 2011-10-13 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacer for semiconductor structure contact |
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JP5121102B2 (en) * | 2001-07-11 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
KR100672753B1 (en) | 2003-07-24 | 2007-01-22 | 주식회사 하이닉스반도체 | Method for preventing electron trapping of trench isolation |
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US20050205963A1 (en) * | 2004-03-16 | 2005-09-22 | Johnson David A | Integrated anneal cap/ ion implant mask/ trench isolation structure for III-V devices |
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KR100766277B1 (en) | 2005-06-09 | 2007-10-15 | 동부일렉트로닉스 주식회사 | Method of forming isolating layer for semiconductor device |
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JP5285835B2 (en) * | 2005-07-13 | 2013-09-11 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP2010021235A (en) * | 2008-07-09 | 2010-01-28 | Toshiba Corp | Semiconductor device and its manufacturing method |
JP6334370B2 (en) * | 2014-11-13 | 2018-05-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP2018133585A (en) * | 2018-04-26 | 2018-08-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
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US6441444B1 (en) | 2002-08-27 |
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