US20020167836A1 - Retention time of memory cells by reducing leakage current - Google Patents

Retention time of memory cells by reducing leakage current Download PDF

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US20020167836A1
US20020167836A1 US09/855,165 US85516501A US2002167836A1 US 20020167836 A1 US20020167836 A1 US 20020167836A1 US 85516501 A US85516501 A US 85516501A US 2002167836 A1 US2002167836 A1 US 2002167836A1
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coupled
memory cell
access
transistor
leakage current
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US6487107B1 (en
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Raj Jain
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from PCT/DE1999/003133 external-priority patent/WO2000019444A1/en
Priority claimed from PCT/DE1999/003151 external-priority patent/WO2000019437A2/en
Priority claimed from US09/615,987 external-priority patent/US6304478B1/en
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Priority to US09/855,165 priority Critical patent/US6487107B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the present invention relates generally to integrated circuits. More particularly, the invention relates to reducing leakage current in integrated circuits.
  • Integrated circuits such as digital signal processors (DSPs) include on-chip memory to store information.
  • the on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC.
  • Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes.
  • a sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
  • FIG. 1 shows a conventional SRAM cell 101 .
  • the SRAM cell comprises first and second transistors 110 and 120 coupled to a latch 130 , which stores a bit of information.
  • One transistor is coupled to a bit line 140 and the other is coupled to a bit line complement 141 while the gates are coupled to a word line 135 .
  • the latch includes first and second inverters 133 and 134 , each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
  • the present invention relates generally to memory cells. More particularly, the invention relates to improving retention time in memory cells.
  • the memory cell comprises first and second access transistors coupled to respective first and second terminals of a storage transistor. Bit lines are coupled to first terminals of the access transistors and word lines are coupled to the gates of the access transistors.
  • a degraded logic 0 is written to the memory cell during a write 0, causing the memory cell to store a degraded logic 0. Storing a degraded logic 0 in the memory cell reduces leakage current.
  • FIG. 1 shows a conventional SRAM cell
  • FIG. 2 shows a memory cell in accordance with one embodiment of the invention.
  • FIG. 2 shows a memory cell 201 in accordance with one embodiment of the invention.
  • the memory cell comprises first and second access transistors 220 and 260 coupled in series to a storage transistor 240 .
  • the transistors in one embodiment, comprise n-FETs.
  • the memory cell can also be implemented with p-FETs or a combination of n and p-FETs.
  • the access transistors can serve as memory access ports, each coupled to a bit line ( 240 or 241 ) and a word line ( 235 or 236 ).
  • the first access transistor's first terminal 221 is coupled to the bit line 240 and its gate is coupled to the word line 235 .
  • the second access transistor's first terminal 261 is coupled to bit line 241 and its gate is coupled to word line 236 .
  • the memory cell can be accessed either through the first or second port. Refreshing of the memory cell can also be performed through the access ports.
  • Second terminals 222 and 262 of the access transistors are coupled respectively to first and second terminals 241 and 242 of the storage transistor.
  • a gate 243 of the storage transistor is coupled to an active signal to render the transistor conductive.
  • the storage transistor is an n-FET with its gate coupled to an active signal.
  • the active signal comprises V DD .
  • a memory access from the first port is performed by activating the word line 235 (e.g., logic 1) to render the first access transistor conductive.
  • the word line 235 e.g., logic 1
  • node A is coupled to the bit line via the first access transistor's first terminal 221 .
  • the charge stored at node A is transferred to the bit line for a read access or the charge on the bit line is transferred to node A for a write access by write circuitry.
  • Accessing the second port of the memory cell is achieved by selecting the word line 236 to couple node A to the bit line 241 .
  • a refresh can be performed in the first or second port by activating the first or second word line.
  • the first port of the memory cell serves as an access port and the second port of the memory cell serves as a dedicated refresh port from which refreshes are performed.
  • the first port is coupled to a bit line and a word line while the refresh port is coupled to a refresh bit line and a refresh word line.
  • write circuitry 280 coupled to the bit lines is designed to write a degraded logic 0 into the memory cell during a write zero operation.
  • the degraded logic 0 is greater than V ss (0V).
  • the degraded logic 0 is equal to V ss +V d , where V d is greater than 0V and less than gate threshold voltage of the access transistor.
  • V d is from 0.1-0.4V.
  • the memory cell is fabricated on a substrate using conventional techniques.
  • Various cell arrangements or layouts such as those described in, for example, parent patent application, titled: “Layout for a SemiConductor Memory”, U.S. Ser. No. 09/615,987 (attorney docket number: 98P 02864US) and which is herein incorporated by reference for all purposes, are also useful.

Abstract

A memory cell having first and second access transistors coupled to a storage transistor is disclosed. During a write 0 operation, a degraded logic 0 is written into the memory cell. By storing a degraded logic 0, the leakage current is reduced.

Description

  • This is a continuation-in-part of patent applications, titled: “Dual-Port Memory Cell”, U.S. Ser. No. ______ (attorney docket number: 98P 02816US; “Single-Port Memory Cell”, U.S. Ser. No. ______ (attorney docket number: 98P 02842US) and “Layout for a SemiConductor Memory”, U.S. Ser. No. 09/615,987 (attorney docket number: 98P 02864US).[0001]
    • FIELD OF THE INVENTION
  • The present invention relates generally to integrated circuits. More particularly, the invention relates to reducing leakage current in integrated circuits. [0002]
    • BACKGROUND OF THE INVENTION
  • Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair. [0003]
  • FIG. 1 shows a [0004] conventional SRAM cell 101. The SRAM cell comprises first and second transistors 110 and 120 coupled to a latch 130, which stores a bit of information. One transistor is coupled to a bit line 140 and the other is coupled to a bit line complement 141 while the gates are coupled to a word line 135. The latch includes first and second inverters 133 and 134, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
  • Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime. In order to restore the information stored in the cell, a refresh operation is required. Typically, refreshing of memory cells interrupt the normal operation, adversely impacting performance. [0005]
  • As evidenced from the above discussion, it is desirable to provide a memory cell with reduced leakage current in order to improve retention time. [0006]
    • SUMMARY OF THE INVENTION
  • The present invention relates generally to memory cells. More particularly, the invention relates to improving retention time in memory cells. In one embodiment, the memory cell comprises first and second access transistors coupled to respective first and second terminals of a storage transistor. Bit lines are coupled to first terminals of the access transistors and word lines are coupled to the gates of the access transistors. In one embodiment, a degraded logic 0 is written to the memory cell during a write 0, causing the memory cell to store a degraded logic 0. Storing a degraded logic 0 in the memory cell reduces leakage current.[0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a conventional SRAM cell; and [0008]
  • FIG. 2 shows a memory cell in accordance with one embodiment of the invention. [0009]
    • PREFERRED EMBODIMENTS OF THE INVENTION
  • FIG. 2 shows a memory cell [0010] 201 in accordance with one embodiment of the invention. The memory cell comprises first and second access transistors 220 and 260 coupled in series to a storage transistor 240. The transistors, in one embodiment, comprise n-FETs. The memory cell can also be implemented with p-FETs or a combination of n and p-FETs.
  • The access transistors can serve as memory access ports, each coupled to a bit line ([0011] 240 or 241) and a word line (235 or 236). In one embodiment, the first access transistor's first terminal 221 is coupled to the bit line 240 and its gate is coupled to the word line 235. Similarly, the second access transistor's first terminal 261 is coupled to bit line 241 and its gate is coupled to word line 236. The memory cell can be accessed either through the first or second port. Refreshing of the memory cell can also be performed through the access ports.
  • [0012] Second terminals 222 and 262 of the access transistors are coupled respectively to first and second terminals 241 and 242 of the storage transistor. A gate 243 of the storage transistor is coupled to an active signal to render the transistor conductive. In one embodiment, the storage transistor is an n-FET with its gate coupled to an active signal. In one embodiment, the active signal comprises VDD. As such, when power is applied to the IC, the storage transistor is rendered conductive to couple the first and second terminals together to form node A. When power is removed from the IC, the first and second terminals are isolated from each other.
  • A memory access from the first port is performed by activating the word line [0013] 235 (e.g., logic 1) to render the first access transistor conductive. As a result, node A is coupled to the bit line via the first access transistor's first terminal 221. The charge stored at node A is transferred to the bit line for a read access or the charge on the bit line is transferred to node A for a write access by write circuitry. Accessing the second port of the memory cell is achieved by selecting the word line 236 to couple node A to the bit line 241. A refresh can be performed in the first or second port by activating the first or second word line.
  • In another embodiment, the first port of the memory cell serves as an access port and the second port of the memory cell serves as a dedicated refresh port from which refreshes are performed. The first port is coupled to a bit line and a word line while the refresh port is coupled to a refresh bit line and a refresh word line. The operation of such a memory cell is described in concurrently filed patent application “Memory Architecture with Refresh and Sense Amplifiers”, U.S. Ser. No. ______ (attorney docket number 00E 16984SG), which is herein incorporated by reference for all purposes. [0014]
  • In accordance with the invention, write [0015] circuitry 280 coupled to the bit lines, is designed to write a degraded logic 0 into the memory cell during a write zero operation. In one embodiment, the degraded logic 0 is greater than Vss (0V). The degraded logic 0 is equal to Vss+Vd, where Vd is greater than 0V and less than gate threshold voltage of the access transistor. In one embodiment Vd is from 0.1-0.4V. By writing a degraded logic 0 into the memory cell, the gate to source voltage of the access transistors is reduced. This reduces the leakage current through the channels of the access transistors, thereby improving the cells retention time as well as reducing power consumption.
  • The memory cell is fabricated on a substrate using conventional techniques. Various cell arrangements or layouts, such as those described in, for example, parent patent application, titled: “Layout for a SemiConductor Memory”, U.S. Ser. No. 09/615,987 (attorney docket number: 98P 02864US) and which is herein incorporated by reference for all purposes, are also useful. [0016]
  • While the invention has been particularly shown and described with reference to various embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from the spirit and scope thereof. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents. [0017]

Claims (1)

What is claimed is:
1. A memory cell comprising:
first and second access transistors, each with a gate and first and second terminals
first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to a first terminal of the second transistor;
first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor;
a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors; and
sense amplifiers coupled to the first and second bit lines, the sense amplifier, during a write logic 0 operation, causes a degraded logic 0 to be stored in the storage transistor.
US09/855,165 1999-09-29 2001-05-14 Retention time of memory cells by reducing leakage current Expired - Lifetime US6487107B1 (en)

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US09/855,165 US6487107B1 (en) 1999-09-29 2001-05-14 Retention time of memory cells by reducing leakage current

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
PCT/DE1999/003133 WO2000019444A1 (en) 1998-09-30 1999-09-29 Single-port memory location
PCT/DE1999/003151 WO2000019437A2 (en) 1998-09-30 1999-09-30 Dual-port memory location
US09/615,987 US6304478B1 (en) 1998-09-30 2000-07-14 Layout for a semiconductor memory
US09/855,165 US6487107B1 (en) 1999-09-29 2001-05-14 Retention time of memory cells by reducing leakage current

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/615,987 Continuation-In-Part US6304478B1 (en) 1998-09-30 2000-07-14 Layout for a semiconductor memory

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7467256B2 (en) 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
US7555630B2 (en) 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6711081B1 (en) * 2002-09-19 2004-03-23 Infineon Technologies Aktiengesellschaft Refreshing of multi-port memory in integrated circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0146075B1 (en) * 1995-05-25 1998-11-02 문정환 Semiconductor memory cell
US5581501A (en) * 1995-08-17 1996-12-03 Altera Corporation Nonvolatile SRAM cells and cell arrays
KR100230740B1 (en) * 1996-06-29 1999-11-15 김영환 A sram and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7555630B2 (en) 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US7467256B2 (en) 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures

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