US20020155637A1 - Flip chip interconnected structure and a fabrication method thereof - Google Patents

Flip chip interconnected structure and a fabrication method thereof Download PDF

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Publication number
US20020155637A1
US20020155637A1 US09/895,554 US89555401A US2002155637A1 US 20020155637 A1 US20020155637 A1 US 20020155637A1 US 89555401 A US89555401 A US 89555401A US 2002155637 A1 US2002155637 A1 US 2002155637A1
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Prior art keywords
chip
solder
region
substrate
locating region
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US09/895,554
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Shih-Chang Lee
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, SHIH-CHANG
Priority to US10/177,898 priority Critical patent/US6624004B2/en
Publication of US20020155637A1 publication Critical patent/US20020155637A1/en
Abandoned legal-status Critical Current

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Definitions

  • a flip chip interconnected technology utilizes solder bumps on bonding pads of a chip to electrically connect to a substrate. Comparing the flip chip interconnected method to a wire bonding method and a tape automatic bonding method, the circular path of the flip chip interconnected package is shorter and the electrical properties are better.
  • the bumps are arranged in a matrix shape; thus, the amount of pin outs of the chip is significantly increased. Since the flip chip technique is faster, denser, thinner, lighter and provides a low cost package, one can expect the flip chip technique to replace wire bonding.
  • FIGS. 1 and 2 illustrate schematic views of a conventional flip chip package.
  • a chip 110 has an active surface 112 , and a plurality of bonding pads 114 are arranged on the active surface 112 .
  • a plurality of bumps 116 are formed on the bonding pads 114 of the chip 110 .
  • a substrate 120 has a surface 122 , and a plurality of nodes 124 are formed on the surface 122 .
  • a position of each node 124 corresponds to a position of each bump 116 .
  • a stencil printing process is carried out to apply solder paste onto the substrate 120 .
  • a plurality of solder structures 130 are formed on the nodes 124 of the substrate 120 . Referring to FIGS.
  • a bonding process is performed to bond the chip 110 to the substrate 120 .
  • the bumps 116 of the chip 110 are bonded to the solder structures 130 of the substrate 120 in a reflow oven.
  • a reflow method allows the bumps 116 to combine with the solder structures 130 to form a plurality of solder balls 140 .
  • the chip 110 is electrically connected to the substrate 120 by the solder balls 140 .
  • a filling process is carried out to fill a gap between the chip 110 and the substrate 120 with a molding compound 150 , and the molding compound 150 encapsulates the solder balls 140 .
  • a conventional method utilizes a clamp (not shown) to hold the chip 110 and pre-heat the chip 110 for a while during a bonding process. Once the heat is transferred to the bumps 116 , the bumps 116 will combine with the solder structures 130 to form the solder balls 140 . Thus the chip 110 is electrically connected to the substrate 120 . Although this method can prevent the substrate from bending, the pre-heating process on the chip 110 can damage the chip 110 because the chip is pre-heated for about 20 to 30 seconds at a temperature of about 200°. The conventional method complicates the fabrication process and the quality of the product is not reliable.
  • a molding compound is filled in between the chip and the substrate and is used to encapsulate the solder balls.
  • the solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region.
  • a heating process is carried out to combine the bumps and solder structures to form a plurality of solder balls.
  • the solder balls are bonded respectively to the bonding pads and the nodes.
  • the chip is bonded to the chip locating region of the substrate through the solder balls.
  • a stencil printing board has a plurality of openings. The stencil printing board is located on the substrate and the nodes are exposed by the openings. The openings are filled with the solder paste by a screen printing method. Positions of the solder paste correspond to positions of the nodes.
  • the solder paste forms solder structures with various sizes because the sizes of the openings are different.
  • the steps of the method comprise first providing a chip having an active surface.
  • a plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads.
  • a substrate having a surface is provided, wherein a chip locating region is on the surface.
  • a solder mask layer and a plurality of nodes are formed on the chip locating region.
  • a plurality of solder mask openings are formed on the solder mask layer, and the nodes are exposed by the solder mask openings, wherein the solder mask openings have various sizes. Solder paste is used to cover the chip locating region and the nodes.
  • FIGS. 1 and 2 are schematic views of a conventional flip chip package.
  • FIG. 3 is a schematic view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention.
  • FIG. 3A is a schematic top view of a stencil printing board.
  • FIG. 4 is a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention.
  • FIG. 4A is a schematic magnified view of a solder ball in accordance with a preferred embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention.
  • FIGS. 6, 7 and 8 are schematic cross-sectional views of a flip chip interconnected structure in accordance with another preferred embodiment of the present invention.
  • FIG. 6A is a schematic top view of solder mask openings on a substrate.
  • FIG. 3 illustrates a schematic view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention.
  • a chip comprises an active surface 212 .
  • a plurality of bonding pads 214 which are formed on the active surface 212 have a plurality of bumps 216 .
  • a substrate 220 comprises a surface 222 and a chip locating region 224 on which a chip is located.
  • a plurality of nodes 226 are formed on the chip locating region 224 .
  • FIG. 3A illustrates a schematic top view of a stencil printing board.
  • a stencil printing board 230 has a plurality of openings 232 .
  • the stencil printing board 230 is located on a substrate 220 , and the nodes 226 , which are located at the chip locating region 224 , are exposed by the openings 232 .
  • the openings 232 are filled with solder paste by a screen printing method.
  • the stencil printing board 230 is removed and the solder paste 240 located in the openings are remained on the surface 222 of the substrate. Positions of the solder paste 240 correspond to positions of the nodes 226 .
  • the openings 232 are arranged in a matrix shape, and sizes of the openings 232 located at a peripheral region of the stencil printing board 230 are larger than sizes of the openings near a center region of the stencil printing board 230 . Therefore, the amount of solder paste filled in the opening 232 at the peripheral region is more than the amount of solder paste filled in the openings 232 at the center region.
  • FIG. 4 illustrates a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention.
  • a bonding process is carried out to bond the active surface 212 of the chip 210 to the surface of the substrate 222 .
  • a reflow process is utilized to bond the bumps 216 to the solder paste 240 into solder balls 250 , which are bonded to the bonding pads 214 and the nodes 226 .
  • the active surface 212 of the chip 210 is bonded onto the surface of chip locating region 224 by the solder balls 250 . Since the sizes of the openings 232 are larger at the peripheral region than at the center region, sizes of solder balls 250 are larger at a peripheral region of the chip locating region 224 than at a center region of the chip locating region 224 .
  • FIG. 4A illustrates a schematic magnified view of a solder ball in accordance with a preferred embodiment of the present invention.
  • the bumps 216 are made of a material such as a tin/lead alloywith a ratio of about 5/95 and an eutectic point of approximately 312°.
  • the solder paste 240 is made of a material such as a tin/lead alloy with a ratio of about 63/37 and an eutectic point of approximately 183°.
  • a temperature in a reflow oven (not shown) is about 200°. Therefore the bumps 216 will not melt but the solder paste 240 will melt and cover the periphery of the bumps 216 to form the solder balls 250 .
  • the chip 210 is bonded to the substrate 220 .
  • FIG. 5 illustrates a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention.
  • a molding process is performed to encapsulate a gap between the active surface 212 of the chip 210 and the chip locating region 224 of the substrate 222 with an encapsulating material including a molding compound 260 .
  • the molding compound 260 encapsulates the solder balls 250 .
  • the bonding between the chip 210 and the substrate 220 is much stronger at the peripheral region than at the center region. Therefore, even though bending of the substrate occurs, the bending effect does not affect the chip and the substrate. The electrical connection and the reliability between the chip 210 and the substrate 220 are improved.
  • FIGS. 6, 7 and 8 illustrate schematic cross-sectional views of a flip chip interconnected structure in accordance with another preferred embodiment of the present invention.
  • a chip 410 which is provided, has an active surface 412 .
  • a plurality of bonding pads 414 are formed on the active surface 412 of the chip 410 .
  • Bumps 416 are formed on the bonding pads 414 .
  • FIG. 6A illustrates a schematic top view of solder mask openings on a substrate. Referring to FIGS. 6 and 6A, a substrate 420 has a surface 422 .
  • the surface 422 of the substrate 420 has a chip locating region 424 .
  • a solder mask layer 426 is formed on the surface 422 of the substrate 420 .
  • a plurality of solder mask openings 428 are formed in the solder mask layer 426 and each opening 428 exposes a node 430 .
  • the solder mask openings 428 are arranged in a matrix shaped, and sizes of the solder mask openings 428 located at a center region of the chip locating region 424 are larger than sizes of the solder mask openings 428 located at a peripheral region of the chip locating region 424 .
  • solder mask openings 428 are filled with solder paste by a screen printing method, wherein the formation of the solder paste 440 corresponds to locations of the nodes 430 of the chip locating region 424 .
  • FIG. 7 illustrates a schematic cross-sectional view of a flip chip interconnected structure in accordance with another preferred embodiment of the present invention.
  • a bonding process is carried out to bond the active surface 412 of the chip 410 to the surface 422 of the substrate 420 .
  • the bumps 416 are bonded to the solder paste 440 and a reflow process is performed to combine the bumps 416 with the solder paste 440 to form a plurality of solder balls 450 .
  • the solder balls 450 are respectively bonded to the bonding pads 414 and the nodes 430 .
  • the sizes of the solder mask openings 428 located at the center region of the chip locating region 424 are larger than the sizes of the solder mask openings 428 located at the peripheral region of the chip locating region 424 .
  • bending occurs at edges of the substrate 420 . Due to the stress of the bending of the substrate 420 , the solder balls 450 at the peripheral region of the chip locating region 424 will form into a cylindrical shape. However, the solder balls 450 at the center region of the chip locating region 424 will form into a circular shape. Therefore, the shapes of the solder balls 450 are varied along the chip location region according to the sizes of the solder mask openings 428 .
  • the solder mask openings 428 have various sizes, the amount of the solder paste 440 in the solder mask openings 428 are different. By utilizing the different sizes of the solder mask openings 428 and the amount of the solder paste 440 , the solder balls 450 are formed into various shapes; thus, the bonding between the chip 410 and the substrate 420 is improved to overcome the stress caused by the bending effect. Because the sizes of the solder mask openings 428 at the center region are larger than the sizes of the solder mask openings 428 at the peripheral region, after the formation of the solder balls 450 , the solder balls located at the center region of the chip locating region 424 are shorter than the solder balls located at the peripheral region of the chip locating region 424 .
  • the substrate 420 will bend after the reflow process, and a deformation will occur. Therefore, a gap at a center region of the chip 410 and the chip locating region 424 is smaller than a gap at the ends of the chip 410 and the chip locating region 224 .
  • the solder mask openings 428 of the present invention are designed in such a way that the sizes of the solder mask openings 428 at the center region of the chip locating region 424 are larger than the solder mask openings 428 located at the peripheral region of the chip locating region 424 .
  • the present invention utilizes the various sizes of the solder mask openings 428 to control the sizes of the solder balls 250 .
  • the solder balls 450 at the center region of the chip locating region 424 are shorter than the solder balls 450 at the peripheral region of the chip locating region 424 . Therefore, despite the stress caused by the bending effect, the bonding between the substrate 420 and the chip 410 is strong enough both at the peripheral region and the center region. Therefore, the gap along the chip locating region 424 varies, but shorter solder balls 450 at the center region and higher solder ball 450 at the peripheral region allow the substrate 420 to bond strongly to the chip 410 . Thus, the bonding between the solder balls 450 , the bonding pads 414 and the nodes 430 are significantly improved.
  • the present invention can combine the above-described methods in both embodiments to fabricate the flip chip interconnected structure, and the bonding effect between the solder balls, chip and the substrate can be significantly improved.

Abstract

A flip chip interconnected structure comprises a chip having an active surface in which a plurality of bonding pads are formed on the active surface of the chip. A substrate has a surface and a chip locating region. The chip locating region is on the surface of the substrate and a plurality of nodes are formed on the chip locating region. A plurality of solder balls are respectively connected to the bonding pads and the nodes. The solder balls have various sizes. The chip is bonded to the chip locating region of the substrate by the solder balls.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority benefit of Taiwan application serial no. 90109499, filed on Apr. 20, 2001. [0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention [0002]
  • The present invention relates generally to a flip chip interconnected structure and a fabrication method thereof. More particularly, the present invention relates to an improved flip chip interconnected structure having good electrical connection and a fabrication method thereof. [0003]
  • 2. Description of the related Art [0004]
  • With the increasing need for high-density devices for use in lightweight, portable electronics, there has been a gradual shift in sizes of integrated circuits and their package configurations. This gradual shift has resulted in developing various techniques for different package types. [0005]
  • A flip chip interconnected technology utilizes solder bumps on bonding pads of a chip to electrically connect to a substrate. Comparing the flip chip interconnected method to a wire bonding method and a tape automatic bonding method, the circular path of the flip chip interconnected package is shorter and the electrical properties are better. The bumps are arranged in a matrix shape; thus, the amount of pin outs of the chip is significantly increased. Since the flip chip technique is faster, denser, thinner, lighter and provides a low cost package, one can expect the flip chip technique to replace wire bonding. [0006]
  • FIGS. 1 and 2 illustrate schematic views of a conventional flip chip package. Referring to FIG. 1, a [0007] chip 110 has an active surface 112, and a plurality of bonding pads 114 are arranged on the active surface 112. A plurality of bumps 116 are formed on the bonding pads 114 of the chip 110. A substrate 120 has a surface 122, and a plurality of nodes 124 are formed on the surface 122. A position of each node 124 corresponds to a position of each bump 116. A stencil printing process is carried out to apply solder paste onto the substrate 120. A plurality of solder structures 130 are formed on the nodes 124 of the substrate 120. Referring to FIGS. 1 and 2, a bonding process is performed to bond the chip 110 to the substrate 120. The bumps 116 of the chip 110 are bonded to the solder structures 130 of the substrate 120 in a reflow oven. A reflow method allows the bumps 116 to combine with the solder structures 130 to form a plurality of solder balls 140. The chip 110 is electrically connected to the substrate 120 by the solder balls 140.
  • Referring to FIG. 2, a filling process is carried out to fill a gap between the [0008] chip 110 and the substrate 120 with a molding compound 150, and the molding compound 150 encapsulates the solder balls 140.
  • However, in the reflow process, the [0009] substrate 120 will bend due to the heating in the reflow process. The distance between the chip 110 and the substrate 120 at a center region is closer due to the bending effect, and the distance between the chip 110 and the substrate 120 at the end regions is greater. Stress caused by the bending effect can affect the bonding between the chip 110 and the substrate 120. The solder balls 140 will easily detach from the nodes 124, and the stress due to the bending can also affect the reliability of the device. Thus the electrical connection and the reliability of the product are affected.
  • A conventional method utilizes a clamp (not shown) to hold the [0010] chip 110 and pre-heat the chip 110 for a while during a bonding process. Once the heat is transferred to the bumps 116, the bumps 116 will combine with the solder structures 130 to form the solder balls 140. Thus the chip 110 is electrically connected to the substrate 120. Although this method can prevent the substrate from bending, the pre-heating process on the chip 110 can damage the chip 110 because the chip is pre-heated for about 20 to 30 seconds at a temperature of about 200°. The conventional method complicates the fabrication process and the quality of the product is not reliable.
    • SUMMARY OF THE INVENTION
  • To achieve the foregoing and other objects and in accordance with the purpose of the present invention, the present invention provides a flip chip interconnected structure comprising a substrate having a surface, a chip locating region and a plurality of nodes. The chip locating region is on the surface of the substrate and the nodes are formed on the chip locating region. A chip is provided and has an active surface, on which a plurality of bonding pads are formed. The active surface of the chip corresponds to the surface of the substrate. A plurality of solder balls are respectively connected to the bonding pads and the nodes, wherein sizes of the solder balls are varied to allow the chip to bond to the chip locating region of the substrate. A molding compound is filled in between the chip and the substrate and is used to encapsulate the solder balls. The solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region. [0011]
  • It is another object of the present invention to provide a flip chip interconnected structure comprising a chip that has an active surface on which a plurality of bonding pads are formed. A substrate also is provided and has a surface, a chip locating region and a plurality of nodes. The chip locating region is on the surface of the substrate and the nodes are formed on the chip locating region. The chip locating region further comprises solder mask openings, and the nodes are exposed by the solder mask openings. Sizes of the solder mask openings are varied. A plurality of solder balls are respectively connected to the bonding pads and the nodes. The chip is bonded to the chip locating region of the substrate by the solder balls. The active surface of the chip corresponds to the surface of the substrate. A molding compound is filled in between the chip and the substrate and is used to encapsulate the solder balls. The solder mask openings are arranged in a matrix, and sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region. [0012]
  • It is another object of the present invention to provide a method of fabricating a flip chip interconnected structure. The steps of the method comprise first providing a chip that has an active surface. A plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads. A substrate is provided, which has a surface and a chip locating region. The chip locating region is on the surface of the substrate, and a plurality of nodes are formed on the chip locating region. Solder paste is used to cover the chip locating region and the nodes. The solder paste forms a plurality of solder structures with various sizes. A bonding process is performed to bond the active surface of the chip to the surface of the substrate by bonding the bumps to the solder structures. A heating process is carried out to combine the bumps and solder structures to form a plurality of solder balls. The solder balls are bonded respectively to the bonding pads and the nodes. The chip is bonded to the chip locating region of the substrate through the solder balls. A stencil printing board has a plurality of openings. The stencil printing board is located on the substrate and the nodes are exposed by the openings. The openings are filled with the solder paste by a screen printing method. Positions of the solder paste correspond to positions of the nodes. The solder paste forms solder structures with various sizes because the sizes of the openings are different. The openings are arranged in a matrix, and sizes of the openings located at a peripheral region of the stencil printing board are larger than sizes of the openings near a center region of the stencil printing board. Therefore, the amount of solder paste filled in the opening at the peripheral region is more than the amount of solder paste filled in the openings at the center region. [0013]
  • It is another object of the present invention to provide a method of fabricating a flip chip interconnected structure. The steps of the method comprise first providing a chip having an active surface. A plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads. A substrate having a surface is provided, wherein a chip locating region is on the surface. A solder mask layer and a plurality of nodes are formed on the chip locating region. A plurality of solder mask openings are formed on the solder mask layer, and the nodes are exposed by the solder mask openings, wherein the solder mask openings have various sizes. Solder paste is used to cover the chip locating region and the nodes. A bonding process is performed to bond the active surface of the chip to the surface of the substrate by bonding the bumps to the solder paste. A heating process is carried out to combine the bumps and solder paste to form a plurality of solder balls. The solder balls are bonded respectively to the bonding pads and the nodes. The chip is bonded to the chip locating region of the substrate through the solder balls. Sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.[0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0015]
  • FIGS. 1 and 2 are schematic views of a conventional flip chip package. [0016]
  • FIG. 3 is a schematic view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention. [0017]
  • FIG. 3A is a schematic top view of a stencil printing board. [0018]
  • FIG. 4 is a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention. [0019]
  • FIG. 4A is a schematic magnified view of a solder ball in accordance with a preferred embodiment of the present invention. [0020]
  • FIG. 5 is a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention. [0021]
  • FIGS. 6, 7 and [0022] 8 are schematic cross-sectional views of a flip chip interconnected structure in accordance with another preferred embodiment of the present invention.
  • FIG. 6A is a schematic top view of solder mask openings on a substrate. [0023]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 3 illustrates a schematic view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, a chip comprises an [0024] active surface 212. A plurality of bonding pads 214, which are formed on the active surface 212 have a plurality of bumps 216. A substrate 220 comprises a surface 222 and a chip locating region 224 on which a chip is located. A plurality of nodes 226 are formed on the chip locating region 224.
  • FIG. 3A illustrates a schematic top view of a stencil printing board. Referring to FIG. 3A, a [0025] stencil printing board 230 has a plurality of openings 232. The stencil printing board 230 is located on a substrate 220, and the nodes 226, which are located at the chip locating region 224, are exposed by the openings 232. The openings 232 are filled with solder paste by a screen printing method. When the screen printing process is carried out, the stencil printing board 230 is removed and the solder paste 240 located in the openings are remained on the surface 222 of the substrate. Positions of the solder paste 240 correspond to positions of the nodes 226. The openings 232 are arranged in a matrix shape, and sizes of the openings 232 located at a peripheral region of the stencil printing board 230 are larger than sizes of the openings near a center region of the stencil printing board 230. Therefore, the amount of solder paste filled in the opening 232 at the peripheral region is more than the amount of solder paste filled in the openings 232 at the center region.
  • FIG. 4 illustrates a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention. Referring to FIGS. 3 and 4, a bonding process is carried out to bond the [0026] active surface 212 of the chip 210 to the surface of the substrate 222. A reflow process is utilized to bond the bumps 216 to the solder paste 240 into solder balls 250, which are bonded to the bonding pads 214 and the nodes 226. The active surface 212 of the chip 210 is bonded onto the surface of chip locating region 224 by the solder balls 250. Since the sizes of the openings 232 are larger at the peripheral region than at the center region, sizes of solder balls 250 are larger at a peripheral region of the chip locating region 224 than at a center region of the chip locating region 224.
  • FIG. 4A illustrates a schematic magnified view of a solder ball in accordance with a preferred embodiment of the present invention. Referring to FIG. 4A, the [0027] bumps 216 are made of a material such as a tin/lead alloywith a ratio of about 5/95 and an eutectic point of approximately 312°. The solder paste 240 is made of a material such as a tin/lead alloy with a ratio of about 63/37 and an eutectic point of approximately 183°. During the reflow process, a temperature in a reflow oven (not shown) is about 200°. Therefore the bumps 216 will not melt but the solder paste 240 will melt and cover the periphery of the bumps 216 to form the solder balls 250. Thus, the chip 210 is bonded to the substrate 220.
  • FIG. 5 illustrates a cross-sectional view of a flip chip interconnected structure in accordance with a preferred embodiment of the present invention. Referring to FIG. 5, a molding process is performed to encapsulate a gap between the [0028] active surface 212 of the chip 210 and the chip locating region 224 of the substrate 222 with an encapsulating material including a molding compound 260. The molding compound 260 encapsulates the solder balls 250.
  • From the above-mentioned fabrication of a flip chip, the [0029] substrate 220 will bend after the reflow process, and a deformation will occur. Therefore, a gap at a center region of the chip 210 and the chip locating region 224 is smaller than a gap at the ends of the chip 210 and the chip locating region 224. However, the openings 232 of the screen printing board 230 of the present invention are designed in such a way that the sizes of the openings 232 are larger at the peripheral region than at the center region. Thus, the sizes of solder balls 250 are larger at a peripheral region of the chip locating region 224 than at a center region of the chip locating region 224. The bonding between the chip 210 and the substrate 220 is much stronger at the peripheral region than at the center region. Therefore, even though bending of the substrate occurs, the bending effect does not affect the chip and the substrate. The electrical connection and the reliability between the chip 210 and the substrate 220 are improved.
  • However, the present invention is not limited to the above-mentioned fabrication method and structure. FIGS. 6, 7 and [0030] 8 illustrate schematic cross-sectional views of a flip chip interconnected structure in accordance with another preferred embodiment of the present invention. A chip 410, which is provided, has an active surface 412. A plurality of bonding pads 414 are formed on the active surface 412 of the chip 410. Bumps 416 are formed on the bonding pads 414. FIG. 6A illustrates a schematic top view of solder mask openings on a substrate. Referring to FIGS. 6 and 6A, a substrate 420 has a surface 422. The surface 422 of the substrate 420 has a chip locating region 424. A solder mask layer 426 is formed on the surface 422 of the substrate 420. A plurality of solder mask openings 428 are formed in the solder mask layer 426 and each opening 428 exposes a node 430. The solder mask openings 428 are arranged in a matrix shaped, and sizes of the solder mask openings 428 located at a center region of the chip locating region 424 are larger than sizes of the solder mask openings 428 located at a peripheral region of the chip locating region 424.
  • Referring to FIG. 6, the [0031] solder mask openings 428 are filled with solder paste by a screen printing method, wherein the formation of the solder paste 440 corresponds to locations of the nodes 430 of the chip locating region 424.
  • FIG. 7 illustrates a schematic cross-sectional view of a flip chip interconnected structure in accordance with another preferred embodiment of the present invention. Referring to FIGS. 6 and 7, a bonding process is carried out to bond the [0032] active surface 412 of the chip 410 to the surface 422 of the substrate 420. The bumps 416 are bonded to the solder paste 440 and a reflow process is performed to combine the bumps 416 with the solder paste 440 to form a plurality of solder balls 450. The solder balls 450 are respectively bonded to the bonding pads 414 and the nodes 430. The sizes of the solder mask openings 428 located at the center region of the chip locating region 424 are larger than the sizes of the solder mask openings 428 located at the peripheral region of the chip locating region 424. Thus, during the bonding process, bending occurs at edges of the substrate 420. Due to the stress of the bending of the substrate 420, the solder balls 450 at the peripheral region of the chip locating region 424 will form into a cylindrical shape. However, the solder balls 450 at the center region of the chip locating region 424 will form into a circular shape. Therefore, the shapes of the solder balls 450 are varied along the chip location region according to the sizes of the solder mask openings 428. Since the solder mask openings 428 have various sizes, the amount of the solder paste 440 in the solder mask openings 428 are different. By utilizing the different sizes of the solder mask openings 428 and the amount of the solder paste 440, the solder balls 450 are formed into various shapes; thus, the bonding between the chip 410 and the substrate 420 is improved to overcome the stress caused by the bending effect. Because the sizes of the solder mask openings 428 at the center region are larger than the sizes of the solder mask openings 428 at the peripheral region, after the formation of the solder balls 450, the solder balls located at the center region of the chip locating region 424 are shorter than the solder balls located at the peripheral region of the chip locating region 424.
  • From the above-mentioned, the [0033] substrate 420 will bend after the reflow process, and a deformation will occur. Therefore, a gap at a center region of the chip 410 and the chip locating region 424 is smaller than a gap at the ends of the chip 410 and the chip locating region 224. However, the solder mask openings 428 of the present invention are designed in such a way that the sizes of the solder mask openings 428 at the center region of the chip locating region 424 are larger than the solder mask openings 428 located at the peripheral region of the chip locating region 424. Thus, the present invention utilizes the various sizes of the solder mask openings 428 to control the sizes of the solder balls 250. As a matter of fact, the solder balls 450 at the center region of the chip locating region 424 are shorter than the solder balls 450 at the peripheral region of the chip locating region 424. Therefore, despite the stress caused by the bending effect, the bonding between the substrate 420 and the chip 410 is strong enough both at the peripheral region and the center region. Therefore, the gap along the chip locating region 424 varies, but shorter solder balls 450 at the center region and higher solder ball 450 at the peripheral region allow the substrate 420 to bond strongly to the chip 410. Thus, the bonding between the solder balls 450, the bonding pads 414 and the nodes 430 are significantly improved.
  • However, the present invention can combine the above-described methods in both embodiments to fabricate the flip chip interconnected structure, and the bonding effect between the solder balls, chip and the substrate can be significantly improved. [0034]
  • Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. [0035]

Claims (20)

What is claimed is:
1. A flip chip interconnected structure, comprising:
a substrate having a first surface, a chip locating region and a plurality of nodes, wherein the chip locating region is on the first surface of the substrate and the nodes are formed on the chip locating region;
a chip having an active surface on which a plurality of bonding pads are formed, the active surface of the chip corresponding to the first surface of the substrate; and
a plurality of solder balls, wherein each solder ball respectively connects to one of the bonding pads and one of the nodes, and sizes of the solder balls are varied to allow the chip to bond to the chip locating region of the substrate.
2. The structure of claim 1, wherein the structure further comprises an encapsulating material filled in between the chip and the substrate, and encapsulating the solder balls.
3. The structure of claim 1, wherein the solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region.
4. The structure of claim 1, wherein each solder ball is made of a solder paste and a bump, wherein the solder paste covers the bump, and the bump is made of a tin/lead alloy containing a high percentage of lead.
5. The structure of claim 4, wherein the bump is made of the tin/lead alloy with a ratio of 5/95, and the solder paste is made of a tin/lead alloy with a ratio of 63/37.
6. The structure of claim 4, wherein a size of the solder paste located at a center region of the chip locating region is smaller than a size of the solder paste located at a peripheral region of the chip locating region.
7. A flip chip interconnected structure, comprising:
a substrate having a first surface, a chip locating region and a plurality of nodes, wherein the chip locating region is on the first surface of the substrate and the nodes are formed on the chip locating region, and the chip locating region further comprises a solder mask layer having a plurality of solder mask openings, and the nodes are exposed by the solder mask openings, wherein sizes of the solder mask openings are varied;
a chip having an active surface and a plurality of bonding pads formed on the active surface, wherein the active surface of the chip corresponds to the first surface of the substrate; and
a plurality of solder balls, wherein each solder ball is respectively connected to one of the bonding pads and one of the nodes, wherein sizes of the solder balls are varied to allow the chip to bond to the chip locating region of the substrate.
8. The structure of claim 7, wherein the flip chip interconnected structure further comprises an encapsulating material filled in between the chip and the substrate, and encapsulating the solder balls.
9. The structure of claim 7, wherein sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.
10. A method of fabricating a flip chip interconnected structure, the steps of the method comprising:
providing a chip having an active surface, wherein a plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads;
providing a substrate having a first surface, wherein a chip locating region is on the first surface, and a plurality of nodes are formed on the chip locating region;
applying a solder paste to cover the nodes of the chip locating region, wherein the solder paste forms a plurality of solder structures with various sizes; and
performing a bonding process, wherein the active surface of the chip is bonded to the surface of the substrate by bonding the bumps to the solder structures, and a heating process is carried out to combine the bumps and the solder structures to form a plurality of solder balls, wherein each solder ball is bonded respectively to one of the bonding pads and one of the nodes, and the chip is bonded to the chip locating region of the substrate through the solder balls.
11. The method of claim 10, wherein the bonding process further comprises an encapsulating process, wherein an encapsulating material is filled in between the chip and the substrate, and encapsulating the solder balls.
12. The method of claim 10, wherein the step of applying the solder paste further comprises:
providing a stencil printing board having a plurality of openings, wherein the stencil printing board is located on the substrate and the nodes of the chip locating region are exposed by the openings;
filling the openings with the solder paste by a screen printing method;
forming solder structures with various sizes according to different sizes of the openings and positions of the solder structures corresponding to positions of the nodes.
13. The method of claim 12, wherein the openings are arranged in a matrix, and sizes of the openings located at a peripheral region of the stencil printing board are larger than sizes of the openings near a center region of the stencil printing board, thereby the amount of the solder paste filled in the opening at the peripheral region is more than the amount of the solder paste filled in the openings at the center region.
14. The method of claim 10, wherein the bonding process further comprises a reflow method to combine the bumps and the solder structures.
15. The method of claim 10, wherein the solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region.
16. The method of claim 10, wherein each solder ball is made of a tin/lead alloy containing a high percentage of lead.
17. A method of fabricating a flip chip interconnected structure, the steps of the method comprising:
providing a chip having an active surface, wherein a plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads;
providing a substrate having a first surface, wherein a chip locating region is on the first surface, and a solder mask layer and a plurality of nodes are formed on the chip locating region, wherein a plurality of solder mask openings having various sizes are formed on the solder mask layer, and the nodes are exposed by the solder mask openings;
applying a solder paste to cover the node of the chip locating region; and
performing a bonding process, wherein the active surface of the chip is bonded to the surface of the substrate by bonding the bumps to the solder paste, and a heating process is carried out to combine each bump and each solder paste to form a solder ball, wherein a plurality of solder balls are formed and are bonded respectively to one of the bonding pads and one of the nodes, and the chip is bonded to the chip locating region of the substrate through the solder balls.
18. The method of claim 17, wherein the bonding process further comprises an encapsulating process, wherein an encapsulating material is filled in between the chip and the substrate, and encapsulating the solder balls.
19. The method of claim 17, wherein sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.
20. The method of claim 17, wherein the bonding process further comprises a reflow method to combine the bumps and the solder structures.
US09/895,554 2001-04-20 2001-06-28 Flip chip interconnected structure and a fabrication method thereof Abandoned US20020155637A1 (en)

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Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050116329A1 (en) * 2001-12-21 2005-06-02 Intel Corporation Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
US20070105277A1 (en) * 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US7235886B1 (en) 2001-12-21 2007-06-26 Intel Corporation Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby
US20100065966A1 (en) * 2006-12-14 2010-03-18 Stats Chippac, Ltd. Solder Joint Flip Chip Interconnection
US20110084386A1 (en) * 2003-11-10 2011-04-14 Stats Chippac, Ltd. Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
US20110121464A1 (en) * 2009-11-24 2011-05-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Electrical Interconnect with Stress Relief Void
US20110309500A1 (en) * 2003-12-31 2011-12-22 Stats Chippac, Ltd. Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
US20120032337A1 (en) * 2010-08-06 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Flip Chip Substrate Package Assembly and Process for Making Same
US20120074560A1 (en) * 2010-09-24 2012-03-29 Hin Hwa Goh Integrated circuit packaging system with warpage control and method of manufacture thereof
US8198699B1 (en) * 2010-04-19 2012-06-12 Altera Corporation Integrated circuit package with non-solder mask defined like pads
US20140103522A1 (en) * 2012-10-15 2014-04-17 Olympus Corporation Semiconductor substrate, semiconductor device, and method of manfacturing semiconductor substrate
US20140131869A1 (en) * 2003-11-10 2014-05-15 Stats Chippac, Ltd. Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
US20140175661A1 (en) * 2012-12-20 2014-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
WO2014160675A1 (en) * 2013-03-27 2014-10-02 Micron Technology, Inc. Semiconductor devices and packages including conductive underfill material and related methods
US20150097286A1 (en) * 2013-04-12 2015-04-09 Xintec Inc. Chip package and method for fabricating the same
US9064858B2 (en) 2003-11-10 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US9087882B2 (en) 2011-06-03 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9159665B2 (en) 2005-03-25 2015-10-13 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US9224680B2 (en) 2011-10-07 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US20160029486A1 (en) * 2014-07-24 2016-01-28 Samsung Electro-Mechanics Co., Ltd. Solder joint structure and electronic component module including the same
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
TWI595662B (en) * 2011-10-01 2017-08-11 英特爾公司 Source/drain contacts for non-planar transistors
US9773685B2 (en) 2003-11-10 2017-09-26 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection having relief structure
US9922915B2 (en) 2003-11-10 2018-03-20 STATS ChipPAC Pte. Ltd. Bump-on-lead flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
WO2021084227A1 (en) * 2019-10-29 2021-05-06 Tannlin Technology Limited Precision cut printing screen
CN113161243A (en) * 2021-04-15 2021-07-23 浙江集迈科微电子有限公司 Surface chip mounting process

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW572361U (en) * 2003-06-03 2004-01-11 Via Tech Inc Flip-chip package carrier
JP2005244035A (en) * 2004-02-27 2005-09-08 Renesas Technology Corp Mounting method of semiconductor device, and semiconductor device
TWI232072B (en) * 2004-04-05 2005-05-01 Wistron Corp Method and structure for printed circuit board assembly and jig for assembling structure
US7312529B2 (en) * 2005-07-05 2007-12-25 International Business Machines Corporation Structure and method for producing multiple size interconnections
TWI267971B (en) * 2005-12-30 2006-12-01 Advanced Semiconductor Eng Packing structure and method forming the same
TWI455263B (en) * 2009-02-16 2014-10-01 Ind Tech Res Inst Chip package structure and chip package method
US20110186899A1 (en) * 2010-02-03 2011-08-04 Polymer Vision Limited Semiconductor device with a variable integrated circuit chip bump pitch
US20120267779A1 (en) * 2011-04-25 2012-10-25 Mediatek Inc. Semiconductor package
US20130133193A1 (en) * 2011-11-28 2013-05-30 Mediatek Singapore Pte. Ltd. Surface mount technology process for advanced quad flat no-lead package process and stencil used therewith
US8756546B2 (en) 2012-07-25 2014-06-17 International Business Machines Corporation Elastic modulus mapping of a chip carrier in a flip chip package
US9960105B2 (en) * 2012-09-29 2018-05-01 Intel Corporation Controlled solder height packages and assembly processes
US8650512B1 (en) 2012-11-15 2014-02-11 International Business Machines Corporation Elastic modulus mapping of an integrated circuit chip in a chip/device package
US20190198474A1 (en) 2017-04-27 2019-06-27 International Business Machines Corporation Multiple sized bump bonds
CN112563231A (en) * 2020-12-01 2021-03-26 全球能源互联网研究院有限公司 Filling type chip interconnection structure and preparation method of chip interconnection structure
CN116093031A (en) * 2020-12-31 2023-05-09 华为技术有限公司 Board level structure and communication equipment

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
JPH07307410A (en) * 1994-05-16 1995-11-21 Hitachi Ltd Semiconductor device
CA2135508C (en) * 1994-11-09 1998-11-03 Robert J. Lyn Method for forming solder balls on a semiconductor substrate
US5620927A (en) * 1995-05-25 1997-04-15 National Semiconductor Corporation Solder ball attachment machine for semiconductor packages
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
US6117759A (en) * 1997-01-03 2000-09-12 Motorola Inc. Method for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit package
US6297559B1 (en) * 1997-07-10 2001-10-02 International Business Machines Corporation Structure, materials, and applications of ball grid array interconnections
AU3865897A (en) * 1997-08-19 1999-03-08 Hitachi Limited Method for forming bump electrode and method for manufacturing semiconductor device
JP3407275B2 (en) * 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Bump and method of forming the same
US6316289B1 (en) * 1998-11-12 2001-11-13 Amerasia International Technology Inc. Method of forming fine-pitch interconnections employing a standoff mask
US6190940B1 (en) * 1999-01-21 2001-02-20 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
US6365976B1 (en) * 1999-02-25 2002-04-02 Texas Instruments Incorporated Integrated circuit device with depressions for receiving solder balls and method of fabrication
JP3399518B2 (en) * 1999-03-03 2003-04-21 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor structure and method of manufacturing the same
US6255142B1 (en) * 1999-10-29 2001-07-03 Nordson Corporation Method for underfilling semiconductor devices
JP3423930B2 (en) * 1999-12-27 2003-07-07 富士通株式会社 Bump forming method, electronic component, and solder paste

Cited By (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235886B1 (en) 2001-12-21 2007-06-26 Intel Corporation Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby
US7122403B2 (en) * 2001-12-21 2006-10-17 Intel Corporation Method of interconnecting die and substrate
US20050116329A1 (en) * 2001-12-21 2005-06-02 Intel Corporation Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
US9379084B2 (en) 2003-11-10 2016-06-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US20110084386A1 (en) * 2003-11-10 2011-04-14 Stats Chippac, Ltd. Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
US9899286B2 (en) 2003-11-10 2018-02-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8810029B2 (en) 2003-11-10 2014-08-19 Stats Chippac, Ltd. Solder joint flip chip interconnection
US9865556B2 (en) 2003-11-10 2018-01-09 STATS ChipPAC Pte Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9773685B2 (en) 2003-11-10 2017-09-26 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection having relief structure
US9385101B2 (en) 2003-11-10 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US9922915B2 (en) 2003-11-10 2018-03-20 STATS ChipPAC Pte. Ltd. Bump-on-lead flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE44608E1 (en) 2003-11-10 2013-11-26 Stats Chippac, Ltd. Solder joint flip chip interconnection
US9373573B2 (en) 2003-11-10 2016-06-21 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection
US9219045B2 (en) * 2003-11-10 2015-12-22 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US20140131869A1 (en) * 2003-11-10 2014-05-15 Stats Chippac, Ltd. Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
US9064858B2 (en) 2003-11-10 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8674500B2 (en) * 2003-12-31 2014-03-18 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US20110309500A1 (en) * 2003-12-31 2011-12-22 Stats Chippac, Ltd. Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask
US20070105277A1 (en) * 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US10580749B2 (en) 2005-03-25 2020-03-03 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming high routing density interconnect sites on substrate
US9159665B2 (en) 2005-03-25 2015-10-13 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US20100065966A1 (en) * 2006-12-14 2010-03-18 Stats Chippac, Ltd. Solder Joint Flip Chip Interconnection
US20110121464A1 (en) * 2009-11-24 2011-05-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Electrical Interconnect with Stress Relief Void
US8350384B2 (en) 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8198699B1 (en) * 2010-04-19 2012-06-12 Altera Corporation Integrated circuit package with non-solder mask defined like pads
US20120032337A1 (en) * 2010-08-06 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Flip Chip Substrate Package Assembly and Process for Making Same
US8766426B2 (en) * 2010-09-24 2014-07-01 Stats Chippac Ltd. Integrated circuit packaging system with warpage control and method of manufacture thereof
US20120074560A1 (en) * 2010-09-24 2012-03-29 Hin Hwa Goh Integrated circuit packaging system with warpage control and method of manufacture thereof
US9515038B2 (en) 2011-06-03 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9087882B2 (en) 2011-06-03 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
TWI595662B (en) * 2011-10-01 2017-08-11 英特爾公司 Source/drain contacts for non-planar transistors
US10283640B2 (en) 2011-10-01 2019-05-07 Intel Corporation Source/drain contacts for non-planar transistors
US10770591B2 (en) 2011-10-01 2020-09-08 Intel Corporation Source/drain contacts for non-planar transistors
US9853156B2 (en) 2011-10-01 2017-12-26 Intel Corporation Source/drain contacts for non-planar transistors
US9741659B2 (en) 2011-10-07 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9224680B2 (en) 2011-10-07 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US9748188B2 (en) 2012-07-31 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device
US10163839B2 (en) 2012-07-31 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure in semiconductor packaged device
US10515917B2 (en) 2012-07-31 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure in semiconductor packaged device
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9123788B2 (en) 2012-08-17 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9397059B2 (en) 2012-08-17 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US11088102B2 (en) 2012-08-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US10468366B2 (en) 2012-08-17 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US20140103522A1 (en) * 2012-10-15 2014-04-17 Olympus Corporation Semiconductor substrate, semiconductor device, and method of manfacturing semiconductor substrate
TWI602272B (en) * 2012-12-20 2017-10-11 史達晶片有限公司 Semiconductor device and method of making bumpless flipchip interconnect structures
KR101773222B1 (en) * 2012-12-20 2017-09-01 스태츠 칩팩 피티이. 엘티디. Semiconductor device and method of making bumpless flipchip interconnect structures
US9240331B2 (en) * 2012-12-20 2016-01-19 Stats Chippac, Ltd. Semiconductor device and method of making bumpless flipchip interconnect structures
US20140175661A1 (en) * 2012-12-20 2014-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures
WO2014160675A1 (en) * 2013-03-27 2014-10-02 Micron Technology, Inc. Semiconductor devices and packages including conductive underfill material and related methods
US20150097286A1 (en) * 2013-04-12 2015-04-09 Xintec Inc. Chip package and method for fabricating the same
CN105321905A (en) * 2014-07-24 2016-02-10 三星电机株式会社 Solder joint structure and electronic component module including the same
US20160029486A1 (en) * 2014-07-24 2016-01-28 Samsung Electro-Mechanics Co., Ltd. Solder joint structure and electronic component module including the same
WO2021084227A1 (en) * 2019-10-29 2021-05-06 Tannlin Technology Limited Precision cut printing screen
GB2588633B (en) * 2019-10-29 2023-11-22 Tannlin Tech Limited Precision cut printing screen
US11932003B2 (en) 2019-10-29 2024-03-19 Tannlin Technology Limited Precision cut printing screen
CN113161243A (en) * 2021-04-15 2021-07-23 浙江集迈科微电子有限公司 Surface chip mounting process

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