US20020110954A1 - Semiconductor device and method of fabricating same - Google Patents
Semiconductor device and method of fabricating same Download PDFInfo
- Publication number
- US20020110954A1 US20020110954A1 US10/122,322 US12232202A US2002110954A1 US 20020110954 A1 US20020110954 A1 US 20020110954A1 US 12232202 A US12232202 A US 12232202A US 2002110954 A1 US2002110954 A1 US 2002110954A1
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- United States
- Prior art keywords
- layer
- semiconductor device
- electrode
- semiconductor substrate
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 126
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 44
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910000679 solder Inorganic materials 0.000 claims abstract description 26
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 22
- 239000010936 titanium Substances 0.000 claims abstract description 19
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 19
- 230000005260 alpha ray Effects 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 23
- 229920001721 polyimide Polymers 0.000 claims description 19
- 239000004642 Polyimide Substances 0.000 claims description 16
- 230000000903 blocking effect Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 58
- 229910052782 aluminium Inorganic materials 0.000 abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 13
- 238000009413 insulation Methods 0.000 abstract description 13
- 239000011229 interlayer Substances 0.000 abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 10
- 230000007246 mechanism Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000004952 Polyamide Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920002647 polyamide Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- -1 Phospho Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to a semiconductor device and, more particularly, to a semiconductor device packaged in CSP (Chip Size Package) form.
- CSP Chip Size Package
- FIG. 9 is a schematic cross-sectional view showing conventional CSP mounting.
- a semiconductor device 1 is directly mounted in the form of a chip on a printed board 2 for the purpose of reducing the area required to mount the semiconductor device 1 on the printed board 2 .
- the semiconductor device 1 in chip form comprises solder bumps 11 through which the semiconductor device 1 is connected to the printed board 2 .
- FIG. 10 is a schematic cross-sectional view showing another type of conventional CSP mounting. As shown in FIG. 10, the semiconductor device 1 in chip form is, in some cases, covered with a molding resin 12 which allows the solder bumps 11 to be exposed.
- FIGS. 11 through 14 are cross-sectional views showing a method of fabricating a conventional semiconductor device in the order of sequential process steps.
- diffusion layers 101 a and 101 b functioning as a source and a drain are formed in an upper surface of a semiconductor substrate 101 of silicon, for example.
- An interlayer insulation film 102 made of, for example, silicon oxide is formed on the semiconductor substrate 101 .
- a gate insulating film (equated with the interlayer insulation film 102 for purposes of simplification of illustration) therebetween, a gate 109 is opposed to the upper surface of a portion of the semiconductor substrate 101 which lies between the diffusion layers 101 a and 101 b .
- An aluminum pad 103 is connected to the diffusion layer 101 b through a connecting mechanism not shown, for example, a contact hole.
- a silicon nitride film 104 is formed on the structure shown in FIG. 11 by the plasma CVD process. Part of the silicon nitride film 104 which overlies the aluminum pad 103 is selectively removed by the photolithography and etching to provide the structure shown in FIG. 12.
- a layer of titanium 105 and a layer of nickel 106 are deposited on the structure shown in FIG. 12 by the sputtering process.
- the photolithography and etching processes are performed so that the layer of titanium 105 and the layer of nickel 106 are left only in an area extending from the aluminum pad 103 to an end of the silicon nitride film 104 , thereby to provide the structure shown in FIG. 13.
- a solder bump 11 is disposed on a multilayer structure consisting of the aluminum pad 103 , the layer of titanium 105 , and the layer of nickel 106 in the structure shown in FIG. 13 to provide the structure shown in FIG. 14.
- a semiconductor device comprises: a semiconductor layer provided in an insulating layer and including a transistor having an SOI structure formed therein; an electrode provided on the insulating layer; and an electrically conductive bump provided on the electrode.
- the transistor in the semiconductor device of the first aspect, includes a plurality of transistors field-shield isolated from each other and formed in the semiconductor layer.
- a third aspect of the present invention is also intended for a method of fabricating a semiconductor device.
- the method comprises the steps of: (a) forming an electrode on a semiconductor substrate; and (b) forming an electrically conductive bump on the electrode and forming an insulating film for blocking an alpha ray and covering an upper surface of the semiconductor substrate except the electrode.
- the step (b) comprises the steps of (b-1) forming the insulating film for blocking the alpha ray and covering the upper surface of the semiconductor substrate so that at least part of the electrode is exposed, and (b-2) forming the electrically conductive bump on the exposed part of the electrode.
- the step (b) comprises the steps of (b-1) forming the bump on the electrode, and (b-2) dropping the material of the insulating film for blocking the alpha ray onto the upper surface of the semiconductor substrate except onto the electrode.
- a semiconductor device comprises: a semiconductor substrate; an electrode disposed on the semiconductor substrate; an electrically conductive bump provided on the electrode; a film covering the semiconductor substrate except the bump and for blocking an alpha ray; a first element disposed in the semiconductor substrate in an area that is visible from the bump without being obstructed by the film; and a second element disposed in the semiconductor substrate in other than the area, the second element being less resistant to the alpha ray than the first element.
- the first element is a MOS transistor having a body at a fixed potential.
- the semiconductor device of the first and second aspects of the present invention may perform the so-called CSP mounting wherein the conductive bump is connected to a printed board. Additionally, the transistor has the SOI structure, and electrons and holes generated due to an alpha ray in the semiconductor layer in which the transistor is formed are in amounts which do not influence the operation of the transistor. Further, there is a low likelihood of cracks generated in the semiconductor layer because of stresses resulting from the difference in thermal expansion coefficient between the printed board and the semiconductor device which have been a problem in the CSP mounting.
- the alpha ray blocking film made of a polyimide which is not resistant to heating after being formed is used as the insulating film, influences of the increase in temperature during the formation of the electrode upon the insulating film are avoided since the formation of the electrode underlying the bump precedes the formation of the insulating film.
- the first element which is highly resistant to an alpha ray is formed in the area wherein no film blocks the alpha ray coming from the bump. This allows effective area use and avoids adverse effects resulting from the alpha ray.
- the body of the MOS transistor serving as the first element is at the fixed potential. This suppresses parasitic bipolar effects to further increase the resistance to the alpha ray.
- FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first preferred embodiment of the present invention
- FIG. 2 is a cross-sectional view illustrating another structure of the first preferred embodiment
- FIGS. 3 through 5 are cross-sectional view showing a method of fabricating the semiconductor device in the order of sequential process steps according to a second preferred embodiment of the present invention.
- FIG. 6 is a cross-sectional view showing the method of fabricating the semiconductor device according to a third preferred embodiment of the present invention.
- FIG. 7 is a cross-sectional view illustrating a structure of the semiconductor device according to a fourth preferred embodiment of the present invention.
- FIG. 8 is a cross-sectional view illustrating a structure of the semiconductor device according to a fifth preferred embodiment of the present invention.
- FIG. 9 is a schematic cross-sectional view showing conventional CSP mounting
- FIG. 10 is a schematic cross-sectional view showing another type of conventional CSP mounting.
- FIGS. 11 through 14 are cross-sectional views showing a method of fabricating a conventional semiconductor device in the order of sequential process steps.
- FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first preferred embodiment of the present invention.
- a buried oxide film 107 is formed on a semiconductor substrate 101 of silicon, for example.
- a MOS transistor having an SOI (Semiconductor On Insulator) structure is formed on the buried oxide film 107 .
- the MOS transistor comprises source and drain regions 120 a and 120 b formed in a semiconductor layer 120 of silicon, for example, and a gate electrode 110 .
- the semiconductor layer 120 and the gate electrode 110 are covered with an interlayer insulation film 108 made of, for example, BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) and NSG (Non-doped Silicate Glass) and formed on the buried oxide film 107 .
- BPTEOS Bopo Phospho Tetra Ethyl Ortho Silicate
- NSG Non-doped Silicate Glass
- a layer of titanium 105 and a layer of nickel 106 are formed only in an area extending from the aluminum pad 103 to an end of the silicon nitride film 104 .
- a solder bump 11 is disposed on the layer of nickel 106 .
- a lower part (including the semiconductor substrate 101 ) of such a structure which lies below and includes the interlayer insulation film 108 may be provided using the technique of forming a conventional SOI transistor.
- An upper part (including the solder bump 11 ) of such a structure which lies above the interlayer insulation film 108 may be formed by the conventional technique shown in FIGS. 11 through 14.
- Electrons 93 and holes 92 are generated in the semiconductor layer 120 and the semiconductor substrate 101 when the structure of FIG. 1 is irradiated with an alpha ray 91 .
- the semiconductor layer 120 is provided for the SOI transistor, the thickness of the semiconductor layer 120 may be reduced to a thickness level required for channel formation.
- the electrons 93 and holes 92 generated in the semiconductor layer 120 are much smaller in number than those generated in the semiconductor substrate 101 .
- the SOI transistor is less affected adversely by the alpha ray 91 than a so-called bulk transistor such as that shown in FIG. 14.
- FIG. 2 is a cross-sectional view illustrating another structure of the semiconductor device according to the first preferred embodiment of the present invention.
- the semiconductor layer 120 extends perpendicularly to the direction of a channel length not shown (that is, in the direction of a channel width).
- FS gates 111 are provided for FS isolation (Field Shield isolation) of a plurality of transistors arranged in the direction of the channel width.
- the semiconductor layer 120 even if elongated in this manner, is much thinner than the semiconductor substrate 101 . Therefore, stresses are prone to be relieved and few cracks are generated in the semiconductor layer 120 . Cracks, if any, in the semiconductor substrate 101 exert no influences upon the characteristics of the transistor formed in the semiconductor layer 120 .
- the structure of FIG. 2 including the elongated semiconductor layer 120 for FS isolation does not impair the effects of the present invention, as compared with the structure of FIG. 1.
- FIGS. 3 through 5 are cross-sectional views showing a method of fabricating the semiconductor device in the order of sequential process steps according to a second preferred embodiment of the present invention.
- an interlayer insulation film 102 is formed on the semiconductor substrate 101 , and a multilayer structure consisting of the aluminum pad 103 , the layer of titanium 105 , and the layer of nickel 106 is formed on the interlayer insulation film 102 .
- the aluminum pad 103 is electrically connected to source and drain regions not shown.
- the local triple metal layer structure as shown in FIG. 3 may be accomplished by the semiconductor fabrication techniques known in the art.
- the silicon nitride film 104 and a polyimide layer 203 are deposited, and an opening is formed therein on the top of the layer of nickel 106 (FIG. 4).
- a multilayer film 201 comprised of the silicon nitride film 104 and the polyimide layer 203 serves as a film for blocking alpha rays. Further, the solder bump 11 is formed in the opening.
- the semiconductor device in chip form is provided (FIG. 5).
- This structure comprising the polyimide layer 203 for preventing the alpha rays from entering the semiconductor substrate 101 may avoid errors resulting from the alpha rays if a bulk transistor is formed in the semiconductor substrate 101 .
- Alpha rays coming from below the semiconductor substrate 101 do not reach the diffusion layers 101 a and 101 b under normal conditions and, hence, substantially need not be taken into consideration.
- the polyimide layer 203 is formed after the layer of titanium 105 and the layer of nickel 106 are formed. Temperature increases up to about 200° C. in the step of providing the solder bump 11 . Therefore, the background art problem of the moisture released from the polyimide layer 203 which has already been formed is avoided.
- FIG. 6 is a cross-sectional view showing the method of fabricating the semiconductor device according to a third preferred embodiment of the present invention.
- Carboxylic polyamide is dropped onto the conventional structure shown in FIG. 14 except onto the solder bump 11 . Thereafter, the resultant structure is heated to form the polyimide layer 203 except on the solder bump 11 . This prevents alpha rays without interfering with the connection between the solder bump 11 and the printed board.
- the material used in the above described technique is not limited to carboxylic polyamide, but any material that is capable of preventing alpha rays and permitted to drop down may be used.
- FIG. 7 is a cross-sectional view illustrating a structure of the semiconductor device according to a fourth preferred embodiment of the present invention.
- An isolation oxide film 400 including an area AR, and diffusion layers 101 a and 101 b serving as source and drain regions are formed in the upper surface of the semiconductor substrate 101 .
- the interlayer insulation film 102 surrounding gate electrodes 109 is formed on the semiconductor substrate 101 .
- the multilayer structure comprised of the aluminum pad 103 , the layer of titanium 105 , and the layer of nickel 106 is locally formed on the interlayer insulation film 102 .
- the solder bump 11 is disposed on the multilayer structure.
- the film 201 is formed on the interlayer insulation film 102 except on the solder bump 11 The formation of the film 201 may be achieved using the process step of forming the polyimide film 203 shown in the second or third preferred embodiment.
- solder bump 11 precludes an alpha ray coming through the air from entering the semiconductor substrate 101 .
- solder generally contains lead as an ingredient and radioactive isotopes as an impurity in no small amounts, there is a likelihood that an alpha ray enters the semiconductor substrate 101 from the solder bump 11 itself.
- the area AR that is visible from the solder bump 11 without being obstructed by the film 201 is established at the upper surface of the semiconductor substrate 101 .
- a capacitor formed in the semiconductor device employed in the CSP mounting is tens of femtocoulombs, and the operation of such a capacitor is influenced by the generation of a small number of electron-hole pairs.
- the isolation oxide film 400 is formed in the area AR.
- the SOI transistor highly resistant to the alpha rays which is shown in the first preferred embodiment or a resistance element may be formed in the area AR. Since the film 201 prevents the alpha ray coming from the solder bump 11 as well as the alpha ray coming through the air from reaching the transistor formed in other than the area AR, errors in the transistor due to the alpha rays are avoided.
- an element which has greater resistance to alpha rays than the element provided in other than the area AR may be formed in the area AR to allow effective area use without impairing the resistance of the entire semiconductor device to the alpha rays.
- FIG. 8 is a cross-sectional view illustrating a structure of the semiconductor device according to a fifth preferred embodiment of the present invention.
- the semiconductor device of the fifth preferred embodiment comprises a plurality of SOI transistors 121 to 123 .
- the SOI transistor 121 includes source and drain regions 121 a and 121 b , a body portion 121 c , and a gate electrode 121 d .
- the SOI transistor 122 includes source and drain regions 122 a and 122 b , a body portion 122 c , and a gate electrode 122 d .
- the SOI transistor 123 includes source and drain regions 123 a and 123 b , a body portion 123 c , and a gate electrode 123 d .
- the body portions 121 c and 122 c are floating, and the body portion 123 c is at a potential fixed by the known technique not shown.
- solder bump made of a lead-free alloy of gold and tin may be employed.
Abstract
A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120 a , 120 b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120 a , 120 b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and, more particularly, to a semiconductor device packaged in CSP (Chip Size Package) form.
- 2. Description of the Background Art
- FIG. 9 is a schematic cross-sectional view showing conventional CSP mounting. A
semiconductor device 1 is directly mounted in the form of a chip on a printedboard 2 for the purpose of reducing the area required to mount thesemiconductor device 1 on the printedboard 2. Thesemiconductor device 1 in chip form comprisessolder bumps 11 through which thesemiconductor device 1 is connected to the printedboard 2. - FIG. 10 is a schematic cross-sectional view showing another type of conventional CSP mounting. As shown in FIG. 10, the
semiconductor device 1 in chip form is, in some cases, covered with a molding resin 12 which allows thesolder bumps 11 to be exposed. - FIGS. 11 through 14 are cross-sectional views showing a method of fabricating a conventional semiconductor device in the order of sequential process steps. Referring to FIG. 11,
diffusion layers semiconductor substrate 101 of silicon, for example. Aninterlayer insulation film 102 made of, for example, silicon oxide is formed on thesemiconductor substrate 101. With a gate insulating film (equated with theinterlayer insulation film 102 for purposes of simplification of illustration) therebetween, agate 109 is opposed to the upper surface of a portion of thesemiconductor substrate 101 which lies between thediffusion layers aluminum pad 103 is connected to thediffusion layer 101 b through a connecting mechanism not shown, for example, a contact hole. - A
silicon nitride film 104 is formed on the structure shown in FIG. 11 by the plasma CVD process. Part of thesilicon nitride film 104 which overlies thealuminum pad 103 is selectively removed by the photolithography and etching to provide the structure shown in FIG. 12. - A layer of
titanium 105 and a layer ofnickel 106 are deposited on the structure shown in FIG. 12 by the sputtering process. The photolithography and etching processes are performed so that the layer oftitanium 105 and the layer ofnickel 106 are left only in an area extending from thealuminum pad 103 to an end of thesilicon nitride film 104, thereby to provide the structure shown in FIG. 13. - A
solder bump 11 is disposed on a multilayer structure consisting of thealuminum pad 103, the layer oftitanium 105, and the layer ofnickel 106 in the structure shown in FIG. 13 to provide the structure shown in FIG. 14. - It is well known in the art that, when irradiated with an
alpha ray 91,electrons 93 andholes 92 generated in semiconductor cause operation errors of a semiconductor device. Although the molding resin 12 covers the semiconductor device with thesolder bumps 11 exposed as shown in FIG. 10, there has been a need to use a polyimide resin, for example, which is less pervious to alpha rays than the material of the typical molding resin 12 to shield and protect the semiconductor device against the alpha rays. - Unfortunately, it has been difficult for the polyimide resin to shield and protect the semiconductor device in chip form used in the conventional CSP mounting against the alpha rays. The production of a polyimide in place of or on the
silicon nitride film 104 might result in the removal of the layer oftitanium 105 and the layer ofnickel 106 and the generation of the uneven or rough surfaces thereof. - These problems result from a film-deposition temperature exceeding 300° C. at which the layer of
titanium 105 and the layer ofnickel 106 are deposited by the sputtering process. In general, a polyimide is produced by dehydrating carboxylic polyamide in a liquid state by heating at a temperature of 300° C. to 350° C. to cause polymerization to occur. However, it is difficult to completely remove moisture contained in the carboxylic polyamide. The moisture remaining in the polyimide might be released during the sputtering of the layer oftitanium 105 and the layer ofnickel 106 to result in the problems of the removal thereof and the generation of the uneven surfaces thereof. - Further, stresses are applied between the semiconductor chip and the printed board since the printed board generally has greater thermal expansion properties than the semiconductor chip. In the CSP mounting, there are no stress-relieved lead frames in lead frame type packaging, resulting in difficulties in relieving stresses after packaging. The difficulties in the stress relief present the likelihood of cracks generated in the
semiconductor substrate 101. Thediffusion layers - According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor layer provided in an insulating layer and including a transistor having an SOI structure formed therein; an electrode provided on the insulating layer; and an electrically conductive bump provided on the electrode.
- Preferably, according to a second aspect of the present invention, in the semiconductor device of the first aspect, the transistor includes a plurality of transistors field-shield isolated from each other and formed in the semiconductor layer.
- A third aspect of the present invention is also intended for a method of fabricating a semiconductor device. According to the present invention, the method comprises the steps of: (a) forming an electrode on a semiconductor substrate; and (b) forming an electrically conductive bump on the electrode and forming an insulating film for blocking an alpha ray and covering an upper surface of the semiconductor substrate except the electrode.
- Preferably, according to a fourth aspect of the present invention, in the method of the third aspect, the step (b) comprises the steps of (b-1) forming the insulating film for blocking the alpha ray and covering the upper surface of the semiconductor substrate so that at least part of the electrode is exposed, and (b-2) forming the electrically conductive bump on the exposed part of the electrode.
- Preferably, according to a fifth aspect of the present invention, in the method of the third aspect, the step (b) comprises the steps of (b-1) forming the bump on the electrode, and (b-2) dropping the material of the insulating film for blocking the alpha ray onto the upper surface of the semiconductor substrate except onto the electrode.
- According to a sixth aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; an electrode disposed on the semiconductor substrate; an electrically conductive bump provided on the electrode; a film covering the semiconductor substrate except the bump and for blocking an alpha ray; a first element disposed in the semiconductor substrate in an area that is visible from the bump without being obstructed by the film; and a second element disposed in the semiconductor substrate in other than the area, the second element being less resistant to the alpha ray than the first element.
- Preferably, according to a seventh aspect of the present invention, in the semiconductor device of the sixth aspect, the first element is a MOS transistor having a body at a fixed potential.
- The semiconductor device of the first and second aspects of the present invention may perform the so-called CSP mounting wherein the conductive bump is connected to a printed board. Additionally, the transistor has the SOI structure, and electrons and holes generated due to an alpha ray in the semiconductor layer in which the transistor is formed are in amounts which do not influence the operation of the transistor. Further, there is a low likelihood of cracks generated in the semiconductor layer because of stresses resulting from the difference in thermal expansion coefficient between the printed board and the semiconductor device which have been a problem in the CSP mounting.
- In accordance with the method of the third to fifth aspects of the present invention, if the alpha ray blocking film made of a polyimide which is not resistant to heating after being formed is used as the insulating film, influences of the increase in temperature during the formation of the electrode upon the insulating film are avoided since the formation of the electrode underlying the bump precedes the formation of the insulating film.
- In accordance with the semiconductor device of the sixth aspect of the present invention, the first element which is highly resistant to an alpha ray is formed in the area wherein no film blocks the alpha ray coming from the bump. This allows effective area use and avoids adverse effects resulting from the alpha ray.
- In accordance with the semiconductor device of the seventh aspect of the present invention, the body of the MOS transistor serving as the first element is at the fixed potential. This suppresses parasitic bipolar effects to further increase the resistance to the alpha ray.
- It is therefore an object of the present invention to provide a semiconductor device for CSP mounting which avoids errors resulting from an alpha ray or which is highly resistant to stresses.
- These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
- FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first preferred embodiment of the present invention;
- FIG. 2 is a cross-sectional view illustrating another structure of the first preferred embodiment;
- FIGS. 3 through 5 are cross-sectional view showing a method of fabricating the semiconductor device in the order of sequential process steps according to a second preferred embodiment of the present invention;
- FIG. 6 is a cross-sectional view showing the method of fabricating the semiconductor device according to a third preferred embodiment of the present invention;
- FIG. 7 is a cross-sectional view illustrating a structure of the semiconductor device according to a fourth preferred embodiment of the present invention;
- FIG. 8 is a cross-sectional view illustrating a structure of the semiconductor device according to a fifth preferred embodiment of the present invention;
- FIG. 9 is a schematic cross-sectional view showing conventional CSP mounting;
- FIG. 10 is a schematic cross-sectional view showing another type of conventional CSP mounting; and
- FIGS. 11 through 14 are cross-sectional views showing a method of fabricating a conventional semiconductor device in the order of sequential process steps.
- First Preferred Embodiment
- FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first preferred embodiment of the present invention. A buried
oxide film 107 is formed on asemiconductor substrate 101 of silicon, for example. A MOS transistor having an SOI (Semiconductor On Insulator) structure is formed on the buriedoxide film 107. The MOS transistor comprises source and drainregions semiconductor layer 120 of silicon, for example, and agate electrode 110. Thesemiconductor layer 120 and thegate electrode 110 are covered with aninterlayer insulation film 108 made of, for example, BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate) and NSG (Non-doped Silicate Glass) and formed on the buriedoxide film 107. - An
aluminum pad 103 connected to any one of the source and drainregions silicon nitride film 104 having an opening on the top of thealuminum pad 103 are formed on theinterlayer insulation film 108. A layer oftitanium 105 and a layer ofnickel 106 are formed only in an area extending from thealuminum pad 103 to an end of thesilicon nitride film 104. Asolder bump 11 is disposed on the layer ofnickel 106. - A lower part (including the semiconductor substrate101) of such a structure which lies below and includes the
interlayer insulation film 108 may be provided using the technique of forming a conventional SOI transistor. An upper part (including the solder bump 11) of such a structure which lies above theinterlayer insulation film 108 may be formed by the conventional technique shown in FIGS. 11 through 14. -
Electrons 93 and holes 92 are generated in thesemiconductor layer 120 and thesemiconductor substrate 101 when the structure of FIG. 1 is irradiated with analpha ray 91. However, since thesemiconductor layer 120 is provided for the SOI transistor, the thickness of thesemiconductor layer 120 may be reduced to a thickness level required for channel formation. Thus, theelectrons 93 and holes 92 generated in thesemiconductor layer 120 are much smaller in number than those generated in thesemiconductor substrate 101. For this reason, the SOI transistor is less affected adversely by thealpha ray 91 than a so-called bulk transistor such as that shown in FIG. 14. - Additionally, when such a structure is cooled after the heating of the
solder bump 11 and the CSP mounting, stresses are produced so that the printed board having a higher thermal expansion coefficient than the semiconductor chip shrinks by a greater amount. However, since thesemiconductor layer 120 is thin in thickness and short in length, the probability of cracks generated in thesemiconductor layer 120 is lower than those generated in thesemiconductor substrate 101. This achieves a semiconductor chip has greater resistance to stresses than the structure shown in FIG. 14 without impairing size reduction which is characteristic of CSP. - FIG. 2 is a cross-sectional view illustrating another structure of the semiconductor device according to the first preferred embodiment of the present invention. The
semiconductor layer 120 extends perpendicularly to the direction of a channel length not shown (that is, in the direction of a channel width).FS gates 111 are provided for FS isolation (Field Shield isolation) of a plurality of transistors arranged in the direction of the channel width. Thesemiconductor layer 120, even if elongated in this manner, is much thinner than thesemiconductor substrate 101. Therefore, stresses are prone to be relieved and few cracks are generated in thesemiconductor layer 120. Cracks, if any, in thesemiconductor substrate 101 exert no influences upon the characteristics of the transistor formed in thesemiconductor layer 120. Thus, the structure of FIG. 2 including theelongated semiconductor layer 120 for FS isolation does not impair the effects of the present invention, as compared with the structure of FIG. 1. - Second Preferred Embodiment FIGS. 3 through 5 are cross-sectional views showing a method of fabricating the semiconductor device in the order of sequential process steps according to a second preferred embodiment of the present invention.
- Referring to FIG. 3, an
interlayer insulation film 102 is formed on thesemiconductor substrate 101, and a multilayer structure consisting of thealuminum pad 103, the layer oftitanium 105, and the layer ofnickel 106 is formed on theinterlayer insulation film 102. Thealuminum pad 103 is electrically connected to source and drain regions not shown. The local triple metal layer structure as shown in FIG. 3 may be accomplished by the semiconductor fabrication techniques known in the art. - Thereafter, the
silicon nitride film 104 and apolyimide layer 203 are deposited, and an opening is formed therein on the top of the layer of nickel 106 (FIG. 4). Amultilayer film 201 comprised of thesilicon nitride film 104 and thepolyimide layer 203 serves as a film for blocking alpha rays. Further, thesolder bump 11 is formed in the opening. Then, the semiconductor device in chip form is provided (FIG. 5). This structure comprising thepolyimide layer 203 for preventing the alpha rays from entering thesemiconductor substrate 101 may avoid errors resulting from the alpha rays if a bulk transistor is formed in thesemiconductor substrate 101. Alpha rays coming from below the semiconductor substrate 101 (where theinterlayer insulation film 102 is not provided) do not reach the diffusion layers 101 a and 101 b under normal conditions and, hence, substantially need not be taken into consideration. - The
polyimide layer 203 is formed after the layer oftitanium 105 and the layer ofnickel 106 are formed. Temperature increases up to about 200° C. in the step of providing thesolder bump 11. Therefore, the background art problem of the moisture released from thepolyimide layer 203 which has already been formed is avoided. - Third Preferred Embodiment
- FIG. 6 is a cross-sectional view showing the method of fabricating the semiconductor device according to a third preferred embodiment of the present invention. Carboxylic polyamide is dropped onto the conventional structure shown in FIG. 14 except onto the
solder bump 11. Thereafter, the resultant structure is heated to form thepolyimide layer 203 except on thesolder bump 11. This prevents alpha rays without interfering with the connection between thesolder bump 11 and the printed board. - Of course, the material used in the above described technique is not limited to carboxylic polyamide, but any material that is capable of preventing alpha rays and permitted to drop down may be used.
- Fourth Preferred Embodiment
- FIG. 7 is a cross-sectional view illustrating a structure of the semiconductor device according to a fourth preferred embodiment of the present invention. An
isolation oxide film 400 including an area AR, anddiffusion layers semiconductor substrate 101. Theinterlayer insulation film 102 surroundinggate electrodes 109 is formed on thesemiconductor substrate 101. The multilayer structure comprised of thealuminum pad 103, the layer oftitanium 105, and the layer ofnickel 106 is locally formed on theinterlayer insulation film 102. Thesolder bump 11 is disposed on the multilayer structure. Thefilm 201 is formed on theinterlayer insulation film 102 except on thesolder bump 11 The formation of thefilm 201 may be achieved using the process step of forming thepolyimide film 203 shown in the second or third preferred embodiment. - The presence of the
film 201 and thesolder bump 11 precludes an alpha ray coming through the air from entering thesemiconductor substrate 101. However, since solder generally contains lead as an ingredient and radioactive isotopes as an impurity in no small amounts, there is a likelihood that an alpha ray enters thesemiconductor substrate 101 from thesolder bump 11 itself. - To prevent this, the area AR that is visible from the
solder bump 11 without being obstructed by thefilm 201 is established at the upper surface of thesemiconductor substrate 101. An element whose operation is influenced by a slight increase in electric charge, such as a transistor and a capacitor, is not formed in the area AR which might be entered by the alpha ray from thesolder bump 11. For example, a capacitor formed in the semiconductor device employed in the CSP mounting is tens of femtocoulombs, and the operation of such a capacitor is influenced by the generation of a small number of electron-hole pairs. - The
isolation oxide film 400, for example, is formed in the area AR. Alternatively, the SOI transistor highly resistant to the alpha rays which is shown in the first preferred embodiment or a resistance element may be formed in the area AR. Since thefilm 201 prevents the alpha ray coming from thesolder bump 11 as well as the alpha ray coming through the air from reaching the transistor formed in other than the area AR, errors in the transistor due to the alpha rays are avoided. - Specifically, an element which has greater resistance to alpha rays than the element provided in other than the area AR may be formed in the area AR to allow effective area use without impairing the resistance of the entire semiconductor device to the alpha rays.
- Fifth Preferred Embodiment
- FIG. 8 is a cross-sectional view illustrating a structure of the semiconductor device according to a fifth preferred embodiment of the present invention. Like the first preferred embodiment, the semiconductor device of the fifth preferred embodiment comprises a plurality of
SOI transistors 121 to 123. TheSOI transistor 121 includes source and drainregions body portion 121 c, and agate electrode 121 d. TheSOI transistor 122 includes source and drainregions body portion 122 c, and agate electrode 122 d. TheSOI transistor 123 includes source and drainregions 123 a and 123 b, abody portion 123 c, and agate electrode 123 d. Thebody portions body portion 123 c is at a potential fixed by the known technique not shown. - For formation of a MOS SOI transistor in the area AR, fixing the potential of the body portion of the transistor using the known technique precludes the parasitic bipolar effects of the electrons and holes generated by alpha rays and allows the effective area use while further increasing the resistance to the alpha rays.
- Variation
- For avoiding the generation of an alpha ray from the
solder bump 11, a solder bump made of a lead-free alloy of gold and tin may be employed. - While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.
Claims (20)
1. A semiconductor device comprising:
a semiconductor layer provided in an insulating layer and including a transistor having an SOI structure formed therein;
an electrode provided on said insulating layer; and
an electrically conductive bump provided on said electrode.
2. The semiconductor device according to claim 1 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel.
3. The semiconductor device according to claim 1 ,
wherein said transistor is a MOS transistor.
4. The semiconductor device according to claim 1 ,
wherein said transistor includes a plurality of transistors field-shield isolated from each other and formed in said semiconductor layer.
5. The semiconductor device according to claim 4 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel.
6. A method of fabricating a semiconductor device, comprising the steps of:
(a) forming an electrode on a semiconductor substrate; and
(b) forming an electrically conductive bump on said electrode and
forming an insulating film for blocking an alpha ray and covering an upper surface of said semiconductor substrate except said electrode.
7. The method according to claim 6 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.
8. The method according to claim 6 ,
wherein said step (b) comprises the steps of
(b-1) forming said insulating film for blocking the alpha ray and covering the upper surface of said semiconductor substrate so that at least part of said electrode is exposed, and
(b-2) forming said electrically conductive bump on the exposed part of said electrode.
9. The method according to claim 8 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.
10. The method according to claim 6 ,
wherein said step (b) comprises the steps of
(b-1) forming said bump on said electrode, and
(b-2) dropping the material of said insulating film for blocking the alpha ray onto the upper surface of said semiconductor substrate except onto said electrode.
11. The method according to claim 10 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.
12. A semiconductor device comprising:
a semiconductor substrate;
an electrode disposed on said semiconductor substrate;
an electrically conductive bump provided on said electrode;
a film covering said semiconductor substrate except said bump and for blocking an alpha ray;
a first element disposed in said semiconductor substrate in an area that is visible from said bump without being obstructed by said film; and
a second element disposed in said semiconductor substrate in other than said area, said second element being less resistant to the alpha ray than said first element.
13. The semiconductor device according to claim 12 ,
wherein said bump is a solder bump.
14. The semiconductor device according to claim 13 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.
15. The semiconductor device according to claim 12 ,
wherein said first element is a MOS transistor having a body at a fixed potential.
16. The semiconductor device according to claim 15 ,
wherein said bump is a solder bump.
17. The semiconductor device according to claim 16 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.
18. A semiconductor device comprising:
a semiconductor substrate;
an electrode disposed on said semiconductor substrate;
an electrically conductive bump provided on said electrode;
a film covering said semiconductor substrate except said bump and for blocking an alpha ray;
an isolation oxide film disposed in said semiconductor substrate in an a re a that is visible from said bump without being obstructed by said film; and
an element disposed in said semiconductor substrate in other than said area.
19. The semiconductor device according to claim 18 ,
wherein said bump is a solder bump.
20. The semiconductor device according to claim 19 ,
wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/122,322 US20020110954A1 (en) | 1998-02-26 | 2002-04-16 | Semiconductor device and method of fabricating same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10-45459 | 1998-02-26 | ||
JP10045459A JPH11243208A (en) | 1998-02-26 | 1998-02-26 | Semiconductor device and method for manufacturing the same |
US09/122,863 US6459125B2 (en) | 1998-02-26 | 1998-07-27 | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
US10/122,322 US20020110954A1 (en) | 1998-02-26 | 2002-04-16 | Semiconductor device and method of fabricating same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/122,863 Division US6459125B2 (en) | 1998-02-26 | 1998-07-27 | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020110954A1 true US20020110954A1 (en) | 2002-08-15 |
Family
ID=12719953
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/122,863 Expired - Fee Related US6459125B2 (en) | 1998-02-26 | 1998-07-27 | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
US10/122,322 Abandoned US20020110954A1 (en) | 1998-02-26 | 2002-04-16 | Semiconductor device and method of fabricating same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/122,863 Expired - Fee Related US6459125B2 (en) | 1998-02-26 | 1998-07-27 | SOI based transistor inside an insulation layer with conductive bump on the insulation layer |
Country Status (6)
Country | Link |
---|---|
US (2) | US6459125B2 (en) |
JP (1) | JPH11243208A (en) |
KR (2) | KR19990071421A (en) |
DE (1) | DE19842441B4 (en) |
FR (1) | FR2775387B1 (en) |
TW (1) | TW382817B (en) |
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JPH11243208A (en) * | 1998-02-26 | 1999-09-07 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same |
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US6762503B2 (en) * | 2002-08-29 | 2004-07-13 | Micron Technology, Inc. | Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same |
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US7736915B2 (en) * | 2006-02-21 | 2010-06-15 | International Business Machines Corporation | Method for neutralizing trapped charge in a charge accumulation layer of a semiconductor structure |
WO2009027888A2 (en) * | 2007-08-24 | 2009-03-05 | Nxp B.V. | Solderable structure |
JP2009064812A (en) * | 2007-09-04 | 2009-03-26 | Panasonic Corp | Electrode structure in semiconductor device and related technology thereof |
US8809182B2 (en) | 2008-05-01 | 2014-08-19 | International Business Machines Corporation | Pad cushion structure and method of fabrication for Pb-free C4 integrated circuit chip joining |
KR101936039B1 (en) | 2012-10-30 | 2019-01-08 | 삼성전자 주식회사 | Semiconductor device |
US10163828B2 (en) * | 2013-11-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
JP6416800B2 (en) * | 2016-01-26 | 2018-10-31 | 株式会社東芝 | Semiconductor device |
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Also Published As
Publication number | Publication date |
---|---|
TW382817B (en) | 2000-02-21 |
KR19990071421A (en) | 1999-09-27 |
DE19842441A1 (en) | 1999-09-09 |
FR2775387A1 (en) | 1999-08-27 |
KR100377893B1 (en) | 2003-03-29 |
US20020003259A1 (en) | 2002-01-10 |
FR2775387B1 (en) | 2002-09-06 |
DE19842441B4 (en) | 2004-07-29 |
JPH11243208A (en) | 1999-09-07 |
KR20010072669A (en) | 2001-07-31 |
US6459125B2 (en) | 2002-10-01 |
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