US20020109236A1 - Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof - Google Patents
Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof Download PDFInfo
- Publication number
- US20020109236A1 US20020109236A1 US10/059,932 US5993202A US2002109236A1 US 20020109236 A1 US20020109236 A1 US 20020109236A1 US 5993202 A US5993202 A US 5993202A US 2002109236 A1 US2002109236 A1 US 2002109236A1
- Authority
- US
- United States
- Prior art keywords
- chip
- wirings
- chip selection
- connection terminals
- insulation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to semiconductor packaging technology and, more particularly, to a three-dimensional, multi-chip package with chip selection pads and a manufacturing method thereof.
- a conventional three-dimensional multi-chip package is manufactured as described below. After manufacturing a wafer and separating the wafer into a plurality of individual chips, the chip is attached and electrically connected to the substrate, and is encapsulated with a molding resin to produce a package. Then, a multi-chip package is obtained by stacking the packages.
- These multi-chip packages employ a lead frame, or a substrate such as a tape circuit board or a printed circuit board.
- a substrate such as a tape circuit board or a printed circuit board.
- Various interconnection methods such as a wire-bonding method, tape automated bonding (TAB) method, or flip chip-bonding method, are employed to establish electrical connection between the chip and the substrate.
- TAB tape automated bonding
- the multi-chip packages formed by stacking a plurality of packages are disclosed in U.S. Pat. Nos. 4,982,265, 4,996,583, 5,172,303, 5,198,888, 5,222,014, 5,247,423, 5,313,096, 5,783,870 and 6,072,233.
- these multi-chip packages are manufactured using complex processes.
- these multi-chip packages have much bigger sizes than the standard chip, thereby reducing the mounting density on the external apparatus.
- the multi-chip packages employ substrates, they cause long signal transmission routes and thereby signal delay results.
- multi-chip packages are classified into two types. One is a multi-chip package formed by stacking different types of chips, thereby achieving multi-functionality. The other is a multi-chip package formed by stacking the same types of chips, thereby improving memory capacity.
- each memory chip comprises a chip selection terminal.
- the Row Address Strobe (RAS), Column Address Strobe (CAS) or Chip Selection Pin (CSP) is used as the chip selection terminal.
- RAS Row Address Strobe
- CAS Column Address Strobe
- CSP Chip Selection Pin
- each substrate should comprise a connection wiring configuration different from the other substrates, thereby increasing the production cost and reducing productivity.
- the present invention increases memory capacity by providing a multi-chip package formed by stacking at least two of the same types of chips.
- the present invention provides a multi-chip package at the wafer-level, thereby reducing package size, increasing mounting density, and preventing signal delay.
- the present invention separates the chip selection terminal of each chip from one another via chip selection pads formed at the chip-level.
- the present invention simplifies the manufacturing process of the multi-chip package.
- a three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips.
- Each chip comprises an integrated circuit die, a chip selection terminal, a number (N- 1 ) of chip selection pads, an insulation layer, a number (N- 1 ) of metal wirings, upper connection terminals, lower connection terminals, and trench wirings.
- the chip selection terminal and the chip selection pads are formed on an upper surface of the die, and the chip selection pads are proximate to the chip selection terminal.
- the insulation layer is formed on the upper surface of the die, and the metal wirings are formed within the insulation layer and connected to the chip selection pads.
- the upper connection terminals are formed on the insulation layer and connected to the metal wiring.
- the lower connection terminals are formed on the lower surface of the die, and each of the lower connection terminals is connected to a corresponding one of the chip selection terminal and the chip selection pads.
- the trench wirings extend through the die, and connect the chip selection terminal and the chip selection pads to the lower connection terminals.
- a first chip selection pad next to the chip selection terminal is connected to the upper connection terminal formed above the chip selection terminal, and the (N- 1 )th chip selection pad is connected to the upper connection terminal formed above the (N- 2 )th chip selection pad.
- the individual chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip.
- the chip selection terminal of each chip is connected to a corresponding one of the lower connection terminals of a lowermost chip.
- the present invention provides a method of manufacturing a chip-level, three-dimensional, multi-chip package by stacking a number (N) of semiconductor integrated circuit chips.
- a chip selection terminal and a number (N- 1 ) of chip selection pads close to the chip selection terminal are formed on the upper active surface of the chip, and a plurality of trenches from the chip selection terminal and the chip selection pads are formed within the chip.
- trench wirings are formed by filling the trenches with a conductive material, and a number (N- 1 ) of first metal wirings formed along the upper surface of the chip, each of the first metal wirings are connected to a corresponding one of the chip selection pads.
- a first insulation layer is formed on the upper surface of the chip and the first metal wirings, and a plurality of upper connection terminals connected to the first metal wirings are formed on the first insulation layer.
- the lower surface of the chip is grinded so that the trench wirings are exposed through the lower surface of the chip.
- a plurality of lower connection terminals are formed on the lower surface of the chip, with each of the lower connection terminals being connected to a corresponding one of the trench wirings.
- the chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip.
- FIG. 1 is a cross-sectional view of a three-dimensional, multi-chip package in accordance with an embodiment of the present invention
- FIG. 2 is a cross-sectional view of an individual semiconductor integrated circuit chip used in the three-dimensional, multi-chip package of FIG. 1;
- FIGS. 3A to 3 K are cross-sectional views showing a manufacturing method of the three-dimensional, multi-chip package of FIG. 1;
- FIG. 4 is a cross-sectional view of a three-dimensional, multi-chip package in accordance with another embodiment of the present invention.
- FIG. 1 is a cross-sectional view of a chip-level, three-dimensional, multi-chip package in accordance with one embodiment of the present invention
- FIG. 2 is a cross-sectional view of an individual semiconductor integrated circuit chip used in the chip-level, three-dimensional, multi-chip package.
- a chip-level three-dimensional multi-chip package 100 of FIG. 1 is formed by stacking four (4) of the same types of semiconductor integrated circuit chips 10 in FIG. 2.
- Reference numerals 110 , 120 , 130 and 140 in FIG. 1 each represent individual integrated circuit chips.
- the chips 10 , 110 , 120 , 130 and 140 are memory chips such as DRAM chips or flash memory chips. It is well known that a memory chip comprises address input terminals for addressing memory cells, data input/output terminals for inputting/outputting data to/from the memory cells, and power supply terminals.
- the chip terminals 12 of the chips are interconnected to one another, while the chip selection terminal 12 a of one chip is separated from another chip selection terminal 12 a of another chip and connected to an external environment.
- the chip 10 comprises a die 11 .
- the die 11 is a die on wafer-level or a die individually separated (singulated) from a wafer.
- a plurality of chip terminals 12 and a chip selection terminal 12 a are formed on an upper active surface of the die 11 .
- Integrated circuits (not shown) are formed within the die 11 and connected to the chip terminals 12 and the chip selection terminal 12 a.
- the chip 10 comprises three (3) chip selection pads 12 b , 12 c , 12 d .
- the chip selection pads 12 b , 12 c , 12 d are formed on the upper surface of the die 11 close or adjacent to the chip selection terminal 12 a .
- the number of the chip selection pads is one less than the total number of stacked chips 10 .
- the multi-chip package is formed by stacking a number (N) of chips, a number (N- 1 ) of chip selection pads are required.
- the chip selection pads 12 b , 12 c , 12 d are not connected to the integrated circuits within the die 11 .
- First metal wirings 15 are formed on the upper surface of the die 11 and the chip selection pads 12 b , 12 c , and 12 d , with each chip selection pad connected to a corresponding one of the first metal wirings 15 .
- a first insulation layer 16 is formed on the upper surface of die 11 .
- the first metal wirings 15 are formed within the first insulation layer 16 .
- the first metal wirings 15 extend toward the chip selection terminal 12 a and electrically separated from one another.
- Each of the chip selection pads 12 b , 12 c , and 12 d is connected to a corresponding one of the lower connection terminals 23 b , 23 c , and 23 d formed on the lower surface of die 11 by trench wirings 14 perforating or extending through the die 11 .
- the chip selection terminal 12 a and the chip terminals 12 are electrically connected to the lower connection terminals 23 a and 23 , respectively, through the trench wirings 14 .
- a second insulation layer 20 is formed on the upper surface of the first insulation layer 16 .
- Second metal wirings 19 , 19 a are formed within the second insulation layer 20 .
- the second metal wirings 19 , 19 a are electrically connected to the first metal wirings 15 through first through wirings 18 formed within the first insulation layer 16 .
- the second metal wirings 19 , 19 a extend toward the chip selection terminal 12 a and are electrically separated from one another.
- the second metal wiring 19 connected to the first chip selection pad 12 b next to the chip selection terminal 12 a is disposed above the chip selection terminal 12 a
- the second metal wiring 19 connected to the second chip selection pad 12 c is disposed above the first chip selection pad 12 b .
- the second metal wiring 19 connected to the third chip selection pad 12 d is disposed above the second chip selection pad 12 c .
- the isolated second metal wiring 19 a is disposed above the third chip selection pad 12 d.
- Second through wirings 21 are formed within the second insulation layer 20 and connected to the second metal wirings 19 , 19 a .
- Upper connection terminals 22 a , 22 b , 22 c , 22 d are formed on the second insulation layer 20 and connected to the second through wirings 21 .
- Upper connection terminals 22 are formed on the second insulation layer 20 , and connected to the chip terminals 12 .
- the trench wiring 14 , the first through wiring 18 , and the second through wiring 21 all are formed on the same position.
- the first selection pad 12 b is connected to the upper connection terminal 22 a
- the second selection pad 12 c is connected to the upper connection terminal 22 b
- the third selection pad 12 d is connected to the upper connection terminal 22 c .
- the upper connection terminal 22 d is connected to the isolated second metal wiring 19 a , and is therefore not connected to any of the chip selection pads 12 b , 12 c , 12 d.
- the multi-chip package 100 in FIG. 1 is obtained by stacking a plurality of the semiconductor integrated circuit chips 10 , each chip having the above-described configuration.
- One chip 10 is connected to another chip by the attachment between the upper connection terminals 22 , 22 a - 22 d and the lower connection terminals 23 , 23 a - 23 d . That is, the upper connection terminals of a lower chip are attached to the lower connection terminals of an upper chip.
- the lower connection terminals 23 , 23 a - 23 d of the lowermost chip 110 serve as external terminals of the multi-chip package 100 and are attached to an external device such as a mother board (not shown).
- an external device such as a mother board (not shown).
- metal bumps or solder balls may be formed on the lower connection terminals 23 , 23 a - 23 d .
- metal bumps or solder balls may be formed on both/either the upper connection terminals 22 , 22 a - 22 d and/or the lower connection terminals 23 , 23 a - 23 d.
- the chip selection terminal 12 a of each chip 110 , 120 , 130 , 140 is connected to a corresponding one of the lower connection terminals 23 a - 23 d of the lowermost chip 110 .
- the chip selection terminal 12 a of the first chip 110 i.e. the lowermost chip 110
- the chip selection terminal 12 a of the third chip 130 is connected to the third lower connection terminals 23 c by passing through the third, the second and the first chip 130 , 120 , 110 .
- the multi-chip package in this embodiment of the present invention does not require that each chip have a different connection-wiring configuration.
- the three-dimensional multi-chip package of the present invention comprises a plurality of stacked chips, each chip with the same structure, the chip selection terminal of each chip is automatically separated from those of other chips.
- the chip selection pads are formed at the chip-level. That is, the chip selection pads are formed directly on the integrated circuit chip. Since the multi-chip package of the present invention does not require any additional substrate for forming the chip selection pads, the present invention can achieve chip-level, multi-chip packages. The present invention minimizes package size and improves mounting density, thus preventing signal delay.
- FIGS. 3A to 3 K are cross-sectional views showing a manufacturing method of the chip-level, three-dimensional, multi-chip package of the present invention.
- the manufacturing method of the chip-level, three-dimensional, multi-chip package of this embodiment is described below.
- a semiconductor integrated circuit die 11 is first fabricated.
- the die 11 may be one of several dies fabricated on a wafer or an individual die separated from the wafer.
- a plurality of the chip terminals 12 and a chip selection terminal 12 a are formed on the upper active surface of the die 11 .
- Three (3) chip selection pads 12 b , 12 c , 12 d are formed on the upper surface of the die 11 close to or proximate to the chip selection terminal 12 a .
- the chip selection pads number one less than the number of stacked chips.
- the chip terminals 12 and the chip selection terminal 12 a are connected to the circuits formed within the die 11 , while the chip selection pads 12 b , 12 c , 12 d are not connected to the circuits.
- trenches 13 each having a predetermined depth, perforate the die 11 from the chip terminals 12 , the chip selection terminal 12 a and the chip selection pads 12 b , 12 c , 12 d .
- the trenches 13 are formed by techniques such as a chemical etching method or a drilling method with a laser drill.
- the width of the trench 13 is smaller than the widths of the chip terminals 12 , the chip selection terminal 12 a and the chip selection pads 12 b , 12 c , 12 d.
- the trenches 13 are filled with a conductive material, forming the trench wirings 14 .
- a conductive material preferably, tungsten (W) is used as the conductive material, but other conductive materials may also be used.
- a conventional deposition technique such as Chemical Vaporization Deposition (CVD) is used in forming the trench wirings 14 .
- the first metal wirings 15 are formed on the upper surface of the die 11 .
- the first metal wirings 15 are formed on the chip selection pads 12 b , 12 c , 12 d , but not formed on the chip selection terminal 12 a and the chip terminals 12 .
- the first metal wirings 15 extend toward the chip selection terminal 12 a along the upper surface of the die 11 , and are separated from each other.
- Various metals such as copper (Cu) or tungsten (W) can be used as the first metal wirings 15 .
- a person skilled art will appreciate that other suitable conductive materials can be used in place.
- the first metal wirings 15 are formed by various methods.
- a metal layer is deposited on the whole upper surface of the die 11 and is etched using photoresist patterns to form the first metal wirings 15 . Also, photoresist patterns are first coated on the upper surface of the die 11 , and the metal layer is deposited thereon.
- the first insulation layer 16 is formed on the upper surface of the die 11 including the first metal wirings 15 .
- an inorganic insulation layer such as a nitride layer or an organic layer such as a polyimide layer or an epoxy layer is used.
- the inorganic insulation layer is formed by a conventional deposition method, and the organic insulation layer is formed by a conventional spin coating method.
- through holes 17 are formed by partially removing the first insulation layer 16 .
- the through holes 17 are formed by a conventional photolithography method.
- the through holes 17 are disposed on the chip terminals 12 and the first metal wirings 15 .
- the through holes 17 on the first metal wirings 15 are disposed between the neighboring trench wirings 14 .
- One end of each first metal wiring 15 is connected to a corresponding one of the chip selection pads 12 b , 12 c , 12 d and the other end is connected to the through hole 17 .
- the through holes 17 are filled with a conductive material, thereby forming the first through wirings 18 .
- the material and the forming method of the first through wirings 18 can be the same as those of the trench wirings 14 .
- the second metal wirings 19 , 19 a are formed on the first insulation layer 16 .
- the second metal wirings 19 are each connected to one of the chip selection pads 12 b , 12 c , 12 d through the first metal wirings 15 within the first insulation layer 16 , and the isolated second metal wiring 19 a is disposed above the third chip selection pad 12 d .
- the second metal wirings 19 are not formed above the chip terminals 12 and are laterally offset from the chip selection terminal 12 a .
- the second metal wirings 19 extend toward the chip selection terminal 12 a along the upper surface of the first insulation layer 16 .
- one of the second metal wirings 19 extends partly above and partly offset from the chip selection terminal 12 a and the others extend above the chip selection pads 12 b , 12 c .
- the material and the forming method of the second metal wirings 19 , 19 a can be the same as those of the first metal wirings 15 .
- the second insulation layer 20 is formed on the first insulation layer 16 .
- Through holes extend through the second insulation layer 20 and are filled with a conductive material, thereby forming the second through wirings 21 .
- the upper connection terminals 22 , 22 a , 22 b , 22 c , 22 d are formed on the second insulation layer 20 and connected to the second through wirings 21 .
- the upper connection terminals 22 , 22 a , 22 b , 22 c , 22 d each corresponds to one of the chip terminals 12 , the chip selection terminal 12 , and the chip selection pads 12 b , 12 c , 12 d .
- the upper connection terminal 22 above the chip terminal 12 is connected directly to the chip terminal 12 .
- the upper connection terminal 22 a above the chip selection terminal 12 a is not connected to the chip selection terminal 12 a , but rather to the first chip selection pad 12 b .
- each of the upper connection terminals 22 b , 22 c above the chip selection pads 12 b , 12 c , respectively, is not connected to the chip selection pads 12 b or 12 c , but connected to the neighboring chip selection pads 12 c , 12 d .
- the outermost upper connection terminal 22 d is connected to the isolated second metal wiring 19 a.
- the lower surface of the die 11 is partially removed by a conventional etching method or a conventional grinding method such as wafer back lapping, so that the trench wirings 14 are exposed through the lower surface of the die 11 .
- lower connection terminals 23 , 23 a , 23 b , 23 c , 23 d are formed on the lower surface of the die 11 so as to be electrically connected to the trench wirings 14 . Therefore, each of the lower connection terminals 23 , 23 a , 23 b , 23 c , 23 d is connected to a corresponding one of the chip terminals 12 , the chip selection terminal 12 a , and the chip selection pads 12 b , 12 c , 12 d through the trench wirings 14 .
- the semiconductor integrated circuit chip 10 in FIG. 2 is manufactured by the above-described processing steps. A plurality of the chips are stacked, and the upper connection terminals of a lower chip are attached to the lower connection terminals of an upper chip, thus obtaining the multi-chip package 100 in FIG. 1. Since each chip of the multi-chip package has the same structure, plural chips at the wafer-level can be collectively manufactured and separated into individual chips.
- FIG. 4 is a cross-sectional view of a chip-level, three-dimensional, multi-chip package 200 in accordance with another embodiment of the present invention.
- the multi-chip package 200 comprises three (3) integrated circuit chips 210 , 220 , 230 . Therefore, each of the chip 210 , 220 , 230 comprises two (2) chip selection pads 12 b , 12 c .
- the insulation layer 16 is formed on the upper surface of the die 11 , and the metal wirings 15 connected to the chip selection pads 12 b , 12 c are formed within the insulation layer 16 . Then, through holes extend through the insulation layer 16 to expose a portion of the metal wirings 15 and are filled with a conductive material, thereby forming the through wirings 18 .
- the through wirings 18 are connected to the upper connection terminals 22 a , 22 b on the insulation layer 16 .
- the upper connection terminal 22 is disposed above the chip terminal 12
- the isolated upper connection terminal 22 c is disposed above the outermost chip selection pad 12 c .
- the chip selection pad 12 a is not connected to any of the upper connection terminals 22 , 22 a , 22 b , 22 c .
- the lower connection terminals 23 , 23 a , 23 b , 23 c are formed on the lower surface of the die 11 correspondingly to the upper connection terminals 22 , 22 a , 22 b , 22 c .
- Each of the chip terminal 12 , the chip selection terminal 12 a , and the chip selection pads 12 b , 12 c is connected to a corresponding one of the lower connection terminals 23 , 23 a , 23 b , 23 c through the trench wirings 14 .
- the chips 210 , 220 , 230 can be stacked using an Anisotropic Conductive Film (ACF) or an Anisotropic Conductive Adhesive (ACA).
- ACF Anisotropic Conductive Film
- ACA Anisotropic Conductive Adhesive
- the ACF 25 or the ACA comprises an insulation film 24 a or an insulating adhesive, and conductive particles 24 b dispersed within the insulation film 24 a or the insulating adhesive.
- the insulation film 24 a or the insulation adhesive is compressed by the upper connection terminals 22 , 22 a - 22 c of a lower chip and the lower connection terminals 23 , 23 a - 23 c of an upper chip, the upper connection terminals 22 , 22 a - 22 c and the lower connection terminals 23 , 23 a - 23 c are electrically interconnected by the conductive particles 24 b .
- the insulation film 24 a or the insulation adhesive attaches the chip to another chip.
- the ACF 25 or the ACA other various insulation adhesives may be used as an adhesion layer.
- the chip selection terminal 12 a of each chip 210 , 220 , 230 is separated from the chip selection terminal 12 a of another chip and connected to a corresponding one of the lower connection terminals 23 a - 23 c of the lowermost chip 210 .
- the chip selection terminal of each chip is separated from the chip selection terminal of another chip by the chip selection pads formed on the chip. Therefore, the multi-chip package of the present invention does not require differently structured chips or any additional substrate. Accordingly, the present invention achieves the chip-level multi-chip package, using a simple process.
- the wafer-level multi-chip package of the present invention reduces package size and increases mounting density, thereby minimizing signal delay.
Abstract
Description
- 1 . Field of the Invention
- The present invention relates to semiconductor packaging technology and, more particularly, to a three-dimensional, multi-chip package with chip selection pads and a manufacturing method thereof.
- 2 . Description of the Related Art
- In order to satisfy the pressing demands for increased integration and multi-functionality, various three-dimensional multi-chip packages have recently been developed. A conventional three-dimensional multi-chip package is manufactured as described below. After manufacturing a wafer and separating the wafer into a plurality of individual chips, the chip is attached and electrically connected to the substrate, and is encapsulated with a molding resin to produce a package. Then, a multi-chip package is obtained by stacking the packages.
- These multi-chip packages employ a lead frame, or a substrate such as a tape circuit board or a printed circuit board. Various interconnection methods such as a wire-bonding method, tape automated bonding (TAB) method, or flip chip-bonding method, are employed to establish electrical connection between the chip and the substrate.
- The multi-chip packages formed by stacking a plurality of packages are disclosed in U.S. Pat. Nos. 4,982,265, 4,996,583, 5,172,303, 5,198,888, 5,222,014, 5,247,423, 5,313,096, 5,783,870 and 6,072,233. However, these multi-chip packages are manufactured using complex processes. Moreover, these multi-chip packages have much bigger sizes than the standard chip, thereby reducing the mounting density on the external apparatus. Further, since the multi-chip packages employ substrates, they cause long signal transmission routes and thereby signal delay results.
- While three-dimensional multi-chip packages on wafer-level or chip-level are disclosed in U.S. Pat. Nos. 4,394,712, 4,807,021, 4,897,708, 4,954,875, 5,202,754, 5,229,647 and 5,767,001. These multi-chip packages have the advantage of simple structures, smaller sizes, and simple manufacturing processes. Further, a multi-chip package at the wafer-level prevents signal delay. However, this technique is applied only to non-memory devices such as Application Specific Integrated Circuit (ASIC) or to multi-chip packages with multiple functions by stacking different types of chips.
- Generally, multi-chip packages are classified into two types. One is a multi-chip package formed by stacking different types of chips, thereby achieving multi-functionality. The other is a multi-chip package formed by stacking the same types of chips, thereby improving memory capacity.
- In order to improve memory capacity by stacking the same types of chips, there must be a chip selection mechanism to operate the desired chip. Therefore, each memory chip comprises a chip selection terminal. For example, in case of a DRAM chip, the Row Address Strobe (RAS), Column Address Strobe (CAS) or Chip Selection Pin (CSP) is used as the chip selection terminal. By selectively transmitting electronic signals to the specific chip selection terminal corresponding to the desired chip of the multi-chip package, the desired chip is selected for operation. Other non-selecting terminals of the memory chips in the multi-chip package are commonly connected together, but the chip selection terminal for each individual chip are isolated and connected to an external electronic component.
- The conventional technique for separating the chip selection terminals of each chip from one another is disclosed in the above-described multi-chip package. That is, the chip selection terminal of each chip is connected to an external electronic component through connection wirings formed on a substrate of the package. Therefore, in order to separate the chip selection terminal of each chip from one another, each substrate should comprise a connection wiring configuration different from the other substrates, thereby increasing the production cost and reducing productivity.
- The drawbacks are prevented by a conventional technique disclosed in U.S. Pat. No. 5,995,379. In this patent, the chip selection terminal of each chip is connected to external electronic components by a substrate with the same connection wiring configuration as the substrate of the other chips. However, since this technique is applied to a multi-chip package by stacking packages, it requires substrates on which connection wirings are formed. Therefore, this technique also has the previously described drawbacks of stacked, multi-chip packages such as large package size, reduced mounting density, complex manufacturing processes, and signal delay.
- The present invention increases memory capacity by providing a multi-chip package formed by stacking at least two of the same types of chips.
- The present invention provides a multi-chip package at the wafer-level, thereby reducing package size, increasing mounting density, and preventing signal delay.
- The present invention separates the chip selection terminal of each chip from one another via chip selection pads formed at the chip-level. The present invention simplifies the manufacturing process of the multi-chip package.
- According to one embodiment, a three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, a number (N-1) of chip selection pads, an insulation layer, a number (N-1) of metal wirings, upper connection terminals, lower connection terminals, and trench wirings.
- The chip selection terminal and the chip selection pads are formed on an upper surface of the die, and the chip selection pads are proximate to the chip selection terminal. The insulation layer is formed on the upper surface of the die, and the metal wirings are formed within the insulation layer and connected to the chip selection pads. The upper connection terminals are formed on the insulation layer and connected to the metal wiring. The lower connection terminals are formed on the lower surface of the die, and each of the lower connection terminals is connected to a corresponding one of the chip selection terminal and the chip selection pads. The trench wirings extend through the die, and connect the chip selection terminal and the chip selection pads to the lower connection terminals.
- Among the chip selection pads, a first chip selection pad next to the chip selection terminal is connected to the upper connection terminal formed above the chip selection terminal, and the (N-1)th chip selection pad is connected to the upper connection terminal formed above the (N-2)th chip selection pad.
- The individual chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip. The chip selection terminal of each chip is connected to a corresponding one of the lower connection terminals of a lowermost chip.
- Further, the present invention provides a method of manufacturing a chip-level, three-dimensional, multi-chip package by stacking a number (N) of semiconductor integrated circuit chips.
- In accordance with the method of the present invention, a chip selection terminal and a number (N-1) of chip selection pads close to the chip selection terminal are formed on the upper active surface of the chip, and a plurality of trenches from the chip selection terminal and the chip selection pads are formed within the chip. Then, trench wirings are formed by filling the trenches with a conductive material, and a number (N-1) of first metal wirings formed along the upper surface of the chip, each of the first metal wirings are connected to a corresponding one of the chip selection pads. A first insulation layer is formed on the upper surface of the chip and the first metal wirings, and a plurality of upper connection terminals connected to the first metal wirings are formed on the first insulation layer. The lower surface of the chip is grinded so that the trench wirings are exposed through the lower surface of the chip. A plurality of lower connection terminals are formed on the lower surface of the chip, with each of the lower connection terminals being connected to a corresponding one of the trench wirings. The chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip.
- These and other objects, features, and advantages of the present invention will be readily understood with reference to the following detailed description provided in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and, in which:
- FIG. 1 is a cross-sectional view of a three-dimensional, multi-chip package in accordance with an embodiment of the present invention;
- FIG. 2 is a cross-sectional view of an individual semiconductor integrated circuit chip used in the three-dimensional, multi-chip package of FIG. 1;
- FIGS. 3A to3K are cross-sectional views showing a manufacturing method of the three-dimensional, multi-chip package of FIG. 1; and
- FIG. 4 is a cross-sectional view of a three-dimensional, multi-chip package in accordance with another embodiment of the present invention.
- Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
- FIG. 1 is a cross-sectional view of a chip-level, three-dimensional, multi-chip package in accordance with one embodiment of the present invention, and FIG. 2 is a cross-sectional view of an individual semiconductor integrated circuit chip used in the chip-level, three-dimensional, multi-chip package. With reference to FIGS. 1 and 2, a first embodiment of the present invention is described below.
- In order to improve memory capacity, a chip-level three-
dimensional multi-chip package 100 of FIG. 1 is formed by stacking four (4) of the same types of semiconductor integratedcircuit chips 10 in FIG. 2.Reference numerals - The
chips chip terminals 12 of the chips are interconnected to one another, while thechip selection terminal 12 a of one chip is separated from anotherchip selection terminal 12 a of another chip and connected to an external environment. - As shown in detail in FIG. 2, the
chip 10 comprises adie 11. Herein, thedie 11 is a die on wafer-level or a die individually separated (singulated) from a wafer. A plurality ofchip terminals 12 and achip selection terminal 12 a are formed on an upper active surface of thedie 11. Integrated circuits (not shown) are formed within thedie 11 and connected to thechip terminals 12 and thechip selection terminal 12 a. - The
chip 10 comprises three (3)chip selection pads chip selection pads chip selection terminal 12 a. Herein, the number of the chip selection pads is one less than the total number of stackedchips 10. For example, if the multi-chip package is formed by stacking a number (N) of chips, a number (N-1) of chip selection pads are required. Thechip selection pads die 11. - First metal wirings15 are formed on the upper surface of the
die 11 and thechip selection pads first metal wirings 15. Afirst insulation layer 16 is formed on the upper surface ofdie 11. Thus, thefirst metal wirings 15 are formed within thefirst insulation layer 16. Thefirst metal wirings 15 extend toward thechip selection terminal 12 a and electrically separated from one another. Each of thechip selection pads lower connection terminals die 11 bytrench wirings 14 perforating or extending through thedie 11. Thechip selection terminal 12 a and thechip terminals 12 are electrically connected to thelower connection terminals trench wirings 14. - A
second insulation layer 20 is formed on the upper surface of thefirst insulation layer 16. Second metal wirings 19, 19 a are formed within thesecond insulation layer 20. Thesecond metal wirings first metal wirings 15 through first throughwirings 18 formed within thefirst insulation layer 16. Thesecond metal wirings chip selection terminal 12 a and are electrically separated from one another. Thesecond metal wiring 19 connected to the firstchip selection pad 12 b next to thechip selection terminal 12 a is disposed above thechip selection terminal 12 a, and thesecond metal wiring 19 connected to the secondchip selection pad 12 c is disposed above the firstchip selection pad 12 b. Thesecond metal wiring 19 connected to the thirdchip selection pad 12 d is disposed above the secondchip selection pad 12 c. The isolatedsecond metal wiring 19 a is disposed above the thirdchip selection pad 12 d. - Second through
wirings 21 are formed within thesecond insulation layer 20 and connected to thesecond metal wirings Upper connection terminals second insulation layer 20 and connected to the second throughwirings 21. -
Upper connection terminals 22 are formed on thesecond insulation layer 20, and connected to thechip terminals 12. Herein, in order to electrically connect thechip terminal 12 to the correspondingupper connection terminal 22 and to the correspondinglower connection terminal 23, thetrench wiring 14, the first throughwiring 18, and the second through wiring 21 all are formed on the same position. Thus, thefirst selection pad 12 b is connected to theupper connection terminal 22 a, and thesecond selection pad 12 c is connected to theupper connection terminal 22 b. Thethird selection pad 12 d is connected to theupper connection terminal 22 c. Theupper connection terminal 22 d is connected to the isolatedsecond metal wiring 19 a, and is therefore not connected to any of thechip selection pads - The
multi-chip package 100 in FIG. 1 is obtained by stacking a plurality of the semiconductor integratedcircuit chips 10, each chip having the above-described configuration. Onechip 10 is connected to another chip by the attachment between theupper connection terminals lower connection terminals - The
lower connection terminals lowermost chip 110 serve as external terminals of themulti-chip package 100 and are attached to an external device such as a mother board (not shown). In order to easily attach thelower connection terminals lower connection terminals chips upper connection terminals lower connection terminals - The
chip selection terminal 12 a of eachchip lower connection terminals 23 a-23 d of thelowermost chip 110. As shown in FIG. 1, thechip selection terminal 12 a of thefirst chip 110, i.e. thelowermost chip 110, is connected to the firstlower connection terminals 23 a by thetrench wiring 14. Thechip selection terminal 12 a of thethird chip 130 is connected to the thirdlower connection terminals 23 c by passing through the third, the second and thefirst chip - In order to separate the chip selection terminal of one chip from the chip selection terminals of other chips, the multi-chip package in this embodiment of the present invention does not require that each chip have a different connection-wiring configuration. Although the three-dimensional multi-chip package of the present invention comprises a plurality of stacked chips, each chip with the same structure, the chip selection terminal of each chip is automatically separated from those of other chips. Also, the chip selection pads are formed at the chip-level. That is, the chip selection pads are formed directly on the integrated circuit chip. Since the multi-chip package of the present invention does not require any additional substrate for forming the chip selection pads, the present invention can achieve chip-level, multi-chip packages. The present invention minimizes package size and improves mounting density, thus preventing signal delay.
- FIGS. 3A to3K are cross-sectional views showing a manufacturing method of the chip-level, three-dimensional, multi-chip package of the present invention. With reference to FIGS. 3A to 3K, the manufacturing method of the chip-level, three-dimensional, multi-chip package of this embodiment is described below.
- As shown in FIG. 3A, a semiconductor integrated circuit die11 is first fabricated. The die 11 may be one of several dies fabricated on a wafer or an individual die separated from the wafer. As is identical to conventional chips, a plurality of the
chip terminals 12 and achip selection terminal 12 a are formed on the upper active surface of thedie 11. Three (3)chip selection pads chip selection terminal 12 a. The chip selection pads number one less than the number of stacked chips. Thechip terminals 12 and thechip selection terminal 12 a are connected to the circuits formed within thedie 11, while thechip selection pads - As shown in FIG. 3B,
trenches 13, each having a predetermined depth, perforate the die 11 from thechip terminals 12, thechip selection terminal 12 a and thechip selection pads trenches 13 are formed by techniques such as a chemical etching method or a drilling method with a laser drill. The width of thetrench 13 is smaller than the widths of thechip terminals 12, thechip selection terminal 12 a and thechip selection pads - Then, as shown in FIG. 3C, the
trenches 13 are filled with a conductive material, forming thetrench wirings 14. Preferably, tungsten (W) is used as the conductive material, but other conductive materials may also be used. A conventional deposition technique such as Chemical Vaporization Deposition (CVD) is used in forming thetrench wirings 14. - As shown in FIG. 3D, the
first metal wirings 15 are formed on the upper surface of thedie 11. Thefirst metal wirings 15 are formed on thechip selection pads chip selection terminal 12 a and thechip terminals 12. Thefirst metal wirings 15 extend toward thechip selection terminal 12 a along the upper surface of the die 11, and are separated from each other. Various metals such as copper (Cu) or tungsten (W) can be used as thefirst metal wirings 15. A person skilled art will appreciate that other suitable conductive materials can be used in place. Thefirst metal wirings 15 are formed by various methods. For example a metal layer is deposited on the whole upper surface of thedie 11 and is etched using photoresist patterns to form thefirst metal wirings 15. Also, photoresist patterns are first coated on the upper surface of the die 11, and the metal layer is deposited thereon. - As shown in FIG. 3E, the
first insulation layer 16 is formed on the upper surface of the die 11 including thefirst metal wirings 15. For thefirst insulation layer 16, an inorganic insulation layer such as a nitride layer or an organic layer such as a polyimide layer or an epoxy layer is used. The inorganic insulation layer is formed by a conventional deposition method, and the organic insulation layer is formed by a conventional spin coating method. - As shown in FIG. 3F, through
holes 17 are formed by partially removing thefirst insulation layer 16. The through holes 17 are formed by a conventional photolithography method. The through holes 17 are disposed on thechip terminals 12 and thefirst metal wirings 15. The through holes 17 on thefirst metal wirings 15 are disposed between the neighboringtrench wirings 14. One end of eachfirst metal wiring 15 is connected to a corresponding one of thechip selection pads hole 17. - As shown in FIG. 3G, the through
holes 17 are filled with a conductive material, thereby forming the first throughwirings 18. The material and the forming method of the first throughwirings 18 can be the same as those of thetrench wirings 14. - As shown in FIG. 3H, the
second metal wirings first insulation layer 16. Thesecond metal wirings 19 are each connected to one of thechip selection pads first metal wirings 15 within thefirst insulation layer 16, and the isolatedsecond metal wiring 19 a is disposed above the thirdchip selection pad 12 d. Thesecond metal wirings 19 are not formed above thechip terminals 12 and are laterally offset from thechip selection terminal 12 a. Thesecond metal wirings 19 extend toward thechip selection terminal 12 a along the upper surface of thefirst insulation layer 16. Therefore, one of thesecond metal wirings 19 extends partly above and partly offset from thechip selection terminal 12 a and the others extend above thechip selection pads second metal wirings first metal wirings 15. - Then, similar to the steps in FIGS. 3E to3G, the
second insulation layer 20 is formed on thefirst insulation layer 16. Through holes extend through thesecond insulation layer 20 and are filled with a conductive material, thereby forming the second throughwirings 21. As shown in FIG. 31, theupper connection terminals second insulation layer 20 and connected to the second throughwirings 21. Theupper connection terminals chip terminals 12, thechip selection terminal 12, and thechip selection pads upper connection terminal 22 above thechip terminal 12 is connected directly to thechip terminal 12. Theupper connection terminal 22 a above thechip selection terminal 12 a is not connected to thechip selection terminal 12 a, but rather to the firstchip selection pad 12 b. Likewise, each of theupper connection terminals chip selection pads chip selection pads chip selection pads upper connection terminal 22 d is connected to the isolatedsecond metal wiring 19 a. - As shown in FIG. 3J, the lower surface of the die11 is partially removed by a conventional etching method or a conventional grinding method such as wafer back lapping, so that the trench wirings 14 are exposed through the lower surface of the
die 11. - As shown in FIG. 3K,
lower connection terminals trench wirings 14. Therefore, each of thelower connection terminals chip terminals 12, thechip selection terminal 12 a, and thechip selection pads trench wirings 14. - The semiconductor integrated
circuit chip 10 in FIG. 2 is manufactured by the above-described processing steps. A plurality of the chips are stacked, and the upper connection terminals of a lower chip are attached to the lower connection terminals of an upper chip, thus obtaining themulti-chip package 100 in FIG. 1. Since each chip of the multi-chip package has the same structure, plural chips at the wafer-level can be collectively manufactured and separated into individual chips. - The second metal wirings of the above-described first embodiment of the present invention may be used as the upper connection terminals. Further, in stacking the chips, an adhesive layer or an anisotropic conductive film may be interposed between the chips. FIG. 4 is a cross-sectional view of a chip-level, three-dimensional,
multi-chip package 200 in accordance with another embodiment of the present invention. - In accordance with the second embodiment of the present invention, the
multi-chip package 200 comprises three (3) integratedcircuit chips chip chip selection pads insulation layer 16 is formed on the upper surface of the die 11, and the metal wirings 15 connected to thechip selection pads insulation layer 16. Then, through holes extend through theinsulation layer 16 to expose a portion of themetal wirings 15 and are filled with a conductive material, thereby forming the throughwirings 18. - The through
wirings 18 are connected to theupper connection terminals insulation layer 16. Theupper connection terminal 22 is disposed above thechip terminal 12, and the isolatedupper connection terminal 22 c is disposed above the outermostchip selection pad 12 c. Thechip selection pad 12 a is not connected to any of theupper connection terminals lower connection terminals upper connection terminals chip terminal 12, thechip selection terminal 12 a, and thechip selection pads lower connection terminals trench wirings 14. - The
chips ACF 25 or the ACA comprises aninsulation film 24 a or an insulating adhesive, andconductive particles 24 b dispersed within theinsulation film 24 a or the insulating adhesive. As theinsulation film 24 a or the insulation adhesive is compressed by theupper connection terminals lower connection terminals upper connection terminals lower connection terminals conductive particles 24 b. Thereby, theinsulation film 24 a or the insulation adhesive attaches the chip to another chip. Instead of theACF 25 or the ACA, other various insulation adhesives may be used as an adhesion layer. - In the above-described
multi-chip package 200 of the second embodiment, thechip selection terminal 12 a of eachchip chip selection terminal 12 a of another chip and connected to a corresponding one of thelower connection terminals 23 a-23 c of thelowermost chip 210. - In the multi-chip package of the present invention, the chip selection terminal of each chip is separated from the chip selection terminal of another chip by the chip selection pads formed on the chip. Therefore, the multi-chip package of the present invention does not require differently structured chips or any additional substrate. Accordingly, the present invention achieves the chip-level multi-chip package, using a simple process.
- The wafer-level multi-chip package of the present invention reduces package size and increases mounting density, thereby minimizing signal delay.
- Although the preferred embodiments of the present invention have been described in detail hereinabove, it should be understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the art will still fall within the spirit and scope of the present invention as defined in the appended claims.
Claims (14)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010006318A KR100364635B1 (en) | 2001-02-09 | 2001-02-09 | Chip-Level Three-Dimensional Multi-Chip Package Having Chip Selection Pad Formed On Chip-Level And Making Method Therefor |
KR2001-6318 | 2001-02-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020109236A1 true US20020109236A1 (en) | 2002-08-15 |
US6448661B1 US6448661B1 (en) | 2002-09-10 |
Family
ID=19705535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/059,932 Expired - Lifetime US6448661B1 (en) | 2001-02-09 | 2002-01-28 | Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof |
Country Status (3)
Country | Link |
---|---|
US (1) | US6448661B1 (en) |
JP (1) | JP4519392B2 (en) |
KR (1) | KR100364635B1 (en) |
Cited By (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030234434A1 (en) * | 2002-06-21 | 2003-12-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
US20040126994A1 (en) * | 2002-12-31 | 2004-07-01 | Rafael Reif | Method of forming a multi-layer semiconductor structure having a seamless bonding interface |
US20040124538A1 (en) * | 2002-12-31 | 2004-07-01 | Rafael Reif | Multi-layer integrated semiconductor structure |
US20040219765A1 (en) * | 2002-12-31 | 2004-11-04 | Rafael Reif | Method of forming a multi-layer semiconductor structure incorporating a processing handle member |
EP1587141A2 (en) | 2004-04-13 | 2005-10-19 | Sun Microsystems, Inc. | Method and apparatus involving capacitively coupled communication within a stack of laminated chips |
EP1686623A1 (en) * | 2003-10-30 | 2006-08-02 | Japan Science and Technology Agency | Semiconductor device and process for fabricating the same |
US20070001312A1 (en) * | 2005-06-30 | 2007-01-04 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
US20070126105A1 (en) * | 2005-12-06 | 2007-06-07 | Elpida Memory Inc. | Stacked type semiconductor memory device and chip selection circuit |
WO2007082854A1 (en) * | 2006-01-18 | 2007-07-26 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20080083976A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20080083977A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20080116544A1 (en) * | 2006-11-22 | 2008-05-22 | Tessera, Inc. | Packaged semiconductor chips with array |
US20080116545A1 (en) * | 2006-11-22 | 2008-05-22 | Tessera, Inc. | Packaged semiconductor chips |
US20080157323A1 (en) * | 2006-12-28 | 2008-07-03 | Tessera, Inc. | Stacked packages |
US20080171413A1 (en) * | 2007-01-17 | 2008-07-17 | International Business Machines Corporation | Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels |
US20080237834A1 (en) * | 2007-03-29 | 2008-10-02 | Advanced Chip Engineering Technology Inc. | Chip packaging structure and chip packaging process |
US20080246136A1 (en) * | 2007-03-05 | 2008-10-09 | Tessera, Inc. | Chips having rear contacts connected by through vias to front contacts |
US20090043917A1 (en) * | 2007-08-06 | 2009-02-12 | Thilo Wagner | Electronic Circuit and Method for Selecting an Electronic Circuit |
US20090039528A1 (en) * | 2007-08-09 | 2009-02-12 | Tessera, Inc. | Wafer level stacked packages with individual chip selection |
US20090039915A1 (en) * | 2007-08-06 | 2009-02-12 | Hermann Ruckerbauer | Integrated Circuit, Chip Stack and Data Processing System |
US20090065907A1 (en) * | 2007-07-31 | 2009-03-12 | Tessera, Inc. | Semiconductor packaging process using through silicon vias |
US20090124072A1 (en) * | 2007-11-14 | 2009-05-14 | Samsung Electronics Co., Ltd. | Semiconductor device having through electrode and method of fabricating the same |
US20090160065A1 (en) * | 2006-10-10 | 2009-06-25 | Tessera, Inc. | Reconstituted Wafer Level Stacking |
US20090212381A1 (en) * | 2008-02-26 | 2009-08-27 | Tessera, Inc. | Wafer level packages for rear-face illuminated solid state image sensors |
US20090269888A1 (en) * | 2005-06-14 | 2009-10-29 | John Trezza | Chip-based thermo-stack |
US20090294916A1 (en) * | 2008-06-02 | 2009-12-03 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3d wafer stacking |
US20090316378A1 (en) * | 2008-06-16 | 2009-12-24 | Tessera Research Llc | Wafer level edge stacking |
US20100053407A1 (en) * | 2008-02-26 | 2010-03-04 | Tessera, Inc. | Wafer level compliant packages for rear-face illuminated solid state image sensors |
WO2010049852A1 (en) * | 2008-10-30 | 2010-05-06 | Nxp B.V. | Through-substrate via and redistribution layer with metal paste |
US7785987B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Isolating chip-to-chip contact |
US20100219503A1 (en) * | 2005-06-14 | 2010-09-02 | John Trezza | Chip capacitive coupling |
US20100225002A1 (en) * | 2009-03-06 | 2010-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional System-in-Package Architecture |
US20100230795A1 (en) * | 2009-03-13 | 2010-09-16 | Tessera Technologies Hungary Kft. | Stacked microelectronic assemblies having vias extending through bond pads |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US20110006432A1 (en) * | 2007-07-27 | 2011-01-13 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US7884483B2 (en) | 2005-06-14 | 2011-02-08 | Cufer Asset Ltd. L.L.C. | Chip connector |
US20110086486A1 (en) * | 2008-06-10 | 2011-04-14 | Ho-Jin Lee | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein |
US8021922B2 (en) | 2005-06-14 | 2011-09-20 | Cufer Asset Ltd. L.L.C. | Remote chip attachment |
US8084851B2 (en) | 2005-06-14 | 2011-12-27 | Cufer Asset Ltd. L.L.C. | Side stacking apparatus and method |
EP2474030A1 (en) * | 2009-09-02 | 2012-07-11 | MOSAID Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
EP2534659A2 (en) * | 2010-02-11 | 2012-12-19 | Micron Technology, Inc. | Memory dies, stacked memories, memory devices and methods |
CN102844862A (en) * | 2010-04-12 | 2012-12-26 | 高通股份有限公司 | Dual-side interconnected cmos for stacked integrated circuits |
US8432045B2 (en) | 2010-11-15 | 2013-04-30 | Tessera, Inc. | Conductive pads defined by embedded traces |
EP2546873A3 (en) * | 2011-06-14 | 2013-05-29 | Elpida Memory, Inc. | Semiconductor device |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US20130228920A1 (en) * | 2009-09-14 | 2013-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for adhesive material at wafer edge |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8593891B2 (en) | 2010-10-13 | 2013-11-26 | Elpida Memory, Inc. | Semiconductor device and test method thereof |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
CN103887288A (en) * | 2012-12-20 | 2014-06-25 | 爱思开海力士有限公司 | Semiconductor Integrated Circuit And Semiconductor System With The Same |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8924903B2 (en) | 2010-11-30 | 2014-12-30 | Ps4 Luxco S.A.R.L. | Semiconductor device having plural memory chip |
CN104465567A (en) * | 2013-09-24 | 2015-03-25 | 南亚科技股份有限公司 | Chip package and method for forming the same |
CN104779218A (en) * | 2014-01-15 | 2015-07-15 | 南亚科技股份有限公司 | Chip package |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
TWI588882B (en) * | 2013-09-13 | 2017-06-21 | 財團法人工業技術研究院 | Thinned integrated circuit device and manufacturing process for the same |
JP2019102744A (en) * | 2017-12-07 | 2019-06-24 | 日本放送協会 | Stacked semiconductor device |
US20190259725A1 (en) * | 2017-07-21 | 2019-08-22 | United Microelectronics Corp. | Manufacturing method of die-stack structure |
US10790266B2 (en) | 2016-09-23 | 2020-09-29 | Toshiba Memory Corporation | Memory device with a plurality of stacked memory core chips |
CN115799230A (en) * | 2023-02-08 | 2023-03-14 | 深圳时识科技有限公司 | Stacked chip and electronic device |
Families Citing this family (203)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003060053A (en) * | 2001-08-10 | 2003-02-28 | Fujitsu Ltd | Semiconductor chip, semiconductor integrated circuit device comprising it and method for selecting semiconductor chip |
US6759275B1 (en) | 2001-09-04 | 2004-07-06 | Megic Corporation | Method for making high-performance RF integrated circuits |
US6762076B2 (en) * | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
KR100497111B1 (en) * | 2003-03-25 | 2005-06-28 | 삼성전자주식회사 | WL CSP, stack package stacking the same and manufacturing method thereof |
JP4419049B2 (en) | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | Memory module and memory system |
US7098541B2 (en) * | 2003-05-19 | 2006-08-29 | Hewlett-Packard Development Company, L.P. | Interconnect method for directly connected stacked integrated circuits |
US20050179120A1 (en) * | 2003-12-16 | 2005-08-18 | Koji Yamaguchi | Process for producing semiconductor device, semiconductor device, circuit board and electronic equipment |
DE102004060345A1 (en) | 2003-12-26 | 2005-10-06 | Elpida Memory, Inc. | Semiconductor device with layered chips |
JP2007250561A (en) * | 2004-04-12 | 2007-09-27 | Japan Science & Technology Agency | Semiconductor element and semiconductor system |
JPWO2005101476A1 (en) * | 2004-04-16 | 2008-03-06 | 独立行政法人科学技術振興機構 | Semiconductor element and method of manufacturing semiconductor element |
JP4353861B2 (en) | 2004-06-30 | 2009-10-28 | Necエレクトロニクス株式会社 | Semiconductor device |
US7419852B2 (en) * | 2004-08-27 | 2008-09-02 | Micron Technology, Inc. | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies |
US7462925B2 (en) * | 2004-11-12 | 2008-12-09 | Macronix International Co., Ltd. | Method and apparatus for stacking electrical components using via to provide interconnection |
JP4577688B2 (en) * | 2005-05-09 | 2010-11-10 | エルピーダメモリ株式会社 | Semiconductor chip selection method, semiconductor chip, and semiconductor integrated circuit device |
US7317256B2 (en) * | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
JP4753725B2 (en) * | 2006-01-20 | 2011-08-24 | エルピーダメモリ株式会社 | Multilayer semiconductor device |
KR100743648B1 (en) * | 2006-03-17 | 2007-07-27 | 주식회사 하이닉스반도체 | Method of manufacturing wafer level system in packge |
US7474005B2 (en) * | 2006-05-31 | 2009-01-06 | Alcatel-Lucent Usa Inc. | Microelectronic element chips |
KR100762206B1 (en) * | 2006-06-08 | 2007-10-01 | 삼성전자주식회사 | Semiconductor memory device and method of generating chip enable signal of the same |
US7446424B2 (en) * | 2006-07-19 | 2008-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor package |
US20080122058A1 (en) * | 2006-09-07 | 2008-05-29 | Masahiro Inohara | Partially stacked semiconductor devices |
JP4312786B2 (en) * | 2006-11-02 | 2009-08-12 | Okiセミコンダクタ株式会社 | Manufacturing method of semiconductor chip |
US8018071B2 (en) | 2007-02-07 | 2011-09-13 | Samsung Electronics Co., Ltd. | Stacked structure using semiconductor devices and semiconductor device package including the same |
US8232183B2 (en) * | 2007-05-04 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process and apparatus for wafer-level flip-chip assembly |
KR100874926B1 (en) | 2007-06-07 | 2008-12-19 | 삼성전자주식회사 | Stack modules, cards containing them and systems containing them |
KR100920039B1 (en) * | 2007-06-21 | 2009-10-07 | 주식회사 하이닉스반도체 | Stacked semiconductor package and method of manufacturing thereof |
KR100945504B1 (en) * | 2007-06-26 | 2010-03-09 | 주식회사 하이닉스반도체 | Stack package and method for manufacturing of the same |
KR100909969B1 (en) * | 2007-06-28 | 2009-07-29 | 삼성전자주식회사 | Semiconductor devices and method of fabricating the same, and stacked modules, card and system including the same |
JP5557419B2 (en) | 2007-10-17 | 2014-07-23 | スパンション エルエルシー | Semiconductor device |
US8492263B2 (en) * | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
JP2009139273A (en) | 2007-12-07 | 2009-06-25 | Elpida Memory Inc | Laminated semiconductor device, and continuity test |
US8399973B2 (en) * | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
KR101465948B1 (en) * | 2007-12-27 | 2014-12-10 | 삼성전자주식회사 | A wafer level stack package and method of manufacturing a wafer level stack package |
KR101420817B1 (en) * | 2008-01-15 | 2014-07-21 | 삼성전자주식회사 | Semiconductor Integrated Circuit Device Electrically Connecting Integrated Circuit Modules Stacked Sequentially With 3-Dimensional Serial And Parallel Circuits And Method Of Forming The Same |
KR100920053B1 (en) * | 2008-01-25 | 2009-10-07 | 주식회사 하이닉스반도체 | Semiconductor package and method of manufacturing the same |
US8138610B2 (en) * | 2008-02-08 | 2012-03-20 | Qimonda Ag | Multi-chip package with interconnected stacked chips |
US11266014B2 (en) | 2008-02-14 | 2022-03-01 | Metrospec Technology, L.L.C. | LED lighting systems and method |
US8007286B1 (en) * | 2008-03-18 | 2011-08-30 | Metrospec Technology, Llc | Circuit boards interconnected by overlapping plated through holes portions |
US8851356B1 (en) | 2008-02-14 | 2014-10-07 | Metrospec Technology, L.L.C. | Flexible circuit board interconnection and methods |
US10334735B2 (en) | 2008-02-14 | 2019-06-25 | Metrospec Technology, L.L.C. | LED lighting systems and methods |
KR100950759B1 (en) * | 2008-03-07 | 2010-04-05 | 주식회사 하이닉스반도체 | Stack package |
US8637883B2 (en) * | 2008-03-19 | 2014-01-28 | Cree, Inc. | Low index spacer layer in LED devices |
US8912654B2 (en) * | 2008-04-11 | 2014-12-16 | Qimonda Ag | Semiconductor chip with integrated via |
KR100988262B1 (en) | 2008-04-25 | 2010-10-18 | 주식회사 하이닉스반도체 | Semiconductor package and stacked semiconductor pacakge having the same |
TWI389291B (en) * | 2008-05-13 | 2013-03-11 | Ind Tech Res Inst | Structure of three-dimensional stacking dice |
US8030208B2 (en) * | 2008-06-02 | 2011-10-04 | Hong Kong Applied Science and Technology Research Institute Company Limited | Bonding method for through-silicon-via based 3D wafer stacking |
CN101542701B (en) * | 2008-06-05 | 2011-05-25 | 香港应用科技研究院有限公司 | Bonding method of three dimensional wafer lamination based on silicon through holes |
US8334170B2 (en) * | 2008-06-27 | 2012-12-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking devices |
KR101001635B1 (en) | 2008-06-30 | 2010-12-17 | 주식회사 하이닉스반도체 | Semiconductor package, stacked semiconductor package having the same, and method for selecting one semiconductor chip of the stacked semiconductor package |
US7851346B2 (en) * | 2008-07-21 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding metallurgy for three-dimensional interconnect |
US7843072B1 (en) | 2008-08-12 | 2010-11-30 | Amkor Technology, Inc. | Semiconductor package having through holes |
US8932906B2 (en) | 2008-08-19 | 2015-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via bonding structure |
JP2010056139A (en) * | 2008-08-26 | 2010-03-11 | Toshiba Corp | Multilayer semiconductor device |
US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
KR20100042021A (en) * | 2008-10-15 | 2010-04-23 | 삼성전자주식회사 | Semiconductor chip, stack module, memory card, and method of fabricating the semiconductor chip |
US7843052B1 (en) | 2008-11-13 | 2010-11-30 | Amkor Technology, Inc. | Semiconductor devices and fabrication methods thereof |
US7943421B2 (en) * | 2008-12-05 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Component stacking using pre-formed adhesive films |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US9117828B2 (en) * | 2009-03-27 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of handling a thin wafer |
WO2010131391A1 (en) * | 2009-05-14 | 2010-11-18 | パナソニック株式会社 | Semiconductor device and electronic device provided with same |
US8377816B2 (en) * | 2009-07-30 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming electrical connections |
US8841766B2 (en) | 2009-07-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
US9160349B2 (en) | 2009-08-27 | 2015-10-13 | Micron Technology, Inc. | Die location compensation |
US8324738B2 (en) | 2009-09-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
US8803332B2 (en) * | 2009-09-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delamination resistance of stacked dies in die saw |
US8143097B2 (en) * | 2009-09-23 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
US9875911B2 (en) * | 2009-09-23 | 2018-01-23 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interposer with opening to contain semiconductor die |
KR101069517B1 (en) | 2009-10-05 | 2011-09-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
US8698321B2 (en) * | 2009-10-07 | 2014-04-15 | Qualcomm Incorporated | Vertically stackable dies having chip identifier structures |
US8492905B2 (en) * | 2009-10-07 | 2013-07-23 | Qualcomm Incorporated | Vertically stackable dies having chip identifier structures |
JP2011082450A (en) | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | Semiconductor device, and information processing system with the same |
JP5448698B2 (en) * | 2009-10-09 | 2014-03-19 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and test method thereof |
EP2500930A4 (en) | 2009-11-09 | 2013-05-22 | Mitsubishi Gas Chemical Co | Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid |
US8299616B2 (en) * | 2010-01-29 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | T-shaped post for semiconductor devices |
US10297550B2 (en) | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
US8610270B2 (en) * | 2010-02-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
US8803319B2 (en) | 2010-02-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8318596B2 (en) | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8519537B2 (en) * | 2010-02-26 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US8378480B2 (en) * | 2010-03-04 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy wafers in 3DIC package assemblies |
US8357932B2 (en) * | 2010-03-25 | 2013-01-22 | International Business Machines Corporation | Test pad structure for reuse of interconnect level masks |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
KR20110112707A (en) | 2010-04-07 | 2011-10-13 | 삼성전자주식회사 | Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating delay time of transmission lines |
US8455995B2 (en) | 2010-04-16 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSVs with different sizes in interposers for bonding dies |
KR20110119087A (en) | 2010-04-26 | 2011-11-02 | 삼성전자주식회사 | Stacked semiconductor device |
US8441124B2 (en) | 2010-04-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
US8716867B2 (en) | 2010-05-12 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming interconnect structures using pre-ink-printed sheets |
US8674513B2 (en) | 2010-05-13 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures for substrate |
US9142533B2 (en) | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US8901736B2 (en) | 2010-05-28 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strength of micro-bump joints |
US9018758B2 (en) | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
US8426961B2 (en) | 2010-06-25 | 2013-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded 3D interposer structure |
TW201203496A (en) * | 2010-07-01 | 2012-01-16 | Nat Univ Tsing Hua | 3D-IC device and decreasing type layer-ID detector for 3D-IC device |
US8241963B2 (en) | 2010-07-13 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed pillar structure |
US8581418B2 (en) | 2010-07-21 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-die stacking using bumps with different sizes |
US8629568B2 (en) | 2010-07-30 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device cover mark |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
KR101179268B1 (en) * | 2010-08-05 | 2012-09-03 | 에스케이하이닉스 주식회사 | Semiconductor package with chip selection by through-vias |
US8540506B2 (en) | 2010-08-16 | 2013-09-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor molding chamber |
US8546254B2 (en) | 2010-08-19 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
US8541262B2 (en) | 2010-09-02 | 2013-09-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die edge contacts for semiconductor devices |
US9343436B2 (en) | 2010-09-09 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked package and method of manufacturing the same |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8936966B2 (en) | 2012-02-08 | 2015-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8105875B1 (en) | 2010-10-14 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for bonding dies onto interposers |
US8338945B2 (en) | 2010-10-26 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molded chip interposer structure and methods |
TWI433296B (en) | 2010-11-19 | 2014-04-01 | Ind Tech Res Inst | Multi-chip stacked system and chip select apparatus thereof |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
JP2012226794A (en) * | 2011-04-18 | 2012-11-15 | Elpida Memory Inc | Semiconductor device and method of controlling semiconductor device |
KR101069441B1 (en) * | 2011-05-12 | 2011-09-30 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
JP2012243910A (en) | 2011-05-18 | 2012-12-10 | Elpida Memory Inc | Semiconductor device having structure for checking and testing crack in semiconductor chip |
US8610285B2 (en) | 2011-05-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC packaging structures and methods with a metal pillar |
US8664760B2 (en) | 2011-05-30 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector design for packaging integrated circuits |
US8587127B2 (en) | 2011-06-15 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods of forming the same |
US8501590B2 (en) | 2011-07-05 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for dicing interposer assembly |
US8580683B2 (en) | 2011-09-27 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for molding die on wafer interposers |
US8476770B2 (en) | 2011-07-07 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for forming through vias |
US8647796B2 (en) | 2011-07-27 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photoactive compound gradient photoresist |
US20130040423A1 (en) | 2011-08-10 | 2013-02-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Multi-Chip Wafer Level Packaging |
US8754514B2 (en) | 2011-08-10 | 2014-06-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip wafer level package |
US8557684B2 (en) | 2011-08-23 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit (3DIC) formation process |
US8963334B2 (en) | 2011-08-30 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die-to-die gap control for semiconductor structure and method |
US8531032B2 (en) | 2011-09-02 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally enhanced structure for multi-chip device |
US9390060B2 (en) | 2011-09-02 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods, material dispensing methods and apparatuses, and automated measurement systems |
US9530761B2 (en) | 2011-09-02 | 2016-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems including passive electrical components |
US9418876B2 (en) | 2011-09-02 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of three dimensional integrated circuit assembly |
US9245773B2 (en) | 2011-09-02 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packaging methods and structures thereof |
US9219016B2 (en) | 2011-09-28 | 2015-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure design for 3DIC testing |
US10475759B2 (en) | 2011-10-11 | 2019-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure having dies with connectors of different sizes |
US8878182B2 (en) | 2011-10-12 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probe pad design for 3DIC package yield analysis |
US8518753B2 (en) | 2011-11-15 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Assembly method for three dimensional integrated circuit |
US8779599B2 (en) | 2011-11-16 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages including active dies and dummy dies and methods for forming the same |
US8759118B2 (en) | 2011-11-16 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plating process and structure |
US8629043B2 (en) | 2011-11-16 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for de-bonding carriers |
US8772929B2 (en) | 2011-11-16 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package for three dimensional integrated circuit |
US8779588B2 (en) | 2011-11-29 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures for multi-chip packaging |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US8653658B2 (en) | 2011-11-30 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarized bumps for underfill control |
US8643148B2 (en) | 2011-11-30 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-Wafer structures and methods for forming the same |
US8557631B2 (en) | 2011-12-01 | 2013-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer wafer bonding method and apparatus |
US8536573B2 (en) | 2011-12-02 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plating process and structure |
US8558229B2 (en) | 2011-12-07 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passivation layer for packaged chip |
US8828848B2 (en) | 2011-12-16 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die structure and method of fabrication thereof |
US8871568B2 (en) | 2012-01-06 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages and method of forming the same |
US8518796B2 (en) | 2012-01-09 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die connection system and method |
US8691706B2 (en) | 2012-01-12 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing substrate warpage in semiconductor processing |
US9620430B2 (en) | 2012-01-23 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sawing underfill in packaging processes |
US8698308B2 (en) | 2012-01-31 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structural designs to minimize package defects |
US9406500B2 (en) | 2012-02-08 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flux residue cleaning system and method |
US9230932B2 (en) | 2012-02-09 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect crack arrestor structure and methods |
US8975183B2 (en) | 2012-02-10 | 2015-03-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
US8900922B2 (en) | 2012-02-16 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fine-pitch package-on-package structures and methods for forming the same |
US8816495B2 (en) | 2012-02-16 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structures and formation methods of packages with heat sinks |
US9646942B2 (en) | 2012-02-23 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for controlling bump height variation |
US8953336B2 (en) | 2012-03-06 | 2015-02-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Surface metal wiring structure for an IC substrate |
US8962392B2 (en) | 2012-03-13 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill curing method using carrier |
JP2013197387A (en) * | 2012-03-21 | 2013-09-30 | Elpida Memory Inc | Semiconductor device |
US9006004B2 (en) | 2012-03-23 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probing chips during package formation |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9034695B2 (en) | 2012-04-11 | 2015-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated thermal solutions for packaging integrated circuits |
US9391000B2 (en) | 2012-04-11 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming silicon-based hermetic thermal solutions |
US9425136B2 (en) | 2012-04-17 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US9646923B2 (en) | 2012-04-17 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
US9299674B2 (en) | 2012-04-18 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
US8741691B2 (en) | 2012-04-20 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating three dimensional integrated circuit |
US9576830B2 (en) | 2012-05-18 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for adjusting wafer warpage |
US9583365B2 (en) | 2012-05-25 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming interconnects for three dimensional integrated circuit |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US8970035B2 (en) | 2012-08-31 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures for semiconductor package |
US9111817B2 (en) | 2012-09-18 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure and method of forming same |
US8628990B1 (en) | 2012-09-27 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image device and methods of forming the same |
JP5543567B2 (en) * | 2012-10-22 | 2014-07-09 | 誠 雫石 | Manufacturing method of semiconductor device |
US9070644B2 (en) | 2013-03-15 | 2015-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
US9646894B2 (en) | 2013-03-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
US9299640B2 (en) | 2013-07-16 | 2016-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
US8860229B1 (en) | 2013-07-16 | 2014-10-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9929050B2 (en) | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
US9087821B2 (en) | 2013-07-16 | 2015-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9250288B2 (en) | 2013-09-05 | 2016-02-02 | Powertech Technology Inc. | Wafer-level testing method for singulated 3D-stacked chip cubes |
KR102161260B1 (en) * | 2013-11-07 | 2020-09-29 | 삼성전자주식회사 | Semiconductor devices having through electrodes and methods for fabricaing the same |
US9768090B2 (en) | 2014-02-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10026671B2 (en) | 2014-02-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9935090B2 (en) | 2014-02-14 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9484328B2 (en) * | 2014-08-01 | 2016-11-01 | Empire Technology Development Llc | Backside through silicon vias and micro-channels in three dimensional integration |
SG11201701725QA (en) * | 2014-09-17 | 2017-04-27 | Toshiba Kk | Semiconductor device |
US9564416B2 (en) | 2015-02-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US9613931B2 (en) | 2015-04-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) having dummy dies and methods of making the same |
US10276541B2 (en) | 2015-06-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D package structure and methods of forming same |
US9831155B2 (en) | 2016-03-11 | 2017-11-28 | Nanya Technology Corporation | Chip package having tilted through silicon via |
US9966363B1 (en) | 2017-02-03 | 2018-05-08 | Nanya Technology Corporation | Semiconductor apparatus and method for preparing the same |
US9893037B1 (en) * | 2017-04-20 | 2018-02-13 | Nanya Technology Corporation | Multi-chip semiconductor package, vertically-stacked devices and manufacturing thereof |
KR102059968B1 (en) | 2018-04-05 | 2019-12-27 | 한국과학기술연구원 | Optical interconnection between semiconductor chips using mid-infrared |
US10849200B2 (en) | 2018-09-28 | 2020-11-24 | Metrospec Technology, L.L.C. | Solid state lighting circuit with current bias and method of controlling thereof |
US20210043545A1 (en) * | 2019-08-07 | 2021-02-11 | Nanya Technology Corporation | Semiconductor device and manufacturing method thereof |
US11600554B2 (en) * | 2021-08-02 | 2023-03-07 | Nvidia Corporation | Interconnection structures to improve signal integrity within stacked dies |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5138438A (en) * | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
US4996583A (en) * | 1989-02-15 | 1991-02-26 | Matsushita Electric Industrial Co., Ltd. | Stack type semiconductor package |
US6355976B1 (en) * | 1992-05-14 | 2002-03-12 | Reveo, Inc | Three-dimensional packaging technology for multi-layered integrated circuits |
US5585675A (en) * | 1994-05-11 | 1996-12-17 | Harris Corporation | Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs |
US5973396A (en) * | 1996-02-16 | 1999-10-26 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
JP3177464B2 (en) * | 1996-12-12 | 2001-06-18 | 株式会社日立製作所 | Input / output circuit cell and semiconductor integrated circuit device |
JP2870530B1 (en) * | 1997-10-30 | 1999-03-17 | 日本電気株式会社 | Stack module interposer and stack module |
US6064114A (en) * | 1997-12-01 | 2000-05-16 | Motorola, Inc. | Semiconductor device having a sub-chip-scale package structure and method for forming same |
JP2865103B2 (en) * | 1998-01-19 | 1999-03-08 | 株式会社日立製作所 | Multi-chip semiconductor device |
JPH11307719A (en) * | 1998-04-20 | 1999-11-05 | Mitsubishi Electric Corp | Semiconductor device |
JP3563604B2 (en) * | 1998-07-29 | 2004-09-08 | 株式会社東芝 | Multi-chip semiconductor device and memory card |
US5986222A (en) * | 1998-09-10 | 1999-11-16 | Zorix International | Fish scale having a pivotal display assembly |
US6381141B2 (en) * | 1998-10-15 | 2002-04-30 | Micron Technology, Inc. | Integrated device and method for routing a signal through the device |
JP3228257B2 (en) * | 1999-01-22 | 2001-11-12 | 日本電気株式会社 | Memory package |
US6130823A (en) * | 1999-02-01 | 2000-10-10 | Raytheon E-Systems, Inc. | Stackable ball grid array module and method |
-
2001
- 2001-02-09 KR KR1020010006318A patent/KR100364635B1/en active IP Right Grant
-
2002
- 2002-01-28 US US10/059,932 patent/US6448661B1/en not_active Expired - Lifetime
- 2002-02-08 JP JP2002032481A patent/JP4519392B2/en not_active Expired - Fee Related
Cited By (202)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6984882B2 (en) * | 2002-06-21 | 2006-01-10 | Renesas Technology Corp. | Semiconductor device with reduced wiring paths between an array of semiconductor chip parts |
US20030234434A1 (en) * | 2002-06-21 | 2003-12-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
WO2004061962A2 (en) * | 2002-12-31 | 2004-07-22 | Massachusetts Institute Of Technology | Multi-layer integrated semiconductor structure |
US7307003B2 (en) | 2002-12-31 | 2007-12-11 | Massachusetts Institute Of Technology | Method of forming a multi-layer semiconductor structure incorporating a processing handle member |
US20040219765A1 (en) * | 2002-12-31 | 2004-11-04 | Rafael Reif | Method of forming a multi-layer semiconductor structure incorporating a processing handle member |
WO2004061962A3 (en) * | 2002-12-31 | 2004-11-11 | Massachusetts Inst Technology | Multi-layer integrated semiconductor structure |
US20040124538A1 (en) * | 2002-12-31 | 2004-07-01 | Rafael Reif | Multi-layer integrated semiconductor structure |
US7064055B2 (en) | 2002-12-31 | 2006-06-20 | Massachusetts Institute Of Technology | Method of forming a multi-layer semiconductor structure having a seamless bonding interface |
US20060087019A1 (en) * | 2002-12-31 | 2006-04-27 | Rafael Reif | Multi-layer integrated semiconductor structure having an electrical shielding portion |
US20060099796A1 (en) * | 2002-12-31 | 2006-05-11 | Rafael Reif | Method of forming a multi-layer semiconductor structure having a seam-less bonding interface |
US20040126994A1 (en) * | 2002-12-31 | 2004-07-01 | Rafael Reif | Method of forming a multi-layer semiconductor structure having a seamless bonding interface |
US7067909B2 (en) | 2002-12-31 | 2006-06-27 | Massachusetts Institute Of Technology | Multi-layer integrated semiconductor structure having an electrical shielding portion |
US20080064183A1 (en) * | 2002-12-31 | 2008-03-13 | Rafael Reif | Method of forming a multi-layer semiconductor structure incorporating a processing handle member |
EP1686623A1 (en) * | 2003-10-30 | 2006-08-02 | Japan Science and Technology Agency | Semiconductor device and process for fabricating the same |
US9887147B2 (en) | 2003-10-30 | 2018-02-06 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
EP1686623A4 (en) * | 2003-10-30 | 2007-07-11 | Japan Science & Tech Agency | Semiconductor device and process for fabricating the same |
US9093431B2 (en) | 2003-10-30 | 2015-07-28 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US11127657B2 (en) | 2003-10-30 | 2021-09-21 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US20110201178A1 (en) * | 2003-10-30 | 2011-08-18 | Oki Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US20080265430A1 (en) * | 2003-10-30 | 2008-10-30 | Masamichi Ishihara | Semiconductor Device an Process for Fabricating the Same |
US8664666B2 (en) | 2003-10-30 | 2014-03-04 | Oki Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US10559521B2 (en) | 2003-10-30 | 2020-02-11 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US9559041B2 (en) | 2003-10-30 | 2017-01-31 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US7944058B2 (en) | 2003-10-30 | 2011-05-17 | Oki Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
US10199310B2 (en) | 2003-10-30 | 2019-02-05 | Lapis Semiconductor Co., Ltd. | Semiconductor device and process for fabricating the same |
EP1587141A2 (en) | 2004-04-13 | 2005-10-19 | Sun Microsystems, Inc. | Method and apparatus involving capacitively coupled communication within a stack of laminated chips |
EP1587141A3 (en) * | 2004-04-13 | 2007-12-05 | Sun Microsystems, Inc. | Method and apparatus involving capacitively coupled communication within a stack of laminated chips |
US7989958B2 (en) | 2005-06-14 | 2011-08-02 | Cufer Assett Ltd. L.L.C. | Patterned contact |
US8846445B2 (en) | 2005-06-14 | 2014-09-30 | Cufer Asset Ltd. L.L.C. | Inverse chip connector |
US8283778B2 (en) | 2005-06-14 | 2012-10-09 | Cufer Asset Ltd. L.L.C. | Thermally balanced via |
US8232194B2 (en) | 2005-06-14 | 2012-07-31 | Cufer Asset Ltd. L.L.C. | Process for chip capacitive coupling |
US10340239B2 (en) | 2005-06-14 | 2019-07-02 | Cufer Asset Ltd. L.L.C | Tooling for coupling multiple electronic chips |
US8456015B2 (en) | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US8197626B2 (en) | 2005-06-14 | 2012-06-12 | Cufer Asset Ltd. L.L.C. | Rigid-backed, membrane-based chip tooling |
US8197627B2 (en) | 2005-06-14 | 2012-06-12 | Cufer Asset Ltd. L.L.C. | Pin-type chip tooling |
US8154131B2 (en) | 2005-06-14 | 2012-04-10 | Cufer Asset Ltd. L.L.C. | Profiled contact |
US20090269888A1 (en) * | 2005-06-14 | 2009-10-29 | John Trezza | Chip-based thermo-stack |
US8093729B2 (en) | 2005-06-14 | 2012-01-10 | Cufer Asset Ltd. L.L.C. | Electrically conductive interconnect system and method |
US8084851B2 (en) | 2005-06-14 | 2011-12-27 | Cufer Asset Ltd. L.L.C. | Side stacking apparatus and method |
US9754907B2 (en) | 2005-06-14 | 2017-09-05 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
US8067312B2 (en) | 2005-06-14 | 2011-11-29 | Cufer Asset Ltd. L.L.C. | Coaxial through chip connection |
US8053903B2 (en) | 2005-06-14 | 2011-11-08 | Cufer Asset Ltd. L.L.C. | Chip capacitive coupling |
US8643186B2 (en) | 2005-06-14 | 2014-02-04 | Cufer Asset Ltd. L.L.C. | Processed wafer via |
US9324629B2 (en) | 2005-06-14 | 2016-04-26 | Cufer Asset Ltd. L.L.C. | Tooling for coupling multiple electronic chips |
US7785987B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Isolating chip-to-chip contact |
US7785931B2 (en) | 2005-06-14 | 2010-08-31 | John Trezza | Chip-based thermo-stack |
US20100219503A1 (en) * | 2005-06-14 | 2010-09-02 | John Trezza | Chip capacitive coupling |
US8021922B2 (en) | 2005-06-14 | 2011-09-20 | Cufer Asset Ltd. L.L.C. | Remote chip attachment |
US9147635B2 (en) | 2005-06-14 | 2015-09-29 | Cufer Asset Ltd. L.L.C. | Contact-based encapsulation |
US7969015B2 (en) | 2005-06-14 | 2011-06-28 | Cufer Asset Ltd. L.L.C. | Inverse chip connector |
US7946331B2 (en) | 2005-06-14 | 2011-05-24 | Cufer Asset Ltd. L.L.C. | Pin-type chip tooling |
US7942182B2 (en) | 2005-06-14 | 2011-05-17 | Cufer Asset Ltd. L.L.C. | Rigid-backed, membrane-based chip tooling |
US7808111B2 (en) | 2005-06-14 | 2010-10-05 | John Trezza | Processed wafer via |
US7932584B2 (en) | 2005-06-14 | 2011-04-26 | Cufer Asset Ltd. L.L.C. | Stacked chip-based system and method |
US7919870B2 (en) | 2005-06-14 | 2011-04-05 | Cufer Asset Ltd. L.L.C. | Coaxial through chip connection |
US7847412B2 (en) | 2005-06-14 | 2010-12-07 | John Trezza | Isolating chip-to-chip contact |
US7851348B2 (en) | 2005-06-14 | 2010-12-14 | Abhay Misra | Routingless chip architecture |
US7884483B2 (en) | 2005-06-14 | 2011-02-08 | Cufer Asset Ltd. L.L.C. | Chip connector |
US20110027990A1 (en) * | 2005-06-30 | 2011-02-03 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
US8338289B2 (en) | 2005-06-30 | 2012-12-25 | Shinko Electric Industries Co., Ltd. | Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole |
US7843068B2 (en) * | 2005-06-30 | 2010-11-30 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
US20070001312A1 (en) * | 2005-06-30 | 2007-01-04 | Shinko Electric Industries Co., Ltd. | Semiconductor chip and method of manufacturing the same |
US20070126105A1 (en) * | 2005-12-06 | 2007-06-07 | Elpida Memory Inc. | Stacked type semiconductor memory device and chip selection circuit |
US8709871B2 (en) | 2005-12-06 | 2014-04-29 | Junji Yamada | Stacked type semiconductor memory device and chip selection circuit |
US8076764B2 (en) * | 2005-12-06 | 2011-12-13 | Elpida Memory Inc. | Stacked type semiconductor memory device and chip selection circuit |
US7626257B2 (en) | 2006-01-18 | 2009-12-01 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
DE112007000267B4 (en) * | 2006-01-18 | 2017-11-09 | Infineon Technologies Ag | Method for producing a semiconductor device |
WO2007082854A1 (en) * | 2006-01-18 | 2007-07-26 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20080083976A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
US8022527B2 (en) | 2006-10-10 | 2011-09-20 | Tessera, Inc. | Edge connect wafer level stacking |
US7829438B2 (en) | 2006-10-10 | 2010-11-09 | Tessera, Inc. | Edge connect wafer level stacking |
US9048234B2 (en) | 2006-10-10 | 2015-06-02 | Tessera, Inc. | Off-chip vias in stacked chips |
US8426957B2 (en) | 2006-10-10 | 2013-04-23 | Tessera, Inc. | Edge connect wafer level stacking |
US8431435B2 (en) | 2006-10-10 | 2013-04-30 | Tessera, Inc. | Edge connect wafer level stacking |
US20110187007A1 (en) * | 2006-10-10 | 2011-08-04 | Tessera, Inc. | Edge connect wafer level stacking |
US8999810B2 (en) | 2006-10-10 | 2015-04-07 | Tessera, Inc. | Method of making a stacked microelectronic package |
US8476774B2 (en) | 2006-10-10 | 2013-07-02 | Tessera, Inc. | Off-chip VIAS in stacked chips |
US20110031629A1 (en) * | 2006-10-10 | 2011-02-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20080083977A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
US8513789B2 (en) | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
US8461673B2 (en) | 2006-10-10 | 2013-06-11 | Tessera, Inc. | Edge connect wafer level stacking |
US9378967B2 (en) | 2006-10-10 | 2016-06-28 | Tessera, Inc. | Method of making a stacked microelectronic package |
US9899353B2 (en) | 2006-10-10 | 2018-02-20 | Tessera, Inc. | Off-chip vias in stacked chips |
US20090160065A1 (en) * | 2006-10-10 | 2009-06-25 | Tessera, Inc. | Reconstituted Wafer Level Stacking |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US8076788B2 (en) | 2006-10-10 | 2011-12-13 | Tessera, Inc. | Off-chip vias in stacked chips |
US20110049696A1 (en) * | 2006-10-10 | 2011-03-03 | Tessera, Inc. | Off-chip vias in stacked chips |
US20110033979A1 (en) * | 2006-10-10 | 2011-02-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20110012259A1 (en) * | 2006-11-22 | 2011-01-20 | Tessera, Inc. | Packaged semiconductor chips |
US20080116545A1 (en) * | 2006-11-22 | 2008-05-22 | Tessera, Inc. | Packaged semiconductor chips |
US20080116544A1 (en) * | 2006-11-22 | 2008-05-22 | Tessera, Inc. | Packaged semiconductor chips with array |
US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
US8704347B2 (en) | 2006-11-22 | 2014-04-22 | Tessera, Inc. | Packaged semiconductor chips |
US9070678B2 (en) | 2006-11-22 | 2015-06-30 | Tessera, Inc. | Packaged semiconductor chips with array |
US8653644B2 (en) | 2006-11-22 | 2014-02-18 | Tessera, Inc. | Packaged semiconductor chips with array |
US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
US20110230013A1 (en) * | 2006-12-28 | 2011-09-22 | Tessera, Inc. | Stacked packages with bridging traces |
US8349654B2 (en) | 2006-12-28 | 2013-01-08 | Tessera, Inc. | Method of fabricating stacked packages with bridging traces |
US7952195B2 (en) | 2006-12-28 | 2011-05-31 | Tessera, Inc. | Stacked packages with bridging traces |
US20080157323A1 (en) * | 2006-12-28 | 2008-07-03 | Tessera, Inc. | Stacked packages |
US20080171413A1 (en) * | 2007-01-17 | 2008-07-17 | International Business Machines Corporation | Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels |
US8310036B2 (en) | 2007-03-05 | 2012-11-13 | DigitalOptics Corporation Europe Limited | Chips having rear contacts connected by through vias to front contacts |
US8735205B2 (en) | 2007-03-05 | 2014-05-27 | Invensas Corporation | Chips having rear contacts connected by through vias to front contacts |
US8405196B2 (en) | 2007-03-05 | 2013-03-26 | DigitalOptics Corporation Europe Limited | Chips having rear contacts connected by through vias to front contacts |
US20100225006A1 (en) * | 2007-03-05 | 2010-09-09 | Tessera, Inc. | Chips having rear contacts connected by through vias to front contacts |
US20080246136A1 (en) * | 2007-03-05 | 2008-10-09 | Tessera, Inc. | Chips having rear contacts connected by through vias to front contacts |
US8304923B2 (en) * | 2007-03-29 | 2012-11-06 | ADL Engineering Inc. | Chip packaging structure |
US20080237834A1 (en) * | 2007-03-29 | 2008-10-02 | Advanced Chip Engineering Technology Inc. | Chip packaging structure and chip packaging process |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US8461672B2 (en) | 2007-07-27 | 2013-06-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US20110006432A1 (en) * | 2007-07-27 | 2011-01-13 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US20090065907A1 (en) * | 2007-07-31 | 2009-03-12 | Tessera, Inc. | Semiconductor packaging process using through silicon vias |
US8193615B2 (en) | 2007-07-31 | 2012-06-05 | DigitalOptics Corporation Europe Limited | Semiconductor packaging process using through silicon vias |
US8735287B2 (en) | 2007-07-31 | 2014-05-27 | Invensas Corp. | Semiconductor packaging process using through silicon vias |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
US7698470B2 (en) | 2007-08-06 | 2010-04-13 | Qimonda Ag | Integrated circuit, chip stack and data processing system |
US20090043917A1 (en) * | 2007-08-06 | 2009-02-12 | Thilo Wagner | Electronic Circuit and Method for Selecting an Electronic Circuit |
US20090039915A1 (en) * | 2007-08-06 | 2009-02-12 | Hermann Ruckerbauer | Integrated Circuit, Chip Stack and Data Processing System |
US20090039528A1 (en) * | 2007-08-09 | 2009-02-12 | Tessera, Inc. | Wafer level stacked packages with individual chip selection |
US8513794B2 (en) | 2007-08-09 | 2013-08-20 | Tessera, Inc. | Stacked assembly including plurality of stacked microelectronic elements |
US8043895B2 (en) | 2007-08-09 | 2011-10-25 | Tessera, Inc. | Method of fabricating stacked assembly including plurality of stacked microelectronic elements |
US9041218B2 (en) | 2007-11-14 | 2015-05-26 | Samsung Electronics Co., Ltd. | Semiconductor device having through electrode and method of fabricating the same |
US20090124072A1 (en) * | 2007-11-14 | 2009-05-14 | Samsung Electronics Co., Ltd. | Semiconductor device having through electrode and method of fabricating the same |
US8659163B2 (en) | 2007-11-14 | 2014-02-25 | Samsung Electronics Co., Ltd. | Semiconductor device having through electrode and method of fabricating the same |
US8288278B2 (en) * | 2007-11-14 | 2012-10-16 | Samsung Electronics Co., Ltd. | Semiconductor device having through electrode and method of fabricating the same |
US20100053407A1 (en) * | 2008-02-26 | 2010-03-04 | Tessera, Inc. | Wafer level compliant packages for rear-face illuminated solid state image sensors |
US20090212381A1 (en) * | 2008-02-26 | 2009-08-27 | Tessera, Inc. | Wafer level packages for rear-face illuminated solid state image sensors |
US7683459B2 (en) | 2008-06-02 | 2010-03-23 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3D wafer stacking |
US20090294916A1 (en) * | 2008-06-02 | 2009-12-03 | Hong Kong Applied Science and Technology Research Institute Company, Ltd. | Bonding method for through-silicon-via based 3d wafer stacking |
US9219035B2 (en) | 2008-06-10 | 2015-12-22 | Samsung Electronics Co., Ltd. | Integrated circuit chips having vertically extended through-substrate vias therein |
US20110086486A1 (en) * | 2008-06-10 | 2011-04-14 | Ho-Jin Lee | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein |
US8629059B2 (en) | 2008-06-10 | 2014-01-14 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit chips having vertically extended through-substrate vias therein |
US8680662B2 (en) | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
US20090316378A1 (en) * | 2008-06-16 | 2009-12-24 | Tessera Research Llc | Wafer level edge stacking |
US20110210452A1 (en) * | 2008-10-30 | 2011-09-01 | Nxp B.V. | Through-substrate via and redistribution layer with metal paste |
CN102197479A (en) * | 2008-10-30 | 2011-09-21 | Nxp股份有限公司 | Through-substrate via and redistribution layer with metal paste |
WO2010049852A1 (en) * | 2008-10-30 | 2010-05-06 | Nxp B.V. | Through-substrate via and redistribution layer with metal paste |
US8395267B2 (en) | 2008-10-30 | 2013-03-12 | Nxp B.V. | Through-substrate via and redistribution layer with metal paste |
US8487444B2 (en) * | 2009-03-06 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional system-in-package architecture |
TWI416693B (en) * | 2009-03-06 | 2013-11-21 | Taiwan Semiconductor Mfg | Semiconductor devices and fabrication methods thereof |
CN101840912A (en) * | 2009-03-06 | 2010-09-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
US9099540B2 (en) * | 2009-03-06 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional system-in-package architecture |
US20130230985A1 (en) * | 2009-03-06 | 2013-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional System-in-Package Architecture |
US20100225002A1 (en) * | 2009-03-06 | 2010-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-Dimensional System-in-Package Architecture |
US20100230795A1 (en) * | 2009-03-13 | 2010-09-16 | Tessera Technologies Hungary Kft. | Stacked microelectronic assemblies having vias extending through bond pads |
US8466542B2 (en) | 2009-03-13 | 2013-06-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
EP2474030A1 (en) * | 2009-09-02 | 2012-07-11 | MOSAID Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
US8711573B2 (en) | 2009-09-02 | 2014-04-29 | Mosaid Technologies Incorporated | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
EP2474030A4 (en) * | 2009-09-02 | 2013-12-04 | Mosaid Technologies Inc | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
US20130228920A1 (en) * | 2009-09-14 | 2013-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for adhesive material at wafer edge |
US9997440B2 (en) * | 2009-09-14 | 2018-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for adhesive material at wafer edge |
US8717796B2 (en) | 2010-02-11 | 2014-05-06 | Micron Technology, Inc. | Memory dies, stacked memories, memory devices and methods |
EP2534659A2 (en) * | 2010-02-11 | 2012-12-19 | Micron Technology, Inc. | Memory dies, stacked memories, memory devices and methods |
EP3852110A1 (en) * | 2010-02-11 | 2021-07-21 | Micron Technology, INC. | Memory dies, stacked memories, memory devices and methods |
TWI467583B (en) * | 2010-02-11 | 2015-01-01 | Micron Technology Inc | Memory dies, memory devices and methods for operating the same |
US8953355B2 (en) | 2010-02-11 | 2015-02-10 | Micron Technology, Inc. | Memory dies, stacked memories, memory devices and methods |
EP2534659A4 (en) * | 2010-02-11 | 2013-08-28 | Micron Technology Inc | Memory dies, stacked memories, memory devices and methods |
US8912043B2 (en) | 2010-04-12 | 2014-12-16 | Qualcomm Incorporated | Dual-side interconnected CMOS for stacked integrated circuits |
CN102844862B (en) * | 2010-04-12 | 2015-07-29 | 高通股份有限公司 | For the two-sided interconnection CMOS of stacked integrated circuit |
CN102844862A (en) * | 2010-04-12 | 2012-12-26 | 高通股份有限公司 | Dual-side interconnected cmos for stacked integrated circuits |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US9847277B2 (en) | 2010-09-17 | 2017-12-19 | Tessera, Inc. | Staged via formation from both sides of chip |
US9355948B2 (en) | 2010-09-17 | 2016-05-31 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8809190B2 (en) | 2010-09-17 | 2014-08-19 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US9362203B2 (en) | 2010-09-17 | 2016-06-07 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
US9312031B2 (en) | 2010-10-13 | 2016-04-12 | Ps4 Luxco S.A.R.L. | Semiconductor device and test method thereof |
US8848473B2 (en) | 2010-10-13 | 2014-09-30 | Ps4 Luxco S.A.R.L. | Semiconductor device and test method thereof |
US8593891B2 (en) | 2010-10-13 | 2013-11-26 | Elpida Memory, Inc. | Semiconductor device and test method thereof |
US8432045B2 (en) | 2010-11-15 | 2013-04-30 | Tessera, Inc. | Conductive pads defined by embedded traces |
US8772908B2 (en) | 2010-11-15 | 2014-07-08 | Tessera, Inc. | Conductive pads defined by embedded traces |
US9252081B2 (en) | 2010-11-30 | 2016-02-02 | Ps4 Luxco S.A.R.L. | Semiconductor device having plural memory chip |
US8924903B2 (en) | 2010-11-30 | 2014-12-30 | Ps4 Luxco S.A.R.L. | Semiconductor device having plural memory chip |
US9269692B2 (en) | 2010-12-02 | 2016-02-23 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
US9099296B2 (en) | 2010-12-02 | 2015-08-04 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US9224649B2 (en) | 2010-12-08 | 2015-12-29 | Tessera, Inc. | Compliant interconnects in wafers |
US8796828B2 (en) | 2010-12-08 | 2014-08-05 | Tessera, Inc. | Compliant interconnects in wafers |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
EP2546873A3 (en) * | 2011-06-14 | 2013-05-29 | Elpida Memory, Inc. | Semiconductor device |
US9035444B2 (en) | 2011-06-14 | 2015-05-19 | Ps4 Luxco S.A.R.L. | Semiconductor device having penetration electrodes penetrating through semiconductor chip |
US9356000B2 (en) * | 2012-12-20 | 2016-05-31 | SK Hynix Inc. | Semiconductor integrated circuit and semiconductor system with the same |
CN103887288A (en) * | 2012-12-20 | 2014-06-25 | 爱思开海力士有限公司 | Semiconductor Integrated Circuit And Semiconductor System With The Same |
US20140175667A1 (en) * | 2012-12-20 | 2014-06-26 | SK Hynix Inc. | Semiconductor integrated circuit and semiconductor system with the same |
TWI588882B (en) * | 2013-09-13 | 2017-06-21 | 財團法人工業技術研究院 | Thinned integrated circuit device and manufacturing process for the same |
CN104465567A (en) * | 2013-09-24 | 2015-03-25 | 南亚科技股份有限公司 | Chip package and method for forming the same |
CN104779218A (en) * | 2014-01-15 | 2015-07-15 | 南亚科技股份有限公司 | Chip package |
US10790266B2 (en) | 2016-09-23 | 2020-09-29 | Toshiba Memory Corporation | Memory device with a plurality of stacked memory core chips |
US10811393B2 (en) | 2016-09-23 | 2020-10-20 | Toshiba Memory Corporation | Memory device |
US11270981B2 (en) | 2016-09-23 | 2022-03-08 | Kioxia Corporation | Memory device |
US20190259725A1 (en) * | 2017-07-21 | 2019-08-22 | United Microelectronics Corp. | Manufacturing method of die-stack structure |
JP2019102744A (en) * | 2017-12-07 | 2019-06-24 | 日本放送協会 | Stacked semiconductor device |
CN115799230A (en) * | 2023-02-08 | 2023-03-14 | 深圳时识科技有限公司 | Stacked chip and electronic device |
Also Published As
Publication number | Publication date |
---|---|
JP4519392B2 (en) | 2010-08-04 |
KR100364635B1 (en) | 2002-12-16 |
KR20020066095A (en) | 2002-08-14 |
JP2002305283A (en) | 2002-10-18 |
US6448661B1 (en) | 2002-09-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6448661B1 (en) | Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof | |
US6822316B1 (en) | Integrated circuit with improved interconnect structure and process for making same | |
CN1983533B (en) | Method for packaging a semiconductor device | |
US8741762B2 (en) | Through silicon via dies and packages | |
US6908785B2 (en) | Multi-chip package (MCP) with a conductive bar and method for manufacturing the same | |
US6075712A (en) | Flip-chip having electrical contact pads on the backside of the chip | |
US8367472B2 (en) | Method of fabricating a 3-D device | |
US6962867B2 (en) | Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof | |
US5977640A (en) | Highly integrated chip-on-chip packaging | |
US7145228B2 (en) | Microelectronic devices | |
US8138021B2 (en) | Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components | |
TW201923984A (en) | Semiconductor package and method of forming same | |
US20020074637A1 (en) | Stacked flip chip assemblies | |
TW202109782A (en) | Semiconductor package and manufacturing method thereof | |
US7030466B1 (en) | Intermediate structure for making integrated circuit device and wafer | |
TW202117952A (en) | Semiconductor packages and method of manufacture | |
JP2015523740A (en) | Reconfigured wafer level microelectronic package | |
US7595268B2 (en) | Semiconductor package having re-distribution lines for supplying power and a method for manufacturing the same | |
US7179740B1 (en) | Integrated circuit with improved interconnect structure and process for making same | |
US9893037B1 (en) | Multi-chip semiconductor package, vertically-stacked devices and manufacturing thereof | |
TW202238907A (en) | Package structure and methods of manufacturing the same | |
US7468550B2 (en) | High-performance semiconductor package | |
US11749629B2 (en) | High-speed die connections using a conductive insert | |
WO2024053103A1 (en) | Ic bridge, ic module, and method for manufacturing ic module | |
TWI779917B (en) | Semiconductor package and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, HYEONG-SEOB;KANG, SA-YOON;CHUNG, MYUNG-KEE;AND OTHERS;REEL/FRAME:012561/0421;SIGNING DATES FROM 20020117 TO 20020119 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |