US20020104764A1 - Electropolishing and chemical mechanical planarization - Google Patents
Electropolishing and chemical mechanical planarization Download PDFInfo
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- US20020104764A1 US20020104764A1 US09/989,338 US98933801A US2002104764A1 US 20020104764 A1 US20020104764 A1 US 20020104764A1 US 98933801 A US98933801 A US 98933801A US 2002104764 A1 US2002104764 A1 US 2002104764A1
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- substrate
- electropolishing
- polishing pad
- polishing
- cmp
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
- B23H5/00—Combined machining
- B23H5/06—Electrochemical machining combined with mechanical working, e.g. grinding or honing
- B23H5/08—Electrolytic grinding
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/046—Lapping machines or devices; Accessories designed for working plane surfaces using electric current
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F3/00—Electrolytic etching or polishing
- C25F3/16—Polishing
- C25F3/30—Polishing of semiconducting materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
- H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Abstract
Removing metal from a semiconductor substrate by dissolving ions of the metal into an electrolyte, comprising the steps of: applying a voltage across a polishing pad and the substrate, while an electropolishing electrolyte is dispensed at an interface of the substrate and the polishing pad, and while pooling the electrolyte about the substrate by the polishing pad.
Description
- This application claims the benefit of provisional application serial No. 60/249,995 filed Nov. 20, 2000.
- The invention relates to a method for planarization of a substrate by a combination of electropolishing and chemical mechanical planarization, CMP.
- A semiconductor substrate comprises, a silicon wafer on which is deposited successive layers of materials. A dielectric layer is deposited, and is provided with multiple trenches that are recessed in the dielectric layer. A thin barrier film, for example, tantalum, tantalum nitride or a tantalum alloy, is deposited to cover the surface of the dielectric layer including the trenches, which provides a barrier to migration of metal ions into the dielectric layer. A metal layer is deposited to fill the trenches with metal to provide electrical circuit interconnects in the trenches.
- During a CMP operation, the substrate is polished by a rotating polishing pad and a polishing fluid at an interface of the substrate and the polishing pad. The polishing operation removes metal by a combination of, abrasion applied by the polishing pad, and chemical reaction of the metal with the polishing fluid.
- A single step polishing operation, or two step polishing operations, may be performed to provide complete removal of the metal layer, and complete removal of the barrier film, without spots of residual metal on the polished surface, while leaving all of the trenches filled with metal at a level that is planar with the smooth planar polished surface.
- U.S. Pat. No. 6,056,864 discloses removing metal from a metal layer on a semiconductor substrate by dissolving ions of the metal into an electopolishing electrolyte, followed by performing CMP to remove a remaining thickness of metal. A faster rate of removal of the metal is attained as compared to that attained solely by performing CMP.
- According to the invention, metal is removed from a semiconductor substrate by dissolving ions of the metal into an electrolyte, comprising the steps of: applying a voltage across a polishing pad and the substrate, while an electropolishing electrolyte is dispensed at an interface of the substrate and the polishing pad, and while pooling the electrolyte about the substrate by the polishing pad.
- According to an embodiment of the invention, an apparatus comprises both an electropolishing apparatus and a CMP apparatus. Further according to an embodiment of the invention, an electropolishing electrolyte comprises a CMP polishing composition.
- According to an embodiment of the invention, performance of both electropolishing and CMP on the same apparatus leads to a significant reduction in processing time per substrate.
- Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, according to which;
- FIG. 1 is a cross section view of a portion of a semiconductor substrate having a dielectric layer provided with multiple trenches, one of which is shown;
- FIG. 2 is a view similar to FIG. 1 with the substrate having a deposited metal layer to fill each of the trenches with metal;
- FIG. 3 is a view similar to FIG. 2 with a reduced thickness of the metal layer obtained by electropolishing;
- FIG. 4 is a view similar to FIG. 3 with complete removal of the metal layer from a polished surface and a metal filled trench with a surface planar with the polished surface;
- FIG. 5 is a diagrammatic view of an electropolishing apparatus;
- FIG. 6 is a diagrammatic view of an apparatus that is both an electropolishing apparatus and a CMP apparatus;
- FIG. 7 is a graph of weight loss of copper metal versus time of electropolishing with an electropolishing electrolyte comprising a CMP slurry; and
- FIG. 8 is a graph of removed thickness of copper metal versus time of electropolishing with an electropolishing electrolyte comprising a CMP slurry.
- FIG. 1 discloses a
trench 10 that is etched or otherwise formed in adielectric layer 11, typically SiO2. The trench is then coated with an adhesion orbarrier layer 12, as shown in FIG. 2, followed by ametal layer 13 which fills thetrench 10 with metal. FIG. 3 discloses a reducedthickness 14 of themetal layer 13 obtained by electropolishing FIG. 5 discloses anelectropolishing apparatus 20 according to whichmultiple substrates 22 are placed in atank 24 filled withelectrolyte 26. Thesubstrates 22 are connected to the positive side of aDC voltage source 28 so that the wafers act as anodes. The negative side of theDC voltage source 28 is connected to a chemicallyinert electrode 30 that acts as a cathode. Thevoltage source 28 applies a DC voltage across the anodes and the cathode. A DC electrical current flows through the electrolyte, causing removal of ions of the metal from thesubstrates 22 and into solution with the electrolyte. TheDC voltage source 28 produces the required current density for the metal layer to be reduced in thickness faster than by performing CMP. Theelectropolishing apparatus 20 is incapable of providing a planar polished surface on thesubstrates 22. Accordingly, thesubstrates 22 are removed from theelectropolishing apparatus 20, and the polished surface is provided on a CMP apparatus, not shown. Because removal and transfer of thesubstrates 22 consumes time, the processing time for eachsubstrate 22 is extended. - FIG. 6 discloses an apparatus that comprises both an electropolishing apparatus and a CMP apparatus. Each
semiconductor substrate 22 that is mounted to the apparatus for electropolishing and CMP, serves as an anode by having a conducting portion thereof being connected to a positive side of aDC voltage source 28. A cathode is provided by a conducting portion of apolishing pad 30 connected to a negative side of theDC voltage source 28.Electrolyte 26 is applied by adispenser 27 at the interface of the substrate and thepolishing pad 30. Thesubstrate 22 is held by an electrically insulating holder, and is positioned in close proximity to the conducting portion of thepolishing pad 30, while maintaining adequate separation between the same to allow for electrolyte flow. A voltage applied by thevoltage source 28 generates a current flow through the known electropolishing electrolyte, which causes the metal of the metal layer on each respective substrate to dissolve in the electrolyte. An advantage of the invention is that, thepolishing pad 30 itself will pool the electrolyte about thesubstrate 22 without requiring immersion in a tank, such as, thetank 24. Electropolishing is performed until substantial reduction of thethickness 24 of themetal layer 15 is attained for eachsubstrate 22 being polished. The removal rate of themetal layer 15 is faster than that resulting from CMP, even while the apparatus of FIG. 6 is not operating to perform CMP during electropolishing. - The removal rate of the
metal layer 15 is faster while the apparatus of FIG. 6, according to another embodiment thereof, performs CMP during electropolishing. - According to another embodiment of the apparatus disclosed by FIG. 6, a nonconducting portion of the
polishing pad 30 contacts the substrate, especially when the nonconducting portion is a polishing surface of thepolishing pad 30, which spaces the conducting portion of thepolishing pad 30 away from thesubstrate 22. According to an embodiment, the conducting portion of thepolishing pad 30 is recessed away from the polishing surface, and is spaced away from thesubstrate 22 in contact with the polishing surface. A further embodiment of the electrolyte comprises a chemical composition for performance of CMP, as well as, for performance of electropolishing. The removal rate of themetal layer 15 is faster than that resulting from CMP solely. Further, by combining both electropolishing and CMP, the removal rate of themetal layer 15 is faster than that resulting from either electropolishing solely or CMP solely. - When a substantial reduction in
thickness 14 is attained, the apparatus of FIG. 6 operates solely to perform CMP. Metal is removed by abrasion applied by the polishing pad and by chemical reaction with the electrolyte that comprises a CMP polishing composition. Although the removal rate of the metal decreases, the CMP operation without electropolishing provides a smooth, planar polished surface on the substrate that is unattainable by performing electropolishing. Further, the removal rate of metal by electropolishing tends to cause dishing, which refers to unwanted recesses in the metal in the trenches, which are considered as damage to the circuit interconnects. Thus performing CMP without electropolishing obtain complete removal of themetal layer 15, with minimized dishing. - CMP without electropolishing is performed by having the DC voltage source turned off. Alternatively, the DC voltage source is reversible in polarity. By performing CMP with the DC voltage source providing a voltage of reversed polarity relative to electropolishing, the current direction is reversed relative to electropolishing, which clears away charged contaminants from the
metal layer 15 during CMP. Any metal ions that tend to plate onto themetal layer 15 are removed by CMP. - CMP is then performed in the presence of the applied electrical field at a downforce of up to about 10 psi to obtain a planar surface. The applied voltage difference will be of such low magnitude as to prevent local hot spots and corrosion on the substrate surface.
- According to an embodiment of the invention, CMP is performed simultaneously with electropolishing, when an electropolishing electrolyte further comprises a CMP polishing compositon. A CMP polishing composition comprises, a metal complexing agent, a metal oxidizing agent and/or a metal corrosion inhibitor. The use of conventional CMP polishing compositions reduces cross-contamination on the tool and the need for multiple rinsing steps. Further, the electrolyte comprising the polishing composition will perform for both electropolishing and CMP. The invention significantly reduces waste and cross contamination when the same apparatus performs electropolishing and CMP.
- A CMP polishing composition may or may not have abrasive particles, oxidizing agents, complexing agents, pH buffers, surfactants and dispersants. Examples of abrasive particles include but are not limited to ceria, alumina, silica, titania, germania, zirconia, diamond, silicon carbide and combinations thereof.
- Exemplary complexing agents comprise, mono- and dicarboxylic aliphatic or aromatic acids and their salts such as malic acid, malates, tartaric acid and tartarates, gluconic acid and gluoconates, citric acid and citrates, malonic acid and malonates, formic acid and formates, lactic acid and lactates, phthalic acid and phtalates. Polyhydroxybenzoic acid and its salts are also used.
- Examples of oxidizing agents comprise, hydrogen peroxide; and iodates, nitrates, carbonates, perchlorates, and/or persulfates of alkali, alkaline earth and rare earth metals.
- Examples of inhibitors include BTA (benzotriazole) and TTA (tolyltriazole) or mixtures thereof. Other inhibitors that can be used are 1-hydroxybenzotriazole, N-(1H-benzotriazole-1-ylmethyl)formamide, 3,5-dimethylpyrazole, indazole, 4-bromopyrazole, 3-amino-5-phenylpyrazole, 3-amino-4-pyrazolecarbonitrile, 1-methyimidazole, Indolin QTS and the like.
- The weight percentages of the complexing agents, oxidizing agents and corrosion inhibitors are adjusted to maximize the electropolishing rate desired.
- This example illustrates the removal rate due to electropolishing copper using a conventional, abrasive free CMP polishing fluid as the electrolyte. A current density of 0.1 Amp per sq. cm. was used during this experiment. Each data point was generated using a copper (Cu) disk, 1.2 cm, available from Johnson Matthey Company, immersed in the CMP polishing fluid for various contact times. The CMP polishing fluid contained about 5% of ammonium hydrogen phthalate, about 1% of iminodiacetic acid, about 0.08% of tolyltriazole and about 1.7% of hydrogen peroxide. The experimental results are tabulated below.
Hold Time Initial (min) Wt (gm) Final Wt (gm) Wt. Loss (gm) Wt. Loss (A) 1 1.26 1.2585 0.0015 59529.15 2 1.2386 1.237 0.0016 63452.92 3 1.2442 1.2417 0.0025 99215.25 4 1.2446 1.2413 0.0033 130941.7 5 1.2635 1.2595 0.004 158632.3 - The results shown in FIGS. 7 and 8 indicate that electropolishing of copper utilizing conventional CMP polishing fluids achieves rapid removal of the metal layer from the substrate.
- CMP of copper results in a removal rate of about 2,000 to about 4,000 Angstroms per minute. Thus for copper layer about 15,000 Angstroms in thickness, the average duration is about 5 minutes. Traditionally, electropolishing requires the use of phosphoric acid or phosphate salt electrolytes or other electrolytes used in the plating industry. This choice of electrolyte makes integration of conventional electropolishing with CMP difficult due to cross-contamination and waste handling issues. Using a CMP slurry as the electrolyte enables integration of electropolishing with CMP resulting in a hybrid process that reduces processing time, significantly reduces wastes and yields substrates with highly planar surfaces.
- Embodiments and modifications of the invention in the disclosed embodiments are intended to be covered by the spirit and scope of the appended claims.
Claims (7)
1. Apparatus for removing metal from a semiconductor substrate, comprising: a polishing pad, a holder of the semiconductor substrate in close proximity to the polishing pad, an electropolishing electrolyte, a dispenser of the electropolishing electrolyte at an interface of the polishing pad and the substrate, and a DC voltage source applying a DC voltage across the polishing pad and the substrate to remove metal from the metal layer.
2. The apparatus as recited in claim 1 , wherein the DC voltage source is reversible in polarity.
3. The apparatus as recited in claim 1 , wherein the electropolishing electrolyte comprises a polishing composition for polishing the substrate with the polishing pad and with the polishing composition.
4. A method for removing metal from a semiconductor substrate by dissolving ions of the metal into an electrolyte, comprising the steps of: applying a voltage across a polishing pad and the substrate, while an electropolishing electrolyte is dispensed at an interface of the substrate and the polishing pad, and while pooling the electrolyte about the substrate by the polishing pad.
5. The method of claim 4 further comprising the steps of: turning off the voltage across the polishing pad and the substrate, and polishing the substrate with the polishing pad and with the electropolishing electrolyte comprising a polishing composition, while the voltage is turned off.
6. The method of claim 4 further comprising the steps of: polishing the substrate with the polishing pad and with the electropolishing electrolyte comprising a polishing composition, while applying the voltage across the polishing pad and the substrate.
7. The method of claim 6 further comprising the steps of: turning off the voltage across the polishing pad and the substrate, and polishing the substrate with the polishing pad and with the electropolishing electrolyte comprising a polishing composition, while the voltage is turned off.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/989,338 US20020104764A1 (en) | 2000-11-20 | 2001-11-20 | Electropolishing and chemical mechanical planarization |
Applications Claiming Priority (2)
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US24999500P | 2000-11-20 | 2000-11-20 | |
US09/989,338 US20020104764A1 (en) | 2000-11-20 | 2001-11-20 | Electropolishing and chemical mechanical planarization |
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US20020104764A1 true US20020104764A1 (en) | 2002-08-08 |
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US09/989,338 Abandoned US20020104764A1 (en) | 2000-11-20 | 2001-11-20 | Electropolishing and chemical mechanical planarization |
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WO (1) | WO2002041369A2 (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
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US20020025759A1 (en) * | 2000-08-30 | 2002-02-28 | Whonchee Lee | Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material |
US20020025763A1 (en) * | 2000-08-30 | 2002-02-28 | Whonchee Lee | Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate |
US20030054729A1 (en) * | 2000-08-30 | 2003-03-20 | Whonchee Lee | Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate |
US20030109198A1 (en) * | 2000-08-30 | 2003-06-12 | Whonchee Lee | Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium |
US20030129927A1 (en) * | 2000-08-30 | 2003-07-10 | Whonchee Lee | Methods and apparatus for selectively removing conductive material from a microelectronic substrate |
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WO2004111146A1 (en) * | 2003-06-06 | 2004-12-23 | Applied Materials, Inc. | Polishing composition and method for polishing a conductive material |
US6848977B1 (en) | 2003-08-29 | 2005-02-01 | Rohm And Haas Electronic Materials Cmp Holdings, Inc. | Polishing pad for electrochemical mechanical polishing |
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US20070093182A1 (en) * | 2005-10-24 | 2007-04-26 | 3M Innovative Properties Company | Polishing fluids and methods for CMP |
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US4140598A (en) * | 1976-06-03 | 1979-02-20 | Hitachi Shipbuilding & Engineering Co., Ltd. | Mirror finishing |
US5911619A (en) * | 1997-03-26 | 1999-06-15 | International Business Machines Corporation | Apparatus for electrochemical mechanical planarization |
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US6328872B1 (en) * | 1999-04-03 | 2001-12-11 | Nutool, Inc. | Method and apparatus for plating and polishing a semiconductor substrate |
US6299741B1 (en) * | 1999-11-29 | 2001-10-09 | Applied Materials, Inc. | Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus |
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2001
- 2001-11-20 WO PCT/US2001/043368 patent/WO2002041369A2/en not_active Application Discontinuation
- 2001-11-20 US US09/989,338 patent/US20020104764A1/en not_active Abandoned
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WO2002041369A3 (en) | 2004-01-08 |
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