US20020076910A1 - High density electronic interconnection - Google Patents

High density electronic interconnection Download PDF

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Publication number
US20020076910A1
US20020076910A1 US09/737,407 US73740700A US2002076910A1 US 20020076910 A1 US20020076910 A1 US 20020076910A1 US 73740700 A US73740700 A US 73740700A US 2002076910 A1 US2002076910 A1 US 2002076910A1
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metal
bumps
conductors
metallic pads
manufacturing
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US09/737,407
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Benedict Pace
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Priority to US09/737,407 priority Critical patent/US20020076910A1/en
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Priority to US10/989,882 priority patent/US7271028B1/en
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/0077Other packages not provided for in groups B81B7/0035 - B81B7/0074
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H05K3/4007Surface contacts, e.g. bumps

Definitions

  • the invention is related to electronic interconnections and methods of forming bumped patterns for these interconnections.
  • Ball grid arrays are made by coating a pad grid on the chip package with high temperature solder, (95% Pb/5% Sn).
  • a glass template is provided with a hole grid corresponding to the pad grid.
  • the holes are filled with copper balls coated with high temperature solder, and the high temperature solder is reflowed to join the balls to the pad.
  • the ball grid package is attached to the next level assembly by a lower temperature solder, e.g. 60% Sn/40% Pb.
  • Ball grid arrays require carefull and precise control of soldering temperatures. Replacement or repair of packages having ball grid arrays also requires temperature control for package removal.
  • Many hermetic packages have covers that are bonded to the package by sealing glass. The covers are sealed with sealing glasses at 360-450° C. Ball grid arrays for such packages cannot be made in advance, but must be added as the last step in making the package.
  • Micro-connection systems have been proposed for testing to produce “known-gooddie”
  • One proposed micro-connection system has microbumps on a copper clad polyimide substrate which are to be temporarily pressed against the die for testing purposes.
  • a silicone rubber sheet backing the micro bumped polyimide surface transmits the contact pressure to the microbumps.
  • These proposed microbumps are not suitable for permanent connections, or for hermetically sealed packages.
  • the Controlled Collapse Chip Connection is a method of flip chip mounting of semiconductor chips.
  • solder bumps are formed on a semiconductor chip.
  • the solder bumps are used to connect the chip to its package, such as a single chip module (SCM) or multichip module (MCM).
  • SCM single chip module
  • MCM multichip module
  • a glass passivation layer is formed on the chip with vias in the layer for the input/output contacts, I/Os.
  • a thin circular pad of chromium is evaporated through a mask. The chromium pad covers the via and forms a ring around the via over the passivation layer sealing the via.
  • the DC sputter cleaning assures low contact resistance to the aluminum I/O pad of the chip and good adhesion to the passivation layer.
  • a phased chromium and copper layer is evaporated to provide resistance to multiple reflows in the subsequent processing. This is followed by a pure copper layer to form a solderable metal.
  • a thin layer of gold is added as an oxidation protection layer for the copper.
  • a thick deposit (100-125 ⁇ m) of high melting solder (97-95% Pb/3-5% Sn) is evaporated through a mask onto the chip and then heated to about 365° C. in a hydrogen atmosphere to fuse the solder into truncated spheres adhering to the pads.
  • solder bumps are fused to gold plated or solder coated pads on the interior surface of the chip package.
  • the solder joints in the C 4 design must be high enough to compensate for substrate non-planarity. Also because solder surface tension holds up the chip, a sufficient number of pads is required to support the weight of the chip. This is a concern with bulky, low 1 /O devices such as memory chips or chip carriers, where multiple dummy pads must be added to support the chip. For this reason, among others, the C 4 process has been used for connecting semiconductor chips to a first level package, but has not been successful or widely used for connecting a package, which is substantially heavier than a chip to a higher level assembly.
  • the invention comprises a novel method of forming bumped substrates by forming the bumps and fusing them to the substrate simultaneously in one operation.
  • the present invention comprises a method of manufacturing an electronic interconnection means for interconnecting one or more conductors on one surface to one or more conductors on another surface.
  • the interconnection means comprises convex metal bumps melted onto the conductors on the first surface, and capable of being bonded to the conductors on the second surface.
  • the bumps being comprised of a metal that does not melt below 350 ° C., and is strong enough to hold the two surfaces a fixed distance apart.
  • the present invention comprises an improved method for manufacturing an electronic package having solderable metal bumps as a connecting means to another electronic package or a higher level assembly.
  • the improvement comprises providing an insulating substrate having metallic pads on the base of the package; depositing a metal on the substrate over the metallic pads, the metal having a melting point over 350° C. and below the melting point of the metal forming the metallic pads; melting the metal so that it draws back onto the metallic pads, and forms metal bumps on the metallic pads.
  • the invention comprises a method for manufacturing bumped conductors for electrically connecting one or more conductors on a first surface to one or more conductors on a second surface by providing contact areas in the conductive pattern on the first surface that are wettable by a molten metal. Then depositing the metal over the contact areas, and raising the temperature of the first surface above the melting point of the deposited metal. The metal melts, and the molten metal forms bumps on the contact areas.
  • the bumps being comprised of a metal having a melting point over 350° C., and the bumps formed being capable of being bonded to the conductors on the second surface
  • a further embodiment of the invention is a method of making electrical connections to electro mechanical devices by means of metal bumps on the conductive pattern of a ceramic substrate.
  • the bumps both support the device and electrically connect it.
  • An additional embodiment of the invention is an connector to interconnect two or more electronic packages or assemblies.
  • the connector comprises a planar, high temperature, insulating substrate with an interconnecting conductive pattern.
  • the conductive pattern terminates in metal bumps capable of metallurgically bonding to contact pads of another assembly.
  • FIG. 1 is a cross section view of a chip-scale package according to the invention.
  • FIG. 2 is a cross section view of a flip chip package according to the invention.
  • FIG. 3 is a cross section view of a multichip module with melted metal bumps as interconnection means
  • FIG. 4 is a plan view of a ceramic substrate having 256 grid arrays of the metal bumps of the invention.
  • FIG. 5 is a plan view of a single grid array from FIG. 4.
  • FIG. 6 is a side view of a connector interconnecting two adjacent packages.
  • FIG. 7 is a side view of a second grid array metal bumped connector.
  • the interconnections of the present invention are by means of metal bumps on a high temperature insulating substrate.
  • the bumps are formed by melting metals onto the contact pads on the substrate.
  • the conductive pattern of a substrate or base is provided with contact pads where the metal forming the bumps can be adhered when the metal is molten, and a background surface of the substrate where the molten metal is non-adherent.
  • the contact pads can be metal pads or metallic sites capable of being wetted by the molten metal on a non-wettable background.
  • the backgrounds include non-wettable metallic surfaces such as chrome or chrome alloys having a thin, non-wettable oxide layer, and non-wettable insulating surfaces and combinations of non-wettable surface background materials. Wettable areas are areas on the substrate surface where the molten metal adsorbs.
  • the bumps are formed by applying metal to areas of the substrate and melting the metal to form the bumps.
  • the metal can be applied or deposited on the substrate by any suitable means such as plating, vacuum deposition, sputtering and the like, or as metal particles or powders, wires, films or foils.
  • the metal is applied to the contact pads and may also be applied to contiguous background areas.
  • the substrate is then heated to a temperature above the melting point of the metal and the surface tension of the molten metal draws it back from the contiguous background area forming a bump on the contact pad.
  • the height of the bump depends on the volume of metal applied on the contact pad and also on the contiguous background area.
  • the metal that is applied on each pad and the contiguous background area associated with it is separated from neighboring areas and their contiguous metal deposits.
  • the surface tension of the molten metal will draw back any metal applied to the contiguous area onto the contact pad.
  • the surface tension of the molten metal may not be sufficient to draw all the metal from the contiguous areas if the contiguous background is rough, textured, or if the surface of the background softens at the temperature of the molten metal. In such cases it is advisable to apply all of the metal required to form the protuberance directly on the contact area with little or no overlap of the contiguous background area.
  • the invention is a method of forming metal bumps on an electronic interconnecting substrate, the bumps being suitable for connecting to another electronic assembly.
  • the bumps are formed by applying metal particles, films or foils to metallic pads on the substrate and melting the metal particles, film or foils to form the bumps on the metallic pads.
  • the invention also provides packages with bumped arrays for forming metallurgical bonds to another assembly.
  • the packages are capable of being hermetically sealed.
  • a characteristic of the metal forming the bumps is a melting point above the temperature at which the package will be joined to another package or to another assembly.
  • the conductors on the surface having the melted metal bumps are joined to the conductors on the second surface by metallurgically or adhesively bonding the bumps to the contact pads on the second surface.
  • the metallurgical bonds can be formed by brazing, soldering, welding or the like.
  • Welding techniques commonly used in the electronics industry include thermocompression bonding, ultrasonic bonding and thermal ultrasonic bonding.
  • Soldering is the standard procedure by which electronic component packages are joined to other assemblies, such as ceramic circuits or laminated glass reinforced epoxy printed wiring boards. The soldering takes place at temperatures between 220° C.
  • the melting point of the metals forming the bumps should be over 350° C. (650° F.).
  • the melting point of the metal forming the bumps must be below the melting point of the metal forming the metallic pads.
  • the bumps must be formed of a metal that has sufficient strength and rigidity to support the surface and prevent collapse when joining it to another surface or another assembly.
  • the bumps should be high enough to compensate for non-planarity of the surfaces being joined, and strong enough to keep the surfaces apart to prevent short circuits, and to permit cleaning between the two surfaces.
  • the bumps should support the package without addition of dummy bumps.
  • the metal that is melted and melted to a substrate to form the bumps must adhere well to the metallic pads of the substrate.
  • Techniques for joining the bumped substrate to contact pads on another surface include adhesive and metallurgical bonding techniques.
  • Adhesive bonding uses conductive organic materials and includes metal filled resins such as conductive epoxies, acrylics and polyimides.
  • Metallurgical bonding techniques include welding, brazing, soldering, and the like.
  • Welding techniques commonly used in the electronics industry include thermocompression bonding, ultrasonic bonding and thermal ultrasonic bonding.
  • the metal of the bumps may be gold or aluminum.
  • the bumped substrate is to be joined to the contact pads on another surface by soldering
  • an important characteristic of the bumps is limited solubility in solder. If the metal dissolves in solder, the bumps may collapse. Also at soldering temperatures the bumps should not dissolve significantly in solder so as to weaken and/or embrittle the solder joints. If the bumps are formed of a metal that may be dissolved in solder, the bumps should be coated with a barrier layer such as nickel.
  • the bumps are formed of metals and alloys with melting points above 350° C.
  • Preferred metals are copper and copper alloys such as copper/nickel, beryllium/copper, brasses and bronzes.
  • Nickel and nickel alloys such as nickel/phosphorus alloys also may be used.
  • Silver and silver alloys such as copper/silver, palladium/silver and gold and gold alloys such as gold/germanium and gold/silver platinum/gold alloys may be used.
  • a barrier metal such as nickel or palladium may be used to reduce the solubility of the bumps in solder or prevent migration of the bump metal into the solder.
  • a solder aid such as a thin layer of gold, tin or a flux may be applied to the barrier metal.
  • the substrate is preferably formed from a high temperature insulating material. Any insulating material may be used that will withstand the process of fusing the metal and forming the bumps on the substrate. Especially suitable high temperature insulating materials are ceramic and glass/ceramic compositions and silicon. Preferred materials comprise aluminum oxide, aluminum nitride, diamond, beryllium oxide, boron nitride, cordierite, mullite, silicon carbide silicon nitride and glass/ceramics.
  • the metallic pads are formed on the high temperature insulating material by any suitable means. On ceramic materials, thick film, thin film, cofired ceramic circuit or copper direct bond metallization techniques may be used.
  • the metallic pads are composed of metals with melting points above the melting point of the bumps, and that will not melt, dissolve or lose adhesion to the insulating substrate when the metals forming the bumps are melted and fused to the pads.
  • the metals for the metallic pads are selected from the group consisting of the metals of Groups 8 and 1 b of the Periodic Table of Elements and the refractory metals such as chromium, molybdenum, tungsten and titanium.
  • Preferred metals for the metallic pads are formed from thick film copper pastes, gold pastes, palladium/silver pastes and platinum/silver pastes. More preferred metals include tungsten, titanium-tungsten, chromium, molybdenum and nickel, and most preferred are combinations of molybdenum and manganese.
  • a barrier material on the metallic pad, such as nickel or palladium may be used to limit the solubility of the metal of the bump into the metal comprising the metallic pad.
  • the high temperature insulating material may have electrical connections from the die to either metallic pads on its bottom or metallic pads on the same side as the die.
  • the die may be connected to the package by wire bonds, or by a flip chip bonding.
  • the connections to the bottom of the package may be through the substrate of the package as metallic vias when the package is a cofired multilayer ceramic, or by metal plugged vias in the substrate of the package.
  • the connections also may be accomplished by edge metallization.
  • the metal or metal alloy that is melted onto the metallic pads may be applied to the substrate as a metal powder, by printing metal pastes, by evaporating metal onto the substrate, by applying a metal foil to the substrate, or other means. After the metal is applied to the substrate, it is heated to a temperature above its melting point. When the metal melts the surface tension of the molten metal causes the metal to draw back and ball up on the metallic pads.
  • Metal pastes applied using thick film screen printing techniques are one method of applying metal powder onto the metallic pads of the substrate.
  • the pastes are formulated with metal powders dispersed in organic vehicles.
  • a metal paste is prepared by dispersing 50-90% by weight metal powder in an organic resin/solvent vehicle.
  • the metal paste is printed over each of the metallic pads on the substrate.
  • the paste is dried and then the temperature ramped up to destroy the organic vehicle, leaving only the powder.
  • the temperature is then raised above the melting point of the powdered metal, and the part is fired in a vacuum or an inert or reducing atmosphere The metal melts and draws back to the metallic pads forming rounded metal bumps.
  • the metallic pads on the high temperature insulating substrate are covered by an organic adhesive and metal particles are applied to the adhesive.
  • the adhesive is formulated so that it will decompose completely in the firing process. After the metal particles are applied, the substrate is heated above the melting point of the metal, so that the surface tension of the molten metal causes the metal to draw back and form bumps on the metallic pads.
  • the metals used to form the bumps may be applied to an insulating substrate by electroplating.
  • the metallic pads may be electroplated by connecting them to the cathode of an electroplating cell.
  • a layer of electroless metal is formed on a ceramic substrate including the metallic pads, and built up to a required thickness by electroplating, e.g., copper.
  • An etch resist is applied over the electroplated metal, and the metal is etched to create an area of metal in contact with each metallic pads on the substrate. After the etch resist is removed the metal is heated to a temperature above the its melting point. When the metal melts the surface tension of the molten metal causes the metal to draw back, ball up on and fuse to the metallic pads.
  • a plating resist is applied to the electroless metal layer described above, leaving exposed metal over each of the metallic pads. Copper is electroplated on the exposed areas. After the plating resist is removed, the underlying layer of electroless metal separating the electroplated areas optionally may be removed by a quick etch prior to melting the copper to form the bumps
  • Metal foils such as copper foils may be used to form the bumps over the metallic pads on the substrate.
  • the foils may be laminated to the bottom of the substrate with an adhesive that decomposes during the firing.
  • the foils may be perforated or porous to better vent the decomposing adhesive. Areas of metal overlapping the metallic pads may be formed by etching. Upon melting, these areas draw back and ball up forming bumps on the metallic pads.
  • the foil could be punched forming a pattern of islands joined by very narrow bands. The punched foil is positioned on the substrate with each punched island overlapping a metallic pad. When it is heated above the melting point of the foil, the narrow bands melt and act as cleavage points as the islands draw back to form bumps over and fuse to the metallic pads.
  • the height of the bumps is determined by the quantity of metal or alloy that is melted on each metallic pad. It would be obvious for one skilled in the art to select the volume of material over the metallic pad in order to obtain the desired bump height.
  • FIG. 1 A package according to the invention is illustrated in FIG. 1.
  • the package shown in cross-section, has a base 110 , a semiconductor device 120 connected by wire bonds 130 to the conductive pattern of the base, a frame 140 , surrounding the device, which is closed by a cover 150 .
  • the conductive pattern includes vias connecting the top and bottom of the base.
  • Melted metal bumps 160 formed on the bottom of the base are suitable for connecting the package to another assembly.
  • the metal bumps of the interconnection package may be soldered to a printed wiring board, thus connecting the semiconductor device to the next level assembly.
  • a “flip-connection” package having melted metal bumps for connection to another assembly is shown in FIG. 2.
  • the metal bumps 260 are formed on the bottom of the ceramic base 210 .
  • the metal bumps are connected by the conductive pattern of the ceramic base and the flip-connections 230 to a semiconductor die 220 .
  • the semiconductor device is enclosed by a frame 240 and cover 250 .
  • FIG. 3 illustrates a multichip module package with three electronic devices 320 , 322 and 324 connected to the conductive pattern of a ceramic base 310 .
  • the ceramic base has melted metal bumps 360 on the bottom to serve as input/output interconnections for the module.
  • FIG. 6 illustrates a connector interconnecting two side-by-side surfaces 614 and 615 .
  • the connector is an insulating substrate 610 with a grid array pattern 670 .
  • Metal bumps have been formed on the grid array by melting metal and fusing it to the grid array.
  • the grid array pattern is interconnected by the conductive pattern (not shown) of the insulating substrate.
  • the metal bumps are metallurgically bonded to the pads 690 on the conductive patterns (not shown) of the two side-by-side surfaces 614 and 615 .
  • FIG. 7 shows another connector having an insulating substrate 710 , with metal bumps 770 on both top and bottom surfaces.
  • the metal bumps are connected by the conductive pattern of the insulating substrate.
  • Two surfaces 714 and 715 are interconnected by being metallurgically bonded to the metal bumps of the connector.
  • the conductive pattern of the connector could be a simple through via pattern for direct interconnection of 714 and 715 , or a more complex conductive pattern to interconnect any contact pad to any other desired contact pad.
  • a 2 in. ⁇ 2 in. ⁇ 0.01 in. thick (50 mm ⁇ 50 mm ⁇ 0.25 mm) alumina substrate 400 was printed with a pattern simulating the connections of 256 chip scale packages.
  • the chip scale package size was 0.125 in. ⁇ 0.125 in. (3.175 mm ⁇ 3.175 mm), and each simulated package had 20 pad connections 470 .
  • FIG. 5 shows an individual package with 20 pads 570 .
  • the paste pattern was fired in a hydrogen atmosphere at about 3150° C. forming metallic pads 0.006′′ (150 ⁇ m) in diameter.
  • a copper paste was prepared by dispersing 80% by weight copper powder in 20% by weight ethyl cellulose/terpineol vehicle.
  • the copper paste was printed in oversize pads, 0.018′′ (0.46 mm) on 0.020′′ centers, where each pad overlapped a tungsten pad.
  • the copper paste was dried, fired in a hydrogen atmosphere at a low temperature to decompose the organic vehicle, and then fired at a temperature above the melting point of copper. In the firing, the temperature was ramped up over 40 minutes to 1100° C.; held at 1100° C. for 30 minutes, and ramped down over a period of 30 minutes.
  • a 2′′ by 2′′ (50 mm ⁇ 50 mm) alumina plate was printed with a molybdenum/manganese (Mo/Mn) paste in a pattern of 5120 pads, 0.006′′ (150 ⁇ m) in diameter.
  • the pads were in 256 groups of 20 pads each on 0.020′′ (0.5 mm) centers as in Example 1.
  • the Mo/Mn paste on the alumina was fired forming metallic pads 0.006′′ in diameter.
  • a copper paste was screen printed over the metallic pads in a pattern of circles 0.018′′ (0.46 mm) on the same 0.020′′ (0.5 mm) centers as the metallic pads.
  • the copper paste on the alumina was dried and then temperature was ramped up over 30 minutes to 1100° C. and held at 1100° C. for 35 minutes before slowly cooling down. The copper melted and the surface tension of the molten copper drew the copper back to form bumps 0.006′′ in diameter on the metallic pads.
  • the copper pattern overlapping one metallic pad is preferably spaced apart from the pattern overlapping a neighboring metallic pad, long, narrow prints are well suited for applications where the metallic pads are so tightly spaced that one could't supply a sufficient volume of material using a circular or square pattern.
  • the melted metal bumps may be used to interconnect packages having a single layer or multilayer conductive patterns.
  • the invention is applicable to packages containing more than one semiconductor chip, or a package containing multiple semiconductor circuits on a single die, wafer or section of a wafer.

Abstract

This is an interconnection between electronic devices and other assemblies (e.g. printed circuits). The electronic devices are mounted on high temperature insulating bases, such as ceramic substrates. The insulating base has a conductive pattern to connect the electronic device to another assembly. The conductive pattern terminates in metal bumps capable of being connected to another assembly (e.g. a printed circuit) by a conductive adhesive or metallurgically by soldering, thermocompression, thermosonic or ultrasonic bonding. The bumps are formed by applying a metal with a melting point over 350° C. to contact pads of the conductive pattern of the insulating base, and raising the temperature of the base above the melting point of the metal causing the molten metal to draw back on to the contact pads forming a convex bump.

Description

  • This application claims the benefit of Provisional Application No. 60/170,975 filed Dec. 15, 1999, and also of Provisional Application No. 60/170,976 filed Dec. 15, 1999.[0001]
  • FIELD OF THE INVENTION
  • The invention is related to electronic interconnections and methods of forming bumped patterns for these interconnections. [0002]
  • BACKGROUND OF THE INVENTION
  • Ball grid arrays are made by coating a pad grid on the chip package with high temperature solder, (95% Pb/5% Sn). A glass template is provided with a hole grid corresponding to the pad grid. The holes are filled with copper balls coated with high temperature solder, and the high temperature solder is reflowed to join the balls to the pad. Subsequently, the ball grid package is attached to the next level assembly by a lower temperature solder, e.g. 60% Sn/40% Pb. Ball grid arrays require carefull and precise control of soldering temperatures. Replacement or repair of packages having ball grid arrays also requires temperature control for package removal. Many hermetic packages have covers that are bonded to the package by sealing glass. The covers are sealed with sealing glasses at 360-450° C. Ball grid arrays for such packages cannot be made in advance, but must be added as the last step in making the package. [0003]
  • Micro-connection systems have been proposed for testing to produce “known-gooddie” One proposed micro-connection system has microbumps on a copper clad polyimide substrate which are to be temporarily pressed against the die for testing purposes. A silicone rubber sheet backing the micro bumped polyimide surface transmits the contact pressure to the microbumps. These proposed microbumps are not suitable for permanent connections, or for hermetically sealed packages. [0004]
  • The Controlled Collapse Chip Connection (C[0005] 4) is a method of flip chip mounting of semiconductor chips. In the C4 process solder bumps are formed on a semiconductor chip. The solder bumps are used to connect the chip to its package, such as a single chip module (SCM) or multichip module (MCM). In the C4 process, first a glass passivation layer is formed on the chip with vias in the layer for the input/output contacts, I/Os. After DC sputter cleaning of the via holes, a thin circular pad of chromium is evaporated through a mask. The chromium pad covers the via and forms a ring around the via over the passivation layer sealing the via. The DC sputter cleaning assures low contact resistance to the aluminum I/O pad of the chip and good adhesion to the passivation layer. Next a phased chromium and copper layer is evaporated to provide resistance to multiple reflows in the subsequent processing. This is followed by a pure copper layer to form a solderable metal. A thin layer of gold is added as an oxidation protection layer for the copper. A thick deposit (100-125 μm) of high melting solder (97-95% Pb/3-5% Sn) is evaporated through a mask onto the chip and then heated to about 365° C. in a hydrogen atmosphere to fuse the solder into truncated spheres adhering to the pads. These solder bumps are fused to gold plated or solder coated pads on the interior surface of the chip package. The solder joints in the C4 design must be high enough to compensate for substrate non-planarity. Also because solder surface tension holds up the chip, a sufficient number of pads is required to support the weight of the chip. This is a concern with bulky, low 1/O devices such as memory chips or chip carriers, where multiple dummy pads must be added to support the chip. For this reason, among others, the C4 process has been used for connecting semiconductor chips to a first level package, but has not been successful or widely used for connecting a package, which is substantially heavier than a chip to a higher level assembly.
  • SUMMARY OF THE INVENTION
  • The invention comprises a novel method of forming bumped substrates by forming the bumps and fusing them to the substrate simultaneously in one operation. [0006]
  • The present invention comprises a method of manufacturing an electronic interconnection means for interconnecting one or more conductors on one surface to one or more conductors on another surface. The interconnection means comprises convex metal bumps melted onto the conductors on the first surface, and capable of being bonded to the conductors on the second surface. The bumps being comprised of a metal that does not melt below [0007] 350° C., and is strong enough to hold the two surfaces a fixed distance apart.
  • In one embodiment the present invention comprises an improved method for manufacturing an electronic package having solderable metal bumps as a connecting means to another electronic package or a higher level assembly. The improvement comprises providing an insulating substrate having metallic pads on the base of the package; depositing a metal on the substrate over the metallic pads, the metal having a melting point over 350° C. and below the melting point of the metal forming the metallic pads; melting the metal so that it draws back onto the metallic pads, and forms metal bumps on the metallic pads. [0008]
  • In another embodiment, the invention comprises a method for manufacturing bumped conductors for electrically connecting one or more conductors on a first surface to one or more conductors on a second surface by providing contact areas in the conductive pattern on the first surface that are wettable by a molten metal. Then depositing the metal over the contact areas, and raising the temperature of the first surface above the melting point of the deposited metal. The metal melts, and the molten metal forms bumps on the contact areas. The bumps being comprised of a metal having a melting point over 350° C., and the bumps formed being capable of being bonded to the conductors on the second surface [0009]
  • A further embodiment of the invention is a method of making electrical connections to electro mechanical devices by means of metal bumps on the conductive pattern of a ceramic substrate. The bumps both support the device and electrically connect it. [0010]
  • An additional embodiment of the invention is an connector to interconnect two or more electronic packages or assemblies. The connector comprises a planar, high temperature, insulating substrate with an interconnecting conductive pattern. The conductive pattern terminates in metal bumps capable of metallurgically bonding to contact pads of another assembly.[0011]
  • DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross section view of a chip-scale package according to the invention. [0012]
  • FIG. 2 is a cross section view of a flip chip package according to the invention. [0013]
  • FIG. 3 is a cross section view of a multichip module with melted metal bumps as interconnection means [0014]
  • FIG. 4 is a plan view of a ceramic substrate having 256 grid arrays of the metal bumps of the invention. [0015]
  • FIG. 5 is a plan view of a single grid array from FIG. 4. [0016]
  • FIG. 6 is a side view of a connector interconnecting two adjacent packages. [0017]
  • FIG. 7 is a side view of a second grid array metal bumped connector.[0018]
  • DESCRIPTION OF THE INVENTION
  • The interconnections of the present invention are by means of metal bumps on a high temperature insulating substrate. The bumps are formed by melting metals onto the contact pads on the substrate. [0019]
  • In the methods of this invention the conductive pattern of a substrate or base is provided with contact pads where the metal forming the bumps can be adhered when the metal is molten, and a background surface of the substrate where the molten metal is non-adherent. The contact pads can be metal pads or metallic sites capable of being wetted by the molten metal on a non-wettable background. The backgrounds include non-wettable metallic surfaces such as chrome or chrome alloys having a thin, non-wettable oxide layer, and non-wettable insulating surfaces and combinations of non-wettable surface background materials. Wettable areas are areas on the substrate surface where the molten metal adsorbs. [0020]
  • The bumps are formed by applying metal to areas of the substrate and melting the metal to form the bumps. The metal can be applied or deposited on the substrate by any suitable means such as plating, vacuum deposition, sputtering and the like, or as metal particles or powders, wires, films or foils. The metal is applied to the contact pads and may also be applied to contiguous background areas. The substrate is then heated to a temperature above the melting point of the metal and the surface tension of the molten metal draws it back from the contiguous background area forming a bump on the contact pad. The height of the bump depends on the volume of metal applied on the contact pad and also on the contiguous background area. Preferably the metal that is applied on each pad and the contiguous background area associated with it, is separated from neighboring areas and their contiguous metal deposits. [0021]
  • If the background surface is smooth, firm and non-wettable, the surface tension of the molten metal will draw back any metal applied to the contiguous area onto the contact pad. The surface tension of the molten metal may not be sufficient to draw all the metal from the contiguous areas if the contiguous background is rough, textured, or if the surface of the background softens at the temperature of the molten metal. In such cases it is advisable to apply all of the metal required to form the protuberance directly on the contact area with little or no overlap of the contiguous background area. [0022]
  • In one embodiment, the invention is a method of forming metal bumps on an electronic interconnecting substrate, the bumps being suitable for connecting to another electronic assembly. The bumps are formed by applying metal particles, films or foils to metallic pads on the substrate and melting the metal particles, film or foils to form the bumps on the metallic pads. [0023]
  • The invention also provides packages with bumped arrays for forming metallurgical bonds to another assembly. The packages are capable of being hermetically sealed. [0024]
  • A characteristic of the metal forming the bumps is a melting point above the temperature at which the package will be joined to another package or to another assembly. The conductors on the surface having the melted metal bumps are joined to the conductors on the second surface by metallurgically or adhesively bonding the bumps to the contact pads on the second surface. The metallurgical bonds can be formed by brazing, soldering, welding or the like. Welding techniques commonly used in the electronics industry include thermocompression bonding, ultrasonic bonding and thermal ultrasonic bonding. Soldering is the standard procedure by which electronic component packages are joined to other assemblies, such as ceramic circuits or laminated glass reinforced epoxy printed wiring boards. The soldering takes place at temperatures between 220° C. (425° F.) and 290° C. (550° F.), so the melting point of the metals forming the bumps should be over 350° C. (650° F.). The melting point of the metal forming the bumps must be below the melting point of the metal forming the metallic pads. [0025]
  • The bumps must be formed of a metal that has sufficient strength and rigidity to support the surface and prevent collapse when joining it to another surface or another assembly. The bumps should be high enough to compensate for non-planarity of the surfaces being joined, and strong enough to keep the surfaces apart to prevent short circuits, and to permit cleaning between the two surfaces. Preferably the bumps should support the package without addition of dummy bumps. The metal that is melted and melted to a substrate to form the bumps must adhere well to the metallic pads of the substrate. [0026]
  • Techniques for joining the bumped substrate to contact pads on another surface include adhesive and metallurgical bonding techniques. Adhesive bonding uses conductive organic materials and includes metal filled resins such as conductive epoxies, acrylics and polyimides. Metallurgical bonding techniques include welding, brazing, soldering, and the like. Welding techniques commonly used in the electronics industry include thermocompression bonding, ultrasonic bonding and thermal ultrasonic bonding. When the bumped substrate is to be joined to contact pads on another surface by thermocompression, ultrasonic or thermal ultrasonic techniques, the metal of the bumps may be gold or aluminum. [0027]
  • When the bumped substrate is to be joined to the contact pads on another surface by soldering, an important characteristic of the bumps is limited solubility in solder. If the metal dissolves in solder, the bumps may collapse. Also at soldering temperatures the bumps should not dissolve significantly in solder so as to weaken and/or embrittle the solder joints. If the bumps are formed of a metal that may be dissolved in solder, the bumps should be coated with a barrier layer such as nickel. [0028]
  • The bumps are formed of metals and alloys with melting points above 350° C. Preferred metals are copper and copper alloys such as copper/nickel, beryllium/copper, brasses and bronzes. Nickel and nickel alloys such as nickel/phosphorus alloys also may be used. Silver and silver alloys such as copper/silver, palladium/silver and gold and gold alloys such as gold/germanium and gold/silver platinum/gold alloys may be used. A barrier metal such as nickel or palladium may be used to reduce the solubility of the bumps in solder or prevent migration of the bump metal into the solder. To enhance the solderability of bumps coated with nickel or other barrier metal, a solder aid such as a thin layer of gold, tin or a flux may be applied to the barrier metal. [0029]
  • The substrate is preferably formed from a high temperature insulating material. Any insulating material may be used that will withstand the process of fusing the metal and forming the bumps on the substrate. Especially suitable high temperature insulating materials are ceramic and glass/ceramic compositions and silicon. Preferred materials comprise aluminum oxide, aluminum nitride, diamond, beryllium oxide, boron nitride, cordierite, mullite, silicon carbide silicon nitride and glass/ceramics. [0030]
  • The metallic pads are formed on the high temperature insulating material by any suitable means. On ceramic materials, thick film, thin film, cofired ceramic circuit or copper direct bond metallization techniques may be used. The metallic pads are composed of metals with melting points above the melting point of the bumps, and that will not melt, dissolve or lose adhesion to the insulating substrate when the metals forming the bumps are melted and fused to the pads. The metals for the metallic pads are selected from the group consisting of the metals of Groups 8 and [0031] 1 b of the Periodic Table of Elements and the refractory metals such as chromium, molybdenum, tungsten and titanium. Preferred metals for the metallic pads are formed from thick film copper pastes, gold pastes, palladium/silver pastes and platinum/silver pastes. More preferred metals include tungsten, titanium-tungsten, chromium, molybdenum and nickel, and most preferred are combinations of molybdenum and manganese. A barrier material on the metallic pad, such as nickel or palladium may be used to limit the solubility of the metal of the bump into the metal comprising the metallic pad.
  • If the high temperature insulating material is used for an electronic package that will contain a semiconductor die, it may have electrical connections from the die to either metallic pads on its bottom or metallic pads on the same side as the die. The die may be connected to the package by wire bonds, or by a flip chip bonding. The connections to the bottom of the package may be through the substrate of the package as metallic vias when the package is a cofired multilayer ceramic, or by metal plugged vias in the substrate of the package. The connections also may be accomplished by edge metallization. [0032]
  • The metal or metal alloy that is melted onto the metallic pads may be applied to the substrate as a metal powder, by printing metal pastes, by evaporating metal onto the substrate, by applying a metal foil to the substrate, or other means. After the metal is applied to the substrate, it is heated to a temperature above its melting point. When the metal melts the surface tension of the molten metal causes the metal to draw back and ball up on the metallic pads. [0033]
  • Metal pastes applied using thick film screen printing techniques are one method of applying metal powder onto the metallic pads of the substrate. The pastes are formulated with metal powders dispersed in organic vehicles. E.g., a metal paste is prepared by dispersing 50-90% by weight metal powder in an organic resin/solvent vehicle. The metal paste is printed over each of the metallic pads on the substrate. The paste is dried and then the temperature ramped up to destroy the organic vehicle, leaving only the powder. The temperature is then raised above the melting point of the powdered metal, and the part is fired in a vacuum or an inert or reducing atmosphere The metal melts and draws back to the metallic pads forming rounded metal bumps. [0034]
  • In one embodiment, the metallic pads on the high temperature insulating substrate are covered by an organic adhesive and metal particles are applied to the adhesive. The adhesive is formulated so that it will decompose completely in the firing process. After the metal particles are applied, the substrate is heated above the melting point of the metal, so that the surface tension of the molten metal causes the metal to draw back and form bumps on the metallic pads. [0035]
  • The metals used to form the bumps may be applied to an insulating substrate by electroplating. The metallic pads may be electroplated by connecting them to the cathode of an electroplating cell. In another electroplating method, a layer of electroless metal is formed on a ceramic substrate including the metallic pads, and built up to a required thickness by electroplating, e.g., copper. An etch resist is applied over the electroplated metal, and the metal is etched to create an area of metal in contact with each metallic pads on the substrate. After the etch resist is removed the metal is heated to a temperature above the its melting point. When the metal melts the surface tension of the molten metal causes the metal to draw back, ball up on and fuse to the metallic pads. [0036]
  • In an alternative procedure, a plating resist is applied to the electroless metal layer described above, leaving exposed metal over each of the metallic pads. Copper is electroplated on the exposed areas. After the plating resist is removed, the underlying layer of electroless metal separating the electroplated areas optionally may be removed by a quick etch prior to melting the copper to form the bumps [0037]
  • Metal foils, such as copper foils may be used to form the bumps over the metallic pads on the substrate. The foils may be laminated to the bottom of the substrate with an adhesive that decomposes during the firing. The foils may be perforated or porous to better vent the decomposing adhesive. Areas of metal overlapping the metallic pads may be formed by etching. Upon melting, these areas draw back and ball up forming bumps on the metallic pads. Alternatively the foil could be punched forming a pattern of islands joined by very narrow bands. The punched foil is positioned on the substrate with each punched island overlapping a metallic pad. When it is heated above the melting point of the foil, the narrow bands melt and act as cleavage points as the islands draw back to form bumps over and fuse to the metallic pads. [0038]
  • The height of the bumps is determined by the quantity of metal or alloy that is melted on each metallic pad. It would be obvious for one skilled in the art to select the volume of material over the metallic pad in order to obtain the desired bump height. [0039]
  • A package according to the invention is illustrated in FIG. 1. The package, shown in cross-section, has a [0040] base 110, a semiconductor device 120 connected by wire bonds 130 to the conductive pattern of the base, a frame 140, surrounding the device, which is closed by a cover 150. The conductive pattern includes vias connecting the top and bottom of the base. Melted metal bumps 160 formed on the bottom of the base are suitable for connecting the package to another assembly. The metal bumps of the interconnection package may be soldered to a printed wiring board, thus connecting the semiconductor device to the next level assembly.
  • A “flip-connection” package having melted metal bumps for connection to another assembly, is shown in FIG. 2. The metal bumps [0041] 260 are formed on the bottom of the ceramic base 210. The metal bumps are connected by the conductive pattern of the ceramic base and the flip-connections 230 to a semiconductor die 220. The semiconductor device is enclosed by a frame 240 and cover 250. Some methods for providing packages with flip connections are more fully described in U.S. Pat. Nos. 5,627,406, 5,904,499 and the copending application entitled INTERCONNECTION METHODS, filed simultaneously with the current application, and which is incorporated herein by reference.
  • FIG. 3 illustrates a multichip module package with three [0042] electronic devices 320, 322 and 324 connected to the conductive pattern of a ceramic base 310. The ceramic base has melted metal bumps 360 on the bottom to serve as input/output interconnections for the module. A frame 340 mounted on the ceramic base, and a cover 350 is attached to the frame to enclose and protect the devices.
  • FIG. 6 illustrates a connector interconnecting two side-by-[0043] side surfaces 614 and 615. The connector is an insulating substrate 610 with a grid array pattern 670. Metal bumps have been formed on the grid array by melting metal and fusing it to the grid array. The grid array pattern is interconnected by the conductive pattern (not shown) of the insulating substrate. The metal bumps are metallurgically bonded to the pads 690 on the conductive patterns (not shown) of the two side-by- side surfaces 614 and 615.
  • FIG. 7 shows another connector having an insulating [0044] substrate 710, with metal bumps 770 on both top and bottom surfaces. The metal bumps are connected by the conductive pattern of the insulating substrate. Two surfaces 714 and 715 are interconnected by being metallurgically bonded to the metal bumps of the connector. It would be obvious to those skilled in the art that the conductive pattern of the connector could be a simple through via pattern for direct interconnection of 714 and 715, or a more complex conductive pattern to interconnect any contact pad to any other desired contact pad.
  • EXAMPLE 1
  • Referring to FIG. 4, a 2 in.×2 in.×0.01 in. thick (50 mm×50 mm×0.25 mm) [0045] alumina substrate 400 was printed with a pattern simulating the connections of 256 chip scale packages. The chip scale package size was 0.125 in.×0.125 in. (3.175 mm×3.175 mm), and each simulated package had 20 pad connections 470. FIG. 5 shows an individual package with 20 pads 570. A tungsten paste, Tungsten Mix No. 3™ from Ceronics Inc., of New Jersey, was printed in 0.006 in. diameter (150 μm) pads on 0.020″ (0.5 mm) centers. The paste pattern was fired in a hydrogen atmosphere at about 3150° C. forming metallic pads 0.006″ (150 μm) in diameter.
  • A copper paste was prepared by dispersing 80% by weight copper powder in 20% by weight ethyl cellulose/terpineol vehicle. The copper paste was printed in oversize pads, 0.018″ (0.46 mm) on 0.020″ centers, where each pad overlapped a tungsten pad. The copper paste was dried, fired in a hydrogen atmosphere at a low temperature to decompose the organic vehicle, and then fired at a temperature above the melting point of copper. In the firing, the temperature was ramped up over 40 minutes to 1100° C.; held at 1100° C. for [0046] 30 minutes, and ramped down over a period of 30 minutes.
  • In the firing process the copper pads pulled back onto and balled up on the tungsten pads forming uniformly high copper bumps suitable for joining the alumina substrate to another electronic package or higher level electronic assembly by soldering or other means. [0047]
  • EXAMPLE 2
  • A 2″ by 2″ (50 mm×50 mm) alumina plate was printed with a molybdenum/manganese (Mo/Mn) paste in a pattern of 5120 pads, 0.006″ (150 μm) in diameter. The pads were in 256 groups of 20 pads each on 0.020″ (0.5 mm) centers as in Example 1. The Mo/Mn paste on the alumina was fired forming metallic pads 0.006″ in diameter. A copper paste was screen printed over the metallic pads in a pattern of circles 0.018″ (0.46 mm) on the same 0.020″ (0.5 mm) centers as the metallic pads. The copper paste on the alumina was dried and then temperature was ramped up over [0048] 30 minutes to 1100° C. and held at 1100° C. for 35 minutes before slowly cooling down. The copper melted and the surface tension of the molten copper drew the copper back to form bumps 0.006″ in diameter on the metallic pads.
  • The procedure was repeated with square, copper paste prints and long, narrow, rectangular, copper paste prints over the 0.006″ diameter metallic pads. In all cases, after firing the copper drew back and formed smooth convex bumps over the metallic pads. [0049]
  • Since the copper pattern overlapping one metallic pad is preferably spaced apart from the pattern overlapping a neighboring metallic pad, long, narrow prints are well suited for applications where the metallic pads are so tightly spaced that one couldn't supply a sufficient volume of material using a circular or square pattern. [0050]
  • It will be obvious to those skilled in the art that the melted metal bumps may be used to interconnect packages having a single layer or multilayer conductive patterns. Likewise the invention is applicable to packages containing more than one semiconductor chip, or a package containing multiple semiconductor circuits on a single die, wafer or section of a wafer. [0051]

Claims (24)

I claim:
1. A method for manufacturing bumped conductors for electrically connecting one or more conductors on a first surface to one or more conductors on a second surface, the method comprising melting a metal on the first surface to form metal bumps fused to the conductors on the first surface, the bumps being capable of being bonded to the conductors on the second surface, and the bumps being comprised of a metal having a melting point over 350° C.
2. A method according to claim 1 wherein the metal being melted to form bumps is capable of being metallurgically bonded to the conductors on the second surface.
3. A method according to claim 1 wherein the metal being melted to form bumps is capable of being adhesively bonded to the conductors on the second surface with an organic adhesive.
4. A method according to claim 1, wherein the metal to be melted to form the bumps is selected from the group consisting of aluminum, copper, nickel, silver, gold, and alloys and combinations of those metals.
5. A method according to claim 1, wherein the metal to be melted to form the bumps is strong enough to support the first surface spaced away from the second surface during and after the bonding of the bumps to the conductors on the second surface.
6. A method according to claim 2, wherein the metal forming the bumps is capable of being metallurgically bonded to the conductors on the second surface by soldering.
7. A method according to claim 2, wherein the bumps are capable of being metallurgically bonded to the conductors on the second surface by welding.
8. A method for manufacturing bumped conductors for electrically connecting one or more conductors on a first surface to one or more conductors on a second surface, the method comprising:
providing contact areas in the conductive pattern on the first surface that are wettable by a molten metal;
depositing the metal over the contact areas;
melting the metal, the molten metal forming bumps on the contact areas, the bumps being capable of being bonded to the conductors on the second surface, and the bumps being comprised of a metal having a melting point over 350° C.
9. The method of claim 8, wherein the metal being deposited over the wettable contact areas includes some metal being deposited on non-wettable areas contiguous to the wettable area, and upon melting the metal, the molten metal draws back from the non-wettable areas to the wettable contact areas to form the bumps.
10. A method according to claim 8, wherein the metal being melted to form bumps is capable of being metallurgically bonded to the conductors on the second surface.
11. A method according to claim 8, wherein the metal being melted to form bumps is capable of being adhesively bonded to the conductors on the second surface with an organic adhesive.
12. In a method according to claim 8, wherein the bumps are formed of a metal selected from the group consisting of aluminum, copper, nickel, silver, gold, and alloys comprising these metals.
13. A method according to claim 8, wherein the metal to be melted to form the bumps is strong enough to support the first surface spaced away from the second surface during and after the bonding of the bumps to the conductors on the second surface.
14. A method according to claim 10, wherein the metal forming the bumps is capable of being metallurgically bonded to the conductors on the second surface by soldering.
15. A method according to claim 10, wherein the bumps are capable of being metallurgically bonded to the conductors on the second surface by welding.
16. In a method for manufacturing an electronic package having solderable metal bumps as a connecting means, the improvement comprising:
providing an insulating substrate having metallic pads as a base for the package;
depositing a metal on the substrate over the metallic pads, the metal having a melting point over 350° C., and below the melting point of the metal forming the metallic pads;
melting the metal so that it draws back onto the metallic pads, forming metal bumps on the metallic pads.
17. In a method for manufacturing an electronic package having metal bumps according to claim 16, wherein the metal is deposited over the metallic pads in a powdered form.
18. In a method for manufacturing an electronic package having metal bumps according to claim 17, wherein the powdered metal is deposited by screen printing.
19. In a method for manufacturing an electronic package having metal bumps according to claim 16, the improvement comprising:
providing the insulating substrate with metallic pads of metals selected from the group consisting of refractory metals and the metals of Groups 8 and 1b of the Periodic Table of Elements and alloys and combinations of those metals;
depositing a lower melting metal selected from the group consisting of aluminum and aluminum alloys, copper and copper alloys, silver and silver alloys, gold and gold alloys, nickel and nickel alloys and combinations of those metals, over the metallic pads; and
melting the lower melting metal so that it draws back onto the metallic pads, forming metal bumps on the metallic pads.
20. In the method of manufacturing an electronic package according to claim 19, wherein the metal of the metallic pads on the insulating substrate are selected from the group consisting of chromium, molybdenum, nickel, tungsten, molybdenum/manganese and titanium/tungsten.
21. In the method of manufacturing an electronic package according to claim 20 wherein the metal forming the bumps comprises copper.
22. In the method of manufacturing an electronic package according to claim 20, wherein the metal forming the bumps is selected from the group consisting of silver, gold, silver alloys and gold alloys.
23. In the method of manufacturing an electronic package according to claim 22, wherein the bumps are coated with a barrier metal capable of preventing the bumps from dissolving in molten solder.
24. In the method of manufacturing an electronic package according to claim 23, wherein the barrier metal is coated with a solder aid to enhance solderability
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116866A1 (en) * 2001-12-20 2003-06-26 Cher 'khng Victor Tan Semiconductor package having substrate with multi-layer metal bumps
US7132356B1 (en) 1999-12-15 2006-11-07 Pace Benedict G Interconnection method
WO2007045204A1 (en) * 2005-10-20 2007-04-26 Epcos Ag Housing with a cavity for a mechanically-sensitive electronic component and method for production
US20070222056A1 (en) * 2004-04-22 2007-09-27 Epcos Ag Encapsulated Electrical Component and Production Method
US20080038577A1 (en) * 2004-08-12 2008-02-14 Epcos Ag Component Arrangement Provided With a Carrier Substrate
US20080279407A1 (en) * 2005-11-10 2008-11-13 Epcos Ag Mems Microphone, Production Method and Method for Installing
US20090140432A1 (en) * 2007-11-29 2009-06-04 Farooq Mukta G Pad structure to provide improved stress relief
WO2009071637A2 (en) * 2007-12-07 2009-06-11 Epcos Ag Mems package and method for the production thereof
US20100013078A1 (en) * 2007-01-10 2010-01-21 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same
US8169041B2 (en) 2005-11-10 2012-05-01 Epcos Ag MEMS package and method for the production thereof
US8184845B2 (en) 2005-02-24 2012-05-22 Epcos Ag Electrical module comprising a MEMS microphone
US20130143364A1 (en) * 2011-12-06 2013-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of processing solder bump by vacuum annealing
US8582788B2 (en) 2005-02-24 2013-11-12 Epcos Ag MEMS microphone
US9556022B2 (en) * 2013-06-18 2017-01-31 Epcos Ag Method for applying a structured coating to a component

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7513035B2 (en) * 2006-06-07 2009-04-07 Advanced Micro Devices, Inc. Method of integrated circuit packaging
US8445329B2 (en) * 2009-09-30 2013-05-21 Ati Technologies Ulc Circuit board with oval micro via
US8138019B2 (en) * 2009-11-03 2012-03-20 Toyota Motor Engineering & Manufactruing North America, Inc. Integrated (multilayer) circuits and process of producing the same
US8093714B2 (en) * 2009-12-10 2012-01-10 Semtech Corporation Chip assembly with chip-scale packaging
TWM425478U (en) * 2011-11-14 2012-03-21 Hon Hai Prec Ind Co Ltd Printed circuit board
US20140106179A1 (en) * 2012-10-17 2014-04-17 Raytheon Company Plating design and process for improved hermeticity and thermal conductivity of gold-germanium solder joints

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493856A (en) * 1982-03-18 1985-01-15 International Business Machines Corporation Selective coating of metallurgical features of a dielectric substrate with diverse metals
US5108027A (en) * 1989-05-16 1992-04-28 Gec-Marconi Limited Flip chip solder bond structure for devices with gold based metallization
US5229213A (en) * 1988-11-14 1993-07-20 Shinko Electric Industries Co., Ltd. Aluminum nitride circuit board
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3663184A (en) 1970-01-23 1972-05-16 Fairchild Camera Instr Co Solder bump metallization system using a titanium-nickel barrier layer
US4742023A (en) 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device
US6077725A (en) 1992-09-03 2000-06-20 Lucent Technologies Inc Method for assembling multichip modules
US5347710A (en) * 1993-07-27 1994-09-20 International Business Machines Corporation Parallel processor and method of fabrication
US5656858A (en) 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
EP0804806A1 (en) 1994-12-22 1997-11-05 Benedict G. Pace Device for superheating steam
US5904499A (en) 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
US6614110B1 (en) 1994-12-22 2003-09-02 Benedict G Pace Module with bumps for connection and support
US5744752A (en) * 1995-06-05 1998-04-28 International Business Machines Corporation Hermetic thin film metallized sealband for SCM and MCM-D modules
US6388264B1 (en) 1997-03-28 2002-05-14 Benedict G Pace Optocoupler package being hermetically sealed
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US6069026A (en) * 1997-08-18 2000-05-30 Texas Instruments Incorporated Semiconductor device and method of fabrication
JPH11231177A (en) * 1997-12-12 1999-08-27 Oki Electric Ind Co Ltd Optical element module and manufacture of the optical element module
US5969418A (en) 1997-12-22 1999-10-19 Ford Motor Company Method of attaching a chip to a flexible substrate
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
JP3420703B2 (en) 1998-07-16 2003-06-30 株式会社東芝 Method for manufacturing semiconductor device
SE512906C2 (en) * 1998-10-02 2000-06-05 Ericsson Telefon Ab L M Procedure for soldering a semiconductor chip and RF power transistor for conducting it
US6613605B2 (en) 1999-12-15 2003-09-02 Benedict G Pace Interconnection method entailing protuberances formed by melting metal over contact areas

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493856A (en) * 1982-03-18 1985-01-15 International Business Machines Corporation Selective coating of metallurgical features of a dielectric substrate with diverse metals
US5229213A (en) * 1988-11-14 1993-07-20 Shinko Electric Industries Co., Ltd. Aluminum nitride circuit board
US5108027A (en) * 1989-05-16 1992-04-28 Gec-Marconi Limited Flip chip solder bond structure for devices with gold based metallization
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132356B1 (en) 1999-12-15 2006-11-07 Pace Benedict G Interconnection method
US20050173788A1 (en) * 2001-12-20 2005-08-11 Cher'khng Victor T. Semiconductor package having wire bonded die and multi layer metal bumps
US7202556B2 (en) * 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
US7208828B2 (en) 2001-12-20 2007-04-24 Micron Technology, Inc. Semiconductor package with wire bonded stacked dice and multi-layer metal bumps
US20030116866A1 (en) * 2001-12-20 2003-06-26 Cher 'khng Victor Tan Semiconductor package having substrate with multi-layer metal bumps
US7253022B2 (en) 2001-12-20 2007-08-07 Micron Technology, Inc. Method for fabricating semiconductor package with multi-layer metal bumps
US20070262469A1 (en) * 2001-12-20 2007-11-15 Khng Victor T C Method for fabricating semiconductor package with multi-layer die contact and external contact
US7550315B2 (en) 2001-12-20 2009-06-23 Micron Technology, Inc. Method for fabricating semiconductor package with multi-layer die contact and external contact
US7544540B2 (en) 2004-04-22 2009-06-09 Epcos Ag Encapsulated electrical component and production method
US20070222056A1 (en) * 2004-04-22 2007-09-27 Epcos Ag Encapsulated Electrical Component and Production Method
US7608789B2 (en) 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
US20080038577A1 (en) * 2004-08-12 2008-02-14 Epcos Ag Component Arrangement Provided With a Carrier Substrate
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US8184845B2 (en) 2005-02-24 2012-05-22 Epcos Ag Electrical module comprising a MEMS microphone
WO2007045204A1 (en) * 2005-10-20 2007-04-26 Epcos Ag Housing with a cavity for a mechanically-sensitive electronic component and method for production
US20090127697A1 (en) * 2005-10-20 2009-05-21 Wolfgang Pahl Housing with a Cavity for a Mechanically-Sensitive Electronic Component and Method for Production
US8169041B2 (en) 2005-11-10 2012-05-01 Epcos Ag MEMS package and method for the production thereof
US8432007B2 (en) 2005-11-10 2013-04-30 Epcos Ag MEMS package and method for the production thereof
US8229139B2 (en) 2005-11-10 2012-07-24 Epcos Ag MEMS microphone, production method and method for installing
US20080279407A1 (en) * 2005-11-10 2008-11-13 Epcos Ag Mems Microphone, Production Method and Method for Installing
US20110133346A1 (en) * 2007-01-10 2011-06-09 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same
US20100013078A1 (en) * 2007-01-10 2010-01-21 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same
US20110127667A1 (en) * 2007-01-10 2011-06-02 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same
US20110121447A1 (en) * 2007-01-10 2011-05-26 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same
US8044524B2 (en) * 2007-01-10 2011-10-25 Hitachi Chemical Company, Ltd. Adhesive for connection of circuit member and semiconductor device using the same
US7755206B2 (en) * 2007-11-29 2010-07-13 International Business Machines Corporation Pad structure to provide improved stress relief
US20090140432A1 (en) * 2007-11-29 2009-06-04 Farooq Mukta G Pad structure to provide improved stress relief
US20110006381A1 (en) * 2007-12-07 2011-01-13 Epcos Ag Mems package and method for the production thereof
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