US20020058356A1 - Semiconductor package and mount board, and mounting method using the same - Google Patents

Semiconductor package and mount board, and mounting method using the same Download PDF

Info

Publication number
US20020058356A1
US20020058356A1 US09/631,524 US63152400A US2002058356A1 US 20020058356 A1 US20020058356 A1 US 20020058356A1 US 63152400 A US63152400 A US 63152400A US 2002058356 A1 US2002058356 A1 US 2002058356A1
Authority
US
United States
Prior art keywords
package
board
lands
mount
side lands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/631,524
Inventor
Yoichi Oya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/631,524 priority Critical patent/US20020058356A1/en
Publication of US20020058356A1 publication Critical patent/US20020058356A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a semiconductor package and a mount board on which the semiconductor package is mounted, and a mounting method using the same, and particularly to a technique for enhancing mount reliability of a semiconductor package having mount terminals arranged at a minute pitch.
  • CSP is typically known a BGA (Ball Grid Array) package in which terminals arranged on a relay board are metal balls such as soldering balls, Cu balls or the like.
  • a semiconductor chip 27 is mounted on a principal plane of a relay board 21 and farther coated with a mold resin layer 30 , and soldering balls 31 are regularly provided in an area arrangement on the other principal plane of the relay board 21 .
  • a first conductive pattern 22 is beforehand formed on one principal plane of the relay board 21 in association with input/output terminals 28 of the semiconductor chip 27 , and the semiconductor chip 27 is adhesively attached in a face-up style onto the relay board 21 through an insulating layer 26 of die bonding agent.
  • the input/output terminals 28 of the semiconductor chip 27 and the first conductive pattern 22 are connected by bonding wires 29 .
  • the first conductive pattern 22 is electrically connected through a penetrating bear hole 24 to a second conductive pattern 23 on the other principal plane side.
  • the second conductive pattern 23 is arranged in a grid shape over the entire surface or at the peripheral portion of the other principal plane of the relay board 21 , and the soldering balls 31 are arranged on the second conductive pattern 23 .
  • the linear arrangement of the input/output terminals 28 along the side of the rectangular semiconductor chip 27 is finally converted through the first conductive pattern 22 , the penetrating bear hole 24 and the second conducive pattern 23 to the grid arrangement of the soldering balls 31 , that is, the ball grid array.
  • the mount board 41 on which the BGA package p is mounted is beforehand provided with lands 42 correspondingly to the arrangement of the soldering balls 31 on one principal plane.
  • preliminary solder is coated on the lands 42 , and the soldering balls 31 of the BGA package p and the lands 42 of the mount board 41 are positioned to each other and joined to each other by a reflow soldering method or the like.
  • the respective adjacent ones of the second conductive pattern 23 on the relay board and the respective adjacent ones of the lands 42 on the mount board 41 are mutually insulated from each other by the soldering resist layer 25 and 43 in order to avoid the adjacent ones from being short-circuited by bridges of solder.
  • the opening edges 25 a and 43 a of the soldering resist layers 25 and 43 are formed on the second conductive pattern 23 and the lands 42 , respectively. That is, the respective opening areas of the soldering resist layers 26 and 43 are set to be smaller than the respective areas of the surfaces of the second conductive pattern 23 and the lands 42 .
  • throttle resist type Such the forming style of the lands and the solder resist layers as described above is hereinafter referred to as “throttle resist type”.
  • the inventor has found out that if lands are wholly exposed from a solder resist layer at least at one of a semiconductor package side and a mount board side to thereby enable a conductive material layer formed of soldering or the like to extend to the side wall surfaces of the lands, the joint strength between the conductive material layer and the lands can be improved by the increasing contact area between the conductive material layer and the lands and a shape of the conductive material layer.
  • a land of the package-side is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of the land.
  • a land of the board-side is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of the land
  • At least one of a package-side land and a board-side land is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface thereof, and the package-side land and the board-side land are electrically connected to each other through a conductive material layer.
  • FIG. 1 is a schematic cross-sectional view showing a conventional BGA package mounted on a mount board.
  • FIG. 2 is a schematic cross-sectional view showing a construction of a semiconductor package of the present invention.
  • FIG. 3 is a schematic cross-sectional view showing a construction of a mount board of the present invention.
  • FIG. 4 is a schematic cross-sectional view showing a state that the semiconductor package is positioned to the mount board in the present invention.
  • FIG. 5 is a schematic cross-sectional view showing a state that the semiconductor package of the present invention is mounted on the mount board of the present invention.
  • FIG. 6 is a schematic cross-sectional view showing a state that the semiconductor package designed in “over resist type” is mounted on the mount board designed in “throttle resist type”.
  • FIG. 7 is a schematic cross-sectional view showing a state that the semiconductor package designed in “throttle resist type” on the mount board designed in “over resist type”.
  • package-side lands arranged on a relay board are wholly exposed from a solder resist layer. Accordingly, the conductive material layer can extend to the side wall surfaces of the package-side lands when it is mounted on a mount board. As a result, the joint strength can be improved by by the increasing contact area between the conductive material layer and the lands and a shape of the conductive material layer, thereby enhancing the mount reliability.
  • Such the forming style of the lands and the solder resist layer as described above is hereinafter referred to as “over resist type”.
  • the semiconductor package of the present invention is made as a so-called LGA (Land Grid Array) package, and this is the most preferable embodiment. This is because the LGA package has a higher probability that the dimension and the arrangement pitch of the package-side lands is reduced as compared with the BGA package, and the improving effect of the joint strength as described above is relatively enhanced.
  • LGA Land Grid Array
  • the semiconductor package of the present invention can be made as a BGA package.
  • soldering balls are formed so as to cover all of the upper surfaces and the side wall surfaces of the package-side lands
  • the conductive material layer extends to the side wall surfaces of the board-side lands to enhance the joint strength as in the case of the package-side lands as described above.
  • the improving effect of the joint strength can be further enhanced. This is because the profile of the conductive material layer in a condition that the semiconductor package is mounted on the mount board is a pillar shape having an uniform section and thus the concentration of the stress to a specific point can be prevented. If the board-side lands and the package-side lands are extremely different in dimension, the profile of the conductive material layer is conical and thus the stress is concentrated to a portion having a small area, so that there is a large risk that cracks occur.
  • At least one of the semiconductor package and the mount board is designed in an over resist type, and both the lands are electrically connected to each other through the conductive material layer.
  • the conductive material layer may be used public-known material such as solder, conductive adhesive agent, anisotropic conductive film or the like.
  • a semiconductor package P 1 is a so-called LGA package in which a semiconductor chip 7 is mounted on a principal plane of a relay board 1 formed of glass-epoxy composite material and further coated with a mold resin layer 10 , and package-side lands 3 a are regularly provided in an area arrangement on the other principal plane.
  • a conductive pattern 2 is beforehand formed on one principal plane of the relay board 1 in association with input/output terminals 8 of a semiconductor chip 7 , and the semiconductor chip 7 is adhesively attached in a face-up style onto the relay board 1 through an insulating layer 6 of die bonding agent.
  • the input/output terminals 8 of the semiconductor chip 7 are connected to the conductive pattern 2 by using bonding wires 9 .
  • the conductive pattern 2 is guided through a penetrating bear hole 4 to the other principal plane side, and connected to the package-side lands 3 a.
  • the package-side lands 3 a are formed by patterning copper foil of 10 to 20 ⁇ m in thickness, and arranged in a grid shape on the whole surface of the other principal plane of the relay board 1 .
  • Each individual package side land 3 a is wholly exposed in the opening 5 a of the solder resist layer 5 as the over resist type.
  • board-side lands 12 a are formed at a area where a semiconductor package is to be mounted on one principal plane of a base 11 formed of ceramic correspondingly to the arrangement of the package-side lands of the semiconductor package.
  • the board-side lands 12 a are formed by pattering copper foil of 10 to 20 ⁇ m thickness, and arranged in a grid shape at the area of the base 11 where the semiconductor package is to be mounted. In this case, if the semiconductor package P 1 shown in FIG. 1 is mounted, the dimension, the shape and the number of the board-side lands 12 a are set to the same as the package-side lands 3 a described above.
  • Each of the board-side lands 12 a is wholly exposed in the opening 13 a of the solder resist layer 13 as the over resist type.
  • the shape and dimension of the opening 13 a are set to the same as the opening 5 a of the package side.
  • FIG. 4 shows a state that the semiconductor package P 1 shown in FIG. 2 and the mount board B 1 shown in FIG. 3 are positioned to each other.
  • a soldering layer 14 is deposited and formed on the board-side lands 12 a of the mount board B 1 by coating soldering paste on screen print.
  • FIG. 5 shows a state that the semiconductor package P 1 and the mount board B 1 are overlapped with each other in the direction as indicated by an arrow in FIG. 4 and subjected to reflow soldering.
  • the soldering layer 14 a adheres to both the package-side land 3 a and the board-side land 12 a while extending to the side wall surfaces thereof.
  • both the lands 3 a and 12 a are equal to each other in shape and dimension, so that the profile of the soldering layer 14 a thus formed is substantially uniform in section, and local stress concentration can be prevented.
  • both of the semiconductor package and the mount board are of the over resist type. In this case, however, it will be described with reference to FIG. 6 that only the semiconductor package is of the over resist type and the mount board is a conventional throttle resist type,
  • the solder resist layer 13 is coated on the edges of the board-side land 12 b, and the board-side land 12 b is exposed to the inside of the opening 13 b.
  • the size relationship between the board-side land 12 b and the opening 13 b is opposite to that in the mount board B 1 described above. That is, the board-side land 12 b is designed in a circular shape of 65 ⁇ m in diameter, the opening 13 b is designed in a circular shape of 45 ⁇ m in diameter.
  • a solder resist layer 5 covers the edges of package-side lands 3 b, and the package-side land 3 b is exposed to the inside of an opening 5 b.
  • the size relationship between the package-side land 3 b and the opening 5 b is opposite to that in the semiconductor package P 1 described above. That is, the package-side land 3 b is designed in a circular shape of 65 ⁇ m in diameter, and the opening 5 b is designed in a circular shape of 45 ⁇ m in diameter.
  • solder layer 14 a is joined to the board-side land 12 a extending to the side wall surface thereof, it is joined on only the upper surface of the package-side land 3 b.
  • the present invention is not limited to these embodiments.
  • the semiconductor chip which is adhesively attached in the face-up style is connected to the conductive pattern by the wire bonding.
  • the semiconductor chip may be mounted in a face-down style by using leads or soldering balls.
  • suitable modifications, selections and combinations may be made on the dimension and shape of the lands, the arrangement of the lands at the semiconductor package side or the mount board side and the details of the constituent materials of the respective parts, etc.

Abstract

The package-side land 3 a of a semiconductor package P1 is wholly exposed into the opening 5 a of a solder resist layer 5. The board-side land 12 a of the mount board B1 is also wholly exposed into the opening 13 a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14 a, the soldering layer 14 a is brought into contact to both the lands 3 a and 12 a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3 a and 12 a are set to be equal to each other in dimension and shape, the soldering layer 14 a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress. To ensure the joint strength based on a conductive material layer and enhance the mount reliability by making fine the terminals on a relay substrate which correspond to the input or output terminals of a semiconductor chip, and making the pitch narrow.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a semiconductor package and a mount board on which the semiconductor package is mounted, and a mounting method using the same, and particularly to a technique for enhancing mount reliability of a semiconductor package having mount terminals arranged at a minute pitch. [0001]
    • BACKGROUND OF THE INVENTION
  • In order to make a further development in miniaturization, high performance and multi-functionalization of electronic equipment, it is an important factor how to increase the mount density of components on a mount board. With respect to the mount of semiconductor chips, there have been proposed various CSP (Chip Size Package or Chip Scale Package) to suppress the dimension of the outer shape of a package to the same level as the dimension of the body of the semiconductor chip by improving the internal structure of the package. No standardization has been established for CSP at present, however, it is a substantially common point that all input/output terminals are formed on an element-formed surface of a semiconductor chip and the arrangement of the input/output terminals is converted to another regular area arrangement through a relay board. [0002]
  • As CSP is typically known a BGA (Ball Grid Array) package in which terminals arranged on a relay board are metal balls such as soldering balls, Cu balls or the like. [0003]
  • In the BGA package p as shown in FIG. 1, a [0004] semiconductor chip 27 is mounted on a principal plane of a relay board 21 and farther coated with a mold resin layer 30, and soldering balls 31 are regularly provided in an area arrangement on the other principal plane of the relay board 21.
  • A first [0005] conductive pattern 22 is beforehand formed on one principal plane of the relay board 21 in association with input/output terminals 28 of the semiconductor chip 27, and the semiconductor chip 27 is adhesively attached in a face-up style onto the relay board 21 through an insulating layer 26 of die bonding agent. The input/output terminals 28 of the semiconductor chip 27 and the first conductive pattern 22 are connected by bonding wires 29.
  • The first [0006] conductive pattern 22 is electrically connected through a penetrating bear hole 24 to a second conductive pattern 23 on the other principal plane side. The second conductive pattern 23 is arranged in a grid shape over the entire surface or at the peripheral portion of the other principal plane of the relay board 21, and the soldering balls 31 are arranged on the second conductive pattern 23.
  • As described above, the linear arrangement of the input/[0007] output terminals 28 along the side of the rectangular semiconductor chip 27 is finally converted through the first conductive pattern 22, the penetrating bear hole 24 and the second conducive pattern 23 to the grid arrangement of the soldering balls 31, that is, the ball grid array.
  • The [0008] mount board 41 on which the BGA package p is mounted is beforehand provided with lands 42 correspondingly to the arrangement of the soldering balls 31 on one principal plane. For example, preliminary solder is coated on the lands 42, and the soldering balls 31 of the BGA package p and the lands 42 of the mount board 41 are positioned to each other and joined to each other by a reflow soldering method or the like.
  • As shown in FIG. 1, the respective adjacent ones of the second [0009] conductive pattern 23 on the relay board and the respective adjacent ones of the lands 42 on the mount board 41 are mutually insulated from each other by the soldering resist layer 25 and 43 in order to avoid the adjacent ones from being short-circuited by bridges of solder.
  • The [0010] opening edges 25 a and 43 a of the soldering resist layers 25 and 43 are formed on the second conductive pattern 23 and the lands 42, respectively. That is, the respective opening areas of the soldering resist layers 26 and 43 are set to be smaller than the respective areas of the surfaces of the second conductive pattern 23 and the lands 42.
  • This is an idea to minimize the effect of dispersion of coplanarity (uniformity in height) of the [0011] soldering balls 31 on the mount reliability and to make the height of the balls uniform irrespective of presence or absence of a wire pattern at the periphery of a lands.
  • Such the forming style of the lands and the solder resist layers as described above is hereinafter referred to as “throttle resist type”. [0012]
  • If it is promoted in the future to further reduce the arrangement pitch of the [0013] soldering balls 31, however, in order to suppress the enlargement of the BGA package p due to increase of the number of the terminals of the semiconductor chip 27, the dimension of the second conductive pattern 23 and the soldering balls 31 themselves must be reduced so that the joint area between the second conductive pattern 23 and the soldering balls 31 is reduced. When such a BGA package p is mounted on the mount board and a predetermined temperature cycle test is performed, stress due to thermal deformation of the mount board 41 is concentrated onto the interface between the second conductive pattern 23 and the soldering balls 31, and the occurrence frequency of cracks (cracks) at this portion rises up. In addition, as the arrangement pitch of the soldering balls 31 is reduced, the risk that cracks occur in a large number of soldering balls 31 at the same time is increased.
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a semiconductor package and a mount board which can beforehand prevent the above disadvantage and enhance the mount reliability, and a mounting method using the same. [0014]
  • As a result of repeated considerations to attain the above object, the inventor has found out that if lands are wholly exposed from a solder resist layer at least at one of a semiconductor package side and a mount board side to thereby enable a conductive material layer formed of soldering or the like to extend to the side wall surfaces of the lands, the joint strength between the conductive material layer and the lands can be improved by the increasing contact area between the conductive material layer and the lands and a shape of the conductive material layer. [0015]
  • In the semiconductor package of the present invention, a land of the package-side is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of the land. [0016]
  • Further, in the mount board of the present invention, a land of the board-side is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of the land [0017]
  • Further, in the mounting method of the present invention, at least one of a package-side land and a board-side land is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface thereof, and the package-side land and the board-side land are electrically connected to each other through a conductive material layer.[0018]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic cross-sectional view showing a conventional BGA package mounted on a mount board. [0019]
  • FIG. 2 is a schematic cross-sectional view showing a construction of a semiconductor package of the present invention. [0020]
  • FIG. 3 is a schematic cross-sectional view showing a construction of a mount board of the present invention. [0021]
  • FIG. 4 is a schematic cross-sectional view showing a state that the semiconductor package is positioned to the mount board in the present invention. [0022]
  • FIG. 5 is a schematic cross-sectional view showing a state that the semiconductor package of the present invention is mounted on the mount board of the present invention. [0023]
  • FIG. 6 is a schematic cross-sectional view showing a state that the semiconductor package designed in “over resist type” is mounted on the mount board designed in “throttle resist type”. [0024]
  • FIG. 7 is a schematic cross-sectional view showing a state that the semiconductor package designed in “throttle resist type” on the mount board designed in “over resist type”.[0025]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In the semiconductor package of the present invention, package-side lands arranged on a relay board are wholly exposed from a solder resist layer. Accordingly, the conductive material layer can extend to the side wall surfaces of the package-side lands when it is mounted on a mount board. As a result, the joint strength can be improved by by the increasing contact area between the conductive material layer and the lands and a shape of the conductive material layer, thereby enhancing the mount reliability. Such the forming style of the lands and the solder resist layer as described above is hereinafter referred to as “over resist type”. [0026]
  • When the above package-side lands are directly mounted through a thin conductive material layer, the semiconductor package of the present invention is made as a so-called LGA (Land Grid Array) package, and this is the most preferable embodiment. This is because the LGA package has a higher probability that the dimension and the arrangement pitch of the package-side lands is reduced as compared with the BGA package, and the improving effect of the joint strength as described above is relatively enhanced. [0027]
  • However, the semiconductor package of the present invention can be made as a BGA package. In this, case, soldering balls are formed so as to cover all of the upper surfaces and the side wall surfaces of the package-side lands [0028]
  • Further, in the mount board of the present invention, by setting the board-side, lands and the soldering resist layer to the over resist type, the conductive material layer extends to the side wall surfaces of the board-side lands to enhance the joint strength as in the case of the package-side lands as described above. [0029]
  • If the dimension and shape of the board-side lands are substantially equal to those of the package-side lands, the improving effect of the joint strength can be further enhanced. This is because the profile of the conductive material layer in a condition that the semiconductor package is mounted on the mount board is a pillar shape having an uniform section and thus the concentration of the stress to a specific point can be prevented. If the board-side lands and the package-side lands are extremely different in dimension, the profile of the conductive material layer is conical and thus the stress is concentrated to a portion having a small area, so that there is a large risk that cracks occur. [0030]
  • In the mounting method of the present invention, at least one of the semiconductor package and the mount board is designed in an over resist type, and both the lands are electrically connected to each other through the conductive material layer. By designing only one of the semiconductor package and the mount board in the over resist type, the mount reliability can be more greatly enhanced as compared with the case where both are designed in the throttle resist type. However, if both are designed in the over resist type, the maximum improving effect can be obtained. [0031]
  • As the conductive material layer may be used public-known material such as solder, conductive adhesive agent, anisotropic conductive film or the like. [0032]
  • More detailed embodiments of the present invention will be hereunder described. [0033]
    • First Embodiment
  • A construction of a semiconductor package of an over-resist type will be described with reference to FIG. 2. [0034]
  • A semiconductor package P[0035] 1 is a so-called LGA package in which a semiconductor chip 7 is mounted on a principal plane of a relay board 1 formed of glass-epoxy composite material and further coated with a mold resin layer 10, and package-side lands 3 a are regularly provided in an area arrangement on the other principal plane.
  • A [0036] conductive pattern 2 is beforehand formed on one principal plane of the relay board 1 in association with input/output terminals 8 of a semiconductor chip 7, and the semiconductor chip 7 is adhesively attached in a face-up style onto the relay board 1 through an insulating layer 6 of die bonding agent. The input/output terminals 8 of the semiconductor chip 7 are connected to the conductive pattern 2 by using bonding wires 9.
  • The [0037] conductive pattern 2 is guided through a penetrating bear hole 4 to the other principal plane side, and connected to the package-side lands 3 a. The package-side lands 3 a are formed by patterning copper foil of 10 to 20 μm in thickness, and arranged in a grid shape on the whole surface of the other principal plane of the relay board 1. The package side lands 3 a are arranged, for example, circular package side lands 3 a of 15×15, 45 μm in diameter and pitch=0.8 mm are arranged in a full matrix shape.
  • Each individual [0038] package side land 3 a is wholly exposed in the opening 5 a of the solder resist layer 5 as the over resist type. The opening 5 a is set to be circular in 65 μmm diameter and depth=20 to 50 μm, for instance.
    • Second Embodiment
  • Here, a construction of a mount board of an over resist type will be described with reference to FIG. 3. [0039]
  • In a mount board B[0040] 1, board-side lands 12 a are formed at a area where a semiconductor package is to be mounted on one principal plane of a base 11 formed of ceramic correspondingly to the arrangement of the package-side lands of the semiconductor package. The board-side lands 12 a are formed by pattering copper foil of 10 to 20 μm thickness, and arranged in a grid shape at the area of the base 11 where the semiconductor package is to be mounted. In this case, if the semiconductor package P1 shown in FIG. 1 is mounted, the dimension, the shape and the number of the board-side lands 12 a are set to the same as the package-side lands 3 a described above.
  • Each of the board-side lands [0041] 12 a is wholly exposed in the opening 13 a of the solder resist layer 13 as the over resist type. The shape and dimension of the opening 13 a are set to the same as the opening 5 a of the package side.
    • Third Embodiment
  • In this case, a method of mounting the above semiconductor package P[0042] 1 on the mount board B1 will be described with reference to FIGS. 4 and 5.
  • FIG. 4 shows a state that the semiconductor package P[0043] 1 shown in FIG. 2 and the mount board B1 shown in FIG. 3 are positioned to each other. Here, a soldering layer 14 is deposited and formed on the board-side lands 12 a of the mount board B1 by coating soldering paste on screen print.
  • FIG. 5 shows a state that the semiconductor package P[0044] 1 and the mount board B1 are overlapped with each other in the direction as indicated by an arrow in FIG. 4 and subjected to reflow soldering. As shown in FIG. 5, the soldering layer 14 a adheres to both the package-side land 3 a and the board-side land 12 a while extending to the side wall surfaces thereof. In addition, both the lands 3 a and 12 a are equal to each other in shape and dimension, so that the profile of the soldering layer 14 a thus formed is substantially uniform in section, and local stress concentration can be prevented.
    • Fourth Embodiment
  • In the third embodiment, both of the semiconductor package and the mount board are of the over resist type. In this case, however, it will be described with reference to FIG. 6 that only the semiconductor package is of the over resist type and the mount board is a conventional throttle resist type, [0045]
  • In a mount board B[0046] 2 of FIG. 6, the solder resist layer 13 is coated on the edges of the board-side land 12 b, and the board-side land 12 b is exposed to the inside of the opening 13 b. The size relationship between the board-side land 12 b and the opening 13 b is opposite to that in the mount board B1 described above. That is, the board-side land 12 b is designed in a circular shape of 65 μm in diameter, the opening 13 b is designed in a circular shape of 45 μm in diameter.
  • When the semiconductor package P[0047] 1 is mounted on the mount board B2, while the soldering layer 14 a is joined to the package side lands 3 a extending to the side wall surfaces thereof as shown in FIG. 6, it is joined on only the upper surfaces of the board-side lands 12 b.
    • Fifth Embodiment
  • In this case, it will be described with reference to FIG. 7 that only the mount board is the over resist type and a semiconductor package of a conventional throttle resist type is used oppositely to the fourth embodiment. [0048]
  • In a semiconductor package P[0049] 2 shown in FIG. 7, a solder resist layer 5 covers the edges of package-side lands 3 b, and the package-side land 3 b is exposed to the inside of an opening 5 b. The size relationship between the package-side land 3 b and the opening 5 b is opposite to that in the semiconductor package P1 described above. That is, the package-side land 3 b is designed in a circular shape of 65 μm in diameter, and the opening 5 b is designed in a circular shape of 45 μm in diameter.
  • When the semiconductor package P[0050] 2 described above is mounted on the mount board B1, while a solder layer 14 a is joined to the board-side land 12 a extending to the side wall surface thereof, it is joined on only the upper surface of the package-side land 3 b.
  • Here, a thermal cycle test of −25° C. to +125° C. was carried out for each mount article obtained in the third to fifth embodiments and a cycle frequency until crack occurred at the soldering joint portion was examined. [0051]
  • As comparative examples, the same thermal cycle test was carried out for a mount article in which both the semiconductor package and the mount board were designed in the throttle resist type. This mount article was obtained by mounting the semiconductor package P[0052] 2 shown in FIG. 7 on the mount board B2 shown in FIG. 6. The result is shown in Table 1.
    TABLE 1
    Mount Board
    Semiconductor Over Resist Type Throttle Resist Type
    Package B1 B2
    Over Resist Type >1000 cycles >500 cycles
    P1 (Third embodiment) (Fourth embodiment)
    Throttle Resist Type  >500 cycles <250 cycles
    P2 (Fifth embodiment) (Comparative example)
  • In the case of the conventional mount article in which both the semiconductor package and the mount board are designed in the throttle resist type, the area of the soldering joint portion is limited to a small value, and thus crack occurred within 250 cycles. [0053]
  • On the other hand, in the case that either the semiconductor package or the mount board is designed in the over resist type, the cycle lifetime is substantially doubled. Further, in the case that both are designed in the over resist type, the cycle lifetime is increased four times. Accordingly, the mount reliability in the over resist type was confirmed, [0054]
  • Although the five embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, with respect to the mount style of the semiconductor chip on the relay board, it is described in the above that the semiconductor chip which is adhesively attached in the face-up style is connected to the conductive pattern by the wire bonding. However, the semiconductor chip may be mounted in a face-down style by using leads or soldering balls. Besides, suitable modifications, selections and combinations may be made on the dimension and shape of the lands, the arrangement of the lands at the semiconductor package side or the mount board side and the details of the constituent materials of the respective parts, etc. [0055]

Claims (4)

What is claimed is:
1. A semiconductor package comprising:
a semiconductor chip having input or output terminals;
a relay board having;
package side lands being arranged on a principal plane thereof in association with said respective input or output terminals of said semiconductor chip, and;
a solder resist layer mutually insulating said package side lands adjacent to each other from each other and having openings having a larger area than the surface area of said package side lands so as to wholly expose each of said package side lands.
2. A mount board comprising:
a base member;
board side lands being disposed on one principal plane of said base member in the same arrangement as package side lands of a semiconductor package to be mounted thereon: and
a solder resist layer mutually insulating said board side lands adjacent to each other from each other and having openings having a larger area than the surface area of said board side lands to wholly expose each of said board side lands.
3. A mount board as claimed in claim 2, wherein the dimension and the shape of said board side lands are set to be substantially equal to those of the package side lands of said semiconductor package.
4. A mounting method comprising the steps of:
providing a semiconductor package having a semiconductor chip having input or output terminals and a relay board having package side lands corresponding to said input or output terminals and being arranged on a principal plane thereof and a mount board having board side lands corresponding to said package side lands on a principal plane thereof, whereby at least one of said package side lands and said board side lands is wholly exposed in an opening of a solder resist layer having an opening area larger than the area of the surface of said lands;
electrically connecting said package side land with said board side land through a conductive material layer.
US09/631,524 1998-04-16 2000-08-03 Semiconductor package and mount board, and mounting method using the same Abandoned US20020058356A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/631,524 US20020058356A1 (en) 1998-04-16 2000-08-03 Semiconductor package and mount board, and mounting method using the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP10-106424 1998-04-16
JP10106424A JPH11297889A (en) 1998-04-16 1998-04-16 Semiconductor package, mounting board and mounting method by use of them
US09/292,133 US6469393B2 (en) 1998-04-16 1999-04-14 Semiconductor package and mount board
US09/631,524 US20020058356A1 (en) 1998-04-16 2000-08-03 Semiconductor package and mount board, and mounting method using the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/292,133 Division US6469393B2 (en) 1998-04-16 1999-04-14 Semiconductor package and mount board

Publications (1)

Publication Number Publication Date
US20020058356A1 true US20020058356A1 (en) 2002-05-16

Family

ID=14433289

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/292,133 Expired - Fee Related US6469393B2 (en) 1998-04-16 1999-04-14 Semiconductor package and mount board
US09/631,524 Abandoned US20020058356A1 (en) 1998-04-16 2000-08-03 Semiconductor package and mount board, and mounting method using the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/292,133 Expired - Fee Related US6469393B2 (en) 1998-04-16 1999-04-14 Semiconductor package and mount board

Country Status (3)

Country Link
US (2) US6469393B2 (en)
EP (1) EP0957520A3 (en)
JP (1) JPH11297889A (en)

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040253845A1 (en) * 2003-06-11 2004-12-16 Brown Dirk D. Remountable connector for land grid array packages
US20040252477A1 (en) * 2003-06-11 2004-12-16 Brown Dirk D. Contact grid array formed on a printed circuit board
US20040253875A1 (en) * 2003-06-11 2004-12-16 Epic Technology Inc. Circuitized connector for land grid array
US20040253846A1 (en) * 2003-06-11 2004-12-16 Epic Technology Inc. Land grid array connector including heterogeneous contact elements
US20050208788A1 (en) * 2004-03-19 2005-09-22 Dittmann Larry E Electrical connector in a flexible host
US20050208786A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer and method for making same
US20050208787A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer with compliant pins
US20050227510A1 (en) * 2004-04-09 2005-10-13 Brown Dirk D Small array contact with precision working range
US20060000642A1 (en) * 2004-07-01 2006-01-05 Epic Technology Inc. Interposer with compliant pins
US7056131B1 (en) 2003-04-11 2006-06-06 Neoconix, Inc. Contact grid array system
US20060258182A1 (en) * 2004-07-20 2006-11-16 Dittmann Larry E Interposer with compliant pins
US20060276059A1 (en) * 2003-04-11 2006-12-07 Neoconix Inc. System for connecting a camera module, or like device, using flat flex cables
US20070054515A1 (en) * 2003-04-11 2007-03-08 Williams John D Method for fabricating a contact grid array
US20070134949A1 (en) * 2005-12-12 2007-06-14 Dittmann Larry E Connector having staggered contact architecture for enhanced working range
US20070141863A1 (en) * 2003-04-11 2007-06-21 Williams John D Contact grid array system
US7280653B2 (en) 2002-07-01 2007-10-09 Nec Infrontia Corporation Telephone system for making call to telephone number read from a sheet
US20080045076A1 (en) * 2006-04-21 2008-02-21 Dittmann Larry E Clamp with spring contacts to attach flat flex cable (FFC) to a circuit board
US20100037761A1 (en) * 2004-04-16 2010-02-18 Bae Systems Survivability Systems, Llc Lethal Threat Protection System For A Vehicle And Method
US7758351B2 (en) 2003-04-11 2010-07-20 Neoconix, Inc. Method and system for batch manufacturing of spring elements
US7989945B2 (en) 2003-12-08 2011-08-02 Neoconix, Inc. Spring connector for making electrical contact at semiconductor scales
JP2012256672A (en) * 2011-06-08 2012-12-27 Panasonic Corp Mounting structure of semiconductor component
US8641428B2 (en) 2011-12-02 2014-02-04 Neoconix, Inc. Electrical connector and method of making it
US9680273B2 (en) 2013-03-15 2017-06-13 Neoconix, Inc Electrical connector with electrical contacts protected by a layer of compressible material and method of making it

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4239310B2 (en) * 1998-09-01 2009-03-18 ソニー株式会社 Manufacturing method of semiconductor device
WO2001097580A1 (en) * 2000-06-12 2001-12-20 Hitachi, Ltd. Electronic device and method of manufacturing the electronic device
US6552436B2 (en) * 2000-12-08 2003-04-22 Motorola, Inc. Semiconductor device having a ball grid array and method therefor
JP2002217377A (en) 2001-01-18 2002-08-02 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing the same
JP2002252311A (en) * 2001-02-26 2002-09-06 Kyocera Corp Board for mounting electronic component
JP4623852B2 (en) * 2001-03-29 2011-02-02 京セラ株式会社 Electronic component mounting board
DE10148120B4 (en) * 2001-09-28 2007-02-01 Infineon Technologies Ag Electronic components with semiconductor chips and a system carrier with component positions and method for producing a system carrier
JP2004165279A (en) * 2002-11-11 2004-06-10 Mitsui Mining & Smelting Co Ltd Film carrier tape for mounting electronic component
US6953893B1 (en) * 2004-03-31 2005-10-11 Infineon Technologies Ag Circuit board for connecting an integrated circuit to a support and IC BGA package using same
US20060049238A1 (en) * 2004-09-03 2006-03-09 Lim Seong C Solderable structures and methods for soldering
US20060055032A1 (en) * 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
KR100783102B1 (en) 2005-01-14 2007-12-07 삼성전자주식회사 structure and method of joining semiconductor package to substrate using solder column
US20070018308A1 (en) * 2005-04-27 2007-01-25 Albert Schott Electronic component and electronic configuration
US7183652B2 (en) * 2005-04-27 2007-02-27 Infineon Technologies Ag Electronic component and electronic configuration
KR101134168B1 (en) * 2005-08-24 2012-04-09 삼성전자주식회사 Semiconductor chip and manufacturing method thereof, display panel using the same and manufacturing method thereof
TW200711154A (en) * 2005-09-08 2007-03-16 Advanced Semiconductor Eng Flip-chip packaging process
JP4707548B2 (en) * 2005-12-08 2011-06-22 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of semiconductor device
US7759782B2 (en) * 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
US7592702B2 (en) * 2006-07-31 2009-09-22 Intel Corporation Via heat sink material
JP2008210993A (en) * 2007-02-26 2008-09-11 Nec Corp Printed wiring board and method of manufacturing the same
JP5073351B2 (en) * 2007-04-12 2012-11-14 日本電波工業株式会社 Electronic devices for surface mounting
JP5331371B2 (en) 2007-04-24 2013-10-30 パナソニック株式会社 Electronic component package, circuit board, electronic component mounting apparatus, and method for inspecting junctions thereof
JP4986738B2 (en) * 2007-06-27 2012-07-25 新光電気工業株式会社 Semiconductor package and semiconductor device using the same
JP5053919B2 (en) * 2008-03-07 2012-10-24 パナソニック株式会社 Mounting structure for surface mount devices
JP4706709B2 (en) * 2008-03-07 2011-06-22 オムロン株式会社 One-part epoxy resin composition and use thereof
CN102142411B (en) * 2010-02-01 2012-12-12 华为终端有限公司 Chip packaging component of printed circuit board assembly (PCBA) and welding component
JP5290215B2 (en) * 2010-02-15 2013-09-18 ルネサスエレクトロニクス株式会社 Semiconductor device, semiconductor package, interposer, and manufacturing method of interposer
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
US8844125B2 (en) * 2011-01-14 2014-09-30 Harris Corporation Method of making an electronic device having a liquid crystal polymer solder mask and related devices
JP5776373B2 (en) * 2011-06-29 2015-09-09 株式会社デンソー Electronic equipment
DE202011103481U1 (en) * 2011-07-20 2012-10-25 Wilo Se Rollover protection for an arrangement of a semiconductor device on a substrate
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
CN205944139U (en) 2016-03-30 2017-02-08 首尔伟傲世有限公司 Ultraviolet ray light -emitting diode spare and contain this emitting diode module
JP6772232B2 (en) * 2018-10-03 2020-10-21 キヤノン株式会社 Printed circuit boards and electronic devices
JP7155214B2 (en) * 2020-09-28 2022-10-18 キヤノン株式会社 Printed circuit boards and electronics

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US248A (en) * 1837-06-30 Lamps and lamp-torches
US5024372A (en) * 1989-01-03 1991-06-18 Motorola, Inc. Method of making high density solder bumps and a substrate socket for high density solder bumps
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03504064A (en) 1989-01-03 1991-09-05 モトローラ・インコーポレーテッド Manufacturing method for high-density solder bumps and substrate sockets for high-density solder bumps
JP2586797B2 (en) 1993-09-03 1997-03-05 日本電気株式会社 Manufacturing method of printed wiring board
JP3138159B2 (en) * 1994-11-22 2001-02-26 シャープ株式会社 Semiconductor device, semiconductor device package, and semiconductor device replacement method
JP3353508B2 (en) 1994-12-20 2002-12-03 ソニー株式会社 Printed wiring board and electronic device using the same
KR0157284B1 (en) 1995-05-31 1999-02-18 김광호 Printed circuit board of solder ball take-on groove furnished and this use of package ball grid array
DE69636212T2 (en) 1995-06-06 2007-04-05 Ibiden Co., Ltd., Ogaki PRINTED CIRCUIT BOARD
US5973931A (en) * 1996-03-29 1999-10-26 Sony Corporation Printed wiring board and electronic device using same
JP3431406B2 (en) * 1996-07-30 2003-07-28 株式会社東芝 Semiconductor package equipment
JP3679199B2 (en) * 1996-07-30 2005-08-03 日本テキサス・インスツルメンツ株式会社 Semiconductor package equipment
JPH10294418A (en) * 1997-04-21 1998-11-04 Oki Electric Ind Co Ltd Semiconductor device
JPH11121688A (en) * 1997-10-15 1999-04-30 Mitsui High Tec Inc Composite type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US248A (en) * 1837-06-30 Lamps and lamp-torches
US5024372A (en) * 1989-01-03 1991-06-18 Motorola, Inc. Method of making high density solder bumps and a substrate socket for high density solder bumps
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7280653B2 (en) 2002-07-01 2007-10-09 Nec Infrontia Corporation Telephone system for making call to telephone number read from a sheet
US7758351B2 (en) 2003-04-11 2010-07-20 Neoconix, Inc. Method and system for batch manufacturing of spring elements
US20060276059A1 (en) * 2003-04-11 2006-12-07 Neoconix Inc. System for connecting a camera module, or like device, using flat flex cables
US20070141863A1 (en) * 2003-04-11 2007-06-21 Williams John D Contact grid array system
US20060189179A1 (en) * 2003-04-11 2006-08-24 Neoconix Inc. Flat flex cable (FFC) with embedded spring contacts for connecting to a PCB or like electronic device
US20070054515A1 (en) * 2003-04-11 2007-03-08 Williams John D Method for fabricating a contact grid array
US7056131B1 (en) 2003-04-11 2006-06-06 Neoconix, Inc. Contact grid array system
US8584353B2 (en) 2003-04-11 2013-11-19 Neoconix, Inc. Method for fabricating a contact grid array
US7891988B2 (en) 2003-04-11 2011-02-22 Neoconix, Inc. System and method for connecting flat flex cable with an integrated circuit, such as a camera module
US6869290B2 (en) 2003-06-11 2005-03-22 Neoconix, Inc. Circuitized connector for land grid array
US6916181B2 (en) 2003-06-11 2005-07-12 Neoconix, Inc. Remountable connector for land grid array packages
US7070419B2 (en) 2003-06-11 2006-07-04 Neoconix Inc. Land grid array connector including heterogeneous contact elements
US20040253846A1 (en) * 2003-06-11 2004-12-16 Epic Technology Inc. Land grid array connector including heterogeneous contact elements
US20040253845A1 (en) * 2003-06-11 2004-12-16 Brown Dirk D. Remountable connector for land grid array packages
US20040253875A1 (en) * 2003-06-11 2004-12-16 Epic Technology Inc. Circuitized connector for land grid array
US20040252477A1 (en) * 2003-06-11 2004-12-16 Brown Dirk D. Contact grid array formed on a printed circuit board
US7989945B2 (en) 2003-12-08 2011-08-02 Neoconix, Inc. Spring connector for making electrical contact at semiconductor scales
US20060211296A1 (en) * 2004-03-19 2006-09-21 Dittmann Larry E Electrical connector in a flexible host
US20050208788A1 (en) * 2004-03-19 2005-09-22 Dittmann Larry E Electrical connector in a flexible host
US7645147B2 (en) 2004-03-19 2010-01-12 Neoconix, Inc. Electrical connector having a flexible sheet and one or more conductive connectors
US20050208787A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer with compliant pins
US20050208786A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Interposer and method for making same
US20050227510A1 (en) * 2004-04-09 2005-10-13 Brown Dirk D Small array contact with precision working range
US20100037761A1 (en) * 2004-04-16 2010-02-18 Bae Systems Survivability Systems, Llc Lethal Threat Protection System For A Vehicle And Method
US20060000642A1 (en) * 2004-07-01 2006-01-05 Epic Technology Inc. Interposer with compliant pins
US20060258182A1 (en) * 2004-07-20 2006-11-16 Dittmann Larry E Interposer with compliant pins
US20070134949A1 (en) * 2005-12-12 2007-06-14 Dittmann Larry E Connector having staggered contact architecture for enhanced working range
US20080045076A1 (en) * 2006-04-21 2008-02-21 Dittmann Larry E Clamp with spring contacts to attach flat flex cable (FFC) to a circuit board
JP2012256672A (en) * 2011-06-08 2012-12-27 Panasonic Corp Mounting structure of semiconductor component
US8641428B2 (en) 2011-12-02 2014-02-04 Neoconix, Inc. Electrical connector and method of making it
US9680273B2 (en) 2013-03-15 2017-06-13 Neoconix, Inc Electrical connector with electrical contacts protected by a layer of compressible material and method of making it

Also Published As

Publication number Publication date
US20010054753A1 (en) 2001-12-27
EP0957520A3 (en) 2001-10-31
JPH11297889A (en) 1999-10-29
US6469393B2 (en) 2002-10-22
EP0957520A2 (en) 1999-11-17

Similar Documents

Publication Publication Date Title
US6469393B2 (en) Semiconductor package and mount board
US5594275A (en) J-leaded semiconductor package having a plurality of stacked ball grid array packages
KR100206893B1 (en) Package &amp; the manufacture method
US7595227B2 (en) Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US5786239A (en) Method of manufacturing a semiconductor package
US5636104A (en) Printed circuit board having solder ball mounting groove pads and a ball grid array package using such a board
US6734557B2 (en) Semiconductor device
US6736306B2 (en) Semiconductor chip package comprising enhanced pads
JP3294740B2 (en) Semiconductor device
US6849945B2 (en) Multi-layered semiconductor device and method for producing the same
US6486551B1 (en) Wired board and method of producing the same
KR20050022336A (en) Semiconductor device
US8067698B2 (en) Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same
US20050054187A1 (en) Method for forming ball pads of BGA substrate
US6379996B1 (en) Package for semiconductor chip having thin recess portion and thick plane portion
JP3370498B2 (en) Substrate for semiconductor device
JP2943788B2 (en) Wiring board for mounting electronic components
US6730539B2 (en) Method of manufacturing semiconductor device package
JP2768315B2 (en) Semiconductor device
KR100199286B1 (en) Chip-scale package having pcb formed with recess
JP3297959B2 (en) Semiconductor device
JP2652222B2 (en) Substrate for mounting electronic components
JP3398556B2 (en) Method for manufacturing semiconductor device
KR100247641B1 (en) Package and method of manufacturing the same
KR20070019359A (en) Two sided mount type substrate having window for encapsulating and method for manufacturing a multi-chip package using the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION