US20020045350A1 - Composition for polishing a semiconductor device and process for manufacturing a semiconductor device using the same - Google Patents

Composition for polishing a semiconductor device and process for manufacturing a semiconductor device using the same Download PDF

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US20020045350A1
US20020045350A1 US09/953,127 US95312701A US2002045350A1 US 20020045350 A1 US20020045350 A1 US 20020045350A1 US 95312701 A US95312701 A US 95312701A US 2002045350 A1 US2002045350 A1 US 2002045350A1
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polishing
semiconductor device
silicon
atom
silicon nitride
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Takanori Kido
Kagetaka Ichikawa
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Showa Denko Materials Co Ltd
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Showa Denko KK
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    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09KMATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00Materials not provided for elsewhere
    • C09K3/14Anti-slip materials; Abrasives
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09KMATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00Materials not provided for elsewhere
    • C09K3/14Anti-slip materials; Abrasives
    • C09K3/1454Abrasive powders, suspensions and pastes for polishing
    • C09K3/1463Aqueous liquid suspensions

Definitions

  • the present invention relates to an abrasive composition for polishing a semiconductor device, more specifically, to an abrasive composition for use in element isolation of a semiconductor device by the shallow trench isolation process, as well as a process for manufacturing a semiconductor device using said abrasive composition.
  • a silicon nitride layer is formed as a lower layer of the oxide layer to be polished, the silicone nitride layer is used as the stopper in the polishing, the surface to be planarized is polished to give uniform and exact removed thickness, and the polishing is finished when a predetermined thickness removed is reached.
  • JP-A -9-194823 describes a composition using silicon nitride, silicon carbide or graphite as the particulate abrasive and JP-A-9-208933 describes an abrasive composition comprising silicone nitride fine powder having added thereto an acid such as gluconic acid.
  • abrasive compositions contain an abrasive having high hardness and certainly ensure a high polishing rate, however, they are disadvantageous in that many scratches are generated on the polished surface and give rise to reduction in the performance of the semiconductor device.
  • the above-described techniques are insufficient in the “selectivity ratio” which is a value obtained by dividing the polishing rate for an oxide layer by the polishing rate for a silicon nitride layer and shows how easy the oxide layer, in many cases, silicon dioxide layer is polished as compared with the silicon nitride stopper layer.
  • the selection ratio is a value obtained by dividing the polishing rate for an oxide layer by the polishing rate for a silicon nitride layer and shows how easy the oxide layer, in many cases, silicon dioxide layer is polished as compared with the silicon nitride stopper layer.
  • the object of the present invention is to provide an abrasive composition for polishing a semiconductor device, which can overcome the above-described problems.
  • Another object of the present invention is to provide a semiconductor device, which have solved the above-described problems.
  • an abrasive composition for polishing a semiconductor device in the shallow trench isolation process said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a —COOH group, a —COOM x group (wherein M x is an atom or functional group capable of displacing a H atom to form a salt), a —SO 3 H group and a —SO 3 M y group (wherein M y represents an atom or functional group capable of displacing a H atom to form a salt).
  • the abrasive composition for manufacturing a semiconductor device of the present invention (2) wherein the concentration of cerium oxide in the abrasive composition is from 0.1 to 10 wt % and the amount of the water-soluble organic compound added, in terms of the weight ratio to the cerium oxide, is from 0.001 to 20, and (3) wherein when a silicon nitride layer and a silicon oxide layer separately formed on a silicon substrate by the CVD method are independently polished under the same conditions, the ratio of the polishing rate for the former to that for the latter is 10 or more, the scratches on the polished surface can be significantly reduced and the value of the selectivity ratio can significantly increase.
  • the present invention also provide a process for manufacturing a semiconductor device, comprising the steps of
  • planalization-polishing is performed by using an abrasive composition for polishing a semiconductor device, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a —COOH group, —COOM x group (wherein M x is an atom or functional group capable of replacing a H atom to form a salt), a —SO 3 H group or a —SO 3 M x group (wherein M y is an atom or functional group capable of replacing a H atom to form a salt).
  • shallow trench isolation can be formed with reduced scratches on the polished surface and with a high controllability.
  • FIGS. 1 - 4 are cross-sectional views of a semiconductor device in the order of the steps for illustrating a process for forming a shallow trench isolation.
  • the cerium oxide fine powder used in the present invention is preferably in a high purity, specifically, the purity is preferably 99 wt % or more, more preferably 99.9 wt % or more. If the purity is less than this range, it is difficult to remove the impurity elements having adverse effects on the properties of the semiconductor from the surface of the semiconductor device even if the semiconductor device after the polishing is cleaned, as a result, defectives increase and the yield disadvantageously decreases.
  • the average particle size of the cerium oxide fine powder is preferably from 0.01 to 1.0 ⁇ m, more preferably from 0.1 to 0.5 ⁇ m. If the average particle size is less than 0.01 ⁇ m, the polishing rate for the oxide layer, in many cases, silicon dioxide layer, is reduced, whereas if it exceeds 1.0 ⁇ m, fine scratches are readily generated on the polished surface.
  • the primary particle size of cerium oxide is preferably from 0.005 to 0.5 ⁇ m, more preferably from 0.02 to 0.2 ⁇ m. If the primary particle size is less than 0.005 ⁇ m, the polishing rate for the oxide layer is extremely reduced and a sufficiently large selection ratio cannot be attained, whereas if it exceeds 0.5 ⁇ m, fine scratches are readily generated on the polished surface.
  • the concentration of cerium oxide (fine powder) in the abrasive composition of the present invention depends on the polishing conditions such as working pressure, however, it is preferably from 0.1 to 10 wt %, more preferably from 0.3 to 5 wt %. If the concentration is less than 0.1 wt %, the polishing rate for the oxide layer is reduced, whereas even if it exceeds 10 wt %, improvement in the effect, namely, improvement of the polishing rate for the oxide layer is not enhanced by the increase in the concentration and profitability disadvantageously decreases.
  • M x is an atom or functional group capable of displacing a H atom to form a salt
  • M y is an atom or functional group capable of displacing a H atom to form a salt.
  • an alkali metal is preferably not contained.
  • the water-soluble organic compound for use in the present invention is not particularly limited as far as it has at least one of the above-described groups.
  • the water-soluble organic compound may be used alone or in combination.
  • polyacrylic acid ((—CH 2 CHCOOH—) n , molecular weight: 500-10000), polymethacrylic acid ((—CH 2 CCH 3 COOH—) n , molecular weight: 500-10000), ammonium salts thereof, naphthalenesulfric acid-formalin condensate (the following formula:
  • the amount of the water-soluble organic compound added varies depending on the kind of the compound, the concentration of the cerium oxide fine powder in the composition of the present invention, the pH value of the composition or the polishing conditions such as working pressure, however, it is preferably in terms of the weight ratio to the cerium oxide, from 0.001 to 20, more preferably from 0.005 to 10, still more preferably from 0.005 to 5.
  • the weight ratio is less than 0.1, the amount of the water-soluble organic compound adsorbing to the surface of the silicon nitride layer is small as compared with the abrasive grain working in the polishing process and a poor adsorption layer is formed, as a result, the effect of preventing the direct contact of the cerium oxide fine powder with the silicon nitride layer is not sufficiently large and the polishing rate for the silicon nitride layer cannot be reduced, whereas even if it exceeds 20, the effect is no more enhanced by the increase in the amount and profitability disadvantageously decreases.
  • the pH should can be controlled if necessary since it has an influence to the polishing rates of both the silicon dioxide layer and the silicon nitride. If the pH is to be lowered, inorganic acids such as nitric acid, hydrochloric acid and sulfric acid, organic acids such as malic acid, lactic acid, tartaric acid, gluconic acid, citric acid monohydrate, succinic acid, adipic acid and fumaric acid, and acidic amino acids such as aspartic acid and glutamic acid may be used.
  • inorganic acids such as nitric acid, hydrochloric acid and sulfric acid
  • organic acids such as malic acid, lactic acid, tartaric acid, gluconic acid, citric acid monohydrate, succinic acid, adipic acid and fumaric acid
  • acidic amino acids such as aspartic acid and glutamic acid
  • ammonia amines such as ethanolamine
  • neutral or basic amino acids such as glycine, 4-aminobutyric acid, 6-aminohexanoic acid, 12-aminolauric acid, argiric acid and glycylglycine may be used.
  • the pH of 4 or more is preferable in some cases but the pH of less than 4 may be used.
  • the abrasive composition of the present invention may further contain an abrasive other than cerium oxide, and additives commonly used in abrasive compositions, such as a viscosity adjusting agent, a buffer, a surface active agent and a chelating agent.
  • an abrasive other than cerium oxide such as a viscosity adjusting agent, a buffer, a surface active agent and a chelating agent.
  • the abrasive composition of the present invention is characterized by a high selectivity in the polishing rate between silicon oxide and silicon nitride and the selectivity ratio can be at least 10, preferably 30 or more and more preferably 50 or more. In addition, it is characterized by great decrease in scratches to the polished surface.
  • FIG. 1 the surface of a semiconductor substrate such as silicon is oxidized to form a thin silicon oxide layer 2, on which a silicon nitride layer 3 is deposited, at a thickness of, for example, 200 nm by CVD.
  • a photoresist for example, openings 3 with a width of, for example, 500-5000 nm is formed on the silicon nitride layer at locations where trenches are to be formed.
  • the semiconductor substrate 1 is subjected to selective etching to form shallow trenches having a depth of, for example, 500 nm.
  • Silicon oxide 5 is deposited on the entire surface of the semiconductor substrate 1 having thereon the silicon nitride layer 3 , for example, by the bias CVD method which allow an excellent filling property, so that the trenches 4 can be completely filled with the silicon oxide 5 (FIG. 2).
  • the surface of the silicon oxide layer 5 is gradually polished as a planar surface in spite of the presence of the recess portions on the trenches 4 .
  • the polished surface reaches the surface of the silicon nitride layer 3 , before which the surface becomes completely planar and the recesses on the trenches disappear.
  • the polishing is finished at the stage when the surface of the silicon nitride layer 3 is exposed.
  • the shallow trench isolations 5 are formed as shown in FIG. 3.
  • the silicon nitride layer 3 may be used as an insulating layer on the semiconductor device, but is usually removed as shown in FIG. 4.
  • the ratio of the polishing ratio of silicon oxide to silicon nitride i.e., the selectivity ratio, should be high in order to effectively polish the silicon oxide and to ensure stopping of polishing at the location of the silicon nitride. Also, it is not desired if there are scratches on the polished surface since they may cause deterioration of the characteristics of the semiconductor device.
  • the abrasive composition of the present invention described before was developed to provide a most adequate composition for the planalization-polishing.
  • the abrasive composition of the present invention at least 10, preferably 50 or more, even 60 or more of said selectivity ratio can be obtained, by which highly controlled planalization-polishing can be made and prevention of scratches on the polished surface can be also attained.
  • the method of carrying out of the polishing using the abrasive composition of the present invention may be any known polishing method or mechanochemical polishing method.
  • silicon dioxide layer (thickness: about 1 ⁇ m) formed on a silicon wafer having a diameter of 6” and a thickness of 625 ⁇ m by the CVD method
  • Pad two layer-type pad for polishing a semiconductor device (IC1000/Suba400, manufactured by Rhodel-Nitta KK)
  • Polishing Machine [0050]
  • Polishing rate light interference-type layer thickness measuring apparatus
  • the polishing rate for the silicon dioxide layer was high and 5,050 ⁇ /min and the polishing rate for the silicon nitride layer was extremely low and 77 ⁇ /min. Accordingly, the selectivity ratio was as high as 66.
  • a slurry of 10 wt % was prepared by diluting a silica slurry (SC-1, produced by Cabot KK, 30 wt %) and evaluated on the polishing performance. The results are shown in Table 3.
  • a slurry of 1 wt % was prepared by diluting the same cerium oxide as used in Example 1. The water-soluble organic compound was not added. The polishing test was performed in the same manner as in Example 1 and the results are shown in Table 3.
  • the abrasive composition for polishing a semiconductor device of the present invention is high in the polishing rate for silicon dioxide as the oxide layer, has a large selectivity ratio to the polishing rate for silicon nitride layer, and is reduced in scratches generated on the polished surface, hence, is suited as a composition for polishing a semiconductor device, used in polishing the oxide layer, in many cases, silicon dioxide layer, with a silicon nitride layer as the stopper.

Abstract

An abrasive composition for polishing a semiconductor device, comprising cerium oxide, a water-soluble organic compound having at least one group of —COOH, —COOMx (wherein Mx is an atom or a functional group capable of substituting a H atom to form a salt), —SO3H or —SO3Mx, (wherein My is an atom or a functional group capable of substituting a H atom to form a salt), and water a process for forming shallow trench isolations using this abrasive composition.

Description

    TECHNICAL FIELD
  • The present invention relates to an abrasive composition for polishing a semiconductor device, more specifically, to an abrasive composition for use in element isolation of a semiconductor device by the shallow trench isolation process, as well as a process for manufacturing a semiconductor device using said abrasive composition. [0001]
  • BACKGROUND ART
  • As a method for isolating elements of a semiconductor device, a great deal of attention is shifting from the LOCOS (Local Oxidation of Silicon) process toward a shallow trench isolation process where a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed and an oxide layer is deposited thereon and then planalized by the CMP technique using the silicon nitride layer as a stopper, as the effective element region is wide and a higher density semiconductor device can be fabricated. [0002]
  • In many of the shallow trench isolation processes, a silicon nitride layer is formed as a lower layer of the oxide layer to be polished, the silicone nitride layer is used as the stopper in the polishing, the surface to be planarized is polished to give uniform and exact removed thickness, and the polishing is finished when a predetermined thickness removed is reached. [0003]
  • As the abrasive composition used to this effect, JP-A -9-194823 describes a composition using silicon nitride, silicon carbide or graphite as the particulate abrasive and JP-A-9-208933 describes an abrasive composition comprising silicone nitride fine powder having added thereto an acid such as gluconic acid. [0004]
  • These abrasive compositions contain an abrasive having high hardness and certainly ensure a high polishing rate, however, they are disadvantageous in that many scratches are generated on the polished surface and give rise to reduction in the performance of the semiconductor device. [0005]
  • Furthermore, the above-described techniques are insufficient in the “selectivity ratio” which is a value obtained by dividing the polishing rate for an oxide layer by the polishing rate for a silicon nitride layer and shows how easy the oxide layer, in many cases, silicon dioxide layer is polished as compared with the silicon nitride stopper layer. Thus, there is a need to increase the selection ratio. [0006]
  • The object of the present invention is to provide an abrasive composition for polishing a semiconductor device, which can overcome the above-described problems. [0007]
  • Another object of the present invention is to provide a semiconductor device, which have solved the above-described problems. [0008]
  • DISCLOSURE OF THE INVENTION
  • As a result of extensive investigations to solve those problems, the present inventors have found (1) an abrasive composition for polishing a semiconductor device in the shallow trench isolation process, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a —COOH group, a —COOM[0009] x group (wherein Mx is an atom or functional group capable of displacing a H atom to form a salt), a —SO3H group and a —SO3My group (wherein My represents an atom or functional group capable of displacing a H atom to form a salt).
  • Preferably, by using the abrasive composition for manufacturing a semiconductor device of the present invention, (2) wherein the concentration of cerium oxide in the abrasive composition is from 0.1 to 10 wt % and the amount of the water-soluble organic compound added, in terms of the weight ratio to the cerium oxide, is from 0.001 to 20, and (3) wherein when a silicon nitride layer and a silicon oxide layer separately formed on a silicon substrate by the CVD method are independently polished under the same conditions, the ratio of the polishing rate for the former to that for the latter is 10 or more, the scratches on the polished surface can be significantly reduced and the value of the selectivity ratio can significantly increase. [0010]
  • The present invention also provide a process for manufacturing a semiconductor device, comprising the steps of [0011]
  • forming a silicon nitride layer on a semiconductor substrate, [0012]
  • selectively removing a portion of said silicon nitride layer to expose said semiconductor substrate, [0013]
  • ething said semiconductor substrate using said silicon nitride layer as a mask to form a trench, [0014]
  • depositing a silicon oxide layer on said silicon nitride layer and said semiconductor substrate to completely fill said trench with the silicon oxide layer, and [0015]
  • planalization-polishing said silicon oxide layer using said silicon nitride layer as a stopper to selectively remain said silicon oxide in said trench, [0016]
  • wherein said planalization-polishing is performed by using an abrasive composition for polishing a semiconductor device, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a —COOH group, —COOM[0017] x group (wherein Mx is an atom or functional group capable of replacing a H atom to form a salt), a —SO3H group or a —SO3Mx group (wherein My is an atom or functional group capable of replacing a H atom to form a salt).
  • In this process, shallow trench isolation can be formed with reduced scratches on the polished surface and with a high controllability.[0018]
  • BRIEF DESCRIPTION OF THE INVENTION
  • FIGS. [0019] 1-4 are cross-sectional views of a semiconductor device in the order of the steps for illustrating a process for forming a shallow trench isolation.
  • BEST MODES FOR CARRYING OUT THE INVENTION
  • The abrasive composition for polishing a semiconductor device of the present invention is first described. [0020]
  • The cerium oxide fine powder used in the present invention is preferably in a high purity, specifically, the purity is preferably 99 wt % or more, more preferably 99.9 wt % or more. If the purity is less than this range, it is difficult to remove the impurity elements having adverse effects on the properties of the semiconductor from the surface of the semiconductor device even if the semiconductor device after the polishing is cleaned, as a result, defectives increase and the yield disadvantageously decreases. [0021]
  • The average particle size of the cerium oxide fine powder is preferably from 0.01 to 1.0 μm, more preferably from 0.1 to 0.5 μm. If the average particle size is less than 0.01 μm, the polishing rate for the oxide layer, in many cases, silicon dioxide layer, is reduced, whereas if it exceeds 1.0 μm, fine scratches are readily generated on the polished surface. [0022]
  • The primary particle size of cerium oxide is preferably from 0.005 to 0.5 μm, more preferably from 0.02 to 0.2 μm. If the primary particle size is less than 0.005 μm, the polishing rate for the oxide layer is extremely reduced and a sufficiently large selection ratio cannot be attained, whereas if it exceeds 0.5 μm, fine scratches are readily generated on the polished surface. [0023]
  • The concentration of cerium oxide (fine powder) in the abrasive composition of the present invention depends on the polishing conditions such as working pressure, however, it is preferably from 0.1 to 10 wt %, more preferably from 0.3 to 5 wt %. If the concentration is less than 0.1 wt %, the polishing rate for the oxide layer is reduced, whereas even if it exceeds 10 wt %, improvement in the effect, namely, improvement of the polishing rate for the oxide layer is not enhanced by the increase in the concentration and profitability disadvantageously decreases. [0024]
  • The water-soluble organic compound for use in the present invention is described below. [0025]
  • This is a water-soluble organic compound having at least one of —COOH group, —COOM[0026] x group (wherein Mx is an atom or functional group capable of displacing a H atom to form a salt), —SO3H group and a —SO3Mx group (wherein My is an atom or functional group capable of displacing a H atom to form a salt). In the case of a salt, an alkali metal is preferably not contained. The water-soluble organic compound for use in the present invention is not particularly limited as far as it has at least one of the above-described groups. The water-soluble organic compound may be used alone or in combination.
  • Specific preferred examples thereof include polyacrylic acid ((—CH[0027] 2CHCOOH—)n, molecular weight: 500-10000), polymethacrylic acid ((—CH2CCH3COOH—)n, molecular weight: 500-10000), ammonium salts thereof, naphthalenesulfric acid-formalin condensate (the following formula:
    Figure US20020045350A1-20020418-C00001
  • molecular weight: 500-10000), ammonium salt thereof, as well as, malic acid (HOOCCH(OH)CH[0028] 2COOH, molecular weight: 134.09), lactic acid (CH3CH(OH)COOH, molecular weight: 90.08), tartaric acid (HOOC(CHOH)3COOH, molecular weight: 150.09), gluconic acid (HOCH2(HCOH)4COOH, molecular weight: 196.16), citric acid monohydrate (HOOCCH2C(OH) (COOH)CH2COOH.H3O, molecular weight: 210.14), succinic acid (HOOC(CH2)2COOH, molecular weight: 118.09), adipic acid (HOOC(CH2)4COOH, molecular weight: 146.14), fumaric acid (HOOCCH═CHCOOH, molecular weight: 116.07) and other organic acids, ammonium salts thereof, aspartic acid (HOOCCH2CH(NH2)COOH, molecular weight: 133.10), glutamic acid (HOOCCH2CH2CH (NH2)COOH, molecular weight: 147.13) and other acidic amino acids, ammonium salts thereof, glycine (H2NCH2COOH, molecular weight: 75.07), 4-aminobutyric acid (H2N(CH2)3COOH, molecular weight: 103.12), 6-aminohexanoic acid (H2N(CH2)5COOH, molecular weight:131.17), 12-aminolauric acid (H2N(CH2)11COOH, molecular weight: 215.33), arginine (H2NC(═NH)NH(CH2)3CH(NH3)COOH, molecular weight: 174.20), glycylglycine (H2NCH2CONHCH2COOH, molecular weight: 132.12) and other neutral or basic amino acids, laurylbenzene sulfric acid (CH3(CH2)11C6H4SO3H, molecular weight: 326.50) and ammonium salt thereof, etc.
  • The amount of the water-soluble organic compound added varies depending on the kind of the compound, the concentration of the cerium oxide fine powder in the composition of the present invention, the pH value of the composition or the polishing conditions such as working pressure, however, it is preferably in terms of the weight ratio to the cerium oxide, from 0.001 to 20, more preferably from 0.005 to 10, still more preferably from 0.005 to 5. If the weight ratio is less than 0.1, the amount of the water-soluble organic compound adsorbing to the surface of the silicon nitride layer is small as compared with the abrasive grain working in the polishing process and a poor adsorption layer is formed, as a result, the effect of preventing the direct contact of the cerium oxide fine powder with the silicon nitride layer is not sufficiently large and the polishing rate for the silicon nitride layer cannot be reduced, whereas even if it exceeds 20, the effect is no more enhanced by the increase in the amount and profitability disadvantageously decreases. [0029]
  • The pH of the abrasive composition of the present invention is next described. [0030]
  • The pH should can be controlled if necessary since it has an influence to the polishing rates of both the silicon dioxide layer and the silicon nitride. If the pH is to be lowered, inorganic acids such as nitric acid, hydrochloric acid and sulfric acid, organic acids such as malic acid, lactic acid, tartaric acid, gluconic acid, citric acid monohydrate, succinic acid, adipic acid and fumaric acid, and acidic amino acids such as aspartic acid and glutamic acid may be used. If the pH is to be increased, ammonia, amines such as ethanolamine, or neutral or basic amino acids such as glycine, 4-aminobutyric acid, 6-aminohexanoic acid, 12-aminolauric acid, argiric acid and glycylglycine may be used. The pH of 4 or more is preferable in some cases but the pH of less than 4 may be used. [0031]
  • The abrasive composition of the present invention may further contain an abrasive other than cerium oxide, and additives commonly used in abrasive compositions, such as a viscosity adjusting agent, a buffer, a surface active agent and a chelating agent. [0032]
  • The abrasive composition of the present invention is characterized by a high selectivity in the polishing rate between silicon oxide and silicon nitride and the selectivity ratio can be at least 10, preferably 30 or more and more preferably 50 or more. In addition, it is characterized by great decrease in scratches to the polished surface. [0033]
  • The process for formation of shallow trench isolation in a semiconductor device using the abrasive composition is now described. [0034]
  • The drawings are referred to. As shown in FIG. 1, the surface of a semiconductor substrate such as silicon is oxidized to form a thin [0035] silicon oxide layer 2, on which a silicon nitride layer 3 is deposited, at a thickness of, for example, 200 nm by CVD. By photolithography using a photoresist, for example, openings 3 with a width of, for example, 500-5000 nm is formed on the silicon nitride layer at locations where trenches are to be formed.
  • Using the silicon nitride layer [0036] 3 with the openings as a mask, the semiconductor substrate 1 is subjected to selective etching to form shallow trenches having a depth of, for example, 500 nm.
  • [0037] Silicon oxide 5 is deposited on the entire surface of the semiconductor substrate 1 having thereon the silicon nitride layer 3, for example, by the bias CVD method which allow an excellent filling property, so that the trenches 4 can be completely filled with the silicon oxide 5 (FIG. 2).
  • If planalization-polishing using an abrasive composition is effected on this construction, the surface of the [0038] silicon oxide layer 5 is gradually polished as a planar surface in spite of the presence of the recess portions on the trenches 4. As the polishing is continued, the polished surface reaches the surface of the silicon nitride layer 3, before which the surface becomes completely planar and the recesses on the trenches disappear. The polishing is finished at the stage when the surface of the silicon nitride layer 3 is exposed. Thus, the shallow trench isolations 5 are formed as shown in FIG. 3. The silicon nitride layer 3 may be used as an insulating layer on the semiconductor device, but is usually removed as shown in FIG. 4.
  • In the planalization-polishing for formation of shallow trench isolation as described above, the ratio of the polishing ratio of silicon oxide to silicon nitride, i.e., the selectivity ratio, should be high in order to effectively polish the silicon oxide and to ensure stopping of polishing at the location of the silicon nitride. Also, it is not desired if there are scratches on the polished surface since they may cause deterioration of the characteristics of the semiconductor device. [0039]
  • The abrasive composition of the present invention described before was developed to provide a most adequate composition for the planalization-polishing. With the abrasive composition of the present invention, at least 10, preferably 50 or more, even 60 or more of said selectivity ratio can be obtained, by which highly controlled planalization-polishing can be made and prevention of scratches on the polished surface can be also attained. [0040]
  • The method of carrying out of the polishing using the abrasive composition of the present invention may be any known polishing method or mechanochemical polishing method. [0041]
  • EXAMPLES
  • The present invention is described in greater detail below by referring to the Examples, however, the present invention should not be construed as being limited thereto. [0042]
  • Example 1
  • 100 g of high-purity cerium oxide slurry (GPL-C1010, produced by Showa Denko KK, d[0043] 50=0.5 μm, primary particle size: 0.1 μm, concentration of cerium oxide having a purity of 99.9 wt % or more: 10 wt %) was mixed with 100 g of a solution obtained by dissolving 10 g of ammonium polyacrylate in water. Water was further added thereto to prepare a slurried abrasive composition in a total amount of 1,000 g. The composition obtained had a pH of 7.2, a cerium oxide concentration of 1 wt % and an ammonium polyacrylate concentration of 1 wt %. The amount of the water-soluble organic compound added, in terms of the weight ratio to the cerium oxide, was 1.0.
  • The polishing performance of this abrasive slurry for the silicon dioxide layer and for the silicon nitride layer was evaluated as follows. [0044]
  • [Polishing Conditions][0045]
  • Material Polished: [0046]
  • (1) silicon dioxide layer (thickness: about 1 μm) formed on a silicon wafer having a diameter of 6” and a thickness of 625 μm by the CVD method [0047]
  • (2) silicon nitride layer (thickness: about 0.5 μm) formed on a silicon wafer having a diameter of 6” and a thickness of 625 μm by the CVD method [0048]
  • Pad: two layer-type pad for polishing a semiconductor device (IC1000/Suba400, manufactured by Rhodel-Nitta KK) [0049]
  • Polishing Machine: [0050]
  • single side polishing machine for polishing a semiconductor device (Model SH-24, manufactured by Speedfam KK, work table diameter: 610 mm) [0051]
    Revolution number of table:  70 rpm
    Working pressure: 300 gf/cm2
    Slurry feeding rate: 100 ml/min
    Polishing time:  1 min
  • [Evaluation Item and Evaluation Method][0052]
  • Polishing rate: light interference-type layer thickness measuring apparatus [0053]
  • Scratch: optical microscope dark-field observation (3% of the wafer surface was observed at 200 magnification and the number of scratches was converted into pieces/wafer) [0054]
  • As a result of the above-described polishing test, the polishing rate for the silicon dioxide layer was high and 5,050 Å/min and the polishing rate for the silicon nitride layer was extremely low and 77 Å/min. Accordingly, the selectivity ratio was as high as 66. [0055]
  • Scratches were not observed either on the silicon dioxide layer or silicon nitride layer. [0056]
  • Examples 2 to 9
  • Slurries were prepared in the same conditions as in Example 1 except for changing the cerium oxide concentration and the ammonium polyacrylate concentration, and then, evaluated on the polishing performance in the same manner as in Example 1. The results are shown in Table 1 together with the results of Example 1. [0057]
  • Examples 10 to 15
  • Slurries were prepared using the same cerium oxide as used in Example 1 but changing the kind of the aqueous organic compound. The cerium oxide concentration and the water-soluble organic compound concentration were set to be the same and each was 1 wt %. The weight ratio therebetween was accordingly 1. The pH of each abrasive slurry was adjusted to be about 7 by adding ammonia. The polishing performance was evaluated in the same manner as in Example 1 and the results obtained are shown in Table 2. [0058]
  • Examples 16 to 23
  • Slurries were prepared using the same cerium oxide as used in Example 1 but changing the kind of the aqueous organic compound. The cerium oxide concentration and the water-soluble organic compound concentration were set to be the same and each was 1 wt %. The weight ratio therebetween was accordingly 1. The polishing performance was evaluated in the same manner as in Example 1 and the results obtained are shown in Table 3. [0059]
  • Comparative Example 1
  • A slurry of 10 wt % was prepared by diluting a silica slurry (SC-1, produced by Cabot KK, 30 wt %) and evaluated on the polishing performance. The results are shown in Table 3. [0060]
  • Comparative Example 2
  • A slurry of 1 wt % was prepared by diluting the same cerium oxide as used in Example 1. The water-soluble organic compound was not added. The polishing test was performed in the same manner as in Example 1 and the results are shown in Table 3. [0061]
  • As seen from the results, when silicon nitride layer and silicon oxide layer separately formed on a silicon substrate by the CVD method were independently polished under the same conditions, the ratio of the polishing rate for the former to that for the latter, namely, the selectivity ratio greatly exceeded 10 in the case of the present invention. [0062]
    TABLE 1
    Scratches on
    Polished Surface
    Ammonium Polishing Rate Polishing Rate (pieces/wafer)
    Cerium Oxide Polyacrylate for Silicon for Silicon Silicon Silicon
    Example Concentration Concentration Weight pH of Dioxide Layer Nitride Layer Selection Dioxide Nitride
    No. (wt %) (wt %) Ratio Slurry (Å/min) (Å/min) Ratio Layer Layer
    1 1 1 2. 7.2 5050 77 66 0 0
    2 1 0.2 0.2 7.1 5920 170 35 0 0
    3 1 0.5 0.5 7.2 5180 81 64 0 0
    4 1 2 2 7.2 3720 76 49 0 0
    5 0.5 0.2 0.4 7.4 3370 70 48 0 0
    6 0.5 0.5 1 7.2 3290 64 51 0 0
    7 0.5 1 2 7.0 3010 60 50 0 0
    8 2 2 1 7.3 6240 110 57 0 0
    9 2 4 2 7.1 5990 110 54 0 0
  • [0063]
    TABLE 2
    Scratches on
    Polished Surface
    Polishing Rate Polishing Rate (pieces/wafer)
    for Silicon for Silicon Silicon Silicon
    Example pH of Dioxide Layer Nitride Layer Selection dioxide Nitride
    No. Water-Soluble Organic Compound Slurry (Å/min) (Å/min) Ratio Layer Layer
    10 polymethacrylic acid 7.8 5280 83 64 0 0
    11 naphthalenesulfonic acid formalin 8.2 5760 98 59 0 0
    condensate
    12 malic acid 7.3 3970 91 44 0 0
    13 lactic acid 7.0 6010 120  50 0 0
    14 tartaric acid 6.2 3560 70 51 0 0
    15 laurylbenzenesulfonic acid 7.5 5040 82 61 0 0
  • [0064]
    TABLE 3
    Scratches on
    Polished Surface
    Polishing Rate Polishing Rate (pieces/wafer)
    for Silicon for Silicon Silicon Silicon
    Example pH of Dioxide Layer Nitride Layer Selection dioxide Nitride
    No. Water-Soluble Organic Compound Slurry (Å/min) (Å/min) Ratio Layer Layer
    16 aspartic acid 3.2 2210 22 100  0 0
    17 glutamic acid 3.3 3270 36 91 0 0
    18 malic acid 2.8 2550 82 31 0 0
    19 lactic acid 2.9 5010 61 82 0 0
    20 tartaric acid 3.0 2790 58 48 0 0
    21 succinic acid 3.2 4960 98 51 0 0
    22 fumaric acid 2.6 3800 77 49 0 0
    23 adipic acid 3.3 4090 91 45 0 0
  • [0065]
    TABLE 4
    Scratches on
    Polishing rate Polishing rate Polished Surface
    for Silicon for Silicon (pieces/wafer)
    Comparative Constitution of Weight pH of Dioxide Layer Nitride Layer Selection Silicon Silicon
    Example No. Compound Ratio Slurry (Å/min) (Å/min) Ratio Dioxide Layer Nitride Layer
    1 silica, 10 wt % 10.3 1610  410 3.9 0 0
    2 cerium oxide, 0 7.0 6130 1050 5.8 0 0
    1 wt %
  • Industrial Applicability [0066]
  • The abrasive composition for polishing a semiconductor device of the present invention is high in the polishing rate for silicon dioxide as the oxide layer, has a large selectivity ratio to the polishing rate for silicon nitride layer, and is reduced in scratches generated on the polished surface, hence, is suited as a composition for polishing a semiconductor device, used in polishing the oxide layer, in many cases, silicon dioxide layer, with a silicon nitride layer as the stopper. [0067]

Claims (6)

1. An abrasive composition for polishing a semiconductor device in the shallow trench isolation process, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a —COOH group, a —COOMx group (wherein Mx is an atom or functional group capable of displacing a H atom to form a salt), a —SO3H group and a —SO3My group (wherein My represents an atom or functional group capable of displacing a H atom to form a salt).
2. The abrasive composition for polishing a semiconductor device as claimed in claim 1, wherein the concentration of cerium oxide in the abrasive composition is from 0.1 to 10 wt % and the amount of the water-soluble organic compound added, in terms of the weight ratio to the cerium oxide, is from 0.001 to 20.
3. The abrasive composition for polishing a semiconductor device as claimed in claim 1, wherein when a silicon nitride layer and a silicon oxide layer separately formed on a silicon substrate by the CVD method are independently polished under the same conditions, the ratio of the polishing rate for the former to that for the latter is 10 or more.
4. A process for manufacturing a semiconductor device, comprising the steps of
forming a silicon nitride layer on a semiconductor substrate,
selectively removing a portion of said silicon nitride layer to expose said semiconductor substrate,
ething said semiconductor substrate using said silicon nitride layer as a mask to form a trench,
depositing a silicon oxide layer on said silicon nitride layer and said semiconductor substrate to completely fill said trench with the silicon oxide layer, and
planalization-polishing said silicon oxide layer using said silicon nitride layer as a stopper to selectively remain said silicon oxide in said trench,
wherein said planalization-polishing is performed by using an abrasive composition for polishing a semiconductor device, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a —COOH group, —COOMx group (wherein Mx is an atom or functional group capable of replacing a H atom to form a salt), a —SO3H group or a —SO3My group (wherein My is an atom or functional group capable of replacing a H atom to form a salt).
5. The process for manufacturing a semiconductor device as set force in claim 4, wherein the concentration of cerium oxide in the abrasive composition is from 0.1 to 10 wt % and the amount of the water-soluble organic compound added, in terms of the weight ratio to the cerium oxide, is from 0.001 to 20.
6. The process for manufacturing a semiconductor device as set forth in claim 4, wherein when a silicon nitride layer and a silicon oxide layer separately formed on a semiconductor substrate by the CVD method are independently polished under the same conditions, the ratio of the polishing rate for the former to that for the latter is 10 or more.
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Cited By (15)

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Publication number Priority date Publication date Assignee Title
US20030196386A1 (en) * 2002-04-22 2003-10-23 Jsr Corporation Aqueous dispersion for chemical mechanical polishing
EP1493789A1 (en) * 2003-07-01 2005-01-05 JSR Corporation Aqueous dispersion for chemical/mechanical polishing
US20050108947A1 (en) * 2003-11-26 2005-05-26 Mueller Brian L. Compositions and methods for chemical mechanical polishing silica and silicon nitride
US20050189322A1 (en) * 2004-02-27 2005-09-01 Lane Sarah J. Compositions and methods for chemical mechanical polishing silica and silicon nitride
US20050211952A1 (en) * 2004-03-29 2005-09-29 Timothy Mace Compositions and methods for chemical mechanical planarization of tungsten and titanium
US20050214191A1 (en) * 2004-03-29 2005-09-29 Mueller Brian L Abrasives and compositions for chemical mechanical planarization of tungsten and titanium
US20060021972A1 (en) * 2004-07-28 2006-02-02 Lane Sarah J Compositions and methods for chemical mechanical polishing silicon dioxide and silicon nitride
WO2006053096A2 (en) * 2004-11-08 2006-05-18 Applied Materials, Inc. High selectivity slurry compositions for chemical mechanical polishing
US20060196848A1 (en) * 2003-02-03 2006-09-07 Carter Phillip W Readily deinkable toners
US20070210278A1 (en) * 2006-03-08 2007-09-13 Lane Sarah J Compositions for chemical mechanical polishing silicon dioxide and silicon nitride
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Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366619B1 (en) * 1999-05-12 2003-01-09 삼성전자 주식회사 Trench isolation method, Method of manufacturing semiconductor device having trench and Semiconductor device formed thereby
JP2001055560A (en) * 1999-08-18 2001-02-27 Hitachi Chem Co Ltd Polishing agent and method for polishing substrate by using the same
CN1125862C (en) * 1999-09-20 2003-10-29 长兴化学工业股份有限公司 Composite ground in chemical machine for semiconductor processing
JP2001144046A (en) * 1999-11-12 2001-05-25 Hitachi Chem Co Ltd Metal polishing fluid and polishing method using it
US6468910B1 (en) 1999-12-08 2002-10-22 Ramanathan Srinivasan Slurry for chemical mechanical polishing silicon dioxide
US6491843B1 (en) * 1999-12-08 2002-12-10 Eastman Kodak Company Slurry for chemical mechanical polishing silicon dioxide
TW586157B (en) * 2000-04-13 2004-05-01 Showa Denko Kk Slurry composition for polishing semiconductor device, and method for manufacturing semiconductor device using the same
US6733553B2 (en) 2000-04-13 2004-05-11 Showa Denko Kabushiki Kaisha Abrasive composition for polishing semiconductor device and method for producing semiconductor device using the same
US6607967B1 (en) * 2000-11-15 2003-08-19 Lsi Logic Corporation Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate
JP5017574B2 (en) * 2001-05-25 2012-09-05 エア プロダクツ アンド ケミカルズ インコーポレイテッド Cerium oxide abrasive and method for producing substrate
US6811470B2 (en) * 2001-07-16 2004-11-02 Applied Materials Inc. Methods and compositions for chemical mechanical polishing shallow trench isolation substrates
US6677239B2 (en) 2001-08-24 2004-01-13 Applied Materials Inc. Methods and compositions for chemical mechanical polishing
US7199056B2 (en) 2002-02-08 2007-04-03 Applied Materials, Inc. Low cost and low dishing slurry for polysilicon CMP
US7677956B2 (en) 2002-05-10 2010-03-16 Cabot Microelectronics Corporation Compositions and methods for dielectric CMP
KR100457743B1 (en) * 2002-05-17 2004-11-18 주식회사 하이닉스반도체 CMP Slurry for Oxide and Formation Method of Semiconductor Device Using the Same
US7063597B2 (en) 2002-10-25 2006-06-20 Applied Materials Polishing processes for shallow trench isolation substrates
KR20040042430A (en) * 2002-11-14 2004-05-20 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device
KR100627510B1 (en) * 2002-12-30 2006-09-22 주식회사 하이닉스반도체 CMP slurry for nitride
US20060246723A1 (en) * 2002-12-31 2006-11-02 Sumitomo Mitsubishi Silicon Corporation Slurry composition for chemical mechanical polishing, method for planarization of surface of semiconductor element using the same, and method for controlling selection ratio of slurry composition
US7066801B2 (en) * 2003-02-21 2006-06-27 Dow Global Technologies, Inc. Method of manufacturing a fixed abrasive material
US6910951B2 (en) 2003-02-24 2005-06-28 Dow Global Technologies, Inc. Materials and methods for chemical-mechanical planarization
KR100570122B1 (en) * 2003-05-12 2006-04-11 학교법인 한양학원 Slurry composition for chemical mechanical polishing capable of compensating nanotopography effect and method of planarizing surface of semiconductor device using the same
KR100539983B1 (en) * 2003-05-15 2006-01-10 학교법인 한양학원 Ceria Abrasives for CMP and Methods of Fabricating the Same
JP4574140B2 (en) * 2003-08-27 2010-11-04 株式会社フジミインコーポレーテッド Polishing composition and polishing method using the same
US6964600B2 (en) * 2003-11-21 2005-11-15 Praxair Technology, Inc. High selectivity colloidal silica slurry
US7470295B2 (en) 2004-03-12 2008-12-30 K.C. Tech Co., Ltd. Polishing slurry, method of producing same, and method of polishing substrate
TWI283008B (en) * 2004-05-11 2007-06-21 K C Tech Co Ltd Slurry for CMP and method of producing the same
US20050279733A1 (en) * 2004-06-18 2005-12-22 Cabot Microelectronics Corporation CMP composition for improved oxide removal rate
TWI273632B (en) * 2004-07-28 2007-02-11 K C Tech Co Ltd Polishing slurry, method of producing same, and method of polishing substrate
US7531105B2 (en) * 2004-11-05 2009-05-12 Cabot Microelectronics Corporation Polishing composition and method for high silicon nitride to silicon oxide removal rate ratios
US7504044B2 (en) * 2004-11-05 2009-03-17 Cabot Microelectronics Corporation Polishing composition and method for high silicon nitride to silicon oxide removal rate ratios
TWI323741B (en) * 2004-12-16 2010-04-21 K C Tech Co Ltd Abrasive particles, polishing slurry, and producing method thereof
KR100641348B1 (en) * 2005-06-03 2006-11-03 주식회사 케이씨텍 Slurry for cmp and method of fabricating the same and method of polishing substrate
JP2007103514A (en) * 2005-09-30 2007-04-19 Fujimi Inc Polishing composition and method therefor
KR101028622B1 (en) * 2005-10-19 2011-04-11 히다치 가세고교 가부시끼가이샤 Cerium oxide slurry, cerium oxide polishing liquid, and method for polishing substrate by using those
EP1994112B1 (en) * 2006-01-25 2018-09-19 LG Chem, Ltd. Cmp slurry and method for polishing semiconductor wafer using the same
KR100814416B1 (en) * 2006-09-28 2008-03-18 삼성전자주식회사 High planarity slurry composition and method of chemical mechanical polishing using the same
JP2008117807A (en) * 2006-10-31 2008-05-22 Fujimi Inc Polishing composition, and polishing method
JP2008130988A (en) * 2006-11-24 2008-06-05 Fujimi Inc Polishing composition and polishing method
JP5375025B2 (en) * 2008-02-27 2013-12-25 日立化成株式会社 Polishing liquid
JP5819036B2 (en) * 2008-03-25 2015-11-18 三井金属鉱業株式会社 Cerium-based abrasive slurry
JP5104796B2 (en) * 2009-03-30 2012-12-19 日立化成工業株式会社 Abrasive and substrate polishing method using the same
WO2010139603A1 (en) 2009-06-05 2010-12-09 Basf Se RASPBERRY-TYPE METAL OXIDE NANOSTRUCTURES COATED WITH CeO2 NANOPARTICLES FOR CHEMICAL MECHANICAL PLANARIZATION (CMP)
KR101675378B1 (en) 2010-02-25 2016-11-23 삼성전자주식회사 slurry for polishing and planarizion method of insulator layer used the same
JP6196155B2 (en) 2010-09-08 2017-09-13 ビーエーエスエフ ソシエタス・ヨーロピアBasf Se Aqueous abrasive composition and method for polishing substrate materials for electrical, mechanical and optical devices
SG188459A1 (en) 2010-09-08 2013-04-30 Basf Se Aqueous polishing compositions containing n-substituted diazenium dioxidesand/or n'-hydroxy-diazenium oxide salts
WO2012032451A1 (en) 2010-09-08 2012-03-15 Basf Se Aqueous polishing composition and process for chemically mechanically polishing substrates containing silicon oxide dielectric and polysilicon films
EP2649144A4 (en) 2010-12-10 2014-05-14 Basf Se Aqueous polishing composition and process for chemically mechanically polishing substrates containing silicon oxide dielectric and polysilicon films
TWI542678B (en) 2011-05-24 2016-07-21 可樂麗股份有限公司 Erosion prevention agent for chemical mechanical polishing, slurry for chemical mechanical polishing, and chemical mechanical polishing method
JP2013084836A (en) * 2011-10-12 2013-05-09 Toshiba Corp Cmp method, and semiconductor device manufacturing method
KR20140122271A (en) * 2012-02-10 2014-10-17 바스프 에스이 Chemical mechanical polishing (cmp) composition comprising a protein
JP5893700B1 (en) * 2014-09-26 2016-03-23 花王株式会社 Polishing liquid composition for silicon oxide film
JP6582567B2 (en) * 2015-06-03 2019-10-02 日立化成株式会社 Slurry and manufacturing method thereof, and polishing method
US10421890B2 (en) * 2016-03-31 2019-09-24 Versum Materials Us, Llc Composite particles, method of refining and use thereof
WO2022113775A1 (en) * 2020-11-27 2022-06-02 花王株式会社 Polishing liquid composition for silicon oxide film

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0841443A (en) * 1994-07-26 1996-02-13 Okuno Chem Ind Co Ltd Polishing composition and polishing method
JPH08302338A (en) * 1995-05-15 1996-11-19 Sony Corp Slurry and production of semiconductor device by using same
JP3230986B2 (en) * 1995-11-13 2001-11-19 株式会社東芝 Polishing method, semiconductor device manufacturing method, and semiconductor manufacturing apparatus.
JP3514908B2 (en) 1995-11-13 2004-04-05 株式会社東芝 Abrasive
JPH09137156A (en) * 1995-11-16 1997-05-27 Mitsubishi Chem Corp Polishing composition for hard disk substrate and polishing method therewith
JPH09208933A (en) 1996-01-29 1997-08-12 Fujimi Inkooporeetetsudo:Kk Composition for polishing
EP0786504A3 (en) * 1996-01-29 1998-05-20 Fujimi Incorporated Polishing composition
US5738800A (en) 1996-09-27 1998-04-14 Rodel, Inc. Composition and method for polishing a composite of silica and silicon nitride
JPH10321570A (en) * 1997-05-15 1998-12-04 Tokuyama Corp Abrasive for polishing semiconductor wafer, its manufacture, and polishing method
JPH11181403A (en) 1997-12-18 1999-07-06 Hitachi Chem Co Ltd Cerium oxide abrasive and grinding of substrate
JPH10279928A (en) 1998-02-27 1998-10-20 Rodel Inc Compound for controlling polishing speed

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EP1535979A3 (en) * 2003-11-26 2005-09-07 Rohm and Haas Electronic Materials CMP Holdings, Inc. Compositions and methods for chemical mechanical polishing silica and silicon nitride
US20050108947A1 (en) * 2003-11-26 2005-05-26 Mueller Brian L. Compositions and methods for chemical mechanical polishing silica and silicon nitride
EP1535979A2 (en) * 2003-11-26 2005-06-01 Rohm and Haas Electronic Materials CMP Holdings, Inc. Compositions and methods for chemical mechanical polishing silica and silicon nitride
US20050189322A1 (en) * 2004-02-27 2005-09-01 Lane Sarah J. Compositions and methods for chemical mechanical polishing silica and silicon nitride
US20050214191A1 (en) * 2004-03-29 2005-09-29 Mueller Brian L Abrasives and compositions for chemical mechanical planarization of tungsten and titanium
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US20060021972A1 (en) * 2004-07-28 2006-02-02 Lane Sarah J Compositions and methods for chemical mechanical polishing silicon dioxide and silicon nitride
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US20070210278A1 (en) * 2006-03-08 2007-09-13 Lane Sarah J Compositions for chemical mechanical polishing silicon dioxide and silicon nitride
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EP2927294A1 (en) * 2014-04-04 2015-10-07 Fujifilm Planar Solutions LLC Polishing compositions and methods for selectively polishing silicon nitride over silicon oxide films
US9558959B2 (en) 2014-04-04 2017-01-31 Fujifilm Planar Solutions, LLC Polishing compositions and methods for selectively polishing silicon nitride over silicon oxide films
US9583359B2 (en) 2014-04-04 2017-02-28 Fujifilm Planar Solutions, LLC Polishing compositions and methods for selectively polishing silicon nitride over silicon oxide films
US20180086943A1 (en) * 2015-03-30 2018-03-29 Jsr Corporation Treatment composition for chemical mechanical polishing, chemical mechanical polishing method, and cleaning method

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US6410444B1 (en) 2002-06-25
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US6436835B1 (en) 2002-08-20
DE69917010T2 (en) 2005-04-07
JP3672493B2 (en) 2005-07-20
KR20010041248A (en) 2001-05-15
ES2216490T3 (en) 2004-10-16
ATE266071T1 (en) 2004-05-15
EP1061111B1 (en) 2004-05-06
WO1999043761A1 (en) 1999-09-02
EP1061111A1 (en) 2000-12-20
EP1061111A4 (en) 2001-05-30
DE69917010D1 (en) 2004-06-09

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