US20020020898A1 - Microelectronic substrates with integrated devices - Google Patents
Microelectronic substrates with integrated devices Download PDFInfo
- Publication number
- US20020020898A1 US20020020898A1 US09/884,595 US88459501A US2002020898A1 US 20020020898 A1 US20020020898 A1 US 20020020898A1 US 88459501 A US88459501 A US 88459501A US 2002020898 A1 US2002020898 A1 US 2002020898A1
- Authority
- US
- United States
- Prior art keywords
- microelectronic
- microelectronic substrate
- substrate core
- core
- microelectronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 421
- 239000000758 substrate Substances 0.000 title claims abstract description 289
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- 230000015572 biosynthetic process Effects 0.000 description 5
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- 229910052782 aluminium Inorganic materials 0.000 description 4
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- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Abstract
A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.
Description
- This is a continuation-in-part of application Ser. No. 09/692,908, filed Oct. 19, 2000, which is a continuation-in-part of application Ser. No. 09/640961, filed Aug. 16, 2000.
- 1. Field of the Invention
- The present invention relates to apparatus and processes for the fabrication of microelectronic substrates. In particular, the present invention relates to a fabrication technology that encapsulates at least one microelectronic device within a microelectronic substrate core or that encapsulates at least one microelectronic device (without a microelectronic substrate core) to form a two-sided microelectronic substrate or a two layer microelectronic substrate.
- 2. State of the Art
- Substrates which connect individual microelectronic devices exist in virtually all recently manufactured electronic equipment. These substrates are generally printed circuit boards. Printed circuit boards are basically dielectric substrates with metallic traces formed in or upon the dielectric substrate. One type of printed circuit board is a single-sided board. As shown in FIG. 23, single-
sided board 300 consists of adielectric substrate 302, such as an FR4 material, epoxy resins, polyimides, triazine resins, and the like, havingconductive traces 304, such as copper, aluminum, and the like, on one side (i.e., first surface 306), wherein theconductive traces 304 electrically interconnect microelectronic devices 308 (shown as flip-chips) attached to thefirst surface 306. However, single-sided boards 300 result in relatively longconductive traces 304, which, in turn, result in slower speeds and performance. Single-sided boards 300 also require substantial surface area for the routing of theconductive traces 304 to interconnect the variousmicroelectronic devices 308, which increases the size of the resulting assembly. - It is, of course, understood that the depiction of the
dielectric substrate 302, theconductive traces 304, and themicroelectronic devices 308 in FIG. 23 (and subsequently FIGS. 24 and 25) are merely for illustration purposes and certain dimensions are greatly exaggerated to show the concept, rather than accurate details thereof. - Double-sided
boards 310 were developed to help alleviate the problem with relatively long conductive traces. As shown in FIG. 24, the double-sided board 310 comprises adielectric substrate 302 havingconductive traces 304 on the dielectric substratefirst surface 306 and on a dielectric substratesecond surface 312. At least one electrically conductive via 314 extends through thedielectric substrate 302 to connect at least oneconductive trace 304 on thefirst surface 306 with at least oneconductive trace 304 on thesecond surface 312. Thus, themicroelectronic devices 308 on the dielectric substratefirst surface 306 and on the dielectric substratesecond surface 312 may be in electrical communication. The electricallyconductive vias 314 are generally plated through-hole vias and may be formed in any manner known in the art. - FIG. 25 illustrates another board design, known as a
multi-layer board 320. Amulti-layer board 320 comprises two or more pieces of dielectric material (shown as firstdielectric material 322 and second dielectric material 324) withconductive traces 304 thereon and therebetween with electricallyconductive vias 314 formed through the firstdielectric material 322 and the seconddielectric material 324. This design allows for shorter traces and reduced surface area requirements forconductive trace 304 routing. - Although such boards have been adequate for past and current microelectronic device applications, the need for higher performance and shorter traces of substrate boards increases as the speed and performance of the microelectronic devices increase. Therefore, it would be advantageous to develop new substrates/boards, which achieve higher speed and performance.
- While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings, in which:
- FIG. 1 is an oblique view of a microelectronic substrate core, according to the present invention;
- FIG. 2 is a top plan view of a microelectronic substrate core having examples of alternate microelectronic substrate core openings, according to the present invention;
- FIG. 3 is a side cross-sectional view of a microelectronic substrate core abutted to a protective film, according to the present invention;
- FIG. 4 is a side cross-sectional view of microelectronic devices disposed within openings of the microelectronic substrate core, which also abuts the protective film, according to the present invention;
- FIG. 5 is a side cross-sectional view of the assembly of FIG. 4 after encapsulation, according to the present invention;
- FIG. 6 is a side cross-sectional view of the assembly of FIG. 5 after the protective film has been removed, according to the present invention;
- FIG. 7 is a side cross-sectional view of multiple microelectronic devices within a single core opening;
- FIG. 8 is a side cross-sectional view of the assembly of FIG. 6 without a microelectronic substrate core, according to the present invention;
- FIG. 9 is a dual substrate assembly, according to the present invention;
- FIG. 10 illustrates the dual substrate assembly of FIG. 9 having conductive via formed therethrough, according to the present invention;
- FIG. 11 is an enlarged view of the dual substrate assembly of FIG. 10, according to the present invention;
- FIG. 12 illustrates the dual substrate assembly of FIG. 11 having interconnection layers formed on opposing surfaces thereof, according to the present invention;
- FIG. 13 illustrates the dual substrate assembly of FIG. 12 having conductive interconnects formed on the interconnection layers, according to the present invention;
- FIG. 14 is a view of FIG. 13 illustrating a plurality of the microelectronic devices encapsulated in each microelectronic substrate core, according to the present invention;
- FIG. 15 illustrates
microelectronic devices - FIG. 16 illustrates the assembly of FIG. 15 attached to an external system board through external attachment feature, according to the present invention;
- FIG. 17 illustrates the dual substrate assembly of FIG. 15 having a heat dissipation device between the first substrate and the second substrate, according to the present invention;
- FIG. 18 is a single substrate microelectronic assembly, according to the present invention;
- FIG. 19 illustrates the single substrate microelectronic assembly having heat dissipation devices attached to the back surface of the microelectronic devices encapsulated therein, according to the present invention;
- FIG. 20 illustrates multiple single substrate microelectronic assemblies of FIG. 19 interconnected to form a layered microelectronic substrate assembly, according to the present invention;
- FIG. 21 is an alternate embodiment of the layered microelectronic substrate assembly of FIG. 20, according to the present invention;
- FIG. 22 is an alternate embodiment of the layered microelectronic substrate assembly of FIG. 21, according to the present invention;
- FIG. 23 is a cross-sectional view of a single-sided board, as known in the art;
- FIG. 24 is a cross-sectional view of a double-sided board, as known in the art; and
- FIG. 25 is a cross-sectional view of a multi-layer board, as known in the art.
- In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implement within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
- The present invention includes a substrate fabrication technology that places at least one microelectronic device within at least one opening in a microelectronic substrate core and secures the microelectronic device(s) within the opening(s) with an encapsulation material or that encapsulates at least one microelectronic device within an encapsulation material without a microelectronic substrate core to form a microelectronic substrate. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device(s), the encapsulation material, and the microelectronic substrate core (if present) to form a microelectronic substrate. Two microelectronic substrates may be attached to one another either before or after the formation of the interconnection layers.
- The technical advantage of this invention is that it enables the microelectronic substrate to be built around the microelectronic device(s), which results in a shorter interconnect distance between microelectronic devices within the microelectronic substrate and other microelectronic devices attached thereto. This, in turn, results in higher speed and performance. Furthermore, the microelectronic substrate of the present invention may also result in a smaller form factor, which is well suited to mobile systems (i.e., laptop computers, handheld devices, personal digital assistants, etc.).
- FIG. 1 illustrates a
microelectronic substrate core 102 used to fabricate a microelectronic substrate. Themicroelectronic substrate core 102 preferably comprises a substantially planar material. The material used to fabricate themicroelectronic substrate core 102 may include, but is not limited to, a Bismaleimide Triazine (“BT”) resin based laminate material, an FR4 laminate material (a flame retarding glass/epoxy material), various polyimide laminate materials, ceramic material, and the like, and metallic materials (such as copper) and the like. Themicroelectronic substrate core 102 has at least oneopening 104 extending therethrough from afirst surface 106 of themicroelectronic substrate core 102 to an opposingsecond surface 108 of themicroelectronic substrate core 102. As shown in FIG. 2, the opening(s) 104 may be of any shape and size including, but not limited to, rectangular/square 104 a, rectangular/square withrounded corners 104 b, and circular 104 c. The only limitation on the size and shape of the opening(s) 104 is that they must be appropriately sized and shaped to house a corresponding microelectronic device therein, as will be discussed below. It is, of course, understood that theopenings 104 need not be in a regular array/spacing, but may be placed wherever desired within themicroelectronic substrate core 102. - FIG. 3 illustrates the microelectronic substrate core
first surface 106 abutting aprotective film 112. Theprotective film 112 is preferably a substantially flexible material, such as Kapton® polyimide film (E. I. du Pont de Nemours and Company, Wilmington, Del.), but may be made of any appropriate material, including metallic films. In a preferred embodiment, theprotective film 112 would have substantially the same coefficient of thermal expansion (CTE) as the microelectronic substrate core. FIG. 4 illustratesmicroelectronic device 114, each having anactive surface 116 and aback surface 118, placed in correspondingopenings 104 of themicroelectronic substrate core 102. Themicroelectronic device 114 may be any known active or passive microelectronic device including, but not limited to, logic (CPUs), memory (DRAM, SRAM, SDRAM, etc.), controllers (chip sets), capacitors, resistors, inductors, and the like. - In a preferred embodiment (illustrated), the
thickness 117 of themicroelectronic substrate core 102 and thethickness 115 of themicroelectronic device 114 are substantially equal. Themicroelectronic device 114 are each placed such that theiractive surfaces 116 abut theprotective film 112. Theprotective film 112 may have an adhesive, such as silicone or acrylic, which attaches to the microelectronic substrate corefirst surface 106 and the microelectronic deviceactive surface 116. This adhesive-type film may be applied prior to placing themicroelectronic device 114 andmicroelectronic substrate core 102 in a mold, liquid dispense encapsulation system (preferred), or other piece of equipment used for the encapsulation process. Theprotective film 112 may also be a non-adhesive film, such as a ETFE (ethylene-tetrafluoroethylene) or Teflon® film, which is held on the microelectronic deviceactive surface 116 and the microelectronic substrate corefirst surface 106 by an inner surface of the mold or other piece of equipment during the encapsulation process. - The
microelectronic device 114 is then encapsulated with anencapsulation material 122, such as plastics, resins, epoxies, elastomeric (i.e., rubbery) materials, and the like. As shown in FIG. 5, theencapsulation material 122 is disposed in portions of the opening(s) 104 not occupied by themicroelectronic device 114. The encapsulation of themicroelectronic device 114 may be achieved by any known process, including but not limited to transfer and compression molding, and dispensing. Theencapsulation material 122 secures themicroelectronic device 114 within themicroelectronic substrate core 102 and provides mechanical rigidity for the resulting structure and provides surface area for the subsequent build-up of trace layers. - After encapsulation, the
protective film 112 is removed, as shown in FIG. 6, to expose the microelectronic deviceactive surface 116, thereby forming afirst substrate 130. As also shown in FIG. 6, theencapsulation material 122 is preferably forms at least onesurface 124 that is substantially planar to the microelectronic deviceactive surface 116 and the microelectronic substrate corefirst surface 106. Theencapsulation material surface 124 may be utilized in further fabrication steps, along with the microelectronic substrate corefirst surface 106, as additional surface area for the formation of interconnection layers, such as dielectric material layers and conductive traces. - As shown in FIG. 7, a plurality of
microelectronic devices 114 of various sizes could be placed in each microelectronicsubstrate core opening 104 and encapsulated withencapsulation material 122. It is also understood that themicroelectronic substrate core 102 is optional. Thefirst substrate 130 could be fabricated with themicroelectronic devices 114 merely encapsulated withencapsulation material 122, as shown in FIG. 8. - FIG. 9 illustrates a
dual substrate assembly 132, according to the present invention, comprising thefirst substrate 130 attached to asecond substrate 130′. Thesecond substrate 130′ has components similar to those illustrated forfirst substrate 130 in FIG. 6, wherein like components are differentiated by a prime (′) designation. Thefirst substrate 130 and thesecond substrate 130′ are attached to one another such that the first microelectronic substrate coresecond surface 108 and the first microelectronic device back surfaces 118 are placed adjacent a second microelectronic substrate coresecond surface 108′ and a second microelectronic device backsurface 118′ to form thedual substrate assembly 132. The attachment of thefirst substrate 130 to thesecond substrate 130′ may be achieved with a layer adhesive 134, or by any attachment technique as will be evident to those skilled in the art. While thefirst substrate 130 and the second substrate are shown for simplicity to be exactly alike in FIG. 9, they do not have to be so. Similarly, for simplicity, FIGS. 10-17 (except FIG. 16) show symmetrical configurations. In practice, they could be dissimilar, as shown in FIG. 16. - As shown in FIG. 10, at least one conductive via136 is formed through the
microelectronic substrate core 102 and the secondmicroelectronic substrate core 102′ by drilling holes therethrough and plating or filling the holes with a conductive material such as copper, aluminum, and the like. Suchconductive vias 136 are used to achieve electrical communication between at least one of the first substratemicroelectronic devices 114 and at least one of the second substratemicroelectronic devices 114′ and/or between microelectronic components which may be mounted on interconnection layers which will be formed on the microelectronic deviceactive surfaces first substrate 130 and thesecond substrate 130′, respectively, as will be discussed. If the substrate core is made of a conductive material, a dielectric material will need to be disposed between the conducting material and the conductive via material, by one of various techniques which are known in the art. - Although the following description relates to a bumpless, built-up layer technique for the formation of interconnection layers, the method of fabrication is not so limited. The interconnection layers may be fabricated by a variety of techniques known in the art.
- FIG. 11 illustrates an enlarged view of the
dual substrate assembly 132 of FIG. 10, wherein thefirst substrate 130 and thesecond substrate 130′ each have a microelectronic device (114, 114′) encapsulated within their microelectronic substrate cores (102, 102′), respectively. Each of themicroelectronic device electrical contacts active surfaces electrical contacts microelectronic device electrical contacts microelectronic device - As shown in FIG. 12,
dielectric layers conductive traces first surface 106, and theencapsulation material surface 124.Dielectric layers conductive traces active surface 116′ (including theelectrical contacts 154′), the microelectronic substrate corefirst surface 106′, and theencapsulation material surface 124′. At least oneconductive trace 158 may contact a first via 136, which in turn contacts aconductive trace 164 to achieve electrical contact between the firstmicroelectronic device 114 and the secondmicroelectronic device 114′. - The dielectric layers156, 156′, 162, 162′ are preferably epoxy resin, polyimide, bisbenzocyclobutene, and the like, and more preferably filled epoxy resins available from Ibiden U.S.A. Corp., Santa Clara, Calif., U.S.A. and from Ajinomoto U.S.A., Inc., Paramus, N.J., U.S.A. The conductive traces 158, 158′, 164, 164′, may be any conductive material including, but not limited to, copper, aluminum, and alloys thereof. The formation of the
dielectric layers dielectric layers electrical contacts dielectric layers first substrate 130 and thesecond substrate 130′. However, it is understood that they could be formed independently on each substrate. - As shown in FIG. 13,
conductive interconnects conductive traces 158′, 164′, respectively, and used for communication with external components (not shown). FIG. 13 illustrates solder bumps extending through solder resistdielectric layers microelectronic substrate 170. - It is, of course, understood that a variety of interconnection configurations may be devised. For example, as shown in the FIG. 13, at least one
conductive trace 164 may contact a second via 136′, which in turn contacts aconductive trace microelectronic device 114 and theconductive interconnect 166 on an opposing side of the layeredmicroelectronic substrate 170. - FIG. 14 illustrates a plurality of
microelectronic devices encapsulation material microelectronic substrate cores microelectronic substrate 170 of the present invention. The layer(s) of dielectric material and conductive traces comprising the interconnection layer is simply designated together as interconnection layers 172, 172′, respectively. - This interconnection layers172, 172′ serve not only to form connections between the
microelectronic device conductive interconnects microelectronic devices 114 and among themicroelectronic devices 114′. - As shown in FIG. 15, once the interconnection layers172, 172′ are formed, at least one
microelectronic device 174 may be attached to an exposedsurface 176 of theinterconnection layer 172 by theconductive interconnects 166 and/or at least onemicroelectronic device 174′ may be attached to an exposedsurface 176′ of theinterconnection layer 172′ by theconductive interconnects 166′. It is, of course, understood that theconductive interconnects interconnection layer microelectronic devices microelectronic devices microelectronic devices - FIG. 16 illustrates the assembly of FIG. 15 including a plurality of the external attachment features182, such as attach pins, solder balls (shown), or other such features, connected to the exposed
surface 176′ of theinterconnection layer 172′. The external attachment features 182 make electrical connection between the layeredmicroelectronic substrate 170 and anexternal system board 184. - Of course, the layered
microelectronic substrate 170 would be most effective if themicroelectronic devices microelectronic devices 114 do need heat removal, aheat dissipation device 190 may be disposed between thefirst substrate 130 and thesecond substrate 130′, as illustrated FIG. 17. Theheat dissipation device 190 may be a heat pipe, as known in the art, or a heat slug, such as a copper plate, an aluminum plate, a thermally conductive polymer, or a micro-electro-mechanical (MEMS) cooling system. Thefirst substrate 130 and thesecond substrate 130′ are preferably attached to theheat dissipation device 190 bylayers conductive vias 136, holes are drilled through thefirst substrate 130, theheat dissipation device 190, and thesecond substrate 130′. If theheat dissipation device 190 is made of an electrically conductive material, the holes are coated with a thin conformal layer ofdielectrical material 194, such as vapor deposition of a polymer, including but not limited to parylene. Another approach known in the art is to fill the via holes with dielectric material and drill a new smaller ole in the center. Thereafter, as previously discussed, a conductive material is plated or filled in the holes to form theconductive vias 136. - FIG. 18 illustrates an embodiment of a single
substrate microelectronic assembly 200, according to the present invention. The singlesubstrate microelectronic assembly 200 comprises asingle substrate 202 having a plurality ofmicroelectronic devices 114 encapsulated in amicroelectronic substrate core 102, as previously discussed. A plurality of thevias 136 is formed through thesingle substrate 202. Afirst interconnection layer 204 is formed on the microelectronic deviceactive surfaces 116 and microelectronic substrate corefirst surface 106, and asecond interconnection layer 204′ is formed on the microelectronic device back surfaces 118 and microelectronic substrate corefirst surface 108, preferably, in the manner previously discussed. At least onemicroelectronic device 174 may be attached to an exposed surface 206 of thefirst interconnection layer 204 byconductive interconnects 208 and/or at least onemicroelectronic device 174′ may be attached to the exposed surface 206′ of thesecond interconnection layer 204′ byconductive interconnects 208′. - If any of the embedded
microelectronic devices 114 require heat removal,heat dissipation devices 212 may be placed in thermal contact with the microelectronic device back surfaces 118, as shown in FIG. 19. As part of the embedding process, the microelectronic device backsurface 118 is exposed either by proper choice of embedding process or by backside grinding, prior to forming the interconnection layer(s) (shown withsecond interconnection layer 204′). The microelectronic device backsurface 118 is preferably metallized during the build-up process used to form the conductive traces (see discussion regarding FIG. 12) of thesecond interconnection layer 204′when a metal is used. The metallized surfaces are illustrated aselements 214. The metallized surfaces 214 may be formed by having an open area of the dielectric patterning mask or by ablating away all of dielectric with a laser at each layering step, as previously discussed. Of course, other techniques, as will be known to those skilled in the art, may be utilized. - As shown in FIG. 20, more than one single substrate
microelectronic substrate assembly 200, as shown in FIG. 19, may be layered to form a layered microelectronic substrate assembly, according to the present invention. The layeredmicroelectronic assembly 220 is fabricated by orienting a first single substratemicroelectronic substrate assembly 200′ to a second single substratemicroelectronic substrate assembly 200″, such that the microelectronic deviceactive surfaces 116′ and 116″, respectively, face one another. The interconnection layers 222′ and 222″, which are formed on the microelectronic deviceactive surfaces 116′ and 116″ and the substrate core first surfaces 106′ and 106′ respectively, may be electrically interconnected by direct lamination, by a plurality ofconductive interconnects 226, such as solder balls (shown), or by any other technique as will be known to those skilled in the art. - Interconnection layers224′ and 224″ are formed on the microelectronic device back surfaces 118 ′ and 118″, and microelectronic substrate core
second surface 108′ and 108″, respectively, in the manner previously discussed. At least onemicroelectronic device 174′ may be attached to an exposedsurface 228′ of the interconnection layers 224′ byconductive interconnections 208′ and/or at least onemicroelectronic device 174″ may be attached to the exposedsurface 228″ of theinterconnection layer 224″ byconductive interconnections 208″. Of course,heat dissipation devices 212′ and 212″ (not shown) may be placed in thermal contact with the microelectronic device back surfaces 118′ and 118″, respectively. As previously discussed, a plurality of thevias 136′ and 136″ may formed through the firstmicroelectronic substrate core 102′ and the secondmicroelectronic substrate core 102″, respectively. - It is, of course, understood that the interconnection layers224′ and 224″ are optional, as shown in FIG. 21, wherein
thermal dissipation devices 212′ and 212″ may be attached directly to the microelectronic device back surfaces 118 ′ and 118″. Further, as shown in FIG. 21, if microelectronic components, such asdecoupling capacitors 234, need to be located close to a particular microelectronic device, such asmicroelectronic device 114′. Thus, they may be positioned withinmicroelectronic substrate assembly 200″ directly opposite themicroelectronic device 114′. Of course, an equivalent arrangement (not shown) is possible for placing components neardice 212″ by embedding them in the oppositemicroelectronic substrate assembly 200′. - Furthermore, as shown in FIG. 22, the
heat dissipation devices 212′ and 212″ and the firstmicroelectronic substrate core 102′ and the secondmicroelectronic substrate core 102″ may be replaced by a first thermally conductivemicroelectronic substrate core 236′ and a second thermally conductivemicroelectronic substrate core 236″. Themicroelectronic device 114′ is disposed within a cavity in the first thermally conductivemicroelectronic substrate core 236′ and theencapsulation material 122′ fills any voids between themicroelectronic device 114′ and the firstmicroelectronic substrate core 102′. Themicroelectronic device 114′ may be secured with a thermally conductive adhesive or solder, or may merely be secured with theencapsulation material 122′. Themicroelectronic devices 114″ and themicroelectronic components 234 are shown likewise situated in cavities in the second thermally conductivemicroelectronic substrate core 236″. - It is understood that the assemblies of FIGS.17-22 may include external attachment features (see
elements 182 in FIG. 16), such as attach pins, solder balls, edge connectors, or other such features (not shown), connected to an external system board (not shown), such as is shown in FIG. 16. - Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims (44)
1. A microelectronic substrate, comprising:
a first microelectronic substrate core having a first surface and an opposing second surface, said first microelectronic substrate core having at least one opening defined therein extending from said first microelectronic substrate core first surface to said first microelectronic substrate core second surface;
at least one first microelectronic device disposed within said at least one opening, said at least one first microelectronic device having an active surface and a back surface, wherein said first microelectronic device active surface is adjacent said first microelectronic substrate core first surface;
an encapsulation material adhering said first microelectronic substrate core to said at least one first microelectronic device forming a first surface adjacent said microelectronic die active surface and said core first surface and a second surface adjacent said microelectronic die back surface and said core second surface; and
at least one conductive via extending from said first microelectronic substrate core first surface to said first microelectronic substrate core second surface.
2. The microelectronic substrate of claim 1 , further including a first interconnection layer disposed proximate said first microelectronic substrate core first surface and said first microelectronic device active surface and further including a second interconnection layer disposed proximate said first microelectronic substrate core second surface and said first microelectronic device back surface, wherein said at least one conductive via electrically connects said first interconnection layer and said second interconnection layer.
3. The microelectronic substrate of claim 2 , further including at least one microelectronic device attached to at least one of said first interconnection layer and said second interconnection layers.
4. The microelectronic substrate of claim 2 , further including at least one heat dissipation device thermally attached to said at least one microelectronic device back surface.
5. The microelectronic substrate of claim 2 , wherein said first interconnection layer comprises at least one dielectric layer abutting at least one of said first microelectronic device active surface, said first microelectronic substrate core first surface, and said encapsulation material first surface, and at least one conductive trace disposed on said at least one dielectric layer.
6. The microelectronic substrate of claim 5 , wherein said at least one conductive trace extends through said at least one dielectric layer to contact at least one electrical contact on said first microelectronic device active surface.
7. The microelectronic substrate of claim 5 , wherein said at least one conductive trace extends through said at least one dielectric layer to contact said at least one conductive via.
8. The microelectronic substrate of claim 2 , wherein said second interconnection layer comprises at least one dielectric layer abutting at least one of said microelectronic device back surface, said microelectronic substrate core second surface, and said encapsulant material second surface, and at least one conductive trace disposed on said at least one dielectric layer.
9. The microelectronic substrate of claim 8 , wherein said at least one conductive trace extends through said at least one dielectric layer to contact said at least one conductive via.
10. The microelectronic substrate of claim 1 , further including:
a second microelectronic substrate core having a first surface and an opposing second surface, said second microelectronic substrate core having at least one opening defined therein extending from said second microelectronic substrate core first surface to said second microelectronic substrate core second surface;
at least one second microelectronic device disposed within said at least one opening, said at least one second microelectronic device having an active surface adjacent said second microelectronic substrate core first surface and a back surface adjacent said second microelectronic substrate core second surface;
an encapsulation material adhering said second microelectronic substrate core to said at least one second microelectronic device forming a first surface adjacent said microelectronic die active surface and said core first surface and a second surface adjacent said microelectronic die back surface and said core second surface;
said first microelectronic substrate core second surface attached to said second microelectronic substrate core second surface; and
said at least one conductive via extends from said first microelectronic substrate core first surface to said second microelectronic substrate core first surface.
11. The microelectronic substrate of claim 10 , further including a heat dissipation device disposed between said first microelectronic substrate core second surface and said second microelectronic substrate core second surface.
12. The microelectronic substrate of claim 11 , further including a dielectric material disposed between said conductive via and said heat dissipation device.
13. A microelectronic substrate, comprising:
at least one first microelectronic device having an active surface and a back surface;
an encapsulation material forming a first surface adjacent said microelectronic die active surface and a second surface adjacent said microelectronic die back surface; and
at least one conductive via extending from said encapsulation material first surface to said encapsulation material second surface.
14. The microelectronic substrate of claim 13 , further including a first interconnection layer disposed proximate said encapsulation material first surface and said first microelectronic device active surface and further including a second interconnection layer disposed proximate said encapsulation material second surface and said first microelectronic device back surface, wherein said at least one conductive via electrically connects said first interconnection layer and said second interconnection layer.
15. A microelectronic substrate, comprising:
a first microelectronic substrate core having a first surface and an opposing second surface, said first microelectronic substrate core having at least one opening defined therein extending from said first microelectronic substrate core first surface to said first microelectronic substrate core second surface;
at least one first microelectronic device disposed within said at least one opening, said at least one first microelectronic device having an active surface and a back surface, wherein said first microelectronic device active surface is adjacent said first microelectronic substrate core first surface;
a first encapsulation material adhering said first microelectronic substrate core to said at least one first microelectronic device forming a first surface adjacent said microelectronic die active surface and said core first surface and a second surface adjacent said microelectronic die back surface and said core second surface;
a second microelectronic substrate core having a first surface and an opposing second surface, said second microelectronic substrate core having at least one opening defined therein extending from said second microelectronic substrate core first surface to said second microelectronic substrate core second surface;
at least one second microelectronic device disposed within said at least one opening, said at least one second microelectronic device having an active surface and a back surface, wherein said second microelectronic device active surface is adjacent said second microelectronic substrate core first surface;
a second encapsulation material adhering said second microelectronic substrate core to said at least one second microelectronic device forming a first surface adjacent said microelectronic die active surface and said core first surface and a second surface adjacent said microelectronic die back surface and said core second surface; and
said first microelectronic device active surface oriented to face said second microelectronic device active surface.
16. The microelectronic substrate of claim 15 , further including a first interconnection layer disposed proximate said first microelectronic substrate core first surface, said first encapsulation first surface, and said first microelectronic device active surface and further including a second interconnection layer disposed proximate said second microelectronic substrate core first surface, said second encapsulation material first surface, and said first microelectronic device active surface, wherein said first and second interconnection layers are electrically connected.
17. The microelectronic substrate of claim 15 , further including an interconnection layer disposed proximate at least one of said first microelectronic substrate core second surface, said first encapsulation material second surface, and said first microelectronic device back surface, and said second microelectronic substrate core second surface, said second encapsulation material second surface, and said second microelectronic device back surface.
18. The microelectronic substrate of claim 15 , further including at least one conductive via extending from said first microelectronic substrate core first surface and said first microelectronic substrate core second surface.
19. The microelectronic substrate of claim 15 , further including at least one conductive via extending between said second microelectronic substrate core first surface and said second microelectronic substrate core second surface.
20. The microelectronic substrate of claim 15 , further including at least one conductive via extending from said first microelectronic substrate core second surface and said second microelectronic substrate core second surface.
21. The microelectronic substrate of claim 15 , further including at least one heat dissipation device thermally attached to at least one of said at least one first microelectronic device back surface and said at least one second microelectronic device back surface.
22. A microelectronic substrate, comprising:
a first microelectronic substrate core having a first surface and an opposing second surface, said first microelectronic substrate core having at least one cavity defined therein;
at least one first microelectronic device disposed within said at least one cavity, said at least one first microelectronic device having an active surface and a back surface, wherein said first microelectronic device active surface is adjacent said first microelectronic substrate core first surface;
a first encapsulation material adhering said first microelectronic substrate core to said at least one first microelectronic device forming a first surface adjacent said microelectronic die active surface;
a second microelectronic substrate core having a first surface and an opposing second surface, said second microelectronic substrate core having at least one cavity defined therein;
at least one second microelectronic device disposed within said at least one cavity, said at least one second microelectronic device having an active surface and a back surface, wherein said second microelectronic device active surface is adjacent said second microelectronic substrate core first surface;
a second encapsulation material adhering said second microelectronic substrate core to said at least one second microelectronic device forming a first surface adjacent said microelectronic die active surface and said core first surface; and
said first microelectronic device active surface oriented to face said second microelectronic device active surface.
23. The microelectronic substrate of claim 22 , further including a first interconnection layer disposed proximate said first microelectronic substrate core first surface, said first encapsulation first surface, and said first microelectronic device active surface and further including a second interconnection layer disposed proximate said second microelectronic substrate core first surface, said second encapsulation material first surface, and said first microelectronic device active surface, wherein said first and second interconnection layers are electrically connected.
24. A method of fabricating a microelectronic substrate, comprising:
providing a first microelectronic substrate core having a first surface and an opposing second surface, said first microelectronic substrate core having at least one opening defined therein extending from said first microelectronic substrate core first surface to said first microelectronic substrate core second surface;
disposing at least one first microelectronic device having an active surface and a back surface within said at least one opening such that said first microelectronic device active surface resides adjacent said first microelectronic substrate core first surface;
disposing an encapsulation material in said at least one opening to adhere said first microelectronic substrate core to said at least one first microelectronic device and forming a first surface adjacent said microelectronic die active surface and a second surface adjacent said microelectronic die back surface; and
forming at least one conductive via to extend from said first microelectronic substrate core first to said first microelectronic substrate core second surface.
25. The method of claim 24 , further including thermally attaching at least one heat dissipation device to at least one microelectronic device back surface.
26. The method of claim 24 , further including:
forming a first interconnection layer disposed proximate said first microelectronic substrate core first surface, said encapsulation material first surface, and said first microelectronic device active surface;
forming a second interconnection layer disposed proximate said first microelectronic substrate core second surface, said encapsulation material second surface, and said first microelectronic device back surface.
27. The method of claim 26 , wherein forming said first interconnection layer comprises:
forming at least one dielectric material layer on at least a portion of said first microelectronic device active surface, said encapsulation material first surface, and said microelectronic substrate core first surface;
forming at least one via through said at least one dielectric material layer to expose a portion of said microelectronic device active surface; and
forming at least one conductive trace on said at least one dielectric material layer which extends into said at least one via to electrically contact said first microelectronic device active surface.
28. The method of claim 27 , wherein forming at least one conductive trace comprises forming said at least one conductive trace to extend through said at least one dielectric layer to contact said at least one conductive via.
29. The method of claim 26 , wherein forming said second interconnection layer comprises:
forming at least one dielectric material layer on at least a portion of said first microelectronic device back surface, said encapsulation material second surface, and said microelectronic substrate core second surface;
forming at least one via through said at least one dielectric material layer; and
forming at least one conductive trace on said at least one dielectric material layer which extends into said at least one via to electrically contact said conductive via.
30. The method of claim 24 , further including:
providing a second microelectronic substrate core having a first surface and an opposing second surface, said second microelectronic substrate core having at least one opening defined therein extending from said second microelectronic substrate core first surface to said second microelectronic substrate core second surface;
disposing at least one second microelectronic device within said at least one opening, such that an active surface of said at least one second microelectronic device resides adjacent said second microelectronic substrate core first surface and such that a back surface of said at least one second microelectronic device resides adjacent said second microelectronic substrate core second surface;
disposing an encapsulation material in said opening to adhere said second microelectronic substrate core to said at least one second microelectronic device;
attaching said first microelectronic substrate core second surface to said second microelectronic substrate core second surface; and
forming said at least one conductive via to extend from said first microelectronic substrate core first surface to said second microelectronic substrate core first surface.
31. The method of claim 30 , further including disposing a heat dissipation device between said first microelectronic substrate core second surface and said second microelectronic substrate core second surface.
32. The method of claim 30 , further including forming at least one conductive via interconnecting said first microelectronic substrate core first surface and said second microelectronic substrate core first surface.
33. The method of claim 32 , further including disposing a dielectric material between said at least one conductive via and said heat dissipation device.
34. The method of claim 24 , further including abutting said first microelectronic substrate core first surface and said first microelectronic device active surface against a protective film prior to disposing said encapsulation material in said at least one opening.
35. The method of claim 34 , wherein abutting said microelectronic substrate core first surface and said at least one microelectronic device active surface against a protective film comprises abutting said first microelectronic substrate core first surface and said first microelectronic device active surface against an adhesive layer on said protective film prior to disposing said encapsulation material in said at least one opening.
36. A method of fabricating a microelectronic substrate, comprising:
providing a first microelectronic substrate core having a first surface and an opposing second surface, said first microelectronic substrate core having at least one opening defined therein extending from said first microelectronic substrate core first surface to said first microelectronic substrate core second surface;
disposing at least one first microelectronic device having an active surface and a back surface within said at least one opening such that said first microelectronic device active surface resides adjacent said first microelectronic substrate core first surface;
disposing a first encapsulation material in said microelectronic substrate core opening adhering said first microelectronic substrate core to said at least one first microelectronic device, forming a first surface adjacent said first microelectronic die active surface and a second surface adjacent said first microelectronic die back surface;
providing a second microelectronic substrate core having a first surface and an opposing second surface, said second microelectronic substrate core having at least one opening defined therein extending from said second microelectronic substrate core first surface to said second microelectronic substrate core second surface;
disposing at least one second microelectronic device having an active surface and a back surface within said at least one opening such that said second microelectronic device active surface resides adjacent said second microelectronic substrate core first surface;
disposing a second encapsulation material in said second microelectronic core opening adhering said second microelectronic substrate core to said at least one second microelectronic device, forming a first surface adjacent said second microelectronic active surface and a second surface adjacent said microelectronic die back surface; and
attaching said first microelectronic core to said second microelectronic core such that said first microelectronic device active surface oriented to face said second microelectronic device active surface.
37. The method of claim 36 , further including forming an interconnection layer disposed proximate said first microelectronic substrate core first surface, said first encapsulation material first surface, and said first microelectronic device active surface and further including forming a second interconnection layer disposed proximate said second microelectronic substrate core first surface, said second encapsulation material first surface, and said first microelectronic device active surface; and wherein said attaching said first microelectronic core to said second microelectronic core includes forming electrical connections between said first and second interconnection layers.
38. The method of claim 36 , further including forming an interconnection layer disposed proximate at least one of said first microelectronic substrate core second surface, said first encapsulation material second surface, and said first microelectronic device back surface, and said second microelectronic substrate core second surface, said second encapsulation material second surface, and said second microelectronic device back surface.
39. The method of claim 36 , further including forming at least one conductive via to extend from said first microelectronic substrate core first surface and said first microelectronic substrate core second surface.
40. The method of claim 36 , further forming including at least one conductive via to extend from said second microelectronic substrate core first surface and said second microelectronic substrate core second surface.
41. The method of claim 36 , further including forming at least one conductive via interconnecting said first microelectronic substrate core second surface and said second microelectronic substrate core second surface.
42. The method of claim 36 , further including thermally attaching at least one heat dissipation device to at least one of said at least one first microelectronic device back surface and said at least one second microelectronic device back surface.
43. The method of claim 42 , further including forming at least one conductive via interconnecting said first microelectronic substrate core first surface and said second microelectronic substrate core first surface.
44. The method of claim 43 , further including disposing a dielectric material between said at least one conductive via and said heat dissipation device.
Priority Applications (2)
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US10/964,238 US7078788B2 (en) | 2000-08-16 | 2004-10-13 | Microelectronic substrates with integrated devices |
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US64096100A | 2000-08-16 | 2000-08-16 | |
US09/692,908 US6734534B1 (en) | 2000-08-16 | 2000-10-19 | Microelectronic substrate with integrated devices |
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US09/692,908 Continuation-In-Part US6734534B1 (en) | 2000-08-16 | 2000-10-19 | Microelectronic substrate with integrated devices |
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Also Published As
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US20050062173A1 (en) | 2005-03-24 |
US7078788B2 (en) | 2006-07-18 |
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