US20020005591A1

US20020005591A1 - Bumpless flip chip assembly with strips-in-via and plating

Info

Publication number: US20020005591A1
Application number: US09/464,561
Authority: US
Inventors: Charles Lin
Original assignee: Individual
Current assignee: Charles Wc Lin
Priority date: 1998-12-17
Filing date: 1999-12-16
Publication date: 2002-01-17
Anticipated expiration: 2019-12-16
Also published as: US6403400B2; TW522536B; US6437452B2; US20010024839A1; SG78324A1

Abstract

A flip chip assembly, and methods of forming the same, including a single or multi-layer substrate having a plurality of via holes or apertures of which preformed strips or wires inside the via holes serve as the connections between the semiconductor device and substrate circuitry. The assembling steps may include attaching an integrated circuit (IC) chip or chips to a rigid or flexible substrate circuitry having a plurality of pre-formed strips extended from the patterned circuitry and hanging inside a plurality of through holes. These through holes are aligned and placed on top of the terminal pads so that the respective traces on the substrate can be connected with the respective input/output terminal pads of the IC chip through the leads inside the via holes. After attachment, electrically conductive material is subsequently connected to these leads to the IC terminal pads through electrolytic plating, electroless (chemical) plating or solder re-flow processes. The joining material can provide mechanical support as well as electrical continuity between IC chip and the circuitry of the substrate.

Description

The present application is an application filed in accordance with 35 U.S.C. § 119 and claims the benefit of earlier filed Singapore application number 9804800-2 filed on Dec. 17, 1998.

1. Field of the Invention

This invention relates generally to a semiconductor device assembly, and in particular, to a chip assembly which includes a single or multi-layered substrate of which circuitry are connected to the input/output terminal pads of the IC chip through deposition of conductive material onto pre-formed leads and IC pads.

2. Background of the Invention

Recent developments in semiconductor packaging suggest an increasingly critical role of the technology. New demands are coming from requirements for more leads per chip (and hence smaller input/output terminal pitch), shrinking die and package footprint, and higher operational frequency that generate more heat (thus requiring advanced heat dissipation designs). All of these considerations must be met and, as usual, are placed in addition to the cost that packaging adds to the overall semiconductor manufacturing process.

Conventionally, there are three predominant chip-level connection technologies in use for integrated circuits, namely wire bonding, tape automated bonding (TAB) and flip chip (FC), to electrically or mechanically connect integrated circuits to lead frame or substrate circuitry. Wire bonding has been by far the most broadly applied technique in the semiconductor industry because of its maturity and cost effectiveness. However, this process can be performed only one at a time between the semiconductor chip's bonding pads and the appropriate interconnect points. Furthermore, because of the ever-increasing operational frequency of the device, the length of the interconnects need to be shorter to minimize inductive noise in power and ground, and also to limit the crosstalk between the signal leads. An example of such a method is disclosed in U.S. Pat. No. 5,397,921 issued to Kamezos et al.

Flip chip technology is generally defined as mounting of an unpackaged semiconductor chip with the active side facing down to an interconnect substrate through some kind of contact anchors such as solder, gold or organic conductive adhesive bumps. The major advantage of the flip chip technology is the short interconnects which can, therefore, handle high speed or high frequency signals. There are essentially no parasitic elements, such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated. Flip chip also allows an array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight, thus effective overall cost savings since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 issued to Casson et al.

When flip chip technology shows tremendous advantage over wire bonding, its cost and technical limitations are significant. First of all, prior art flip chip technology must confront the challenges of forming protruded contact anchors or bumps to serve as electrical connections between integrated circuit chip and substrate circuitry. Examples of such an approach are disclosed in U.S. Pat. No. 5,803,340 issued to Yeh, al. et. al. and U.S. Pat No. 5,736,456 issued to Akram. These typically include a very costly vacuum process to deposit an intermediate under-bump layer that serves as an adhesive and diffusion barrier. This barrier layer is typically composed of a film stack that can be in the structure of chromium/copper/gold. Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a re-flow step to form the solder contacts. Although evaporation and sputtering techniques can potentially offer high density bumps, these processes need very tight controls and normally result in poor yield. In addition, from the mechanical structural viewpoint, the coefficient of thermal expansion (CTE) of silicon and substrate may be quite different, and the stress between these two parts after attachment will build up and be fully loaded onto these bumps. This will then cause severe joint cracking and disconnection problems during normal operation conditions. As a result, a conventional flip chip assembly is not only very costly but also suffers from very serious reliability problems and high fatality ratio.

Techniques for fabricating the intermediate under-bump barrier layer as well as bump material utilizing electroless plating methods are also known in the prior art. An example of such a method is described in the U.S. Pat. No. 5,583,073 issued to Lin et al. Although this electroless technique provides an economical, simple and effective method for under bump barrier layer, contacting material such as solder or adhesive is still required for assembling. Solder dipping or screen printing of solder paste onto these bumps have been explored but have been met with very limited success due to lack of solder bridging control and non-uniform deposition of solder on the metal bump. This process can be very troublesome and suffers from poor process control as input/output terminal pad space is getting smaller and smaller. Additional problems have been encountered with the tin/lead solder systems due to its increase in electrical resistance over time, and these solder contacts are easily fatigued in thermo-mechanical stressing.

In view of the limitations of currently available integrated circuits assembling methods, a high performance, reliable and economical device and method that can effectively interconnect integrated circuits to the external circuitry would be greatly desirable.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a flip chip assembly to address high density, low cost and high performance requirements of semiconductor packaging. It involves the bonding of substrate circuitry to semiconductor device through connection of preformed leads to the IC terminal pads inside the via holes or apertures without the need for conventional bump, bonding wire, or other media. These unique joining approaches are capable of providing both electrical and mechanical connections between IC chip and circuitry of the substrate.

To achieve the foregoing, the assembly includes a rigid or flexible dielectric substrate having a plurality of electrically conductive circuitry and a plurality of via holes formed in the dielectric substrate. These conductive traces on the surface of the substrate are extended into each specific via hole through leads that are fabricated by conventional circuitry patterning process, cutting or punching methods.

The orientation of the contact ensures that at least one of the via holes in the dielectric substrate aligns with the pads of the IC chip so that these pads can be totally or partially exposed and/or accessed through the opposite side of the substrate. After alignment, the IC chip is attached to the dielectric substrate through adhesive film or paste, or mechanical techniques to form a chip assembly. Electrically conductive material is subsequently deposited onto the leads and the input/output pads of the IC chip to complete the connection of the IC chip and the substrate circuitry.

In one embodiment of the invention, the connection method may take the form of electrolytic plating. In this method, the assembly is connected to an external power source and serves as one of the electrodes for electrochemical plating. Electrolytic plating of metals and alloys, are common and are well known in the industry, and so further elaboration is not necessary. The metallic leads as well as other conductive parts of the assembly that are connected to the external power and exposed to the plating solution will generate cathodic reaction on the surfaces and continuously deposit metal or alloys thereon. This deposition of metal or alloys will result in a longer and wider lead as electroplating reaction proceeds. In the initial stage, the terminal pads of the IC chip that are also immersed in the plating solution, will not receive any deposition due to lack of connection to the external power source. However, as the plating process continues, the leads which are bent toward inside the via holes, will lengthen out and finally reach the surface of the terminal pads which are located at the bottom of the via holes. These metallic contacts will then provide electrical power to the IC terminal pads and subsequently initiate electroplating reaction thereon. This simultaneous electroplating of leads and terminal pads will then form an integral part of a joint thus providing an effective means for electrical and mechanical connections between the IC chip and the dielectric circuitry. This is important in that it not only assures a very desired intermetallic structure but also assures a pre-defined, very reliable connection between substrate and IC chip due to the flexibility of the leads. In several embodiments of the present invention, in order to provide a good contact and prevent oxidation or dissolution of the IC terminal pads before the plating starts, these pads are commonly pre-treated or coated with a protective layer such as a stack of thin film thereon before assembly.

In another embodiment of the invention, the connection is achieved by electroless (chemical) plating. In this method, the electroless plating can be initiated on the catalyzed leads and continuously deposit metal or alloys thereon. In contrast to the electrolytic plating, there is no external power necessary to sustain the plating reaction and the metal deposition can be achieved by a chemical reaction controlled by at least one reducing agent (catalyst) such as hypophosphite. Since electroless plating is a common practice and well known to those skilled in the art, no further explanation is deemed necessary. Under certain pre-defined bath conditions (e.g., temperature and chemical composition), the catalyzed leads that are immersed in the plating bath will be readily initiated and will continuously deposit metal or alloys thereon. Similarly, this deposition of metal or alloys will result in a longer and wider lead as plating reaction proceeds. The terminal pads of the IC chip that are immersed in the plating solution may also receive deposition simultaneously depending on their surface energy and chemical potential.

According to another embodiment of the invention, the connection method may take the form of soldering. In this method, the connecting leads inside the via holes are pre-coated with the soldering materials and brought near to or in contact with the IC terminal pads after the IC attachment. Heat, which serves to activate the flux and bring the solder to its melting point to effect the metallurgical bonding, is then applied to the assembly. This re-flow process will result in a solder joint which will electrically and physically connect the pre-coated lead and IC pad for permanent contact thereafter. This is considered important in that it not only assures a very low cost and simple process, but also provides a compliant joint with significant stress release, which results in a very reliable connection between the substrate circuitry and IC chip.

Various techniques including electroplating, wave soldering, meniscus solder coating, solder paste printing and dispensing techniques can accomplish the pre-coating of solder materials onto the leads.

The via holes of the substrate circuitry can be formed by various techniques including mechanical drilling, punching, plasma etching or laser drilling. They are formed in the substrate at the locations where the electrical circuitry on one side of the substrate can be connected to the opposite side of the surface on which the semiconductor chip or chips are mounted and their input/output terminal pads can be exposed through these holes.

Using extended leads and conductive material directly deposited in the via hole can effectively connect IC chip and dielectric substrate circuitry without external bumps or wires. This approach allows a reliable, low profile, high performance and low cost assembly to be achieved. In particular, a small via hole, which can be formed by laser or other techniques, allows very fine pitch terminal pad to be interconnected, and can significantly enhance the capability of packaging future high I/O semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fragmented perspective view of a substrate showing via hole and traces of the substrate circuitry. [0020]
FIGS. [0021] 2A-2E are fragmented partial sectional side elevational views showing sequentially the manufacture of an integrated circuit assembly by electroless plating according to the present invention.
FIGS. [0022] 3A-3E are fragmented partial sectional side elevational views showing sequentially the manufacture of an integrated circuit assembly by electrolytic plating according to another embodiment of the present invention.
FIGS. [0023] 4A-4F are fragmented partial sectional side elevational views showing sequentially the manufacturing of an integrated circuit assembly by pre-deposited solder and re-flowing process according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

According to the invention, a flip chip assembly is provided to address high density, low cost and high performance requirements of semiconductor packaging. It involves the bonding of substrate circuitry to semiconductor device through connection of pre-formed leads to the IC terminal pads inside the via holes without the need for conventional bump, bonding wire, or other media. These unique joining approaches are capable of providing both electrical and mechanical connections between the IC chip and circuitry of the substrate. [0024]
To achieve the foregoing, the assembly includes a rigid or flexible dielectric substrate having a plurality of electrically conductive circuitry and a plurality of via holes formed in the dielectric substrate. These conductive traces on the surface of the substrate are extended into each specific via hole through the leads that are fabricated by conventional circuitry patterning process, cutting or punching methods. FIG. 1 is an isometric view of a section of such a [0025] substrate 101 on which vias 102 are normally formed by laser or mechanical drilling. These via holes 102 are to serve as the interconnecting channels between circuitry traces 103 and IC terminal pads through the pre-formed leads 104 hanging inside the vias. Circuitry traces 103, which extend from vias 102 along an outer surface of the substrate, will lead to another pad connection for next level assembly.
The orientation of the contact ensures that at least one of the via holes in the dielectric substrate are aligned to the pads of the IC chip so that these pads can be totally or partially exposed through the opposite side of the substrate. After alignment, the IC chip is attached to the dielectric substrate through adhesive film or paste, or mechanical techniques to form a chip assembly. Electrically conductive material is subsequently deposited onto the leads and the input/output pads of the IC chip to complete the connection of the IC chip and the substrate circuitry. [0026]
As defined herein, the preferred embodiment is particularly directed to the bonding of an integrated circuit (IC) chip to a flexible circuitized substrate, or to a more rigid, circuitized substrate, a particular example of the latter being a printed circuit board. It is to be understood, however, that the invention is not limited to attachment to printed circuit boards, in that other circuitized substrates, including known flexible substrate tapes or ceramic substrates, may be employed. Typically, an organic-type substrate is preferable for the purpose of lower cost, superior dielectric property whereas an inorganic type of substrate is preferable when high thermal dissipation and matched coefficient of expansion are desired. The term “substrate” as used herein is meant as at least one layer of dielectric material having at least one conductive layer thereon. Printed circuit boards of similar type are well known in the electronic industry, as well as the processes for making the same and, therefore, further definition is not believed to be necessary. Such structures may include many more electrically conductive layers than those depicted in FIGS. 1 through 4, depending on the desired operational characteristics. As is known, such electrically conductive layers may function as signal, power, and/or ground layers. [0027]
In one embodiment of the invention, the connection method may take the form of electrolytic plating. In this method, the assembly is connected to an external power source and serves as one of the electrodes for electrochemical plating. Electrolytic plating of metals and alloys, are common and are well known in the industry, and so further elaboration is not necessary. The metallic leads as well as other conductive parts of the assembly that are connected to the external power and exposed to the plating solution will generate cathodic reaction on the surfaces and continuously deposit metal or alloys thereon. This deposition of metal or alloys will result in a longer and wider lead as electroplating reaction proceeds. In the initial stage, the terminal pads of the IC chip that are also immersed in the plating solution, will not receive any deposition due to lack of connection to the external power source. However, as the plating process continues, the leads which are bent toward inside the via holes, will lengthen out and finally reach the surface of the terminal pads which are located at the bottom of the via holes. These metallic contacts will then provide electrical power to the IC terminal pads and subsequently initiate electroplating reaction thereon. This simultaneous electroplating of leads and terminal pads will then form an integral part of a joint thus providing an effective means for electrical and mechanical connections between the IC chip and the dielectric circuitry. This is important in that it not only assures a very desired intermetallic structure but also assures a pre-defined, very reliable connection between the substrate and IC chip due to the flexibility of the leads. In some of the embodiments, in order to provide a good contact and prevent oxidation or dissolution of the IC terminal pads before the plating starts, these pads are commonly pre-treated or coated with a protective layer such as a stack of thin film thereon before assembly. [0028]
In another embodiment of the invention, the connection is achieved by electroless (chemical) plating. In this method, the electroless plating can be initiated on the catalyzed leads and continuously deposit metal or alloys thereon. In contrast to the electrolytic plating, there is no external power necessary to sustain the plating reaction and the metal deposition can be achieved by a chemical reaction controlled by at least one reducing agent (catalyst) such as hypophosphite. Since electroless plating is a common practice and well known in the industry, no further explanation is necessary. Under certain pre-defined bath conditions (e.g., temperature and chemical composition), the catalyzed leads that are immersed in the plating bath will be readily initiated and will continuously deposit metal or alloys thereon. Similarly, this deposition of metal or alloys will result in a longer and wider lead as plating reaction proceeds. The terminal pads of the IC chip that are immersed in the plating solution may also receive deposition simultaneously depending on their surface energy and chemical potential. [0029]
For example, a catalyzed or oxide-free nickel which is pre-coated on the aluminum surface will enable the plating reaction to proceed on the IC pads as well. As the plating process continues, the leads which are bent toward inside the via holes, will lengthen out and finally touch the terminal pads located at the bottom of the via holes. Likewise, the simultaneously plated-up parts of leads and terminal pads will joint together providing an effective means for electrical and mechanical connections between IC chip and dielectric circuitry. This is important in that it not only assures a very flexible design in the substrate circuitry since no external contact is necessary, but also assures a very reliable metallic interface between substrate and chip. [0030]
According to another embodiment of the invention, the connection method may take the form of soldering. In this method, the connecting leads inside the via holes are pre-coated with the soldering materials and brought near to or in contact with the IC terminal pads after the IC attachment. Heat, which serves to activate the flux and bring the solder to its melting point to effect the metallurgical bonding, is then applied to the assembly. This re-flow process will result in a solder joint which will electrically and physically connect the pre-coated lead and IC pad for permanent contact thereafter. This is considered important in that it not only assures a very low cost and simple process but also provides a complaint joint with significant stress release, which results in a very reliable connection between the substrate circuitry and IC chip. [0031]
Various techniques including electroplating, wave soldering, meniscus solder coating, solder paste printing and dispending techniques can accomplish the pre-coating of solder materials onto the leads. It is understood from the teaching herein that the particular solder material and methods of dispensing techniques depicted here are not meant to limit the invention, in that it is also possible to directly place solder particles onto the leads and re-flow them prior to the IC mounting. In the case of solder paste application, flux is normally incorporated and the considerations are the same as described for conventional printed circuit board assembly. Since the soldering material on the leads may take the form of paste, or plated-up deposition, heat transfer techniques such as conduction, convection, radiation, or a combination of these is normally needed to re-flow them in order to wet the IC pad surface. A preferred application of such heat is achieved by using laser. Alternatively, the attached assembly may be positioned within a suitable oven to effect solder re-flow and bonding to the IC terminals which are in the vicinity of the via holes. One example of such an approach is an infrared (IR) continuous belt re-flow oven. In the alternative, hot nitrogen gas may be directed onto the solder members of the assembly. It is understood from the teaching herein that the particular re-flow techniques depicted above are not meant to limit the invention, in that it is also possible to re-flow the solder by vapor phase re-flow or other similar techniques. [0032]
A barrier layer over-coated on the aluminum pad is preferred as it provides good solder wetting and protects the aluminum surface against leaching, oxidation or degradation resulting from heat and soldering contact. This coating can be accomplished by sputtering a stake of thin film thereon or by wet chemical direct plating technique such as electroless nickel and immersion gold. For copper terminal pads, the pretreatment may not be necessary as long as its surface is free of oxide and contamination. [0033]
The contacting leads that are located inside of the via holes may take the form of strips with various shapes. A preferred fabrication process is conventional photolithographic patterning and etching. Alternately, they can be fabricated by micro-machining or laser cutting. After these leads are formed, they are bent toward inside the via holes in order to provide an effective connection path between IC pads and the circuitry. The bending of the leads can be achieved by a variety of methods such as vacuum suction, air blowing or mechanical pushing. [0034]
The via holes of the substrate circuitry can be formed by various techniques including mechanical drilling, punching, plasma etching, or laser drilling. They are formed in the substrate at the locations where the electrical circuitry on one side of the substrate can be connected to the opposite side of the surface on which the semiconductor chip or chips are mounted and their input/output terminal pads can be exposed through these holes. [0035]
If the finished product is, for instance, a ball grid array package, solder balls will normally be placed on the specific pads on the surface of the dielectric substrate. This finished package can be connected to a printed circuit board by re-flowing the solder balls to form an attachment to the traces of the printed circuit board. [0036]
Using extended leads and conductive material directly deposited in via holes can effectively connect IC chip and dielectric substrate circuitry without external bumps or wires. This approach allows a reliable, low profile, high performance and low cost assembly to be achieved. In particular, a small via hole, which can be formed by laser or other techniques, allows a very fine pitch terminal pad to be interconnected, and can significantly enhance the capability of packaging future high I/O semiconductor chips. The present invention will be illustrated further by the following examples. These examples are meant to illustrate and not to limit the invention, the scope of which is defined solely by the appended claims. [0037]

EXAMPLE 1

FIG. 2A shows an [0038] integrated circuit chip 201 with various types of transistor, wiring and the like were (not shown) having a plurality of exposed input/output terminal pads 202 (only one shown). These pads 202 were firstly cleaned by dipping the integrated circuitry chip 201 in a phosphoric acid solution at room temperature with an immersion time of 10 minutes to remove the surface oxide film. This chip was next dipped in a diluted catalytic solution Enthone “Alumon EN” (trademark) at 25 degrees C∇ for 20 seconds to form a thin zinc film (not shown) on the surface of aluminum alloy terminals 202. The following steps include a thorough distillated water rinse and electroless plating using Shipley “NIPOSIT 468” (trademark) at 85 degrees Celsius. The electroless plating will continuously deposit a thin layer of nickel film 203 containing phosphorous (to be referred to as a nickel film hereafter) on the input/output terminal pads 202 of the integrated circuit chips 201.
FIG. 2B shows a [0039] substrate 204 having a plurality of electrically conductive circuitry traces 205 partially covered by the solder mask 206. The traces 205 on the substrate extend to the via holes 207 and split into a plurality of leads 208 which are bent toward the inside of the via hole. The holes 207 are arranged in such a manner that the terminal pads 202 of the integrated circuit chip 201 can be totally or partially exposed when integrated circuit chip 201 is mounted on the substrate 204. The bent leads 208 are to serve as the electrically connecting channels for the respective traces 205 of the substrate 204 with respective terminal pads 202 of the integrated circuit chips 201. These leads were activated by immersing them in a palladium chloride solution (0.05 M) for electroless (chemical) plating before attachment.
As shown in FIG. 2C, the IC chip is securely attached to the substrate circuitry by adhesive paste ABLESTIK “ABLEBOND 961-2” [0040] 209 and this assembly is immersed in the electroless plating solution Shipley “NIPOSIT 468” at 65 degrees C∇. The electroless plating will initiate and continuously deposit nickel 210 on the leads 208 as well as on the pre-deposited nickel film 203 on the input/output terminal pads 202 of the integrated circuit chips 201.
As FIG. 2D shows, the bent leads and input/output terminals finally contact and join together to become an integrated part. These simultaneously-plated joints will then provide an effective means for electrical and mechanical connections between the input/output terminals and the traces of the dielectric circuitry. [0041]
As shown in FIG. 2E, the [0042] solder ball 211 is attached to the substrate at the opening site of the solder mask to provide the finished assembly for the next level connection.
Though only one integrated [0043] circuit chip 201 is shown in the figure, it is to be understood that additional integrated circuit chips, as well as passive components such as resistors or capacitors, can also be mounted on the substrate 204.

EXAMPLE 2

Referring now to FIG. 3A, an [0044] integrated circuit chip 301 similar to that in example 1 was cleaned in an alkaline solution containing 0.05M phosphoric acid at room temperature (25 degree C∇) with an immersion time of 1 minute. The chip was then thoroughly rinsed in distillated water to ensure there is no residue on the surface of the IC chip. A stake of thin film 303 in the structure of chromium (500 Angstroms)/copper (700 Angstroms)/gold (1000 Angstroms) was deposited and patterned on the terminal pads 302 to serve as the barrier and adhesive layer.
FIG. 3B shows a [0045] dielectric substrate 304 having a plurality of electrically conductive circuitry traces 305 partially covered by the solder mask 306. These traces 305 on the substrate extend into via hoes 307 and split into a plurality of leads 308 which are bent toward the inside of the via holes 307. The holes 307 are arranged in such a manner that the terminal pads 302 of the integrated circuit chip 301 can be totally or partially exposed when integrated circuit chip 301 is mounted on the substrate 304. The bent leads 308 are to serve as the electrically connecting channels for the respective traces 305 of the substrate 304 with respective terminal pads 302 of the integrated circuit chips 301.
As shown in FIG. 3C, the IC chip is securely attached to the substrate circuitry by adhesive film ABLESTIK “ABLEFILM 561K” [0046] 309 and the assembly is immersed in the copper plating solution Sel-Rex “CUBATH M” at 25 degrees Celsius. The electrical power source is connected to the circuitry of the dielectric substrate. Electroplating reaction initiates and continuously deposits copper 310 on the bent leads 307. As the plating process proceeds, the length and width of the leads will continuously increase.
FIG. 3D shows that the plated copper has reached [0047] gold surface 303 of the terminal pads 302 to provide electrical contact with the terminal pads and to initiate copper plating thereon. These electroplated joints 310 will then provide an effective means for electrical and mechanical connections between the input/output terminals and the top surface of the dielectric circuitry.
As shown in FIG. 3E, the [0048] solder ball 311 is attached to the substrate at the opening site of the solder mask to provide the finished assembly for the next level connection.

EXAMPLE 3

FIG. 4A shows an [0049] integrated circuit chip 401 with various types of transistor, wiring and the like (not shown) having a plurality of exposed input/output terminal pads 402 (only one shown). These pads 402 were firstly cleaned by dipping the integrated circuitry chip 401 in a phosphoric acid solution at room temperature with an immersion time of 10 minutes to remove the surface oxide film. This chip was next dipped in a diluted catalytic solution Enthone “Alumon EN” at 25 degrees C∇ for 20 seconds to form a thin zinc film (not shown) on the surface of aluminum alloy terminals 402. The following steps include a thorough distillated water rinse and electroless plating using Shipley “NIPOSIT 468” at 65 degrees C∇. The electroless plating will continuously deposit a thin layer of nickel film 403 containing phosphorous (to be referred to as a nickel film hereafter) on the input/output terminal pads 402 of the integrated circuits chips 401.
FIG. 4B shows a [0050] dielectric substrate 404 having a plurality of electrically conductive circuitry traces 405 partially covered by the solder mask 406. The traces 405 on the substrate extend to via holes 407 and split into a plurality of leads 408 which are bent towards the inside of the via hole. The holes 407 are arranged in such a manner that the terminal pads 402 of the integrated circuit chip 401 can be totally or partially exposed when integrated circuit chip 401 is mounted on the substrate 404. The bent leads 408 are to serve as electrically connecting channels for respective traces 405 of the substrate 404 with respective terminal pads 402 of the integrated circuit chips 401.
As shown in FIG. 4C, the [0051] substrate 404 is brought in contact with molten solder bath (Sn—Pb) from the surface where there is no circuitry thereon. Solder 409 is readily deposited onto the leads 407 the moment they are in contact with the molten solder bath.
As shown in FIG. 4D, the IC chip is next securely attached to the substrate circuitry by adhesive paste ABLESTIK “ABLEBOND 961-2” [0052] 410.
FIG. 4E shows the [0053] solder 409 west on the IC terminal pad after the assembly is re-flowed under a conventional re-flow oven, and forms an integrated part of a solder joint.
FIG. 4F shows the [0054] solder ball 411 is attached to the substrate at the opening site of the solder mask to provide the finished assembly for the next level connection.
Though only one solder system is shown in the figure, it is to be understood that many solder systems including lead-free ones, can also be applied and serve the connection purpose. [0055]
The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are, therefore, to be embraced therein.[0056]

Claims

What is claimed is:

1. A flip chip assembly, comprising:

(a) a dielectric substrate having a plurality of via apertures;

(b) said dielectric substrate having first and second opposite surfaces and a plurality of electrically conductive traces being formed on the first surface of the said dielectric substrate, each one of said traces extend into a specific via aperture through at least one lead fabricated on the top of and bent into said via aperture;

(c) a semiconductor device having a first surface and a plurality of input/output terminal pads with a stack of metal film formed thereon;

(d) said second surface of said substrate engages said semiconductor device, wherein the via apertures of said substrate are aligned on the top of said terminal pads so that at least one of said terminal pads can be at least partially exposed through said via aperture from said first surface of said substrate; and

(e) an electrical continuity of said substrate to said semiconductor device is achieved by depositing conductive material on said bent leads of the substrate as well as on said terminal pads of said semiconductor device, thereby jointly forming an integral part in the flip chip assembly.

2. The flip chip assembly according to claim 1, wherein a dielectric portion of said dielectric substrate is made of plastics.

3. The flip chip assembly according to claim 1, wherein a dielectric portion of said dielectric substrate is made of flexible film.

4. The flip chip assembly according to claim 1, wherein a dielectric portion of said dielectric substrate is made of ceramics.

5. The flip chip assembly according to claim 1, wherein said via apertures are formed in said dielectric substrate by at least one method selected from the group consisting of laser drilling, mechanical punching, plasma etching or chemical etching.

6. The flip chip assembly according to claim 1, wherein said bent leads are fabricated by photolithographic patterning and etching.

7. The flip chip assembly according to claim 1, wherein said bent leads are fabricated by laser cutting.

8. The flip chip assembly according to claim 1, wherein said stack of metal film is deposited by a sputtering process.

9. The flip chip assembly according to claim 1, wherein said stack of metal is deposited by an evaporation process.

10. The flip chip assembly according to claim 1, wherein said stack of metal is deposited by electroless plating.

11. The flip chip assembly according to claim 1, wherein said semiconductor device is attached to said dielectric substrate with adhesive film.

12. The flip chip assembly according to claim 1, wherein said semiconductor device is attached to said dielectric substrate with adhesive paste.

13. The flip chip assembly according to claim 1, wherein said semiconductor device is attached to the said dielectric substrate with clamps.

14. The flip chip assembly according to claim 1, wherein said conductive material is deposited using electrolytic plating.

15. The flip chip assembly according to claim 1, wherein said conductive material is deposited using chemical plating.

16. A flip chip assembly, comprising:

(a) a dielectric substrate having a plurality of via apertures;

(b) said dielectric substrate having first and second opposite surfaces and a plurality of electrically conductive traces formed on the first surface of the said dielectric substrate, each one of said traces extending into a specific via aperture through at least one lead positioned on a top of and bent into said via apertures;

(c) said bent leads extending from said circuitry traces have at least one soldering material deposited thereon;

(d) a semiconductor device having a first surface and a plurality of input/output terminal pads with a stack of metal film deposited thereon, said second surface of said substrate is attached to said semiconductor device, wherein the via apertures of said substrate align with said terminal pads such that at least one of said terminal pads is at least partially exposed through said via aperture and accessible from said first surface of said substrate; and

(e) an electrical continuity between said substrate and said semiconductor device is achieved by a solder re-flowing process, wherein a pre-coated solder on said bent leads contact and wet said terminal pads of said semiconductor device during the solder re-flowing process, thus providing electrical connection between said semiconductor device and at least one of the traces of said substrate.

17. The flip chip assembly according to claim 16, wherein a soldering material on the leads is deposited by electroplating.

18. The flip chip assembly according to claim 16, wherein a soldering material on the leads is deposited by chemical plating.

19. The flip chip assembly according to claim 16, wherein a soldering material on the leads is deposited by wave soldering.

20. The flip chip assembly according to claim 16, wherein a soldering material on the leads is deposited by solder paste printing.

21. The flip chip assembly according to claim 16, wherein a soldering material on the leads is deposited by meniscus coating.