US20010055074A1 - In-plane switching mode lcd with specific arrangement of common bus line, data electrode, and common electrode - Google Patents
In-plane switching mode lcd with specific arrangement of common bus line, data electrode, and common electrode Download PDFInfo
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- US20010055074A1 US20010055074A1 US09/116,707 US11670798D US2001055074A1 US 20010055074 A1 US20010055074 A1 US 20010055074A1 US 11670798 D US11670798 D US 11670798D US 2001055074 A1 US2001055074 A1 US 2001055074A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
Definitions
- the present invention relates to a liquid crystal display device, and more particularly to an in-plane switching mode liquid crystal display device.
- TFT LCDs thin film transistor liquid crystal display devices
- the in-plane switching mode LCD is disclosed, for example, in JAPAN DISPLAY 92 page 547, Japanese Patent Unexamined Publication No. 7-36058, Japanese Patent Unexamined Publication No. 7-225388, and ASIA DISPLAY 95 page 707.
- FIG. 1 a and FIG. 1 b are respectively plane and sectional views of the conventional in-plane switching mode liquid crystal display device (IPS mode LCD).
- FIG. 1 b is a sectional view taken along line A-A′ of FIG. 1 a.
- a gate bus line 1 and a data bus line 2 are formed on a first substrate 10 , defining a pixel.
- a liquid crystal display device generally has a plurality of pixels.
- a common bus line 3 is aligned in the pixel, being parallel to gate bus line 1 .
- a thin film transistor (TFT) is disposed at the intersection of gate and data bus lines 1 and 2 . As shown in FIG.
- TFT thin film transistor
- the TFT comprises a gate electrode 5 , a gate insulator 12 , a semiconductor layer 15 , and an n + semiconductor layer 16 , a source electrode 6 , and a drain electrode 7 .
- a data electrode 8 and a common electrode 9 are formed parallel to data bus line 2 .
- a portion of data electrode 8 which overlaps common bus line 3 is formed to obtain a storage capacitor, which functions as maintaining a grey level voltage applied into data electrode 8 .
- Common electrode 9 is connected to common bus line 3 .
- Data electrode 8 is formed on gate insulator 12 and is connected to drain electrode 7 .
- the TFT, data electrode 8 and gate insulator 12 are covered with a passivation layer 20 .
- a first alignment layer 23 a is coated to determine the alignment direction.
- a black mask 28 is formed to prevent a leakage of light through the regions of the TFT and gate and data bus lines 1 and 2 .
- a color filter layer 29 and a second alignment layer 23 b are formed.
- a liquid crystal layer 30 is formed between first and second substrates 10 and 11 .
- the conventional IPS mode LCD has the following problems.
- An object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the aperture ratio is improved.
- Another object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the driving voltage is decreased.
- a further object of the present invention is to reduce the fabricating cost of provide an in-plane switching mode liquid crystal display device.
- the in-plane switching mode liquid crystal display device of the present invention comprises: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in the pixel regions; a gate insulator over the common bus line; a data electrode over the gate insulator and having a portion overlying the common bus line to form a first storage capacitor; a passivation layer over the data electrode; and a common electrode over the passivation layer at least partially overlying the gate and data bus lines and at least partially overlying the data electrode to form a second storage capacitor.
- the in-plane switching mode liquid crystal display device comprises: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in the pixel regions; a gate insulator over the common bus line; a thin film transistor coupled to each of the pixel regions and including at least a part of the gate insulator; a data electrode over the gate insulator and having a portion overlying the common bus line to form a first storage capacitor; a passivation layer over the data electrode and the thin film transistor; a common electrode over the passivation layer and at least partially overlying the data electrode to form a second storage capacitor; and a metal layer over the passivation layer and the thin film transistor.
- the in-plane switching mode liquid crystal display device comprises: first and second substrates having a plurality of pixel regions; a common bus line aligned in the pixel regions; a first insulating layer over the common bus line; a data electrode over the first insulating layer and having a portion overlying the common bus line to form a first storage capacitor; a second insulating layer over the data electrode; a common electrode over the second insulating layer, the common electrode having one or more openings, at least one of the openings having a substantially rectangular shape with four corner areas, at least one corner area being cut at an angle, and the common electrode having a portion overlying the data electrode to form a second storage capacitor; and a liquid crystal layer formed between the first and second substrates.
- FIG. 1 a and FIG. 1 b are respectively plane and sectional views of the conventional in-plane switching mode liquid crystal display device
- FIG. 2 a is a plane view showing a first embodiment of the present invention
- FIG. 2 b and FIG. 2 c are respectively sectional views taken along line B-B′ and C-C′ of FIG. 2 a ;
- FIG. 3 is a view showing the operation of liquid crystal molecules in the first embodiment
- FIG. 4 is a view showing the alignment direction in the first embodiment
- FIG. 5 is a plane view of the TFT array structure of the present invention.
- FIG. 6 a and FIG. 6 b are respectively plane and sectional views showing the structure of the IPS mode LCD according to the present invention.
- FIG. 7 is a plane view of a second embodiment of the present invention.
- FIG. 8 is a view showing the alignment direction and the direction of first and second oblique sides of the second embodiment
- FIG. 9 a and FIG. 9 b are views showing the direction of electric field and the operation of LC molecules in the first and second embodiments respectively;
- FIG. 10 a is a plane view showing a third embodiment of the present invention.
- FIG. 10 b is a view showing the alignment direction and the direction of first and second oblique sides of the third embodiment
- FIG. 11 a is a plane view showing a fourth embodiment of the present invention.
- FIG. 11 b and FIG. 11 c are respectively sectional views taken along lines E-E′ and F-F′ of FIG. 11 a ;
- FIG. 12 is a plane view showing a fifth embodiment of the present invention.
- FIG. 2 a , FIG. 2 b and FIG. 2 c are views showing a first embodiment according to the present invention, where FIG. 2 b and FIG. 2 c are respectively sectional views taken along line B-B′ and line C-C′ of FIG. 2 a .
- gate and data bus lines 101 and 102 are formed on a first substrate 110 , defining a pixel. Although only one pixel is drawn in these figures, the liquid crystal display device generally has a plurality of pixels. In the pixel, a common bus line 103 is formed parallel to gate bus line 101 . At the intersection of gate and data bus lines 101 and 102 , a thin film transistor (TFT) is formed as shown in FIG.
- TFT thin film transistor
- a gate electrode 105 which comprises a gate electrode 105 , a gate insulator 112 , a semiconductor layer 115 , an n + semiconductor layer 116 , a source electrode 106 , and a drain electrodes 107 .
- data and common electrodes 108 and 109 are disposed parallel to data bus line 102 .
- a passivation layer 120 is formed, and common electrode 109 is formed thereon to be parallel to data electrode 108 and overlap gate and data bus lines 102 and 103 .
- a first alignment layer 123 a is formed.
- data electrode 108 has a portion overlapping common bus line 103 for obtaining a first storage capacitor (C st1 ) as shown in FIGS. 2 a and 2 c .
- common electrode 109 has a portion overlapping data electrode 108 for obtaining a second storage capacitor (C st2 )
- Common electrode 109 is connected to common bus line 103 through a first hole 125 which is formed in passivation layer 120 and gate insulator 112 .
- Common electrode 109 also overlaps gate and data bus lines 101 and 102 . Thus, it functions to block the electric effect of two bus lines 101 and 102 to prevent the crosstalk problem.
- Gate electrode 105 , gate bus line 101 , and common bus line 103 are formed by patterning double metal layers (Mo/Al) which is deposited by sputtering an Al layer having a thickness of 2000 ⁇ and a Mo layer having a thickness of 1000 ⁇ in the named order.
- Gate insulator 112 is formed thereon by depositing an inorganic insulating layer such as silicon nitride having a thickness of 4000 ⁇ by a chemical vapor deposition method.
- a semiconductor layer 115 and an n + semiconductor layer 116 are formed by depositing and etching an amorphous silicon (a-Si) layer having a thickness of 1700 ⁇ and an n + a-Si layer having a thickness of 300 ⁇ .
- Data bus line 102 , data electrode 108 , source electrode 106 , and drain electrode 107 are formed by depositing and etching a Cr metal layer having a thickness of 1500 ⁇ .
- the gate and data bus line may be formed of high conductive metal layers such as Mo metal layer, Mo/Al/Mo triple metal layers, or Cr/Al/Cr triple metal layers in order to prevent signal delay in the gate and data bus lines which is generated by being overlapped with the common electrode.
- the TFT and data electrode 108 are covered with a passivation layer 120 such as silicon oxide and silicon nitride having a thickness of 2000 ⁇ .
- a passivation layer 120 such as silicon oxide and silicon nitride having a thickness of 2000 ⁇ .
- common electrode 109 is formed by depositing and etching a transparent conducting layer such as indium tin oxide (ITO) having a thickness of 500 ⁇ .
- ITO indium tin oxide
- a first alignment layer 123 a is formed by coating polyimide or polyamide or photo-alignment materials.
- the polyimide or polyamide alignment layer is rubbed to impart an alignment direction thereto.
- the photo-alignment layer such as polyvinylcinnamate (PVCN) or polysiloxane based materials is exposed to an ultraviolet light to impart an alignment direction thereto.
- data and common electrodes 108 and 109 have portions for first and second storage capacitors whose capacitances are C st1 and C st2 respectively. Accordingly, the total storage capacitance (C st ) in the present invention becomes the sum of storage capacitances C st1 and C st2 .
- the storage capacitor (C st ) is double the conventional storage capacitor (C st1 ) so that the area for storage capacitor can be reduced to half the conventional area, thereby improving the aperture ratio.
- a black mask 128 and a color filter layer 129 are formed on a second substrate 111 .
- An overcoat layer may be formed thereon to flatten and stabilize the surface.
- Black mask 128 prevents a leakage of light through the regions of TFT and gate, data and common bus lines 101 , 102 , and 103 .
- Black mask 128 is made of a Cr or a CrOx metal layer having a thickness of 0.1 ⁇ m and a width of 10 ⁇ m.
- Color filter layer 129 has one of R, G, and B color filter elements in each pixel.
- a second alignment layer 123 b is formed by coating polyimide or photo-alignment materials. Second alignment layer 123 b is rubbed or exposed to UV light to impart an alignment direction.
- a liquid crystal layer 130 is inserted between two substrates 110 and 111 by injecting liquid crystal in vacuum state.
- FIG. 3 is a view showing the operation of liquid crystal molecules in the IPS mode LCD according to the present invention.
- FIG. 4 is a view showing the alignment direction, where the Y axis direction indicates the extension direction of data and common electrodes 108 and 109 , and ⁇ R indicates the angle between the alignment direction and the X axis direction, which is the extension direction of data bus line 102 .
- the liquid crystal molecules are aligned according to the alignment direction.
- electric field parallel to the substrates is generated between common and data electrodes 109 and 108 , and thereby liquid crystal molecules 132 rotates clockwise according to the electric field.
- a reference number 133 indicates the positions of the liquid crystal molecules after applying the voltage.
- FIG. 5 is a view showing the TFT array structure of the present invention.
- Gate and data bus lines 101 and 102 are connected to gate and data driving circuits through gate and data pads 151 and 155 respectively.
- Gate and data bus lines 101 and 102 are connected to a grounding wiring 165 through an electrostatic discharging circuit 167 composed of TFT.
- common bus line 103 is grounded through common pad 157 .
- gate, data and common pads 151 , 155 and 157 are made of first, second and third metal layers.
- the first metal layer is formed of Mo/Al double metal layers together with gate electrode 105 and common bus line 103 , as shown in FIGS. 2 a , 2 b , and 2 c .
- the second metal layer is formed of Cr together with source and drain electrode 106 and 107 .
- the third metal layer is formed of ITO together with common electrode 109 .
- gate insulator 112 and passivation layer 120 In order to connect the pads to the driving circuits, it is necessary to etch gate insulator 112 and passivation layer 120 in the pad region. The two insulating layers in the pad region are etched when hole 125 is formed.
- FIG. 6 a and FIG. 6 b are plane and sectional views showing the structure of the in-plane switching mode LCD consistent with the present invention, where FIG. 6 b is a sectional view taken along line D-D′ of FIG. 6 a .
- gate and data driving circuits 150 and 154 are disposed in a frame 145 outside display region 140 .
- Gate and data driving circuits 150 and 154 are connected to gate and data bus lines 101 and 102 through gate and data pads 151 and 154 respectively.
- a backlight housing 147 is disposed on the upper side of frame 145 .
- a backlight 148 is disposed to project a light into a liquid crystal panel 139 through a light pipe 149 .
- a polarizer 135 is disposed to polarize the light linearly.
- An analyzer 136 is disposed on the front of panel 139 .
- passivation layer 120 and gate insulator 112 do not absorb the electric field applied to liquid crystal layer 130 because common electrode 109 is disposed above two insulating layers 112 and 120 . Accordingly, the driving voltage is lowered.
- common electrode 109 is formed of ITO to obtain an IOP structure, the contacting electric resistance between the pads and the driving circuits is decreased, and the aperture ratio is improved.
- FIG. 7 is a view showing a second embodiment of the present invention.
- this embodiment differs from the first embodiment in that a common electrode 209 has first and second oblique sides 210 and 211 .
- FIG. 8 is a view showing the alignment direction and the direction of the first and second oblique sides of the second embodiment, where Y axis indicates the extension direction of the data electrode 108 .
- first oblique side 210 is inclined counterclockwise from the X axis with an angle ⁇ A .
- second oblique side 210 is inclined clockwise from the X axis with an angle ⁇ B .
- the alignment direction is determined to be inclined counterclockwise to X axis direction with an angle ⁇ R in the range of 0 to 90°.
- Angle ⁇ A is determined to be in the range of ⁇ R to 90°.
- the angle ⁇ B is determined to be in the range of 90° ⁇ R to 90°.
- the figures show a case where the angle ⁇ R is larger than 45°, and therefore the angle ⁇ A is larger than the angle ⁇ B .
- the angle ⁇ B is determined to be larger than the angle ⁇ A .
- the object of this embodiment is to prevent the problem of the first embodiment, in which disclination may be generated in the region where common electrode 209 crosses with data electrode 109 .
- the electric field is generated between common and data electrodes 108 and 109 as shown in FIG. 9 a .
- the direction of electric field is perpendicular to the extension direction of electrodes 108 and 109 .
- LC molecules 132 are given a clockwise turning force according to the electric field perpendicular to the extension direction of electrodes 108 and 109 , and thereby they rotate clockwise to be aligned perpendicular to the extension direction of the electrodes.
- regions A and B where common electrode 109 crosses with data electrode 108 an electric field is deformed not to be perpendicular to the extension direction of electrodes 108 and 109 .
- LC molecules 132 are aligned to be different from the middle region. Particularly in the region bounded by chain lines, the LC molecules are given with a counterclockwise turning force according to the deformed electric field, and thereby they rotate in opposite direction to those in the middle region. Consequently, in the border region denoted by chain lines, the alignment of LC molecules 132 is not defined, thereby generating disclination. Particularly when using liquid crystal having a low viscosity for lowering the driving voltage, since the interaction between LC molecules 132 is weak, a possibility of generating the disclination is increased to deteriorate the image quality. In this figure, reference number 133 denotes LC molecules after applying the voltage.
- common electrode 209 has first and second oblique sides 210 and 211 , as shown in FIG. 7, the electric field is slightly deformed in regions A and B, as shown in FIG. 9 b .
- the electric field gives a clockwise turning force to LC molecules 232 in regions A and B. Accordingly, although using liquid crystal having a low viscosity for lowering the driving voltage, LC molecules 232 in regions A and B rotate in the same direction with those in the middle region, thereby preventing the disclination.
- reference number 233 denotes LC molecules after applying the voltage.
- the second embodiment has an aperture ratio lower than the first embodiment, and however has a more improved image quality by preventing the disclination. In this case, it is preferable to form common electrode 209 out of ITO for improving the aperture ratio.
- FIG. 10 is a view showing a third embodiment. This embodiment is similar to the second embodiment except for angles ⁇ A and ⁇ B of common electrode 309 .
- angles ⁇ A , ⁇ B and ⁇ R are approximately 45°, 45°, and 75° respectively.
- region B because angle ⁇ B is in the range of 90° ⁇ R , to 90°, the LC molecules are given with a clockwise turning force, thereby not generating the disclination.
- region A since the angle ⁇ A is out of the range of ⁇ R to 90°, the LC molecules are given a counterclockwise turning force.
- the disclination is not generated in the region A because there is an interaction between the liquid crystal molecules when using a usual liquid crystal.
- FIGS. 11 a , 11 b , and 11 c are plane and sectional views showing the fourth embodiment, where FIGS. 11 b and 11 c are sectional views taken along lines E-E′ and F-F′ of FIG. 11 a respectively.
- data and common electrodes 108 and 409 have portions for first and second storage capacitors as in the previous embodiments.
- This embodiment differs from the previous embodiments in that the common electrode does not overlap gate and data bus lines 101 and 102 , and a light shielding electrode 160 is formed on passivation layer 120 in the region of the TFT.
- Common electrode 409 and light shielding electrode 160 are formed together by sputtering and etching Mo metal layer having a thickness of 1000 ⁇ . Because light shielding electrode 160 functions as a black mask for the TFT, as shown in FIG. 11 b, the black mask is not formed in the region of TFT.
- two electrodes 409 and 160 are formed of metal layers including ITO, and it is preferable that they are formed of a double layer ITO/Mo which is formed by depositing Mo metal layer and ITO in the named order.
- Light shielding electrode 160 is formed to overlap a portion of gate bus line 101 so as to be connected with gate bus line 101 through a second hole 161 formed in gate insulator 112 and passivation layer 120 . Accordingly, light shielding electrode 160 is provided with the same voltage as gate electrode 105 .
- light shielding electrode 160 overlaps the TFT with passivation layer 120 interposed therebetween in order to prevent a light incident on semiconductor layer 115 of the TFT. Accordingly, there is no need to form a black mask in the region of TFT, decreasing the fabricating cost. Further, the leakage current is prevented which is generated by excitation of semiconductor layer 115 when semiconductor layer 115 is exposed to light, so that a backlight having a high light intensity can be used improving the luminosity of the device.
- light shielding electrode 160 is connected with the gate bus line for obtaining the same voltage as gate electrode 105 , it functions as a back gate electrode increasing the switching current of the TFT. Accordingly, switching speed of the TFT is increased so that the same switching speed as the prior art can be obtained using TFT of relatively small size.
- FIG. 12 is a view showing a fifth embodiment. As shown in this figure, this embodiment is similar to the fourth embodiment except that a common electrode 509 overlaps gate and data bus lines 101 and 102 as in the first, second, and third embodiments.
- Common electrode 509 and a light shielding electrode 260 are formed of opaque metals as the fourth embodiment, and function as a light shielding layer so that there is no need to form a black mask in the regions of the TFT, and two bus lines 101 and 102 . Accordingly, the fabricating cost for the black mask is reduced, and prevented is the conventional problem in that the aperture ratio is lowered by having to compensate for imprecise lamination when forming the black mask on the second substrate. Further, as in the fourth embodiment, light shielding electrode 260 prevents a light incident on the active layer.
- a parasitic capacitor may be formed between the common electrode and the gate and data bus lines, causing the signal delay in the two bus lines.
- This signal delay problem can be eliminated by forming the gate and data bus lines out of low resistance metal layers such as Mo metal layer, Mo/Al/Mo triple metal layers or Cr/Al/Cr triple metal layers.
- the present invention is characterized in that the common electrode is formed on passivation layer 120 , and the data and common electrodes have portions for first and second storage capacitors. Accordingly, passivation layer 120 and gate insulator 112 do not absorb the electric field applied to liquid crystal layer 130 because the common electrode is disposed above two insulating layers 112 and 120 . Accordingly, the driving voltage is lowered. Further, because the areas for storage capacitor can be decreased, the aperture ratio is much more improved. Furthermore, because the common electrode is formed out of ITO for obtaining IOP structure, the contacting electric resistance between the pads and the driving circuits 16 decreased as well as the aperture ratio is improved.
- first, second, third, and fifth embodiments according to the present invention because the common electrode overlaps the gate and data bus lines to block the electric effect of the two bus lines, the crosstalk problem can be removed. Accordingly, the pixel region can be enlarged improving the aperture ratio.
- the light shielding electrode functions as a back gate electrode for increasing the switching speed of TFT, and prevents a leakage current caused by excitation of the active layer.
- the light shielding electrode and the common electrode function as a black mask, there is no need to form the black mask in the regions of TFT and the two bus lines 101 and 102 , removing the problems generated when forming the black mask on the second substrate.
Abstract
Description
- A. Field of the Invention
- The present invention relates to a liquid crystal display device, and more particularly to an in-plane switching mode liquid crystal display device.
- B. Description of the Related Art
- Recently, the thin film transistor liquid crystal display devices (TFT LCDs) have been used as display devices in such applications as portable televisions and notebook computers, but these TFT LCDs have small viewing angles.
- In order to solve this problem, twisted nematic LCDs having, for example, optical compensation plates and multi-domains, have been introduced. In these LCDs, however, the color of the image is shifted because the contrast ratio depends on the viewing angle direction.
- For a wide viewing angle, the in-plane switching mode LCD is disclosed, for example, in JAPAN DISPLAY 92 page 547, Japanese Patent Unexamined Publication No. 7-36058, Japanese Patent Unexamined Publication No. 7-225388, and ASIA DISPLAY 95 page 707.
- FIG. 1a and FIG. 1b are respectively plane and sectional views of the conventional in-plane switching mode liquid crystal display device (IPS mode LCD). FIG. 1b is a sectional view taken along line A-A′ of FIG. 1a. As shown in these figures, a gate bus line 1 and a data bus line 2 are formed on a
first substrate 10, defining a pixel. Although only one pixel is shown in the figures, a liquid crystal display device generally has a plurality of pixels. Acommon bus line 3 is aligned in the pixel, being parallel to gate bus line 1. A thin film transistor (TFT) is disposed at the intersection of gate and data bus lines 1 and 2. As shown in FIG. 1b, the TFT comprises agate electrode 5, agate insulator 12, asemiconductor layer 15, and an n+ semiconductor layer 16, asource electrode 6, and adrain electrode 7. In the pixel, adata electrode 8 and acommon electrode 9 are formed parallel to data bus line 2. A portion ofdata electrode 8 which overlapscommon bus line 3 is formed to obtain a storage capacitor, which functions as maintaining a grey level voltage applied intodata electrode 8. -
Common electrode 9 is connected tocommon bus line 3.Data electrode 8 is formed ongate insulator 12 and is connected todrain electrode 7. The TFT,data electrode 8 andgate insulator 12 are covered with apassivation layer 20. Thereon, afirst alignment layer 23 a is coated to determine the alignment direction. - On a
second substrate 11, ablack mask 28 is formed to prevent a leakage of light through the regions of the TFT and gate and data bus lines 1 and 2. Thereon, acolor filter layer 29 and asecond alignment layer 23 b are formed. Between first andsecond substrates liquid crystal layer 30 is formed. - When a voltage is applied to the conventional IPS mode LCD, electric field parallel to
substrates common electrodes liquid crystal layer 30. - However, the conventional IPS mode LCD has the following problems.
- First, because the area for storage capacitor occupies quite a portion of the pixel region and because the data and common electrodes are made of opaque metals, the aperture ratio is lowered.
- Second, because the electric field applied to the LC layer is weakened by both
gate insulator 12 andpassivation layer 20 formed over twoelectrodes - Third, because data bus line2 should be apart from the pixel region so as to avoid the crosstalk problem, the pixel region is decreased, thereby lowering the aperture ratio.
- Fourth, when the black mask is formed on the second substrate, the fabricating cost is increased and the aperture ratio is lowered to compensate for the imprecise lamination of the two substrates.
- An object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the aperture ratio is improved.
- Another object of the present invention is to provide an in-plane switching mode liquid crystal display device wherein the driving voltage is decreased.
- A further object of the present invention is to reduce the fabricating cost of provide an in-plane switching mode liquid crystal display device.
- Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
- To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the in-plane switching mode liquid crystal display device of the present invention comprises: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in the pixel regions; a gate insulator over the common bus line; a data electrode over the gate insulator and having a portion overlying the common bus line to form a first storage capacitor; a passivation layer over the data electrode; and a common electrode over the passivation layer at least partially overlying the gate and data bus lines and at least partially overlying the data electrode to form a second storage capacitor.
- According to another aspect of the present invention, the in-plane switching mode liquid crystal display device comprises: a substrate; a plurality of gate and data bus lines over the substrate, defining a plurality of pixel regions; a common bus line aligned in the pixel regions; a gate insulator over the common bus line; a thin film transistor coupled to each of the pixel regions and including at least a part of the gate insulator; a data electrode over the gate insulator and having a portion overlying the common bus line to form a first storage capacitor; a passivation layer over the data electrode and the thin film transistor; a common electrode over the passivation layer and at least partially overlying the data electrode to form a second storage capacitor; and a metal layer over the passivation layer and the thin film transistor.
- According to a further aspect of the present invention, the in-plane switching mode liquid crystal display device comprises: first and second substrates having a plurality of pixel regions; a common bus line aligned in the pixel regions; a first insulating layer over the common bus line; a data electrode over the first insulating layer and having a portion overlying the common bus line to form a first storage capacitor; a second insulating layer over the data electrode; a common electrode over the second insulating layer, the common electrode having one or more openings, at least one of the openings having a substantially rectangular shape with four corner areas, at least one corner area being cut at an angle, and the common electrode having a portion overlying the data electrode to form a second storage capacitor; and a liquid crystal layer formed between the first and second substrates.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the figures:
- FIG. 1a and FIG. 1b are respectively plane and sectional views of the conventional in-plane switching mode liquid crystal display device;
- FIG. 2a is a plane view showing a first embodiment of the present invention;
- FIG. 2b and FIG. 2c are respectively sectional views taken along line B-B′ and C-C′ of FIG. 2a ;
- FIG. 3 is a view showing the operation of liquid crystal molecules in the first embodiment;
- FIG. 4 is a view showing the alignment direction in the first embodiment;
- FIG. 5 is a plane view of the TFT array structure of the present invention;
- FIG. 6a and FIG. 6b are respectively plane and sectional views showing the structure of the IPS mode LCD according to the present invention;
- FIG. 7 is a plane view of a second embodiment of the present invention;
- FIG. 8 is a view showing the alignment direction and the direction of first and second oblique sides of the second embodiment;
- FIG. 9a and FIG. 9b are views showing the direction of electric field and the operation of LC molecules in the first and second embodiments respectively;
- FIG. 10a is a plane view showing a third embodiment of the present invention;
- FIG. 10b is a view showing the alignment direction and the direction of first and second oblique sides of the third embodiment;
- FIG. 11a is a plane view showing a fourth embodiment of the present invention;
- FIG. 11b and FIG. 11c are respectively sectional views taken along lines E-E′ and F-F′ of FIG. 11a ; and
- FIG. 12 is a plane view showing a fifth embodiment of the present invention.
- Hereinafter, in-plane switching mode LCDs according to the present invention are described in detail accompanying the figures.
- FIG. 2a, FIG. 2b and FIG. 2c are views showing a first embodiment according to the present invention, where FIG. 2b and FIG. 2c are respectively sectional views taken along line B-B′ and line C-C′ of FIG. 2a. As shown in these figures, gate and
data bus lines first substrate 110, defining a pixel. Although only one pixel is drawn in these figures, the liquid crystal display device generally has a plurality of pixels. In the pixel, acommon bus line 103 is formed parallel togate bus line 101. At the intersection of gate anddata bus lines gate electrode 105, agate insulator 112, asemiconductor layer 115, an n+ semiconductor layer 116, asource electrode 106, and adrain electrodes 107. In the pixel, data andcommon electrodes data bus line 102. Over the TFT anddata electrode 108, apassivation layer 120 is formed, andcommon electrode 109 is formed thereon to be parallel todata electrode 108 and overlap gate anddata bus lines common electrode 109 andpassivation layer 120, afirst alignment layer 123 a is formed. - As in the conventional IPS mode LCD,
data electrode 108 has a portion overlappingcommon bus line 103 for obtaining a first storage capacitor (Cst1) as shown in FIGS. 2a and 2 c. In addition,common electrode 109 has a portion overlappingdata electrode 108 for obtaining a second storage capacitor (Cst2)Common electrode 109 is connected tocommon bus line 103 through afirst hole 125 which is formed inpassivation layer 120 andgate insulator 112.Common electrode 109 also overlaps gate anddata bus lines bus lines -
Gate electrode 105,gate bus line 101, andcommon bus line 103 are formed by patterning double metal layers (Mo/Al) which is deposited by sputtering an Al layer having a thickness of 2000 Å and a Mo layer having a thickness of 1000 Å in the named order.Gate insulator 112 is formed thereon by depositing an inorganic insulating layer such as silicon nitride having a thickness of 4000 Å by a chemical vapor deposition method. Asemiconductor layer 115 and an n+ semiconductor layer 116 are formed by depositing and etching an amorphous silicon (a-Si) layer having a thickness of 1700 Å and an n+ a-Si layer having a thickness of 300 Å.Data bus line 102,data electrode 108,source electrode 106, anddrain electrode 107 are formed by depositing and etching a Cr metal layer having a thickness of 1500 Å. Also, the gate and data bus line may be formed of high conductive metal layers such as Mo metal layer, Mo/Al/Mo triple metal layers, or Cr/Al/Cr triple metal layers in order to prevent signal delay in the gate and data bus lines which is generated by being overlapped with the common electrode. - The TFT and
data electrode 108 are covered with apassivation layer 120 such as silicon oxide and silicon nitride having a thickness of 2000 Å. Onpassivation layer 120,common electrode 109 is formed by depositing and etching a transparent conducting layer such as indium tin oxide (ITO) having a thickness of 500 Å. - Over
common electrode 109 andpassivation layer 120, afirst alignment layer 123 a is formed by coating polyimide or polyamide or photo-alignment materials. The polyimide or polyamide alignment layer is rubbed to impart an alignment direction thereto. On the other hand, the photo-alignment layer such as polyvinylcinnamate (PVCN) or polysiloxane based materials is exposed to an ultraviolet light to impart an alignment direction thereto. - As shown in FIG. 2c, data and
common electrodes - As shown in FIG. 2b, on a
second substrate 111, ablack mask 128 and acolor filter layer 129 are formed. An overcoat layer may be formed thereon to flatten and stabilize the surface.Black mask 128 prevents a leakage of light through the regions of TFT and gate, data andcommon bus lines Black mask 128 is made of a Cr or a CrOx metal layer having a thickness of 0.1 μm and a width of 10 μm.Color filter layer 129 has one of R, G, and B color filter elements in each pixel. Oncolor filter layer 129, asecond alignment layer 123 b is formed by coating polyimide or photo-alignment materials.Second alignment layer 123 b is rubbed or exposed to UV light to impart an alignment direction. Aliquid crystal layer 130 is inserted between twosubstrates - FIG. 3 is a view showing the operation of liquid crystal molecules in the IPS mode LCD according to the present invention. FIG. 4 is a view showing the alignment direction, where the Y axis direction indicates the extension direction of data and
common electrodes data bus line 102. When a voltage is not applied to the device, the liquid crystal molecules are aligned according to the alignment direction. When a voltage is applied to the device, electric field parallel to the substrates is generated between common anddata electrodes liquid crystal molecules 132 rotates clockwise according to the electric field. In FIG. 3, areference number 133 indicates the positions of the liquid crystal molecules after applying the voltage. - FIG. 5 is a view showing the TFT array structure of the present invention. Gate and
data bus lines data pads data bus lines grounding wiring 165 through an electrostatic dischargingcircuit 167 composed of TFT. Alsocommon bus line 103 is grounded throughcommon pad 157. - Although not illustrated in the figure, gate, data and
common pads gate electrode 105 andcommon bus line 103, as shown in FIGS. 2a, 2 b, and 2 c. The second metal layer is formed of Cr together with source anddrain electrode common electrode 109. In order to connect the pads to the driving circuits, it is necessary to etchgate insulator 112 andpassivation layer 120 in the pad region. The two insulating layers in the pad region are etched whenhole 125 is formed. In the prior art, an oxide layer is generated on the pads by the exposure to the air, causing a problem that the contacting electric resistance is increased when connecting the pads to the driving circuits. However, in this embodiment, because the third metal layer of the pads is made of ITO to obtain an IOP (ITO On Passivation) structure, the above-mentioned problem is not generated. - FIG. 6a and FIG. 6b are plane and sectional views showing the structure of the in-plane switching mode LCD consistent with the present invention, where FIG. 6b is a sectional view taken along line D-D′ of FIG. 6a. As shown in these figures, gate and
data driving circuits frame 145outside display region 140. Gate anddata driving circuits data bus lines data pads backlight housing 147 is disposed on the upper side offrame 145. Inbacklight housing 147, abacklight 148 is disposed to project a light into aliquid crystal panel 139 through alight pipe 149. Betweenlight pipe 149 andliquid crystal panel 139, apolarizer 135 is disposed to polarize the light linearly. Ananalyzer 136 is disposed on the front ofpanel 139. - The advantages of the first embodiment according to the present invention are summarized as follows.
- First,
passivation layer 120 and gate insulator 112 (shown in FIGS. 2b and 2 c) do not absorb the electric field applied toliquid crystal layer 130 becausecommon electrode 109 is disposed above two insulatinglayers - Second, because the areas for storage capacitor can be decreased, the aperture ratio is much more improved.
- Third, because
common electrode 109 overlaps gate anddata bus lines bus lines - Fourth, because
common electrode 109 is formed of ITO to obtain an IOP structure, the contacting electric resistance between the pads and the driving circuits is decreased, and the aperture ratio is improved. - FIG. 7 is a view showing a second embodiment of the present invention. Hereinafter, constituent elements similar to those of the first embodiment are denoted by the same reference numbers. As shown in this figure, this embodiment differs from the first embodiment in that a
common electrode 209 has first and secondoblique sides data electrode 108. In region A of FIG. 7,first oblique side 210 is inclined counterclockwise from the X axis with an angle θA. In region B,second oblique side 210 is inclined clockwise from the X axis with an angle θB. The alignment direction is determined to be inclined counterclockwise to X axis direction with an angle θR in the range of 0 to 90°. Angle θA is determined to be in the range of θR to 90°. The angle θB is determined to be in the range of 90°−θR to 90°. The figures show a case where the angle θR is larger than 45°, and therefore the angle θA is larger than the angle θB. On the contrary, when the angle θR is smaller than 45°, the angle θB is determined to be larger than the angle θA. - The object of this embodiment is to prevent the problem of the first embodiment, in which disclination may be generated in the region where
common electrode 209 crosses withdata electrode 109. - In the first embodiment, the electric field is generated between common and
data electrodes electrodes LC molecules 132 are given a clockwise turning force according to the electric field perpendicular to the extension direction ofelectrodes common electrode 109 crosses withdata electrode 108, an electric field is deformed not to be perpendicular to the extension direction ofelectrodes electrodes LC molecules 132 are aligned to be different from the middle region. Particularly in the region bounded by chain lines, the LC molecules are given with a counterclockwise turning force according to the deformed electric field, and thereby they rotate in opposite direction to those in the middle region. Consequently, in the border region denoted by chain lines, the alignment ofLC molecules 132 is not defined, thereby generating disclination. Particularly when using liquid crystal having a low viscosity for lowering the driving voltage, since the interaction betweenLC molecules 132 is weak, a possibility of generating the disclination is increased to deteriorate the image quality. In this figure,reference number 133 denotes LC molecules after applying the voltage. - However, in the second embodiment, since
common electrode 209 has first and secondoblique sides LC molecules 232 in regions A and B. Accordingly, although using liquid crystal having a low viscosity for lowering the driving voltage,LC molecules 232 in regions A and B rotate in the same direction with those in the middle region, thereby preventing the disclination. In FIG. 9b,reference number 233 denotes LC molecules after applying the voltage. - The second embodiment has an aperture ratio lower than the first embodiment, and however has a more improved image quality by preventing the disclination. In this case, it is preferable to form
common electrode 209 out of ITO for improving the aperture ratio. - FIG. 10 is a view showing a third embodiment. This embodiment is similar to the second embodiment except for angles θA and θB of
common electrode 309. In this embodiment, angles θA, θB and θR are approximately 45°, 45°, and 75° respectively. In region B, because angle θB is in the range of 90°−θR, to 90°, the LC molecules are given with a clockwise turning force, thereby not generating the disclination. On the other hand, in region A, since the angle θA is out of the range of θR to 90°, the LC molecules are given a counterclockwise turning force. - However, the disclination is not generated in the region A because there is an interaction between the liquid crystal molecules when using a usual liquid crystal.
- FIGS. 11a, 11 b, and 11 c are plane and sectional views showing the fourth embodiment, where FIGS. 11b and 11 c are sectional views taken along lines E-E′ and F-F′ of FIG. 11a respectively.
- In this embodiment, as shown in these figures, data and
common electrodes data bus lines light shielding electrode 160 is formed onpassivation layer 120 in the region of the TFT.Common electrode 409 andlight shielding electrode 160 are formed together by sputtering and etching Mo metal layer having a thickness of 1000 Å. Becauselight shielding electrode 160 functions as a black mask for the TFT, as shown in FIG. 11b, the black mask is not formed in the region of TFT. To obtain an IOP structure, twoelectrodes Light shielding electrode 160 is formed to overlap a portion ofgate bus line 101 so as to be connected withgate bus line 101 through asecond hole 161 formed ingate insulator 112 andpassivation layer 120. Accordingly,light shielding electrode 160 is provided with the same voltage asgate electrode 105. - In this embodiment,
light shielding electrode 160 overlaps the TFT withpassivation layer 120 interposed therebetween in order to prevent a light incident onsemiconductor layer 115 of the TFT. Accordingly, there is no need to form a black mask in the region of TFT, decreasing the fabricating cost. Further, the leakage current is prevented which is generated by excitation ofsemiconductor layer 115 whensemiconductor layer 115 is exposed to light, so that a backlight having a high light intensity can be used improving the luminosity of the device. - In addition, since
light shielding electrode 160 is connected with the gate bus line for obtaining the same voltage asgate electrode 105, it functions as a back gate electrode increasing the switching current of the TFT. Accordingly, switching speed of the TFT is increased so that the same switching speed as the prior art can be obtained using TFT of relatively small size. - FIG. 12 is a view showing a fifth embodiment. As shown in this figure, this embodiment is similar to the fourth embodiment except that a
common electrode 509 overlaps gate anddata bus lines -
Common electrode 509 and alight shielding electrode 260 are formed of opaque metals as the fourth embodiment, and function as a light shielding layer so that there is no need to form a black mask in the regions of the TFT, and twobus lines light shielding electrode 260 prevents a light incident on the active layer. - In the first, second, third, and fifth embodiments, a parasitic capacitor may be formed between the common electrode and the gate and data bus lines, causing the signal delay in the two bus lines. This signal delay problem can be eliminated by forming the gate and data bus lines out of low resistance metal layers such as Mo metal layer, Mo/Al/Mo triple metal layers or Cr/Al/Cr triple metal layers.
- The present invention is characterized in that the common electrode is formed on
passivation layer 120, and the data and common electrodes have portions for first and second storage capacitors. Accordingly,passivation layer 120 andgate insulator 112 do not absorb the electric field applied toliquid crystal layer 130 because the common electrode is disposed above two insulatinglayers circuits 16 decreased as well as the aperture ratio is improved. - In first, second, third, and fifth embodiments according to the present invention, because the common electrode overlaps the gate and data bus lines to block the electric effect of the two bus lines, the crosstalk problem can be removed. Accordingly, the pixel region can be enlarged improving the aperture ratio.
- In fourth and fifth embodiments, the light shielding electrode functions as a back gate electrode for increasing the switching speed of TFT, and prevents a leakage current caused by excitation of the active layer. Particularly in the fifth embodiment, since the light shielding electrode and the common electrode function as a black mask, there is no need to form the black mask in the regions of TFT and the two
bus lines - It will be apparent to those skilled in the art that various modifications and variations can be made in the in plane switching mode liquid crystal display device of the present invention and in construction of this device without departing from the scope or spirit of the invention.
- Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims (33)
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KR1019970034196A KR100257976B1 (en) | 1997-07-22 | 1997-07-22 | An in-plane switching mode liquid crystal display device |
KR1997-34196 | 1997-07-22 | ||
KR1019970036569A KR100251655B1 (en) | 1997-07-31 | 1997-07-31 | In-plane switching mode lcd |
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US09/116,707 Expired - Lifetime US6335770B1 (en) | 1997-07-22 | 1998-07-17 | In-plane switching mode LCD with specific arrangement of common bus line, data electrode, and common electrode |
US09/116,707 Granted US20010055074A1 (en) | 1997-07-22 | 1998-07-17 | In-plane switching mode lcd with specific arrangement of common bus line, data electrode, and common electrode |
US09/613,730 Expired - Lifetime US6400436B1 (en) | 1997-07-22 | 2000-07-11 | In-plane switching mode liquid crystal display device with specific arrangement of common bus line, data electrode and common electrode |
US10/015,765 Expired - Lifetime US6803982B2 (en) | 1997-07-22 | 2001-12-17 | In-plane switching mode liquid crystal display device including common electrode on passivation layer which is formed over TFT and data electrode |
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US10/015,765 Expired - Lifetime US6803982B2 (en) | 1997-07-22 | 2001-12-17 | In-plane switching mode liquid crystal display device including common electrode on passivation layer which is formed over TFT and data electrode |
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JP2973934B2 (en) * | 1996-07-11 | 1999-11-08 | 日本電気株式会社 | Liquid crystal display device and electronic equipment equipped with liquid crystal display device |
JP2701832B2 (en) * | 1996-07-31 | 1998-01-21 | 株式会社日立製作所 | Liquid crystal display |
KR100264238B1 (en) * | 1996-10-21 | 2000-08-16 | 윤종용 | Ips type lcd |
JPH10142635A (en) * | 1996-11-15 | 1998-05-29 | Furontetsuku:Kk | Liquid crystal display device |
KR100250796B1 (en) * | 1996-11-29 | 2000-04-01 | 김영환 | Liquid crystal display element and its manufacturing method |
KR100257369B1 (en) * | 1997-05-19 | 2000-05-15 | 구본준 | In plane switching mode liquid crystal display device |
JP4024901B2 (en) | 1997-05-22 | 2007-12-19 | エルジー フィリップス エルシーディー カンパニー リミテッド | Active matrix type liquid crystal display device |
JP3966614B2 (en) * | 1997-05-29 | 2007-08-29 | 三星電子株式会社 | Wide viewing angle LCD |
JP3022463B2 (en) * | 1998-01-19 | 2000-03-21 | 日本電気株式会社 | Liquid crystal display device and method of manufacturing the same |
KR100293811B1 (en) * | 1998-05-29 | 2001-10-26 | 박종섭 | Ips mode liquid crystal display device |
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-
1998
- 1998-07-17 US US09/116,707 patent/US6335770B1/en not_active Expired - Lifetime
- 1998-07-17 US US09/116,707 patent/US20010055074A1/en active Granted
-
2000
- 2000-07-11 US US09/613,730 patent/US6400436B1/en not_active Expired - Lifetime
-
2001
- 2001-12-17 US US10/015,765 patent/US6803982B2/en not_active Expired - Lifetime
Cited By (4)
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US20060232720A1 (en) * | 2005-04-19 | 2006-10-19 | Samsung Electronics Co., Ltd. | Array substrate, method of manufacturing the same and liquid crystal display panel having the same |
US7639313B2 (en) * | 2005-04-19 | 2009-12-29 | Samsung Electronics Co., Ltd. | Array substrate with switching device and storage electrode part formed of a common line and blocking common electrode on the same plane and having an oblique side parallel with transmission axis of polarizing plate |
US8711303B2 (en) | 2010-09-13 | 2014-04-29 | Samsung Display Co., Ltd. | Liquid crystal display panel |
CN105301855A (en) * | 2015-09-09 | 2016-02-03 | 友达光电股份有限公司 | Pixel structure and pixel array |
Also Published As
Publication number | Publication date |
---|---|
US6803982B2 (en) | 2004-10-12 |
US6400436B1 (en) | 2002-06-04 |
US6335770B1 (en) | 2002-01-01 |
US20020067455A1 (en) | 2002-06-06 |
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