US20010053057A1 - Capacitor with conductively doped Si-Ge alloy electrode - Google Patents
Capacitor with conductively doped Si-Ge alloy electrode Download PDFInfo
- Publication number
- US20010053057A1 US20010053057A1 US09/846,520 US84652001A US2001053057A1 US 20010053057 A1 US20010053057 A1 US 20010053057A1 US 84652001 A US84652001 A US 84652001A US 2001053057 A1 US2001053057 A1 US 2001053057A1
- Authority
- US
- United States
- Prior art keywords
- capacitor
- capacitor electrode
- silicon
- forming
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Definitions
- This invention relates to capacitors, to methods of forming capacitors, and to DRAM cells.
- DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area.
- One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
- Densification of Ta 2 O 5 as deposited has been reported to significantly improve the leakage characteristics of such layers to acceptable levels.
- Prior art densification of such layers includes exposing the Ta 2 O 5 layer to extreme annealing and oxidizing conditions.
- the anneal drives any carbon present out of the layer and advantageously injects additional oxygen into the layer such that the layer uniformly approaches a stoichiometry of five oxygen atoms for every two tantalum atoms.
- the oxygen anneal is commonly conducted at a temperature of from about 400° C. to about 1000° C. utilizing an ambient comprising an oxygen containing gas.
- the oxygen containing gas commonly comprises one or more of O 3 , NO, N 2 O and O 2 .
- the oxygen containing gas is typically flowed through a reactor at a rate of from about 0.5 slm to about 10 slm.
- the Ta 2 O 5 layer is typically from about 40 angstroms to about 150 angstroms thick and can be either amorphous or crystalline.
- Ta 2 O 5 is generally amorphous if formed below 600° C. and will be crystalline if formed, or later processed, at or above 600° C.
- a Ta 2 O 5 layer is deposited as an amorphous layer and the above-described oxygen anneal is conducted at a temperature of 600° C. or greater to convert the amorphous Ta 2 O 5 layer to a crystalline layer.
- a thin SiO 2 layer will also typically inherently form during the Ta 2 O 5 deposition due to the presence of oxygen at the polysilicon layer interface. It would be desirable to remove or eliminate this SiO 2 layer intermediate the Ta 2 O 5 and polysilicon layers, yet allow for such desired densification.
- One prior art technique reported includes exposing the polysilicon layer to rapid thermal nitridation prior to subsequent deposition of the Ta 2 O 5 layer.
- rapid thermal nitridation includes exposing the subject polysilicon layer to temperatures of from 800° C.
- the nitride layer acts as a barrier layer to oxidation during Ta 2 O 5 deposition and subsequent high temperature densification processes to prevent oxidation of the underlying polysilicon electrode.
- These processes do however have several drawbacks, including the undesired high temperature cycling and formation of a fairly thick native SiO 2 on the nitride in series with the Ta 2 O 5 , all of which adversely effects the realization of high capacitance promised by inherent Ta 2 O 5 layers.
- a capacitor comprises a capacitor dielectric layer comprising Ta 2 O 5 formed over a first capacitor electrode.
- a second capacitor electrode is formed over the Ta 2 O 5 capacitor dielectric layer.
- at least a portion of the second capacitor electrode is formed over and in contact with the Ta 2 O 5 in an oxygen containing environment at a temperature of at least about 175° C.
- Chemical vapor deposition is one example forming method.
- the preferred second capacitor electrode comprises a conductive metal oxide.
- a more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer.
- a preferred first capacitor electrode comprises a conductively doped Si—Ge alloy.
- a Si 3 N 4 layer is formed over the first capacitor electrode.
- FIG. 1 is a diagrammatic depiction of a capacitor stack in accordance with one aspect of the invention.
- FIG. 2 is a diagrammatic depiction of another capacitor stack in accordance with one aspect of the invention.
- FIG. 3 is a diagrammatic depiction of yet another capacitor stack in accordance with one aspect of the invention.
- FIG. 4 is a diagrammatic depiction of still another capacitor stack in accordance with one aspect of the invention.
- FIG. 5 is a view an alternate embodiment semiconductor wafer fragment in accordance with the invention.
- FIG. 1 diagrammatically depicts a capacitor stack 10 which would be formed over a substrate.
- substrate is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substrate refers to any supporting structure, including but not limited to, the semiconductive substrates described above.
- Capacitor 10 comprises a first capacitor electrode 12 , a capacitor dielectric layer 14 , and a second capacitor electrode 15 .
- first capacitor electrode 12 comprises silicon material 16 , such as elemental silicon in polycrystalline form which is suitably conductively doped with desired dopant impurities. Such can be formed, for example, by chemical vapor deposition using SiH 4 as a precursor gas at a temperature of 535° C. and a pressure of 200 mTorr. Doping can occur during or after deposition. An example preferred thickness range for layer 12 is from 400 Angstroms to 1000 Angstroms. Electrode 12 could of course constitute some other conductive material. Further, electrode 12 could comprise a composite of conductive materials, such as by way of example only Ru or RuO x formed over conductively doped silicon.
- Capacitor dielectric layer 14 is preferably formed over and in contact with electrode 12 , and preferably comprises Ta 2 O 5 material 18 . Where electrode 12 comprises silicon, an intervening oxidation barrier layer (not shown) is ideally provided intermediate the Ta 2 O 5 and silicon.
- Example conductive oxidation barrier layers include RuO x and Ru.
- Ta 2 O 5 can be deposited by low pressure chemical vapor deposition utilizing Ta(C 3 H 5 ) 5 , O 2 and N 2 as precursor gases.
- Example flow rates are 120 sccm; 2-5 slm; and 2-5 slm, respectively.
- An example temperature is 410° C., with an example pressure being from 200 to 400 mTorr.
- An example deposition thickness is from 60 to 90 Angstroms, with 70 Angstroms being preferred.
- the Ta 2 O 5 layer is thereafter preferably subjected to a high temperature oxidation anneal by any one of the following processes, or other processes.
- rapid thermal processing is conducted over 40 seconds up to a temperature of 850° C. in a N 2 O ambient, with pressure being 660 Torr. Processing continues at 850° C. and 660 Torr for one minute.
- furnace heating is conducted to 800° C. at a temperature increase rate of 7° C./min. in a N 2 O ambient, with pressure remaining at atmospheric and the wafer being maintained at 800° C. for 30 minutes.
- a higher pressure oxidation is conducted at 800° C. for 30 minutes in a N 2 O atmosphere at a pressure from 1 to 3 atmospheres, with the temperature being ramped to 800° C. at an approximate rate of 15° C./min.
- Second capacitor electrode 15 is preferably formed over and in contact with Ta 2 O 5 material 18 of capacitor dielectric layer 14 . Such preferably is formed in an oxygen-containing environment at a temperature of at least about 175° C. Second capacitor electrode 14 preferably comprises a conductive metal oxide material 20 formed to a thickness of from about 400 Angstroms to about 1000 Angstroms. In the context of this document, a conductive metal oxide is any oxide having a resistance of less than or equal to about microohms.cm.
- Example materials include RuO 2 , IrO 2 , SnO 2 , In 2 O 3 :SnO 2 , VO 3 , CuO, Cu 2 O, and mixtures thereof. RuO 2 and IrO 2 are more preferred.
- An example process for forming such conductive metal oxide is by chemical vapor deposition.
- RuO x an example deposition process would be conducted at a pressure of 1 Torr and a temperature of 175° C., with precursor feeds of Ru(tricarbonyl cyclohexdienyl) at 300 sccm and O 2 at 300 sccm.
- second capacitor electrode 15 a comprises a conductive silicon comprising layer 23 formed over and in contact with a conductive titanium comprising layer 22 (i.e., Ti or TiN), formed over and in contact with conductive metal oxide layer 20 a.
- Conductive metal oxide layer 20 a is also formed over and preferably in contact with Ta 2 O 5 material 18 of capacitor dielectric layer 14 .
- second capacitor electrode 15 a comprises both conductive silicon and a conductive metal oxide.
- a titanium comprising layer 22 is provided intermediate conductive metal oxide layer 20 a and conductive silicon layer 23 .
- the preferred material for titanium-comprising layer 22 is TiN formed by chemical vapor deposition using an organic precursor.
- An example process utilizes precursors of ((CH 3 ) 2 N) 4 Ti at 150 sccm and N 2 at 80 sccm at a temperature of 420° C. and a pressure of 0.7 Torr.
- Silicon layer 23 preferably comprises conductively doped elemental polycrystalline silicon, with thus both the first and second capacitor electrodes comprising silicon.
- An example thickness for TiN layer 22 is from 150 Angstroms to 300 Angstroms.
- An example thickness for silicon layer 23 is from 400 Angstroms to 1000 Angstroms.
- capacitor stack 10 b is shown in FIG. 3. Like numerals from the first described embodiments are utilized where appropriate, with differences being indicated by the suffix “b” or with different numerals.
- silicon material 16 b of first capacitor electrode 12 b is subjected to rapid thermal nitridation to form a silicon nitride layer 26 atop material 16 b and in contact with Ta 2 O 5 material 18 .
- the capacitor dielectric layer 14 b essentially comprises a combination of the Ta 2 O 5 and Si 3 N 4 .
- the nitridation is ideally conducted prior to formation of the Ta 2 O 5 , and functions as a diffusion restricting or barrier layer to formation of SiO 2 during deposition of Ta 2 O 5 material 18 .
- Thickness of layer 26 is preferably from 30 Angstroms to 60 Angstroms.
- Exemplary rapid thermal nitridation conditions include exposing the substrate to a NH 3 atmosphere at a flow rate of from about 10 to 20 sccm for 20 seconds at atmospheric pressure and 900-950° C.
- rapid thermal nitridation is intended to define any process where a substrate is ramped to a temperature of at least 900° C. at a rate of 20° C./sec in a nitrogen containing environment.
- Second capacitor electrode 15 b is formed to provide silicon both as polycrystalline silicon and as a silicide. Specifically, a silicide layer 24 is formed over silicon layer 23 b.
- Example techniques include a refractory metal deposition and conventional salicide process, or direct chemical vapor deposition of a silicide.
- Example precursor gases for chemical vapor depositing WSi x include WF 6 and WSH 4 .
- An example preferred thickness for silicide layer 24 is from about 300 Angstroms to 600 Angstroms.
- first capacitor electrode 12 c comprises a conductively doped silicon-germanium alloy material 16 c.
- the capacitor dielectric layer comprises Ta 2 O 5
- the capacitor dielectric layer comprises Ta 2 O 5
- a conductive metal oxide is formed in contact with Ta 2 O 5 , reduction of the Ta 2 O 5 can be avoided or at least reduced.
- FIG. 5 depicts implementation of the invention in fabrication of DRAM circuitry.
- a wafer fragment 31 comprises two memory cells, with each comprising a capacitor 36 and a shared bit contact 46 .
- Capacitors 36 electrically connect with substrate diffusion regions 34 through silicide regions 33 .
- capacitors 36 are shown as comprising a first capacitor electrode 38 , a capacitor dielectric layer 40 , and a second capacitor electrode/cell plate 42 .
- Such can be fabricated of materials described above, preferably to include silicon, barrier layers metal oxide, and a high K oxygen containing capacitor dielectric layers such as Ta 2 O 5 . Processing preferably occurs as described above.
- a dielectric layer 44 is formed over second capacitor plate 42 .
- a bit line 47 is fabricated in electrical connection with bit contact 46 .
- Word lines 48 are fabricated to enable selective gating of the capacitors relative to bit contact 47 .
Abstract
Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.
Description
- This invention relates to capacitors, to methods of forming capacitors, and to DRAM cells.
- As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors.
- Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO2 and Si3N4 might not be suitable because of small dielectric constants.
- Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO2 equivalent thickness. Chemical vapor deposited (CVD) Ta2O5 films are considered to- be very promising cell dielectric layers for this purpose, as the dielectric constant of Ta2O5 is approximately three times that of conventional Si3N4 capacitor dielectric layers. However, one drawback associated with Ta2O5 dielectric layers is undesired leakage current characteristics. Accordingly, although Ta2O5 material has inherently higher dielectric properties, as-deposited Ta2O5 typically produces unacceptable results due to leakage current.
- Densification of Ta2O5 as deposited has been reported to significantly improve the leakage characteristics of such layers to acceptable levels. Prior art densification of such layers includes exposing the Ta2O5 layer to extreme annealing and oxidizing conditions. The anneal drives any carbon present out of the layer and advantageously injects additional oxygen into the layer such that the layer uniformly approaches a stoichiometry of five oxygen atoms for every two tantalum atoms. The oxygen anneal is commonly conducted at a temperature of from about 400° C. to about 1000° C. utilizing an ambient comprising an oxygen containing gas. The oxygen containing gas commonly comprises one or more of O3, NO, N2O and O2. The oxygen containing gas is typically flowed through a reactor at a rate of from about 0.5 slm to about 10 slm.
- The Ta2O5 layer is typically from about 40 angstroms to about 150 angstroms thick and can be either amorphous or crystalline. Ta2O5 is generally amorphous if formed below 600° C. and will be crystalline if formed, or later processed, at or above 600° C. Typically, a Ta2O5 layer is deposited as an amorphous layer and the above-described oxygen anneal is conducted at a temperature of 600° C. or greater to convert the amorphous Ta2O5 layer to a crystalline layer. Undesirably, however, such has a tendency to form an SiO2 layer intermediate or between the polysilicon and Ta2O5. Further and regardless, a thin SiO2 layer will also typically inherently form during the Ta2O5 deposition due to the presence of oxygen at the polysilicon layer interface. It would be desirable to remove or eliminate this SiO2 layer intermediate the Ta2O5 and polysilicon layers, yet allow for such desired densification.
- One prior art technique reported includes exposing the polysilicon layer to rapid thermal nitridation prior to subsequent deposition of the Ta2O5 layer. Such are reported by Kamiyama et al., “Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation prior to Low Pressure Chemical Vapor Deposition”, J. Electrochem. Soc., Vol. 140, No. 6, June 1993 and Kamiyama et al., “Highly Reliable 2.5 nm Ta2O5 Capacitor Process Technology for 256 Mbit DRAMs”, 830-IEDM 91, pp. 32.2.1-32.2.4. Such rapid thermal nitridation includes exposing the subject polysilicon layer to temperatures of from 800° C. to 1100° C. for sixty seconds in an ammonia atmosphere at atmospheric pressure. The nitride layer acts as a barrier layer to oxidation during Ta2O5 deposition and subsequent high temperature densification processes to prevent oxidation of the underlying polysilicon electrode. These processes do however have several drawbacks, including the undesired high temperature cycling and formation of a fairly thick native SiO2 on the nitride in series with the Ta2O5, all of which adversely effects the realization of high capacitance promised by inherent Ta2O5 layers.
- The invention comprises capacitors, methods of forming capacitors and DRAM circuitry. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode.
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
- FIG. 1 is a diagrammatic depiction of a capacitor stack in accordance with one aspect of the invention.
- FIG. 2 is a diagrammatic depiction of another capacitor stack in accordance with one aspect of the invention.
- FIG. 3 is a diagrammatic depiction of yet another capacitor stack in accordance with one aspect of the invention.
- FIG. 4 is a diagrammatic depiction of still another capacitor stack in accordance with one aspect of the invention.
- FIG. 5 is a view an alternate embodiment semiconductor wafer fragment in accordance with the invention.
- This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
- FIG. 1 diagrammatically depicts a
capacitor stack 10 which would be formed over a substrate. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including but not limited to, the semiconductive substrates described above. -
Capacitor 10 comprises afirst capacitor electrode 12, a capacitordielectric layer 14, and asecond capacitor electrode 15. In the illustrated example,first capacitor electrode 12 comprisessilicon material 16, such as elemental silicon in polycrystalline form which is suitably conductively doped with desired dopant impurities. Such can be formed, for example, by chemical vapor deposition using SiH4 as a precursor gas at a temperature of 535° C. and a pressure of 200 mTorr. Doping can occur during or after deposition. An example preferred thickness range forlayer 12 is from 400 Angstroms to 1000 Angstroms. Electrode 12 could of course constitute some other conductive material. Further,electrode 12 could comprise a composite of conductive materials, such as by way of example only Ru or RuOx formed over conductively doped silicon. - Capacitor
dielectric layer 14 is preferably formed over and in contact withelectrode 12, and preferably comprises Ta2O5 material 18. Whereelectrode 12 comprises silicon, an intervening oxidation barrier layer (not shown) is ideally provided intermediate the Ta2O5 and silicon. Example conductive oxidation barrier layers include RuOx and Ru. Ta2O5 can be deposited by low pressure chemical vapor deposition utilizing Ta(C3H5)5, O2 and N2 as precursor gases. Example flow rates are 120 sccm; 2-5 slm; and 2-5 slm, respectively. An example temperature is 410° C., with an example pressure being from 200 to 400 mTorr. An example deposition thickness is from 60 to 90 Angstroms, with 70 Angstroms being preferred. The Ta2O5 layer is thereafter preferably subjected to a high temperature oxidation anneal by any one of the following processes, or other processes. In a first, rapid thermal processing is conducted over 40 seconds up to a temperature of 850° C. in a N2O ambient, with pressure being 660 Torr. Processing continues at 850° C. and 660 Torr for one minute. In a second process, furnace heating is conducted to 800° C. at a temperature increase rate of 7° C./min. in a N2O ambient, with pressure remaining at atmospheric and the wafer being maintained at 800° C. for 30 minutes. In a third, a higher pressure oxidation is conducted at 800° C. for 30 minutes in a N2O atmosphere at a pressure from 1 to 3 atmospheres, with the temperature being ramped to 800° C. at an approximate rate of 15° C./min. -
Second capacitor electrode 15 is preferably formed over and in contact with Ta2O5 material 18 ofcapacitor dielectric layer 14. Such preferably is formed in an oxygen-containing environment at a temperature of at least about 175° C.Second capacitor electrode 14 preferably comprises a conductivemetal oxide material 20 formed to a thickness of from about 400 Angstroms to about 1000 Angstroms. In the context of this document, a conductive metal oxide is any oxide having a resistance of less than or equal to about microohms.cm. Example materials include RuO2, IrO2, SnO2, In2O3:SnO2, VO3, CuO, Cu2O, and mixtures thereof. RuO2 and IrO2 are more preferred. An example process for forming such conductive metal oxide is by chemical vapor deposition. For RuOx, an example deposition process would be conducted at a pressure of 1 Torr and a temperature of 175° C., with precursor feeds of Ru(tricarbonyl cyclohexdienyl) at 300 sccm and O2 at 300 sccm. - Referring to FIG. 2, a second
embodiment capacitor stack 10 a is shown. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “a” or with different numerals. Here,second capacitor electrode 15 a comprises a conductivesilicon comprising layer 23 formed over and in contact with a conductive titanium comprising layer 22 (i.e., Ti or TiN), formed over and in contact with conductivemetal oxide layer 20 a. Conductivemetal oxide layer 20 a is also formed over and preferably in contact with Ta2O5 material 18 ofcapacitor dielectric layer 14. Accordingly,second capacitor electrode 15 a comprises both conductive silicon and a conductive metal oxide. Atitanium comprising layer 22 is provided intermediate conductivemetal oxide layer 20 a andconductive silicon layer 23. The preferred material for titanium-comprisinglayer 22 is TiN formed by chemical vapor deposition using an organic precursor. An example process utilizes precursors of ((CH3)2N)4Ti at 150 sccm and N2 at 80 sccm at a temperature of 420° C. and a pressure of 0.7 Torr.Silicon layer 23 preferably comprises conductively doped elemental polycrystalline silicon, with thus both the first and second capacitor electrodes comprising silicon. An example thickness forTiN layer 22 is from 150 Angstroms to 300 Angstroms. An example thickness forsilicon layer 23 is from 400 Angstroms to 1000 Angstroms. - Yet another alternate
embodiment capacitor stack 10 b is shown in FIG. 3. Like numerals from the first described embodiments are utilized where appropriate, with differences being indicated by the suffix “b” or with different numerals. Here,silicon material 16 b offirst capacitor electrode 12 b is subjected to rapid thermal nitridation to form asilicon nitride layer 26 atopmaterial 16 b and in contact with Ta2O5 material 18. Thereby, thecapacitor dielectric layer 14 b essentially comprises a combination of the Ta2O5 and Si3N4. The nitridation is ideally conducted prior to formation of the Ta2O5, and functions as a diffusion restricting or barrier layer to formation of SiO2 during deposition of Ta2O5 material 18. Thickness oflayer 26 is preferably from 30 Angstroms to 60 Angstroms. Exemplary rapid thermal nitridation conditions include exposing the substrate to a NH3 atmosphere at a flow rate of from about 10 to 20 sccm for 20 seconds at atmospheric pressure and 900-950° C. In the context of this document, rapid thermal nitridation is intended to define any process where a substrate is ramped to a temperature of at least 900° C. at a rate of 20° C./sec in a nitrogen containing environment. -
Second capacitor electrode 15 b is formed to provide silicon both as polycrystalline silicon and as a silicide. Specifically, asilicide layer 24 is formed oversilicon layer 23 b. Example techniques include a refractory metal deposition and conventional salicide process, or direct chemical vapor deposition of a silicide. Example precursor gases for chemical vapor depositing WSix include WF6 and WSH4. An example preferred thickness forsilicide layer 24 is from about 300 Angstroms to 600 Angstroms. - Still a further alternate
embodiment capacitor stack 10 c is described with reference to FIG. 4. Like numerals from the first described embodiments have been utilized where appropriate, with differences being indicated by the suffix “c” or with different numerals. Here,first capacitor electrode 12 c comprises a conductively doped silicon-germanium alloy material 16 c. - In each of the above described preferred embodiments where at least one of the first and second capacitor electrodes comprises titanium, no titanium-comprising material of either the first and second capacitor electrodes is formed in contact with the Ta2O5 material of the capacitor dielectric layer. Where the capacitor dielectric layer comprises Ta2O5, preferably such effectively gets heated in an oxygen rich atmosphere during top electrode deposition, which can minimize oxygen vacancy content in the Ta2O5. Where a conductive metal oxide is formed in contact with Ta2O5, reduction of the Ta2O5 can be avoided or at least reduced.
- FIG. 5 depicts implementation of the invention in fabrication of DRAM circuitry. A
wafer fragment 31 comprises two memory cells, with each comprising acapacitor 36 and a sharedbit contact 46.Capacitors 36 electrically connect withsubstrate diffusion regions 34 throughsilicide regions 33. For simplicity,capacitors 36 are shown as comprising afirst capacitor electrode 38, acapacitor dielectric layer 40, and a second capacitor electrode/cell plate 42. Such can be fabricated of materials described above, preferably to include silicon, barrier layers metal oxide, and a high K oxygen containing capacitor dielectric layers such as Ta2O5. Processing preferably occurs as described above. Adielectric layer 44 is formed oversecond capacitor plate 42. Abit line 47 is fabricated in electrical connection withbit contact 46.Word lines 48 are fabricated to enable selective gating of the capacitors relative tobit contact 47. - In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (51)
1. A capacitor comprising:
a first capacitor electrode;
a capacitor dielectric layer comprising Ta2O5 over the first capacitor electrode; and
a second capacitor electrode over the Ta2O5 capacitor dielectric layer, the second capacitor electrode comprising a conductive metal oxide in contact with the Ta2O5.
2. The capacitor of wherein the second capacitor electrode comprises titanium in addition to the conductive metal oxide.
claim 1
3. The capacitor of wherein the titanium comprises elemental titanium.
claim 2
4. The capacitor of wherein the titanium comprises TiN.
claim 2
5. The capacitor of wherein the second capacitor electrode comprises titanium and silicon in addition to the conductive metal oxide.
claim 1
6. The capacitor of wherein the silicon is present both as polycrystalline silicon and as silicide.
claim 5
7. The capacitor of wherein the first capacitor electrode comprises silicon.
claim 1
8. The capacitor of wherein the first capacitor electrode comprises elemental silicon.
claim 1
9. The capacitor of wherein the Ta2O5 is formed in contact with the first capacitor electrode.
claim 1
10. The capacitor of wherein the conductive metal oxide is selected from the group consisting of RuO2, IrO2 and mixtures thereof.
claim 1
11. A method of forming a capacitor comprising:
forming a first capacitor electrode over a substrate;
forming a capacitor dielectric layer comprising Ta2O5 over the first capacitor electrode; and
chemical vapor depositing a conductive metal oxide onto the Ta2O5.
12. The method of wherein the first capacitor electrode is formed to comprise silicon, and further comprising rapid thermal nitridizing the first capacitor electrode and forming a silicon nitride layer, the Ta2O5 of the capacitor dielectric layer being formed in contact with the silicon nitride.
claim 11
13. The method of comprising forming the conductive metal oxide into a second capacitor electrode, and further comprising providing the second capacitor electrode to comprise titanium in addition to the conductive metal oxide.
claim 11
14. The method of comprising forming the conductive metal oxide into a second capacitor electrode, and further comprising providing the second capacitor electrode to comprise titanium and silicon in addition to the conductive metal oxide.
claim 11
15. The method of comprising forming the silicon to comprise both polycrystalline silicon and silicide.
claim 14
16. The method of wherein,
claim 11
the first capacitor electrode is formed to comprise silicon, and further comprising rapid thermal nitridizing the first capacitor electrode and forming a silicon nitride layer, the Ta2O5 of the capacitor dielectric layer being formed in contact with the silicon nitride; and
forming the conductive metal oxide into a second capacitor electrode, and further comprising providing the second capacitor electrode to comprise titanium and silicon in addition to the conductive metal oxide, the silicon of the second capacitor electrode comprising both polycrystalline silicon and a silicide, the titanium comprising titanium nitride, the polycrystalline silicon and being formed over the titanium nitride, the silicide being formed over the polycrystalline silicon.
17. A method of forming a capacitor comprising:
forming a first capacitor electrode over a substrate;
forming a capacitor dielectric layer comprising Ta2O5 over the first capacitor electrode; and
forming at least a portion of a second capacitor electrode over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C.
18. The method of comprising forming the second capacitor electrode to comprise a conductive metal oxide.
claim 17
19. The method of comprising forming the second capacitor electrode by chemical vapor deposition.
claim 17
20. A capacitor comprising:
a first capacitor electrode comprising a conductively doped Si—Ge alloy;
a Si3N4 layer over the first capacitor electrode;
a capacitor dielectric layer comprising Ta2O5 over the Si3N4 layer; and
a second capacitor electrode over the Ta2O5 capacitor dielectric layer.
21. The capacitor of wherein the Si3N4 layer is less than or equal to about 50 Angstroms thick.
claim 20
22. The capacitor of wherein the second capacitor electrode comprises a conductive metal oxide.
claim 20
23. The capacitor of wherein the Si3N4 is formed in contact with the Si—Ge alloy.
claim 20
24. The capacitor of wherein the Ta2O5 is formed in contact with the Si3N4.
claim 20
25. The capacitor of wherein the Si3N4 is formed in contact with the Si—Ge alloy, and the Ta2O5 is formed in contact with the Si3N4.
claim 20
26. The capacitor of wherein the second capacitor electrode comprises a conductive metal oxide, the Si3N4 is formed in contact with the Si—Ge alloy, and the Ta2O5 is formed in contact with the Si3N4.
claim 20
27. A method of forming a capacitor comprising:
forming a first capacitor electrode comprising a conductively doped Si—Ge alloy;
rapid thermal nitridizing the first capacitor electrode and forming Si3N4 to a thickness less than about 60 Angstroms;
forming a capacitor dielectric layer comprising Ta2O5 over the Si3N4 layer; and
forming a second capacitor electrodes over the Ta2O5 capacitor dielectric layer.
28. The method of comprising forming the Ta2O5 in contact with the Si3N4.
claim 27
29. The method of comprising forming the second capacitor electrode to comprise a conductive metal oxide.
claim 27
30. The method of comprising forming the second capacitor electrode to comprise a conductive metal oxide, the conductive metal oxide being in contact with the Ta2O5.
claim 27
31. A capacitor comprising:
a first capacitor electrode;
a capacitor dielectric layer over the first capacitor electrode; and
a second capacitor electrode over the capacitor dielectric layer, the second capacitor electrode comprising a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer.
32. The capacitor of wherein the conductive metal oxide is in contact with the capacitor dielectric layer.
claim 31
33. The capacitor of wherein the conductive silicon comprises polycrystalline silicon and silicide.
claim 31
34. The capacitor of wherein the conductive silicon is formed in contact with the titanium comprising layer, the titanium comprising layer is formed in contact with the conductive metal oxide, and the conductive metal oxide is formed in contact with the capacitor dielectric layer.
claim 31
35. A method of forming a capacitor comprising:
forming a first capacitor electrode over a substrate;
forming a capacitor dielectric layer over the first capacitor electrode; forming a second capacitor electrode over the capacitor dielectric layer, at least one of the first and second capacitor dielectric layers comprising a conductive metal oxide and a conductive silicon; and
providing a titanium comprising layer intermediate the conductive metal oxide and conductive silicon, the titanium comprising layer being provided by chemical vapor deposition using an organic precursor.
36. The method of comprising forming the conductive metal oxide in contact with the capacitor dielectric layer.
claim 35
37. The method of comprising forming the conductive silicon to comprise polycrystalline silicon and silicide.
claim 35
38. The method of comprising forming the conductive silicon in contact with the titanium comprising layer, the titanium comprising layer in contact with the conductive metal oxide, and the conductive metal oxide in contact with the capacitor dielectric layer.
claim 35
39. A capacitor comprising:
a first capacitor electrode;
a capacitor dielectric layer over the first capacitor electrode; and
a second capacitor electrode over the capacitor dielectric layer, the capacitor dielectric layer comprising Ta2O5, at least one of the first and second capacitor electrodes comprising titanium, no titanium comprising material of either the first and the second capacitor electrodes being in contact with the Ta2O5 of the capacitor dielectric layer.
40. The capacitor of wherein both the first and the second capacitor electrodes comprise silicon.
claim 39
41. The capacitor of wherein both the first and the second capacitor electrodes comprise silicon, at least one of the electrodes comprising silicon in the form of a silicide.
claim 39
42. The capacitor of wherein both the first and the second capacitor electrodes comprise silicon, only one of the electrodes comprising silicon in the form of a silicide.
claim 39
43. The capacitor of wherein the titanium comprises TiN.
claim 39
44. The capacitor of wherein only one of the first and second capacitor electrodes comprises titanium.
claim 39
45. The capacitor of wherein at least one of the first and second capacitor electrodes comprises silicon and germanium.
claim 39
46. The capacitor of wherein only one of the first and is second capacitor electrodes comprises silicon and germanium.
claim 39
47. The capacitor of wherein at least one of the first and second capacitor electrodes comprises a conductive metal oxide.
claim 39
48. The capacitor of wherein only one of the first and second capacitor electrodes comprises a conductive metal oxide.
claim 39
49. A DRAM cell comprising:
a first capacitor electrode;
a capacitor dielectric layer comprising Ta2O5 over the first capacitor electrode;
a second capacitor electrode over the Ta2O5 capacitor dielectric layer, the second capacitor electrode comprising a conductive metal oxide in contact with the Ta2O5; and
a field effect transistor having a pair of source/drain regions, one of the source/drain regions being in electrical connection with the first capacitor electrode, the other of the source drain regions being in electrical connection with a bit line.
50. A DRAM cell comprising:
a first capacitor electrode;
a capacitor dielectric layer over the first capacitor electrode;
a second capacitor electrode over the capacitor dielectric layer, the second capacitor electrode comprising a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer; and
a field effect transistor having a pair of source/drain regions, one of the source/drain regions being in electrical connection with the first capacitor electrode, the other of the source drain regions being in electrical connection with a bit line.
51. A method of forming a DRAM cell comprising:
forming a first capacitor electrode over a substrate;
forming a capacitor dielectric layer over the first capacitor electrode; forming a second capacitor electrode over the capacitor dielectric layer, at least one of the first and second capacitor dielectric layers comprising a conductive metal oxide and a conductive silicon;
providing a titanium comprising layer intermediate the conductive metal oxide and conductive silicon, the titanium comprising layer being provided by chemical vapor deposition using an organic precursor; and
providing a field effect transistor having a pair of source/drain regions, one of the source/drain regions being provided in electrical connection with the first capacitor electrode, the other of the source drain regions being provided in electrical connection with a bit line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/846,520 US6400552B2 (en) | 1998-02-28 | 2001-04-30 | Capacitor with conductively doped Si-Ge alloy electrode |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/033,063 US6191443B1 (en) | 1998-02-28 | 1998-02-28 | Capacitors, methods of forming capacitors, and DRAM memory cells |
US09/630,850 US6773981B1 (en) | 1998-02-28 | 2000-08-02 | Methods of forming capacitors |
US09/846,520 US6400552B2 (en) | 1998-02-28 | 2001-04-30 | Capacitor with conductively doped Si-Ge alloy electrode |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/630,850 Continuation US6773981B1 (en) | 1998-02-28 | 2000-08-02 | Methods of forming capacitors |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010053057A1 true US20010053057A1 (en) | 2001-12-20 |
US6400552B2 US6400552B2 (en) | 2002-06-04 |
Family
ID=21868374
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/033,063 Expired - Lifetime US6191443B1 (en) | 1998-02-28 | 1998-02-28 | Capacitors, methods of forming capacitors, and DRAM memory cells |
US09/630,850 Expired - Fee Related US6773981B1 (en) | 1998-02-28 | 2000-08-02 | Methods of forming capacitors |
US09/846,520 Expired - Fee Related US6400552B2 (en) | 1998-02-28 | 2001-04-30 | Capacitor with conductively doped Si-Ge alloy electrode |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/033,063 Expired - Lifetime US6191443B1 (en) | 1998-02-28 | 1998-02-28 | Capacitors, methods of forming capacitors, and DRAM memory cells |
US09/630,850 Expired - Fee Related US6773981B1 (en) | 1998-02-28 | 2000-08-02 | Methods of forming capacitors |
Country Status (1)
Country | Link |
---|---|
US (3) | US6191443B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030030093A1 (en) * | 1997-12-19 | 2003-02-13 | Micron Technology, Inc. | Capacitor forming methods and capacitor constructions |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5910880A (en) | 1997-08-20 | 1999-06-08 | Micron Technology, Inc. | Semiconductor circuit components and capacitors |
US6191443B1 (en) | 1998-02-28 | 2001-02-20 | Micron Technology, Inc. | Capacitors, methods of forming capacitors, and DRAM memory cells |
US6730559B2 (en) * | 1998-04-10 | 2004-05-04 | Micron Technology, Inc. | Capacitors and methods of forming capacitors |
KR100574678B1 (en) * | 1998-05-25 | 2006-04-27 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and Process for Manufacturing the same |
US7012292B1 (en) * | 1998-11-25 | 2006-03-14 | Advanced Technology Materials, Inc | Oxidative top electrode deposition process, and microelectronic device structure |
JP3768357B2 (en) * | 1998-12-01 | 2006-04-19 | 富士通株式会社 | Manufacturing method of high dielectric capacitor |
US6696718B1 (en) * | 1999-04-06 | 2004-02-24 | Micron Technology, Inc. | Capacitor having an electrode formed from a transition metal or a conductive metal-oxide, and method of forming same |
US7005695B1 (en) * | 2000-02-23 | 2006-02-28 | Micron Technology, Inc. | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region |
DE10010821A1 (en) | 2000-02-29 | 2001-09-13 | Infineon Technologies Ag | Increasing capacity in a storage trench comprises depositing a first silicon oxide layer in the trench, depositing a silicon layer over the first layer to sufficiently |
US6462368B2 (en) | 2000-10-31 | 2002-10-08 | Hitachi, Ltd. | Ferroelectric capacitor with a self-aligned diffusion barrier |
KR20030002863A (en) * | 2001-06-30 | 2003-01-09 | 주식회사 하이닉스반도체 | Ferroelectric memory device over cored pulg and method for fabricating the same |
US6495428B1 (en) * | 2001-07-11 | 2002-12-17 | Micron Technology, Inc. | Method of making a capacitor with oxygenated metal electrodes and high dielectric constant materials |
US7160577B2 (en) * | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
US7589029B2 (en) * | 2002-05-02 | 2009-09-15 | Micron Technology, Inc. | Atomic layer deposition and conversion |
KR100640631B1 (en) * | 2005-01-29 | 2006-10-31 | 삼성전자주식회사 | Capacitor of semiconductor device and method for fabricating the same |
US9312557B2 (en) * | 2005-05-11 | 2016-04-12 | Schlumberger Technology Corporation | Fuel cell apparatus and method for downhole power systems |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
US7750173B2 (en) | 2007-01-18 | 2010-07-06 | Advanced Technology Materials, Inc. | Tantalum amido-complexes with chelate ligands useful for CVD and ALD of TaN and Ta205 thin films |
JP5299105B2 (en) * | 2009-06-16 | 2013-09-25 | ソニー株式会社 | Vanadium dioxide nanowire and method for producing the same, and nanowire device using vanadium dioxide nanowire |
US20120113561A1 (en) * | 2010-11-04 | 2012-05-10 | National Chiao Tung University | Capacitor device and method for forming the same |
US10784172B2 (en) * | 2017-12-29 | 2020-09-22 | Texas Instruments Incorporated | Testing solid state devices before completing manufacture |
Family Cites Families (117)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3210607A (en) | 1961-09-07 | 1965-10-05 | Texas Instruments Inc | Ferroelectric capacitor apparatus |
US3886415A (en) * | 1968-04-01 | 1975-05-27 | Itek Corp | Capacitor with photo-conductive dielectric |
US4333808A (en) | 1979-10-30 | 1982-06-08 | International Business Machines Corporation | Method for manufacture of ultra-thin film capacitor |
JPS59108468A (en) | 1982-12-14 | 1984-06-22 | Olympus Optical Co Ltd | Solid-state image pickup device |
US4437139A (en) | 1982-12-17 | 1984-03-13 | International Business Machines Corporation | Laser annealed dielectric for dual dielectric capacitor |
US4464701A (en) | 1983-08-29 | 1984-08-07 | International Business Machines Corporation | Process for making high dielectric constant nitride based materials and devices using the same |
US5079191A (en) | 1985-11-29 | 1992-01-07 | Hitachi, Ltd. | Process for producing a semiconductor device |
JPS62222512A (en) | 1986-03-20 | 1987-09-30 | キヤノン株式会社 | Dielectric material |
JPH01222469A (en) | 1988-03-01 | 1989-09-05 | Fujitsu Ltd | Semiconductor memory device and manufacture thereof |
US4952904A (en) | 1988-12-23 | 1990-08-28 | Honeywell Inc. | Adhesion layer for platinum based sensors |
JPH0832304B2 (en) | 1989-08-18 | 1996-03-29 | 株式会社日立製作所 | Method for forming inorganic polymer thin film |
DE69017802T2 (en) | 1989-08-30 | 1995-09-07 | Nec Corp | Thin film capacitor and its manufacturing process. |
DE69123422T2 (en) | 1990-04-24 | 1997-06-05 | Ramtron Int Corp | SEMICONDUCTOR ARRANGEMENT WITH FERROELECTRIC MATERIAL AND METHOD FOR THE PRODUCTION THEREOF |
EP0468758B1 (en) | 1990-07-24 | 1997-03-26 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming insulating films, capacitances, and semiconductor devices |
EP0469555B1 (en) * | 1990-07-31 | 1996-04-17 | Nec Corporation | Charge storage capacitor electrode and method of manufacturing the same |
US5111355A (en) | 1990-09-13 | 1992-05-05 | National Semiconductor Corp. | High value tantalum oxide capacitor |
JPH07118522B2 (en) | 1990-10-24 | 1995-12-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Method and semiconductor structure for oxidizing a substrate surface |
US5641703A (en) | 1991-07-25 | 1997-06-24 | Massachusetts Institute Of Technology | Voltage programmable links for integrated circuits |
JPH0582747A (en) * | 1991-09-19 | 1993-04-02 | Fujitsu Ltd | Semiconductor device |
JP3055242B2 (en) | 1991-09-19 | 2000-06-26 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5192871A (en) | 1991-10-15 | 1993-03-09 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
JPH05110024A (en) | 1991-10-18 | 1993-04-30 | Sharp Corp | Semiconductor device and manufacture thereof |
US5142438A (en) | 1991-11-15 | 1992-08-25 | Micron Technology, Inc. | Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact |
JP3120528B2 (en) * | 1992-01-29 | 2000-12-25 | 日本電気株式会社 | Semiconductor device |
JPH05221644A (en) | 1992-02-13 | 1993-08-31 | Matsushita Electric Ind Co Ltd | Production of thin tantalum oxide film |
US5191510A (en) | 1992-04-29 | 1993-03-02 | Ramtron International Corporation | Use of palladium as an adhesion layer and as an electrode in ferroelectric memory devices |
US6081034A (en) | 1992-06-12 | 2000-06-27 | Micron Technology, Inc. | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer |
US5723382A (en) | 1992-06-12 | 1998-03-03 | Sandhu; Gurtej S. | Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug |
EP0575194B1 (en) | 1992-06-18 | 1997-11-12 | Matsushita Electronics Corporation | Method for semiconductor device having capacitor |
JPH0799771B2 (en) | 1992-06-26 | 1995-10-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Method of controlling stress in coating |
JPH0677402A (en) | 1992-07-02 | 1994-03-18 | Natl Semiconductor Corp <Ns> | Dielectric structure for semiconductor device and its manufacture |
JPH0621333A (en) | 1992-07-03 | 1994-01-28 | Seiko Epson Corp | Method for fabricating semiconductor device |
JP2877618B2 (en) | 1992-07-06 | 1999-03-31 | シャープ株式会社 | Method of forming ferroelectric film |
JPH0685173A (en) | 1992-07-17 | 1994-03-25 | Toshiba Corp | Capacitor for semiconductor integrated circuit |
JP3407204B2 (en) | 1992-07-23 | 2003-05-19 | オリンパス光学工業株式会社 | Ferroelectric integrated circuit and method of manufacturing the same |
JP3141553B2 (en) | 1992-08-06 | 2001-03-05 | 日本電気株式会社 | Method for manufacturing semiconductor device |
KR960004462B1 (en) | 1992-08-07 | 1996-04-06 | 삼성전자주식회사 | Process for producing memory capacitor in semiconductor device |
US5442585A (en) | 1992-09-11 | 1995-08-15 | Kabushiki Kaisha Toshiba | Device having dielectric thin film |
US5390072A (en) | 1992-09-17 | 1995-02-14 | Research Foundation Of State University Of New York | Thin film capacitors |
US5372859A (en) | 1992-10-20 | 1994-12-13 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment |
US5348894A (en) | 1993-01-27 | 1994-09-20 | Texas Instruments Incorporated | Method of forming electrical connections to high dielectric constant materials |
US5335138A (en) | 1993-02-12 | 1994-08-02 | Micron Semiconductor, Inc. | High dielectric constant capacitor and method of manufacture |
JP2786071B2 (en) | 1993-02-17 | 1998-08-13 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5471364A (en) | 1993-03-31 | 1995-11-28 | Texas Instruments Incorporated | Electrode interface for high-dielectric-constant materials |
JP3412051B2 (en) | 1993-05-14 | 2003-06-03 | 日本テキサス・インスツルメンツ株式会社 | Capacitor |
US5407855A (en) | 1993-06-07 | 1995-04-18 | Motorola, Inc. | Process for forming a semiconductor device having a reducing/oxidizing conductive material |
JPH0730077A (en) | 1993-06-23 | 1995-01-31 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
US5933316A (en) | 1993-08-02 | 1999-08-03 | Motorola Inc. | Method for forming a titanate thin film on silicon, and device formed thereby |
US5330931A (en) * | 1993-09-22 | 1994-07-19 | Northern Telecom Limited | Method of making a capacitor for an integrated circuit |
JP2679599B2 (en) * | 1993-12-02 | 1997-11-19 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5362632A (en) | 1994-02-08 | 1994-11-08 | Micron Semiconductor, Inc. | Barrier process for Ta2 O5 capacitor |
JP3045928B2 (en) | 1994-06-28 | 2000-05-29 | 松下電子工業株式会社 | Semiconductor device and manufacturing method thereof |
US5468687A (en) | 1994-07-27 | 1995-11-21 | International Business Machines Corporation | Method of making TA2 O5 thin film by low temperature ozone plasma annealing (oxidation) |
US5504041A (en) * | 1994-08-01 | 1996-04-02 | Texas Instruments Incorporated | Conductive exotic-nitride barrier layer for high-dielectric-constant materials |
US5585300A (en) | 1994-08-01 | 1996-12-17 | Texas Instruments Incorporated | Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes |
US6331325B1 (en) | 1994-09-30 | 2001-12-18 | Texas Instruments Incorporated | Barium strontium titanate (BST) thin films using boron |
US5728603A (en) | 1994-11-28 | 1998-03-17 | Northern Telecom Limited | Method of forming a crystalline ferroelectric dielectric material for an integrated circuit |
US5555486A (en) | 1994-12-29 | 1996-09-10 | North Carolina State University | Hybrid metal/metal oxide electrodes for ferroelectric capacitors |
US5668040A (en) | 1995-03-20 | 1997-09-16 | Lg Semicon Co., Ltd. | Method for forming a semiconductor device electrode which also serves as a diffusion barrier |
US6088216A (en) * | 1995-04-28 | 2000-07-11 | International Business Machines Corporation | Lead silicate based capacitor structures |
US5557122A (en) | 1995-05-12 | 1996-09-17 | Alliance Semiconductors Corporation | Semiconductor electrode having improved grain structure and oxide growth properties |
US5654222A (en) | 1995-05-17 | 1997-08-05 | Micron Technology, Inc. | Method for forming a capacitor with electrically interconnected construction |
US5663088A (en) | 1995-05-19 | 1997-09-02 | Micron Technology, Inc. | Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer |
WO1997001854A1 (en) | 1995-06-28 | 1997-01-16 | Bell Communication Research, Inc. | Barrier layer for ferroelectric capacitor integrated on silicon |
JP3012785B2 (en) | 1995-07-14 | 2000-02-28 | 松下電子工業株式会社 | Capacitive element |
US5675028A (en) | 1995-08-29 | 1997-10-07 | Board Of Regents, The University Of Texas System | Bisamido azides of gallium, aluminum and indium and their use as precursors for the growth of nitride films |
KR0183732B1 (en) | 1995-09-01 | 1999-03-20 | 김광호 | Method of manufacturing semiconductor device capacitor |
JP2762968B2 (en) | 1995-09-28 | 1998-06-11 | 日本電気株式会社 | Method for manufacturing field effect thin film transistor |
US5786248A (en) | 1995-10-12 | 1998-07-28 | Micron Technology, Inc. | Semiconductor processing method of forming a tantalum oxide containing capacitor |
JP3413444B2 (en) | 1995-10-31 | 2003-06-03 | ヤマハマリン株式会社 | 4 cycle engine for outboard motor |
KR0165484B1 (en) | 1995-11-28 | 1999-02-01 | 김광호 | Method of depositing ta2o5 and apparatus thereof |
US5780359A (en) | 1995-12-11 | 1998-07-14 | Applied Materials, Inc. | Polymer removal from top surfaces and sidewalls of a semiconductor wafer |
US5798903A (en) | 1995-12-26 | 1998-08-25 | Bell Communications Research, Inc. | Electrode structure for ferroelectric capacitor integrated on silicon |
TW318932B (en) | 1995-12-28 | 1997-11-01 | Hitachi Ltd | |
JP3612839B2 (en) | 1996-02-13 | 2005-01-19 | 三菱電機株式会社 | High dielectric constant thin film structure, high dielectric constant thin film forming method, and high dielectric constant thin film forming apparatus |
JP3063606B2 (en) * | 1996-02-13 | 2000-07-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
US5920775A (en) | 1996-02-23 | 1999-07-06 | Vanguard International Semiconductor Corporation | Method for forming a storage capacitor within an integrated circuit |
KR100207467B1 (en) | 1996-02-29 | 1999-07-15 | 윤종용 | Fabricating method for capacitor in semiconductor device |
US5930584A (en) | 1996-04-10 | 1999-07-27 | United Microelectronics Corp. | Process for fabricating low leakage current electrode for LPCVD titanium oxide films |
US5843830A (en) | 1996-06-26 | 1998-12-01 | Micron Technology, Inc. | Capacitor, and methods for forming a capacitor |
JP3396131B2 (en) | 1996-06-28 | 2003-04-14 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
US5760474A (en) | 1996-07-09 | 1998-06-02 | Micron Technology, Inc. | Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier |
US5990507A (en) | 1996-07-09 | 1999-11-23 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor structures |
US5930106A (en) | 1996-07-11 | 1999-07-27 | Micron Technology, Inc. | DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films |
US5888295A (en) | 1996-08-20 | 1999-03-30 | Micron Technology, Inc. | Method of forming a silicon film |
KR100223939B1 (en) | 1996-09-07 | 1999-10-15 | 구본준 | Manufacturing method of film with high dielectric constant and the manufacturing method of capacitors using the same |
US5916634A (en) | 1996-10-01 | 1999-06-29 | Sandia Corporation | Chemical vapor deposition of W-Si-N and W-B-N |
KR100282413B1 (en) * | 1996-10-24 | 2001-03-02 | 김영환 | Thin film formation method using nitrous oxide gas |
JP3869089B2 (en) * | 1996-11-14 | 2007-01-17 | 株式会社日立製作所 | Manufacturing method of semiconductor integrated circuit device |
US5807774A (en) | 1996-12-06 | 1998-09-15 | Sharp Kabushiki Kaisha | Simple method of fabricating ferroelectric capacitors |
US5790366A (en) | 1996-12-06 | 1998-08-04 | Sharp Kabushiki Kaisha | High temperature electrode-barriers for ferroelectric and other capacitor structures |
JP3272979B2 (en) * | 1997-01-08 | 2002-04-08 | 株式会社東芝 | Semiconductor device |
US5876788A (en) * | 1997-01-16 | 1999-03-02 | International Business Machines Corporation | High dielectric TiO2 -SiN composite films for memory applications |
JP3466851B2 (en) | 1997-01-20 | 2003-11-17 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
GB2324408A (en) * | 1997-01-21 | 1998-10-21 | United Microelectronics Corporation | Forming DRAM cells |
US6096597A (en) | 1997-01-31 | 2000-08-01 | Texas Instruments Incorporated | Method for fabricating an integrated circuit structure |
KR100243286B1 (en) | 1997-03-05 | 2000-03-02 | 윤종용 | Method for manufacturing a semiconductor device |
US5858873A (en) | 1997-03-12 | 1999-01-12 | Lucent Technologies Inc. | Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof |
US6197653B1 (en) * | 1997-03-27 | 2001-03-06 | Texas Instruments Incorporated | Capacitor and memory structure and method |
JPH1140501A (en) | 1997-05-20 | 1999-02-12 | Fujitsu Ltd | Semiconductor device and method for manufacturing it |
TW408433B (en) | 1997-06-30 | 2000-10-11 | Hitachi Ltd | Method for fabricating semiconductor integrated circuit |
US5910880A (en) | 1997-08-20 | 1999-06-08 | Micron Technology, Inc. | Semiconductor circuit components and capacitors |
US5864496A (en) | 1997-09-29 | 1999-01-26 | Siemens Aktiengesellschaft | High density semiconductor memory having diagonal bit lines and dual word lines |
JP3319994B2 (en) | 1997-09-29 | 2002-09-03 | シャープ株式会社 | Semiconductor storage element |
US5943580A (en) | 1997-12-15 | 1999-08-24 | Motorola, Inc. | Method of forming a capacitor or an inductor on a substrate |
US6165833A (en) | 1997-12-19 | 2000-12-26 | Micron Technology, Inc. | Semiconductor processing method of forming a capacitor |
US6010744A (en) | 1997-12-23 | 2000-01-04 | Advanced Technology Materials, Inc. | Method for nucleation controlled chemical vapor deposition of metal oxide ferroelectric thin films |
US6180481B1 (en) | 1998-01-09 | 2001-01-30 | Micron Technology, Inc. | Barrier layer fabrication methods |
US6150706A (en) * | 1998-02-27 | 2000-11-21 | Micron Technology, Inc. | Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer |
US6162744A (en) | 1998-02-28 | 2000-12-19 | Micron Technology, Inc. | Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers |
US6191443B1 (en) | 1998-02-28 | 2001-02-20 | Micron Technology, Inc. | Capacitors, methods of forming capacitors, and DRAM memory cells |
US6156638A (en) | 1998-04-10 | 2000-12-05 | Micron Technology, Inc. | Integrated circuitry and method of restricting diffusion from one material to another |
US6165834A (en) | 1998-05-07 | 2000-12-26 | Micron Technology, Inc. | Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell |
US6255186B1 (en) | 1998-05-21 | 2001-07-03 | Micron Technology, Inc. | Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom |
US6027969A (en) | 1998-06-04 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Capacitor structure for a dynamic random access memory cell |
US6235594B1 (en) | 1999-01-13 | 2001-05-22 | Agere Systems Guardian Corp. | Methods of fabricating an integrated circuit device with composite oxide dielectric |
JP2000223683A (en) | 1999-02-02 | 2000-08-11 | Canon Inc | Composite member and its isolation method, laminated substrate and its isolation method, relocation method of relocation layer, and method for manufacturing soi substrate |
-
1998
- 1998-02-28 US US09/033,063 patent/US6191443B1/en not_active Expired - Lifetime
-
2000
- 2000-08-02 US US09/630,850 patent/US6773981B1/en not_active Expired - Fee Related
-
2001
- 2001-04-30 US US09/846,520 patent/US6400552B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030030093A1 (en) * | 1997-12-19 | 2003-02-13 | Micron Technology, Inc. | Capacitor forming methods and capacitor constructions |
US7205600B2 (en) * | 1997-12-19 | 2007-04-17 | Micron Technology, Inc. | Capacitor constructions with a barrier layer to threshold voltage shift inducing material |
Also Published As
Publication number | Publication date |
---|---|
US6191443B1 (en) | 2001-02-20 |
US6773981B1 (en) | 2004-08-10 |
US6400552B2 (en) | 2002-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6191443B1 (en) | Capacitors, methods of forming capacitors, and DRAM memory cells | |
US5899725A (en) | Method of forming a hemispherical grained silicon on refractory metal nitride | |
US5972791A (en) | Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier | |
US5733816A (en) | Method for depositing a tungsten layer on silicon | |
JP4107731B2 (en) | Capacitor for semiconductor device and method for forming the same | |
US7446363B2 (en) | Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material | |
US6162744A (en) | Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers | |
US7691743B2 (en) | Semiconductor device having a capacitance element and method of manufacturing the same | |
US20030203608A1 (en) | Fabrication of semiconductor devices with transition metal boride films as diffusion barriers | |
US6511896B2 (en) | Method of etching a substantially amorphous TA2O5 comprising layer | |
JP2001053253A (en) | Capacitor of semiconductor memory element and its manufacture | |
KR100377593B1 (en) | Semiconductor device and manufacturing method thereof | |
US6949477B2 (en) | Method of fabricating a capacitive element for a semiconductor device | |
US20130071986A1 (en) | Partial etch of dram electrode | |
JP3683764B2 (en) | Capacitor manufacturing method for memory device | |
US7300852B2 (en) | Method for manufacturing capacitor of semiconductor element | |
KR100342873B1 (en) | Method for forming capacitor of semiconductor device | |
US6432801B1 (en) | Gate electrode in a semiconductor device and method for forming thereof | |
KR100293721B1 (en) | Capacitor manufacturing method having a tantalum oxide film as a dielectric film | |
KR100382610B1 (en) | Method for forming of capacitor the cell used high-integrated DRAM | |
KR100772685B1 (en) | A fabricating method of capacitor | |
JP2000216360A (en) | Semiconductor memory element | |
KR20010020024A (en) | Method For Treating The High Temperature Of Tantalium Oxide Capacitor | |
KR20040001866A (en) | Method for fabricating capacitor | |
KR20020002753A (en) | Method of forming a capacitor in a semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140604 |