US20010048151A1 - Stackable ball grid array semiconductor package and fabrication method thereof - Google Patents
Stackable ball grid array semiconductor package and fabrication method thereof Download PDFInfo
- Publication number
- US20010048151A1 US20010048151A1 US09/922,103 US92210301A US2001048151A1 US 20010048151 A1 US20010048151 A1 US 20010048151A1 US 92210301 A US92210301 A US 92210301A US 2001048151 A1 US2001048151 A1 US 2001048151A1
- Authority
- US
- United States
- Prior art keywords
- conductive
- chip
- conductive traces
- chip package
- stackable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73219—Layer and TAB connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a stackable ball grid array (BGA) semiconductor package and a fabrication method thereof.
- BGA ball grid array
- solder balls which are attached to a substrate are used as external terminals.
- a plurality of solder balls are attached to an upper or a lower surface of a substrate by the application of heat.
- the solder balls which act as external terminals, are not easily bent or deformed by inpacts with solid objects.
- FIG. 1 shows a structure of a background art BGA semiconductor package.
- an elastomer 2 is attached to a center portion of an upper surface of a semiconductor chip 1 , and a high strength adhesive resin 3 is formed on the elastomer 2 .
- a plurality of metal traces, which transmit electric signals, are formed on the adhesive resin 3 .
- First ends 4 a of the metal traces extend across a top surface of the adhesive resin 3
- second ends 4 b of each of the metal 5 traces are connected to chip pads 6 formed on a marginal portion of the upper surface of the semiconductor chip 1 .
- a solder resist 5 covers the metal traces 4 a and the adhesive resin 3 , except for exposed portions of the first ends 4 a of the metal traces, onto which solder balls will be attached.
- An encapsulant 7 such as a molding resin, covers the upper surface of the semiconductor chip 1 , and the portions of the metal 10 traces that are not covered with the solder resist 5 .
- Conductive balls 8 are then attached to the exposed portions of the metal traces to serve as output terminals.
- a stackable chip package embodying the invention includes a supporting member having a plurality of conductive patterns formed therein.
- a plurality of first conductive traces are formed on a surface of the supporting member, and respective ones of the first conductive traces are coupled to corresponding ones of the conductive patterns.
- a chip having chip pads is attached to a second surface of the supporting member, and a plurality of second conductive traces are arranged over the chip. Respective ones of the second conductive traces are electrically coupled to corresponding chip pads on the chip, and corresponding ones of the conductive patterns in the supporting member.
- An embodiment of the invention could also include a solder resist that covers selected portions of the first and second conductive traces. The solder resist would leave connecting portions of the first and second conductive traces exposed.
- Exterior leads in the form of conductive balls, could then be connected to the connecting portions of the first and second conductive traces.
- a device embodying the invention could also include a molding resin that encapsulates portions of the conductive traces and the chip.
- the supporting member could include a supporting plate and a supporting frame that surrounds the supporting plate.
- a supporting member having a plurality of conductive patterns is first formed.
- a plurality of first conductive traces are then formed on a first surface of the supporting member such that the conductive traces are electrically coupled to corresponding ones of the conductive patterns in the supporting member.
- a plurality of second traces are then attached to a surface of a chip, and the chip is attached to a second surface of the supporting member. Respective ones of the second conductive traces are attached to corresponding chip pads on the chip, and to corresponding ones of the conductive patterns in the supporting member.
- a method embodying the invention could also include the step of forming layers of solder resist over the first and second conductive traces, and removing portions of the solder resist to expose connecting portions of the first and second conductive traces.
- a method embodying the invention could also include attaching leads, in the form of conductive balls, to respective ones of the exposed connecting portions of the first and second conductive traces.
- FIG. 1 is a vertical cross-sectional diagram of a background art BGA semiconductor package
- FIG. 2 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a first embodiment of the present invention
- FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention.
- FIG. 4 is a vertical cross-sectional diagram of stacked BGA semiconductor packages according to the present invention.
- FIGS. 5A through 5H illustrate steps of a method of manufacturing a stackable BGA semiconductor package according to the present invention.
- FIG. 2 illustrates a stackable BGA semiconductor package according to a first embodiment of the present invention.
- a supporting member 21 includes a supporting plate 23 surrounded by a supporting frame 25 having a predetermined height.
- Metal traces 24 a are attached to a lower surface of the supporting plate 23 .
- a solder resist 27 covers portions of the metal traces 24 a and the supporting plate 23 to prevent short circuiting between solder balls and the metal traces, and to protect the metal traces 24 a from outside impacts.
- the solder resist 27 is partially removed to expose portions of the metal traces 24 a .
- the exposed portions of the metal traces 24 a act as connecting portions 24 b .
- the connecting portions 24 b are used to electrically connect the metal traces 24 a to conductive balls that act as external terminals.
- Metal patterns 26 are formed between upper and lower surfaces of the supporting frame 25 . One end of each of the metal patterns 26 is connected with an end of each of the metal traces 24 a . The other end of each of the metal patterns 26 is exposed at the upper surface of the supporting frame 25 .
- a semiconductor chip 1 is attached by an adhesive onto the supporting plate 23 of the supporting member 21 .
- An elastomer 2 is attached to a center portion of the upper surface of the semiconductor chip 1 , and a high strength adhesive resin 3 is formed on the elastomer 2 .
- Metal traces which transmit electric signals are attached onto the adhesive resin 3 .
- First ends 4 a of the metal traces extend over the top surface of the adhesive resin.
- Middle portions 4 b of the metal traces are connected with chip pads 6 formed on a marginal portion of the upper surface of the semiconductor chip 1 .
- Second ends 4 c of the metal traces are connected with upper surfaces of the metal patterns 26 formed in the supporting frame 25 .
- a solder resist 5 covers the upper surface of the adhesive resin 3 and portions of the first ends 4 a of the metal traces. Conductive balls 8 a are attached to the exposed portions of the first ends 4 a of the metal traces.
- An encapsulant 28 such as a molding resin, covers exposed portions of the upper surface of the semiconductor chip 1 , the metal traces, and the upper portion of the supporting frame 25 .
- Electrical signals which are output by the semiconductor chip 1 through the chip pads 6 can be externally transmitted over the conductive balls 8 a connected with the first ends 4 a of the metal traces.
- the electrical signals can also be externally transmitted through the connecting portions 24 b on the lower part of the supporting member 21 , which are connected to the second ends 4 c of the metal traces through the metal patterns 26 .
- FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention.
- the second embodiment is the same as the embodiment shown in FIG. 2, except that conductive balls 8 b are also attached to the exposed portions 24 b , of the metal traces 24 a formed on the lower part of the supporting member 21 .
- FIG. 4 illustrates stacked BGA semiconductor packages using the stackable BGA semiconductor package according to the first embodiment of the present invention shown in FIG. 2.
- a plurality of stackable BGA semiconductor packages 100 , 110 , 120 , 130 are stacked.
- Conductive balls 108 a which are formed on an upper surface of the first package 100 , connect the first ends 4 a of the metal traces on the first package 100 to the connecting portions 24 b formed on a lower surface of the second BGA semiconductor package 110 .
- Conductive balls 118 a formed on an upper surface of the second package 110 connect the first ends 4 a of the metal traces on the second package 110 to the connecting portions 24 b on a lower surface of the third BGA semiconductor package 120 .
- Conductive balls 128 a formed on an upper surface of the third package 120 connect the first ends 4 a of the metal traces on the third package 120 to the connecting portions 24 b on a lower surface of the fourth package 130 .
- FIG. 4 illustrates four stacked BGA packages, but the actual number of stacked BGA packages may be variously adjusted by a user according to his requirements.
- Conductive balls 138 a formed on the fourth package 130 can serve as external terminals which transmit signals from all the BGA packages to external circuits. For instance, the conductive balls 138 a could be connected to pads of a printed circuit board.
- FIGS. 5 A- 5 H A method of fabricating a stackable BGA semiconductor chip package according to the present invention will now be described with reference to FIGS. 5 A- 5 H.
- the supporting member 21 includes the supporting plate 23 and the supporting frame 25 .
- Metal traces 24 a are formed on a lower surface of the supporting plate 23 .
- the solder resist 27 covers portions of the metal traces 24 a , but leaves the connecting portions 24 b exposed.
- the metal patterns 26 formed in the supporting frame 25 are exposed at the upper surface of the supporting frame 25 , and are connected with the metal traces 24 a on the bottom of the supporting plate 23 .
- the semiconductor chip 1 which has chip pads 6 on a marginal portion of an upper surface thereof, is connected to a lower surface of an elastomer 2 .
- a high strength adhesive 3 is attached to an upper surface of the elastomer 2 .
- the metal traces are then attached to the upper surface of the adhesive 3 .
- First end portions of each of the metal traces are attached to the adhesive 3 , and the other end portions thereof extend from outer sides of the adhesive 3 .
- a layer of the solder resist 5 is formed on the metal traces and on the adhesive resin 3 .
- the chip pads 6 formed on the semiconductor chip 1 are connected to the middle portions 4 b of the metal traces by pressing down the middle portions 4 b.
- second ends 4 c of the metal traces are cut off by the bond tool 30 , and the second ends 4 c are connected with upper surfaces of the metal patterns 26 in the supporting frame 25 .
- a molding resin 28 is molded over the package so that it covers the exposed portions of the metal traces and the exposed portions of the chip 1 and chip pads 6 .
- portions of the solder resist 5 formed on the metal traces is removed to expose portions of the first ends 4 a of the metal traces that will be connected to conductive balls.
- the conductive balls 8 a are then placed on the exposed portions of the first ends 4 a of the metal traces, and a reflow process is performed to attach the conductive balls 8 a to the metal traces.
- One BGA package embodying the invention can be attached to a second BGA package embodying the invention by stacking the second package on the first package so that conductive balls on the first package align with corresponding connecting portions on a bottom surface of the second package, and then performing a reflow process to connect the two packages.
- metal traces and a conductive region in a semiconductor may not be structural equivalents in that metal traces use metal as an electrical conductor, whereas the conductive region in a semiconductor relies on charge carriers in the material to provide electrical conductivity, in the environment of conducting electricity, metal traces and a conductive region of a semiconductor may be equivalent structures.
Abstract
Description
- This application is a divisional of application Ser. No. 09/239,152, filed Jan. 28, 1999.
- 1. Field of the Invention
- The present invention relates to a stackable ball grid array (BGA) semiconductor package and a fabrication method thereof.
- 2. Background of the Related Art
- Currently, there is an effort to produce a highly integrated semiconductor package having a large number of exterior connections. One example is a BGA semiconductor package in which a plurality of solder balls which are attached to a substrate are used as external terminals. In these BGA packages, a plurality of solder balls are attached to an upper or a lower surface of a substrate by the application of heat. The solder balls, which act as external terminals, are not easily bent or deformed by inpacts with solid objects.
- FIG. 1 shows a structure of a background art BGA semiconductor package. As seen in FIG. 1, an
elastomer 2 is attached to a center portion of an upper surface of asemiconductor chip 1, and a high strengthadhesive resin 3 is formed on theelastomer 2. A plurality of metal traces, which transmit electric signals, are formed on theadhesive resin 3.First ends 4 a of the metal traces extend across a top surface of theadhesive resin 3, andsecond ends 4 b of each of themetal 5 traces are connected tochip pads 6 formed on a marginal portion of the upper surface of thesemiconductor chip 1. Asolder resist 5 covers themetal traces 4 a and theadhesive resin 3, except for exposed portions of thefirst ends 4 a of the metal traces, onto which solder balls will be attached. An encapsulant 7, such as a molding resin, covers the upper surface of thesemiconductor chip 1, and the portions of the metal 10 traces that are not covered with thesolder resist 5.Conductive balls 8 are then attached to the exposed portions of the metal traces to serve as output terminals. - Since the conductive balls are exposed on only one side of the package (in FIG. 1, the conductive balls are exposed at the upper surface thereof), it is impossible to fabricate a stackable package of high mount density.
- It is an object of the present invention to provide a stackable BGA semiconductor package, and a fabrication method thereof, that maintain advantages of the conventional BGA package.
- A stackable chip package embodying the invention includes a supporting member having a plurality of conductive patterns formed therein. A plurality of first conductive traces are formed on a surface of the supporting member, and respective ones of the first conductive traces are coupled to corresponding ones of the conductive patterns. A chip having chip pads is attached to a second surface of the supporting member, and a plurality of second conductive traces are arranged over the chip. Respective ones of the second conductive traces are electrically coupled to corresponding chip pads on the chip, and corresponding ones of the conductive patterns in the supporting member. An embodiment of the invention could also include a solder resist that covers selected portions of the first and second conductive traces. The solder resist would leave connecting portions of the first and second conductive traces exposed. Exterior leads, in the form of conductive balls, could then be connected to the connecting portions of the first and second conductive traces. A device embodying the invention could also include a molding resin that encapsulates portions of the conductive traces and the chip. The supporting member could include a supporting plate and a supporting frame that surrounds the supporting plate.
- In a method embodying the invention, a supporting member having a plurality of conductive patterns is first formed. A plurality of first conductive traces are then formed on a first surface of the supporting member such that the conductive traces are electrically coupled to corresponding ones of the conductive patterns in the supporting member. A plurality of second traces are then attached to a surface of a chip, and the chip is attached to a second surface of the supporting member. Respective ones of the second conductive traces are attached to corresponding chip pads on the chip, and to corresponding ones of the conductive patterns in the supporting member. A method embodying the invention could also include the step of forming layers of solder resist over the first and second conductive traces, and removing portions of the solder resist to expose connecting portions of the first and second conductive traces. A method embodying the invention could also include attaching leads, in the form of conductive balls, to respective ones of the exposed connecting portions of the first and second conductive traces.
- Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
- The accompanying drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawing figures, like elements are identified with like reference numerals, and:
- FIG. 1 is a vertical cross-sectional diagram of a background art BGA semiconductor package;
- FIG. 2 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a first embodiment of the present invention;
- FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention;
- FIG. 4 is a vertical cross-sectional diagram of stacked BGA semiconductor packages according to the present invention; and
- FIGS. 5A through 5H illustrate steps of a method of manufacturing a stackable BGA semiconductor package according to the present invention.
- FIG. 2 illustrates a stackable BGA semiconductor package according to a first embodiment of the present invention. As shown in FIG. 2, a supporting
member 21 includes a supportingplate 23 surrounded by a supportingframe 25 having a predetermined height.Metal traces 24 a are attached to a lower surface of the supportingplate 23. In addition, a solder resist 27 covers portions of themetal traces 24 a and the supportingplate 23 to prevent short circuiting between solder balls and the metal traces, and to protect themetal traces 24 a from outside impacts. Thesolder resist 27 is partially removed to expose portions of themetal traces 24 a. The exposed portions of the metal traces 24 a act as connectingportions 24 b. The connectingportions 24 b are used to electrically connect themetal traces 24 a to conductive balls that act as external terminals. -
Metal patterns 26 are formed between upper and lower surfaces of the supportingframe 25. One end of each of themetal patterns 26 is connected with an end of each of themetal traces 24 a. The other end of each of themetal patterns 26 is exposed at the upper surface of the supportingframe 25. - A
semiconductor chip 1 is attached by an adhesive onto the supportingplate 23 of the supportingmember 21. Anelastomer 2 is attached to a center portion of the upper surface of thesemiconductor chip 1, and a high strengthadhesive resin 3 is formed on theelastomer 2. Metal traces which transmit electric signals are attached onto theadhesive resin 3.First ends 4 a of the metal traces extend over the top surface of the adhesive resin.Middle portions 4 b of the metal traces are connected withchip pads 6 formed on a marginal portion of the upper surface of thesemiconductor chip 1. Second ends 4 c of the metal traces are connected with upper surfaces of themetal patterns 26 formed in the supportingframe 25. - A solder resist5 covers the upper surface of the
adhesive resin 3 and portions of the first ends 4 a of the metal traces.Conductive balls 8 a are attached to the exposed portions of the first ends 4 a of the metal traces. Anencapsulant 28, such as a molding resin, covers exposed portions of the upper surface of thesemiconductor chip 1, the metal traces, and the upper portion of the supportingframe 25. - Electrical signals which are output by the
semiconductor chip 1 through thechip pads 6 can be externally transmitted over theconductive balls 8 a connected with the first ends 4 a of the metal traces. The electrical signals can also be externally transmitted through the connectingportions 24 b on the lower part of the supportingmember 21, which are connected to the second ends 4 c of the metal traces through themetal patterns 26. - FIG. 3 is a vertical cross-sectional diagram of a stackable BGA semiconductor package according to a second embodiment of the present invention. The second embodiment is the same as the embodiment shown in FIG. 2, except that
conductive balls 8 b are also attached to the exposedportions 24 b, of the metal traces 24 a formed on the lower part of the supportingmember 21. - With each of the embodiments shown in FIGS. 2 and 3, it becomes possible to stack a plurality of BGA semiconductor packages over a single mounting position on a printed circuit board. Thus, the density of the semiconductor devices on a circuit board can be increased by using BGA packages embodying the invention.
- FIG. 4 illustrates stacked BGA semiconductor packages using the stackable BGA semiconductor package according to the first embodiment of the present invention shown in FIG. 2. As shown therein, a plurality of stackable BGA semiconductor packages100, 110, 120, 130 are stacked.
Conductive balls 108 a, which are formed on an upper surface of thefirst package 100, connect the first ends 4 a of the metal traces on thefirst package 100 to the connectingportions 24 b formed on a lower surface of the secondBGA semiconductor package 110.Conductive balls 118 a formed on an upper surface of thesecond package 110 connect the first ends 4 a of the metal traces on thesecond package 110 to the connectingportions 24 b on a lower surface of the thirdBGA semiconductor package 120.Conductive balls 128 a formed on an upper surface of thethird package 120 connect the first ends 4 a of the metal traces on thethird package 120 to the connectingportions 24 b on a lower surface of thefourth package 130. - FIG. 4 illustrates four stacked BGA packages, but the actual number of stacked BGA packages may be variously adjusted by a user according to his requirements.
Conductive balls 138 a formed on thefourth package 130 can serve as external terminals which transmit signals from all the BGA packages to external circuits. For instance, theconductive balls 138 a could be connected to pads of a printed circuit board. - A method of fabricating a stackable BGA semiconductor chip package according to the present invention will now be described with reference to FIGS.5A-5H.
- In FIG. 5A, first the supporting
member 21 is provided. The supportingmember 21, includes the supportingplate 23 and the supportingframe 25. Metal traces 24 a are formed on a lower surface of the supportingplate 23. The solder resist 27 covers portions of the metal traces 24 a, but leaves the connectingportions 24 b exposed. Themetal patterns 26 formed in the supportingframe 25, are exposed at the upper surface of the supportingframe 25, and are connected with the metal traces 24 a on the bottom of the supportingplate 23. - As shown in FIG. 5B, the
semiconductor chip 1, which haschip pads 6 on a marginal portion of an upper surface thereof, is connected to a lower surface of anelastomer 2. Ahigh strength adhesive 3 is attached to an upper surface of theelastomer 2. The metal traces are then attached to the upper surface of the adhesive 3. First end portions of each of the metal traces are attached to the adhesive 3, and the other end portions thereof extend from outer sides of the adhesive 3. Next, a layer of the solder resist 5 is formed on the metal traces and on theadhesive resin 3. - Next, as shown in FIG. 5C, the semiconductor chip assembly shown in FIG. 5B is attached to the supporting
member 21 shown in FIG. 5A. - In FIG. 5D, using a
bond tool 30, thechip pads 6 formed on thesemiconductor chip 1 are connected to themiddle portions 4 b of the metal traces by pressing down themiddle portions 4 b. - As shown in FIG. 5E, second ends4 c of the metal traces are cut off by the
bond tool 30, and the second ends 4 c are connected with upper surfaces of themetal patterns 26 in the supportingframe 25. - As shown in FIG. 5F and 5G, a
molding resin 28 is molded over the package so that it covers the exposed portions of the metal traces and the exposed portions of thechip 1 andchip pads 6. Next, portions of the solder resist 5 formed on the metal traces is removed to expose portions of the first ends 4 a of the metal traces that will be connected to conductive balls. - As shown in FIG. 5G, the
conductive balls 8 a are then placed on the exposed portions of the first ends 4 a of the metal traces, and a reflow process is performed to attach theconductive balls 8 a to the metal traces. - One BGA package embodying the invention can be attached to a second BGA package embodying the invention by stacking the second package on the first package so that conductive balls on the first package align with corresponding connecting portions on a bottom surface of the second package, and then performing a reflow process to connect the two packages.
- The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. For example, although metal traces and a conductive region in a semiconductor may not be structural equivalents in that metal traces use metal as an electrical conductor, whereas the conductive region in a semiconductor relies on charge carriers in the material to provide electrical conductivity, in the environment of conducting electricity, metal traces and a conductive region of a semiconductor may be equivalent structures.
Claims (26)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/922,103 US6407448B2 (en) | 1998-05-30 | 2001-08-06 | Stackable ball grid array semiconductor package and fabrication method thereof |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980020098A KR100266693B1 (en) | 1998-05-30 | 1998-05-30 | Stackable ball grid array semiconductor package and fabrication method thereof |
KR98-20098U | 1998-05-30 | ||
KR20098/1998 | 1998-05-30 | ||
US09/239,152 US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
US09/922,103 US6407448B2 (en) | 1998-05-30 | 2001-08-06 | Stackable ball grid array semiconductor package and fabrication method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/239,152 Division US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010048151A1 true US20010048151A1 (en) | 2001-12-06 |
US6407448B2 US6407448B2 (en) | 2002-06-18 |
Family
ID=19537977
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/239,152 Expired - Lifetime US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
US09/922,103 Expired - Lifetime US6407448B2 (en) | 1998-05-30 | 2001-08-06 | Stackable ball grid array semiconductor package and fabrication method thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/239,152 Expired - Lifetime US6291259B1 (en) | 1998-05-30 | 1999-01-28 | Stackable ball grid array semiconductor package and fabrication method thereof |
Country Status (4)
Country | Link |
---|---|
US (2) | US6291259B1 (en) |
JP (1) | JP3063032B2 (en) |
KR (1) | KR100266693B1 (en) |
DE (1) | DE19845316C2 (en) |
Cited By (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030026556A1 (en) * | 2001-08-03 | 2003-02-06 | National Semiconductor Corporation | Optical sub-assembly for optoelectronic modules |
US20030030143A1 (en) * | 2001-08-10 | 2003-02-13 | Ingo Wennemuth | Electronic component with stacked electronic elements and method for fabricating an electronic component |
US20030057535A1 (en) * | 2001-09-24 | 2003-03-27 | National Semiconductor Corporation | Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package |
US20030141583A1 (en) * | 2002-01-31 | 2003-07-31 | Yang Chaur-Chin | Stacked package |
US6624507B1 (en) * | 2000-05-09 | 2003-09-23 | National Semiconductor Corporation | Miniature semiconductor package for opto-electronic devices |
US20030189214A1 (en) * | 2000-05-09 | 2003-10-09 | National Semiconductor Corporation, A Delaware Corp. | Techniques for joining an opto-electronic module to a semiconductor package |
US20050013581A1 (en) * | 2003-07-15 | 2005-01-20 | National Semiconductor Corporation | Multi-purpose optical light pipe |
US20050013560A1 (en) * | 2003-07-15 | 2005-01-20 | National Semiconductor Corporation | Opto-electronic module form factor having adjustable optical plane height |
US20060046436A1 (en) * | 2000-09-11 | 2006-03-02 | Shinji Ohuchi | Manufacturing method of stack-type semiconductor device |
US7023705B2 (en) | 2001-08-03 | 2006-04-04 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US20060140534A1 (en) * | 2001-08-03 | 2006-06-29 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US20060278968A1 (en) * | 2005-06-13 | 2006-12-14 | Shinko Electric Industries Co., Ltd. | Laminated semiconductor package |
KR100658734B1 (en) | 2004-11-11 | 2006-12-19 | 주식회사 유니세미콘 | A stack semiconductor package and its manufacture method |
US20070015314A1 (en) * | 2004-05-24 | 2007-01-18 | Chippac, Inc | Adhesive/Spacer Island Structure for Multiple Die Package |
US20080083976A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
EP1916713A2 (en) * | 2006-10-27 | 2008-04-30 | Shinko Electric Industries Co., Ltd. | Semiconductor package and stacked layer type semiconductor package formed with it |
US20080203552A1 (en) * | 2005-02-15 | 2008-08-28 | Unisemicon Co., Ltd. | Stacked Package and Method of Fabricating the Same |
US20090039528A1 (en) * | 2007-08-09 | 2009-02-12 | Tessera, Inc. | Wafer level stacked packages with individual chip selection |
US20090316378A1 (en) * | 2008-06-16 | 2009-12-24 | Tessera Research Llc | Wafer level edge stacking |
US20100230795A1 (en) * | 2009-03-13 | 2010-09-16 | Tessera Technologies Hungary Kft. | Stacked microelectronic assemblies having vias extending through bond pads |
US20110006432A1 (en) * | 2007-07-27 | 2011-01-13 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US20110031629A1 (en) * | 2006-10-10 | 2011-02-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20110049696A1 (en) * | 2006-10-10 | 2011-03-03 | Tessera, Inc. | Off-chip vias in stacked chips |
GB2477291A (en) * | 2010-01-27 | 2011-08-03 | Thales Holdings Uk Plc | Microwave circuit package |
US8101459B2 (en) | 2001-08-24 | 2012-01-24 | Micron Technology, Inc. | Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween |
US20120119380A1 (en) * | 2010-11-15 | 2012-05-17 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
US8697457B1 (en) | 2011-06-22 | 2014-04-15 | Bae Systems Information And Electronic Systems Integration Inc. | Devices and methods for stacking individually tested devices to form multi-chip electronic modules |
US9041227B2 (en) | 2011-10-17 | 2015-05-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9095074B2 (en) | 2012-12-20 | 2015-07-28 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9123664B2 (en) | 2010-07-19 | 2015-09-01 | Tessera, Inc. | Stackable molded microelectronic packages |
US9153562B2 (en) | 2004-11-03 | 2015-10-06 | Tessera, Inc. | Stacked packaging improvements |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US9218988B2 (en) | 2005-12-23 | 2015-12-22 | Tessera, Inc. | Microelectronic packages and methods therefor |
US9224717B2 (en) | 2011-05-03 | 2015-12-29 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US9324681B2 (en) | 2010-12-13 | 2016-04-26 | Tessera, Inc. | Pin attachment |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
US20210111132A1 (en) * | 2018-02-15 | 2021-04-15 | Micron Technology, Inc. | Method for Substrate Moisture NCF Voiding Elimination |
Families Citing this family (86)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IL123207A0 (en) | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
KR100318293B1 (en) * | 1999-11-02 | 2001-12-24 | 김 무 | Flip chip semiconductor package and manufacturing method thereof |
KR100324333B1 (en) | 2000-01-04 | 2002-02-16 | 박종섭 | Stacked package and fabricating method thereof |
KR100386081B1 (en) * | 2000-01-05 | 2003-06-09 | 주식회사 하이닉스반도체 | Semiconductor package and fabricating method thereof |
JP3813402B2 (en) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
KR100639700B1 (en) * | 2000-02-14 | 2006-10-31 | 삼성전자주식회사 | Chip scale stack chip package |
JP2001250907A (en) * | 2000-03-08 | 2001-09-14 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
US6545868B1 (en) * | 2000-03-13 | 2003-04-08 | Legacy Electronics, Inc. | Electronic module having canopy-type carriers |
US6713854B1 (en) | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
US7102892B2 (en) | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
JP3822043B2 (en) * | 2000-09-25 | 2006-09-13 | 太陽誘電株式会社 | Chip part assembly manufacturing method |
US7337522B2 (en) * | 2000-10-16 | 2008-03-04 | Legacy Electronics, Inc. | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
KR100375168B1 (en) * | 2000-11-02 | 2003-03-08 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and method for manufacturing the same |
EP1356718A4 (en) | 2000-12-21 | 2009-12-02 | Tessera Tech Hungary Kft | Packaged integrated circuits and methods of producing thereof |
US6885106B1 (en) | 2001-01-11 | 2005-04-26 | Tessera, Inc. | Stacked microelectronic assemblies and methods of making same |
JP4586273B2 (en) * | 2001-01-15 | 2010-11-24 | ソニー株式会社 | Semiconductor device structure |
EP1378152A4 (en) * | 2001-03-14 | 2006-02-01 | Legacy Electronics Inc | A method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
DE10120408B4 (en) * | 2001-04-25 | 2006-02-02 | Infineon Technologies Ag | Electronic component with a semiconductor chip, electronic assembly of stacked semiconductor chips and method for their production |
JP3999945B2 (en) * | 2001-05-18 | 2007-10-31 | 株式会社東芝 | Manufacturing method of semiconductor device |
US6548759B1 (en) | 2001-06-28 | 2003-04-15 | Amkor Technology, Inc. | Pre-drilled image sensor package |
US6730536B1 (en) | 2001-06-28 | 2004-05-04 | Amkor Technology, Inc. | Pre-drilled image sensor package fabrication method |
US6486545B1 (en) * | 2001-07-26 | 2002-11-26 | Amkor Technology, Inc. | Pre-drilled ball grid array package |
US20030048624A1 (en) * | 2001-08-22 | 2003-03-13 | Tessera, Inc. | Low-height multi-component assemblies |
DE10147376B4 (en) * | 2001-09-26 | 2009-01-15 | Infineon Technologies Ag | Electronic component and leadframe and method for producing the same |
US6897565B2 (en) * | 2001-10-09 | 2005-05-24 | Tessera, Inc. | Stacked packages |
KR100980356B1 (en) * | 2002-02-26 | 2010-09-06 | 레가시 일렉트로닉스, 인크. | Modular integrated circuit chip carrier |
WO2004017399A1 (en) * | 2002-08-16 | 2004-02-26 | Tessera, Inc. | Microelectronic packages with self-aligning features |
DE10239866B3 (en) * | 2002-08-29 | 2004-04-08 | Infineon Technologies Ag | Production of a semiconductor component used in circuit boards comprises forming electrical contact surfaces together within a smaller contacting region as the whole surface of the front side of the chip and further processing |
US7294928B2 (en) * | 2002-09-06 | 2007-11-13 | Tessera, Inc. | Components, methods and assemblies for stacked packages |
US7071547B2 (en) * | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
KR20040026530A (en) * | 2002-09-25 | 2004-03-31 | 삼성전자주식회사 | Semiconductor package and stack package using the same |
WO2004034434A2 (en) * | 2002-10-11 | 2004-04-22 | Tessera, Inc. | Components, methods and assemblies for multi-chip packages |
US7208825B2 (en) * | 2003-01-22 | 2007-04-24 | Siliconware Precision Industries Co., Ltd. | Stacked semiconductor packages |
KR100604821B1 (en) * | 2003-06-30 | 2006-07-26 | 삼성전자주식회사 | Stack type Ball grid array package and method for manufacturing the same |
US20050017337A1 (en) * | 2003-07-21 | 2005-01-27 | Cherng-Chiao Wu | Stacking apparatus for integrated circuit assembly |
KR100546374B1 (en) * | 2003-08-28 | 2006-01-26 | 삼성전자주식회사 | Multi chip package having center pads and method for manufacturing the same |
US7061121B2 (en) | 2003-11-12 | 2006-06-13 | Tessera, Inc. | Stacked microelectronic assemblies with central contacts |
DE102004010614B4 (en) * | 2004-03-02 | 2006-12-14 | Infineon Technologies Ag | A base semiconductor device for a semiconductor component stack and method of making the same |
DE102004027788A1 (en) * | 2004-06-08 | 2006-01-05 | Infineon Technologies Ag | Semiconductor base component for semiconductor component pile, has boundary regions of substrate surrounding chip, with elastic contact unit which is electrically connected with regions of distribution plate |
DE102004036909B4 (en) | 2004-07-29 | 2007-04-05 | Infineon Technologies Ag | A semiconductor base device with a wiring substrate and an intermediate wiring board for a semiconductor device stack, and a method of manufacturing the same |
KR100626618B1 (en) * | 2004-12-10 | 2006-09-25 | 삼성전자주식회사 | Semiconductor chip stack package and related fabrication method |
JP4444088B2 (en) * | 2004-12-10 | 2010-03-31 | 新光電気工業株式会社 | Semiconductor device |
WO2006076381A2 (en) * | 2005-01-12 | 2006-07-20 | Legacy Electronics, Inc. | Radial circuit board, system, and methods |
US20070141751A1 (en) * | 2005-12-16 | 2007-06-21 | Mistry Addi B | Stackable molded packages and methods of making the same |
DE102006024147B3 (en) * | 2006-05-22 | 2007-11-29 | Infineon Technologies Ag | An electronic module including a semiconductor device package and a semiconductor chip and method of making the same |
US7615409B2 (en) * | 2006-06-29 | 2009-11-10 | Sandisk Corporation | Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages |
US7550834B2 (en) * | 2006-06-29 | 2009-06-23 | Sandisk Corporation | Stacked, interconnected semiconductor packages |
SG139573A1 (en) * | 2006-07-17 | 2008-02-29 | Micron Technology Inc | Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods |
US7928582B2 (en) * | 2007-03-09 | 2011-04-19 | Micron Technology, Inc. | Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces |
US8188586B2 (en) * | 2007-11-01 | 2012-05-29 | Stats Chippac Ltd. | Mountable integrated circuit package system with mounting interconnects |
US20090152740A1 (en) * | 2007-12-17 | 2009-06-18 | Soo-San Park | Integrated circuit package system with flip chip |
US8120186B2 (en) | 2008-02-15 | 2012-02-21 | Qimonda Ag | Integrated circuit and method |
US7919871B2 (en) * | 2008-03-21 | 2011-04-05 | Stats Chippac Ltd. | Integrated circuit package system for stackable devices |
US7859094B2 (en) * | 2008-09-25 | 2010-12-28 | Stats Chippac Ltd. | Integrated circuit package system for stackable devices |
US8458477B2 (en) * | 2008-12-01 | 2013-06-04 | Novell, Inc. | Communication with non-repudiation |
KR101534680B1 (en) * | 2009-02-23 | 2015-07-07 | 삼성전자주식회사 | Stack type semiconductor package |
JP2010212273A (en) * | 2009-03-06 | 2010-09-24 | Elpida Memory Inc | Semiconductor package substrate, semiconductor package using the substrate, and method of manufacturing semiconductor package substrate |
US20100244212A1 (en) * | 2009-03-27 | 2010-09-30 | Jong-Woo Ha | Integrated circuit packaging system with post type interconnector and method of manufacture thereof |
US8236610B2 (en) * | 2009-05-26 | 2012-08-07 | International Business Machines Corporation | Forming semiconductor chip connections |
US9070851B2 (en) | 2010-09-24 | 2015-06-30 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US8409923B2 (en) * | 2011-06-15 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit packaging system with underfill and method of manufacture thereof |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
JP2016092292A (en) * | 2014-11-07 | 2016-05-23 | イビデン株式会社 | Wiring board, and method of manufacturing the same |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US10043779B2 (en) | 2015-11-17 | 2018-08-07 | Invensas Corporation | Packaged microelectronic device for a package-on-package device |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
CN205944139U (en) | 2016-03-30 | 2017-02-08 | 首尔伟傲世有限公司 | Ultraviolet ray light -emitting diode spare and contain this emitting diode module |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US9917041B1 (en) * | 2016-10-28 | 2018-03-13 | Intel Corporation | 3D chip assemblies using stacked leadframes |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5045921A (en) * | 1989-12-26 | 1991-09-03 | Motorola, Inc. | Pad array carrier IC device using flexible tape |
US5172303A (en) * | 1990-11-23 | 1992-12-15 | Motorola, Inc. | Electronic component assembly |
US5477611A (en) * | 1993-09-20 | 1995-12-26 | Tessera, Inc. | Method of forming interface between die and chip carrier |
US5454160A (en) * | 1993-12-03 | 1995-10-03 | Ncr Corporation | Apparatus and method for stacking integrated circuit devices |
US6025258A (en) * | 1994-01-20 | 2000-02-15 | Fujitsu Limited | Method for fabricating solder bumps by forming solder balls with a solder ball forming member |
KR950027550U (en) * | 1994-03-07 | 1995-10-18 | 정의훈 | Left side of the inclined guide of the cloth guide. Right feeder |
US5776796A (en) * | 1994-05-19 | 1998-07-07 | Tessera, Inc. | Method of encapsulating a semiconductor package |
JP2531382B2 (en) * | 1994-05-26 | 1996-09-04 | 日本電気株式会社 | Ball grid array semiconductor device and manufacturing method thereof |
JP2780649B2 (en) * | 1994-09-30 | 1998-07-30 | 日本電気株式会社 | Semiconductor device |
US5783870A (en) * | 1995-03-16 | 1998-07-21 | National Semiconductor Corporation | Method for connecting packages of a stacked ball grid array structure |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US5821456A (en) * | 1996-05-01 | 1998-10-13 | Motorola, Inc. | Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same |
JPH09321169A (en) * | 1996-05-24 | 1997-12-12 | Toray Ind Inc | Semiconductor package, semiconductor package circuit board, and semiconductor package member |
US6054337A (en) * | 1996-12-13 | 2000-04-25 | Tessera, Inc. | Method of making a compliant multichip package |
KR100214549B1 (en) * | 1996-12-30 | 1999-08-02 | 구본준 | Buttom lead package |
US5994166A (en) * | 1997-03-10 | 1999-11-30 | Micron Technology, Inc. | Method of constructing stacked packages |
US6117705A (en) * | 1997-04-18 | 2000-09-12 | Amkor Technology, Inc. | Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate |
US6020637A (en) * | 1997-05-07 | 2000-02-01 | Signetics Kp Co., Ltd. | Ball grid array semiconductor package |
US5950072A (en) * | 1997-07-25 | 1999-09-07 | Stmicroelectronics, Inc. | Low-profile removable ball-grid-array integrated circuit package |
KR100266637B1 (en) * | 1997-11-15 | 2000-09-15 | 김영환 | Stackable ball grid array semiconductor package and a method thereof |
US6051890A (en) * | 1997-12-24 | 2000-04-18 | Intel Corporation | Interleaving a bondwire between two bondwires coupled to a same terminal |
US6020633A (en) * | 1998-03-24 | 2000-02-01 | Xilinx, Inc. | Integrated circuit packaged for receiving another integrated circuit |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US6072233A (en) * | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
US6180881B1 (en) * | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
US5977640A (en) * | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
-
1998
- 1998-05-30 KR KR1019980020098A patent/KR100266693B1/en not_active IP Right Cessation
- 1998-10-01 DE DE19845316A patent/DE19845316C2/en not_active Expired - Fee Related
-
1999
- 1999-01-28 US US09/239,152 patent/US6291259B1/en not_active Expired - Lifetime
- 1999-04-01 JP JP11094767A patent/JP3063032B2/en not_active Expired - Fee Related
-
2001
- 2001-08-06 US US09/922,103 patent/US6407448B2/en not_active Expired - Lifetime
Cited By (120)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6642613B1 (en) * | 2000-05-09 | 2003-11-04 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US7247942B2 (en) | 2000-05-09 | 2007-07-24 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US7199440B2 (en) | 2000-05-09 | 2007-04-03 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US6624507B1 (en) * | 2000-05-09 | 2003-09-23 | National Semiconductor Corporation | Miniature semiconductor package for opto-electronic devices |
US20030189214A1 (en) * | 2000-05-09 | 2003-10-09 | National Semiconductor Corporation, A Delaware Corp. | Techniques for joining an opto-electronic module to a semiconductor package |
US20050100294A1 (en) * | 2000-05-09 | 2005-05-12 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US20040048417A1 (en) * | 2000-05-09 | 2004-03-11 | National Semiconductor Corporation, A Delaware Corp. | Techniques for joining an opto-electronic module to a semiconductor package |
US6838317B2 (en) | 2000-05-09 | 2005-01-04 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US20050117835A1 (en) * | 2000-05-09 | 2005-06-02 | National Semiconductor Corporation, A Delaware Corp. | Techniques for joining an opto-electronic module to a semiconductor package |
US6858468B2 (en) | 2000-05-09 | 2005-02-22 | National Semiconductor Corporation | Techniques for joining an opto-electronic module to a semiconductor package |
US7405138B2 (en) | 2000-09-11 | 2008-07-29 | Oki Electric Industry Co., Ltd. | Manufacturing method of stack-type semiconductor device |
US7019397B2 (en) * | 2000-09-11 | 2006-03-28 | Oki Electric Industry Co., Ltd. | Semiconductor device, manufacturing method of semiconductor device, stack type semiconductor device, and manufacturing method of stack type semiconductor device |
US20060046436A1 (en) * | 2000-09-11 | 2006-03-02 | Shinji Ohuchi | Manufacturing method of stack-type semiconductor device |
US7269027B2 (en) | 2001-08-03 | 2007-09-11 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US6916121B2 (en) | 2001-08-03 | 2005-07-12 | National Semiconductor Corporation | Optical sub-assembly for optoelectronic modules |
US20030026556A1 (en) * | 2001-08-03 | 2003-02-06 | National Semiconductor Corporation | Optical sub-assembly for optoelectronic modules |
US7023705B2 (en) | 2001-08-03 | 2006-04-04 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US20060140534A1 (en) * | 2001-08-03 | 2006-06-29 | National Semiconductor Corporation | Ceramic optical sub-assembly for optoelectronic modules |
US7086788B2 (en) | 2001-08-03 | 2006-08-08 | National Semiconductor Corporation | Optical sub-assembly for opto-electronic modules |
US20030030143A1 (en) * | 2001-08-10 | 2003-02-13 | Ingo Wennemuth | Electronic component with stacked electronic elements and method for fabricating an electronic component |
US8101459B2 (en) | 2001-08-24 | 2012-01-24 | Micron Technology, Inc. | Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween |
US6973225B2 (en) | 2001-09-24 | 2005-12-06 | National Semiconductor Corporation | Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package |
US20030057535A1 (en) * | 2001-09-24 | 2003-03-27 | National Semiconductor Corporation | Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package |
US20030141583A1 (en) * | 2002-01-31 | 2003-07-31 | Yang Chaur-Chin | Stacked package |
US6717253B2 (en) * | 2002-01-31 | 2004-04-06 | Advanced Semiconductor Engineering, Inc. | Assembly package with stacked dies and signal transmission plate |
US7156562B2 (en) | 2003-07-15 | 2007-01-02 | National Semiconductor Corporation | Opto-electronic module form factor having adjustable optical plane height |
US20050013581A1 (en) * | 2003-07-15 | 2005-01-20 | National Semiconductor Corporation | Multi-purpose optical light pipe |
US6985668B2 (en) | 2003-07-15 | 2006-01-10 | National Semiconductor Corporation | Multi-purpose optical light pipe |
US20050013560A1 (en) * | 2003-07-15 | 2005-01-20 | National Semiconductor Corporation | Opto-electronic module form factor having adjustable optical plane height |
US20070015314A1 (en) * | 2004-05-24 | 2007-01-18 | Chippac, Inc | Adhesive/Spacer Island Structure for Multiple Die Package |
US8623704B2 (en) * | 2004-05-24 | 2014-01-07 | Chippac, Inc. | Adhesive/spacer island structure for multiple die package |
US9153562B2 (en) | 2004-11-03 | 2015-10-06 | Tessera, Inc. | Stacked packaging improvements |
US9570416B2 (en) | 2004-11-03 | 2017-02-14 | Tessera, Inc. | Stacked packaging improvements |
KR100658734B1 (en) | 2004-11-11 | 2006-12-19 | 주식회사 유니세미콘 | A stack semiconductor package and its manufacture method |
US20080203552A1 (en) * | 2005-02-15 | 2008-08-28 | Unisemicon Co., Ltd. | Stacked Package and Method of Fabricating the Same |
US7288841B2 (en) | 2005-06-13 | 2007-10-30 | Shinko Electric Industries, Co., Ltd. | Laminated semiconductor package |
US20060278968A1 (en) * | 2005-06-13 | 2006-12-14 | Shinko Electric Industries Co., Ltd. | Laminated semiconductor package |
EP1734581A1 (en) * | 2005-06-13 | 2006-12-20 | Shinko Electric Industries Co., Ltd. | Laminated semiconductor package |
US9984901B2 (en) | 2005-12-23 | 2018-05-29 | Tessera, Inc. | Method for making a microelectronic assembly having conductive elements |
US9218988B2 (en) | 2005-12-23 | 2015-12-22 | Tessera, Inc. | Microelectronic packages and methods therefor |
US8513789B2 (en) | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
US8461673B2 (en) | 2006-10-10 | 2013-06-11 | Tessera, Inc. | Edge connect wafer level stacking |
US20110031629A1 (en) * | 2006-10-10 | 2011-02-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20110033979A1 (en) * | 2006-10-10 | 2011-02-10 | Tessera, Inc. | Edge connect wafer level stacking |
US20110049696A1 (en) * | 2006-10-10 | 2011-03-03 | Tessera, Inc. | Off-chip vias in stacked chips |
US9899353B2 (en) | 2006-10-10 | 2018-02-20 | Tessera, Inc. | Off-chip vias in stacked chips |
US20110187007A1 (en) * | 2006-10-10 | 2011-08-04 | Tessera, Inc. | Edge connect wafer level stacking |
US9048234B2 (en) | 2006-10-10 | 2015-06-02 | Tessera, Inc. | Off-chip vias in stacked chips |
US8022527B2 (en) * | 2006-10-10 | 2011-09-20 | Tessera, Inc. | Edge connect wafer level stacking |
US20080083976A1 (en) * | 2006-10-10 | 2008-04-10 | Tessera, Inc. | Edge connect wafer level stacking |
US8076788B2 (en) | 2006-10-10 | 2011-12-13 | Tessera, Inc. | Off-chip vias in stacked chips |
US8999810B2 (en) | 2006-10-10 | 2015-04-07 | Tessera, Inc. | Method of making a stacked microelectronic package |
US9378967B2 (en) | 2006-10-10 | 2016-06-28 | Tessera, Inc. | Method of making a stacked microelectronic package |
US8476774B2 (en) | 2006-10-10 | 2013-07-02 | Tessera, Inc. | Off-chip VIAS in stacked chips |
US8426957B2 (en) | 2006-10-10 | 2013-04-23 | Tessera, Inc. | Edge connect wafer level stacking |
US8431435B2 (en) | 2006-10-10 | 2013-04-30 | Tessera, Inc. | Edge connect wafer level stacking |
EP1916713A3 (en) * | 2006-10-27 | 2010-01-27 | Shinko Electric Industries Co., Ltd. | Semiconductor package and stacked layer type semiconductor package formed with it |
US8253229B2 (en) | 2006-10-27 | 2012-08-28 | Shinko Electric Industries Co., Ltd. | Semiconductor package and stacked layer type semiconductor package |
US20080290491A1 (en) * | 2006-10-27 | 2008-11-27 | Shinko Electric Industries Co., Ltd. | Semiconductor package and stacked layer type semiconductor package |
EP1916713A2 (en) * | 2006-10-27 | 2008-04-30 | Shinko Electric Industries Co., Ltd. | Semiconductor package and stacked layer type semiconductor package formed with it |
US8883562B2 (en) | 2007-07-27 | 2014-11-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US20110006432A1 (en) * | 2007-07-27 | 2011-01-13 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US8461672B2 (en) | 2007-07-27 | 2013-06-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
US8551815B2 (en) | 2007-08-03 | 2013-10-08 | Tessera, Inc. | Stack packages using reconstituted wafers |
US8513794B2 (en) | 2007-08-09 | 2013-08-20 | Tessera, Inc. | Stacked assembly including plurality of stacked microelectronic elements |
US20090039528A1 (en) * | 2007-08-09 | 2009-02-12 | Tessera, Inc. | Wafer level stacked packages with individual chip selection |
US8043895B2 (en) | 2007-08-09 | 2011-10-25 | Tessera, Inc. | Method of fabricating stacked assembly including plurality of stacked microelectronic elements |
US20090316378A1 (en) * | 2008-06-16 | 2009-12-24 | Tessera Research Llc | Wafer level edge stacking |
US8680662B2 (en) | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
US8466542B2 (en) | 2009-03-13 | 2013-06-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
US20100230795A1 (en) * | 2009-03-13 | 2010-09-16 | Tessera Technologies Hungary Kft. | Stacked microelectronic assemblies having vias extending through bond pads |
US8647927B2 (en) | 2010-01-27 | 2014-02-11 | Thales Holdings Uk Plc | Microwave circuit package |
US20110210431A1 (en) * | 2010-01-27 | 2011-09-01 | Thales Holdings Uk Plc | Microwave circuit package |
GB2477291A (en) * | 2010-01-27 | 2011-08-03 | Thales Holdings Uk Plc | Microwave circuit package |
GB2477291B (en) * | 2010-01-27 | 2014-06-11 | Thales Holdings Uk Plc | Microwave circuit package |
US9123664B2 (en) | 2010-07-19 | 2015-09-01 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US10128216B2 (en) | 2010-07-19 | 2018-11-13 | Tessera, Inc. | Stackable molded microelectronic packages |
US9570382B2 (en) | 2010-07-19 | 2017-02-14 | Tessera, Inc. | Stackable molded microelectronic packages |
US9553076B2 (en) | 2010-07-19 | 2017-01-24 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8637991B2 (en) * | 2010-11-15 | 2014-01-28 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US20120119380A1 (en) * | 2010-11-15 | 2012-05-17 | Tessera, Inc. | Microelectronic package with terminals on dielectric mass |
US9324681B2 (en) | 2010-12-13 | 2016-04-26 | Tessera, Inc. | Pin attachment |
US9224717B2 (en) | 2011-05-03 | 2015-12-29 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US11424211B2 (en) | 2011-05-03 | 2022-08-23 | Tessera Llc | Package-on-package assembly with wire bonds to encapsulation surface |
US9691731B2 (en) | 2011-05-03 | 2017-06-27 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
US8697457B1 (en) | 2011-06-22 | 2014-04-15 | Bae Systems Information And Electronic Systems Integration Inc. | Devices and methods for stacking individually tested devices to form multi-chip electronic modules |
US10756049B2 (en) | 2011-10-17 | 2020-08-25 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US11735563B2 (en) | 2011-10-17 | 2023-08-22 | Invensas Llc | Package-on-package assembly with wire bond vias |
US9041227B2 (en) | 2011-10-17 | 2015-05-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9252122B2 (en) | 2011-10-17 | 2016-02-02 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9761558B2 (en) | 2011-10-17 | 2017-09-12 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US11189595B2 (en) | 2011-10-17 | 2021-11-30 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US9691679B2 (en) | 2012-02-24 | 2017-06-27 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9917073B2 (en) | 2012-07-31 | 2018-03-13 | Invensas Corporation | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package |
US10297582B2 (en) | 2012-08-03 | 2019-05-21 | Invensas Corporation | BVA interposer |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9615456B2 (en) | 2012-12-20 | 2017-04-04 | Invensas Corporation | Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface |
US9095074B2 (en) | 2012-12-20 | 2015-07-28 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9601454B2 (en) | 2013-02-01 | 2017-03-21 | Invensas Corporation | Method of forming a component having wire bonds and a stiffening layer |
US10460958B2 (en) | 2013-08-07 | 2019-10-29 | Invensas Corporation | Method of manufacturing embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US10008477B2 (en) | 2013-09-16 | 2018-06-26 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US10026717B2 (en) | 2013-11-22 | 2018-07-17 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9728527B2 (en) | 2013-11-22 | 2017-08-08 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9852969B2 (en) | 2013-11-22 | 2017-12-26 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US10529636B2 (en) | 2014-01-17 | 2020-01-07 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9837330B2 (en) | 2014-01-17 | 2017-12-05 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US11404338B2 (en) | 2014-01-17 | 2022-08-02 | Invensas Corporation | Fine pitch bva using reconstituted wafer with area array accessible for testing |
US10475726B2 (en) | 2014-05-29 | 2019-11-12 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US10032647B2 (en) | 2014-05-29 | 2018-07-24 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US20210111132A1 (en) * | 2018-02-15 | 2021-04-15 | Micron Technology, Inc. | Method for Substrate Moisture NCF Voiding Elimination |
Also Published As
Publication number | Publication date |
---|---|
JPH11354669A (en) | 1999-12-24 |
DE19845316C2 (en) | 2002-01-24 |
JP3063032B2 (en) | 2000-07-12 |
DE19845316A1 (en) | 1999-12-02 |
US6407448B2 (en) | 2002-06-18 |
KR19990086916A (en) | 1999-12-15 |
US6291259B1 (en) | 2001-09-18 |
KR100266693B1 (en) | 2000-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6407448B2 (en) | Stackable ball grid array semiconductor package and fabrication method thereof | |
US5684330A (en) | Chip-sized package having metal circuit substrate | |
US7391105B2 (en) | Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same | |
US6043430A (en) | Bottom lead semiconductor chip package | |
US5677566A (en) | Semiconductor chip package | |
US6738263B2 (en) | Stackable ball grid array package | |
US6531337B1 (en) | Method of manufacturing a semiconductor structure having stacked semiconductor devices | |
US8269323B2 (en) | Integrated circuit package with etched leadframe for package-on-package interconnects | |
US5838061A (en) | Semiconductor package including a semiconductor chip adhesively bonded thereto | |
US20090032913A1 (en) | Component and assemblies with ends offset downwardly | |
US7105919B2 (en) | Semiconductor package having ultra-thin thickness and method of manufacturing the same | |
US20030089983A1 (en) | Ball grid array semiconductor package | |
US6329708B1 (en) | Micro ball grid array semiconductor device and semiconductor module | |
US6285086B1 (en) | Semiconductor device and substrate for semiconductor device | |
US5708304A (en) | Semiconductor device | |
US6137162A (en) | Chip stack package | |
US5951804A (en) | Method for simultaneously manufacturing chip-scale package using lead frame strip with a plurality of lead frames | |
US5994772A (en) | Semiconductor package | |
CA2095609C (en) | Leadless pad array chip carrier | |
US6166435A (en) | Flip-chip ball grid array package with a heat slug | |
US20050156322A1 (en) | Thin semiconductor package including stacked dies | |
JP3850712B2 (en) | Multilayer semiconductor device | |
USRE43112E1 (en) | Stackable ball grid array package | |
KR100464561B1 (en) | Semiconductor package and manufacturing method the same | |
US6285077B1 (en) | Multiple layer tape ball grid array package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:HYUNDAI ELECTRONICS INDUSTRIES CO., LTD.;REEL/FRAME:026828/0688 Effective date: 20010329 |
|
AS | Assignment |
Owner name: 658868 N.B. INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR INC.;REEL/FRAME:027234/0549 Effective date: 20110822 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, CANADA Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196 Effective date: 20111223 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: CHANGE OF NAME;ASSIGNOR:658868 N.B. INC.;REEL/FRAME:032439/0547 Effective date: 20140101 |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT IP N.B. 276 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001 Effective date: 20140611 Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:036159/0386 Effective date: 20150514 |
|
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054371/0884 Effective date: 20201028 |