US20010041943A1 - Simultaneous wired and wireless remote in-system programming of multiple remote systems - Google Patents

Simultaneous wired and wireless remote in-system programming of multiple remote systems Download PDF

Info

Publication number
US20010041943A1
US20010041943A1 US08/964,421 US96442197A US2001041943A1 US 20010041943 A1 US20010041943 A1 US 20010041943A1 US 96442197 A US96442197 A US 96442197A US 2001041943 A1 US2001041943 A1 US 2001041943A1
Authority
US
United States
Prior art keywords
isp
programming
data
control
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US08/964,421
Other versions
US6389321B2 (en
Inventor
Howard Y. Tang
Albert Chan
Cyrus Y. Tsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Lattice Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corp filed Critical Lattice Semiconductor Corp
Assigned to LATTICE SEMICONDUCTOR CORPORATION reassignment LATTICE SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAN, ALBERT, TANG, HOWARD Y.M., TSUI, CYRUS Y.
Priority to US08/964,421 priority Critical patent/US6389321B2/en
Priority to GB0013382A priority patent/GB2346997B/en
Priority to AU13092/99A priority patent/AU1309299A/en
Priority to PCT/US1998/023562 priority patent/WO1999023588A1/en
Publication of US20010041943A1 publication Critical patent/US20010041943A1/en
Publication of US6389321B2 publication Critical patent/US6389321B2/en
Application granted granted Critical
Assigned to JEFFERIES FINANCE LLC reassignment JEFFERIES FINANCE LLC SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DVDO, INC., LATTICE SEMICONDUCTOR CORPORATION, SIBEAM, INC., SILICON IMAGE, INC.
Anticipated expiration legal-status Critical
Assigned to LATTICE SEMICONDUCTOR CORPORATION, SILICON IMAGE, INC., DVDO, INC., SIBEAM, INC. reassignment LATTICE SEMICONDUCTOR CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JEFFERIES FINANCE LLC
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/34Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Definitions

  • the present invention relates to programmable integrated circuits, and in particular, the present invention relates to techniques for remotely programming multiple programmable systems sequentially or simultaneously over wired or wireless links between a programming host device and the programmable systems.
  • ISP PLD In-System programmable logic device
  • U.S. Pat. No. 5,635,855 entitled “Method for Simultaneous Programming of In-System Programmable Integrated Circuits”, to Tang et al, filed on Jul. 21, 1995 and issued on Jun. 3, 1997.
  • a reprogrammable system is reprogrammed by a host programming device over a hardwired connection. It is desirable to allow such a reprogrammable system to be reprogrammed over wired or wireless links established at the time of reprogramming, so as to allow reprogramming by a “remotely located” programmer, such as a portable programming device or a programming device physically located at any arbitrary location.
  • the present invention provides an in-system programmable (ISP) system which can be reprogrammed by remote access.
  • ISP in-system programmable
  • the ISP system includes an access interface for sending and receiving data over a communication link, so as to allow control and programming data used in ISP programming to be downloaded.
  • Each ISP system includes one or more ISP controllers for programming multiple ISP devices according to the control and programming data received by the access interface.
  • each ISP device is programmed under the control of a programming clock signal and a mode signal.
  • the ISP device receives control and programming data from a serial input signal and provides data output, including status and echoed control and programming data, through a serial data output signal.
  • the ISP system of the present invention can be coupled to a host programming system through a communication link that may include a wired or wireless data network, such as a telephone network, or a radio channel.
  • a communication link may include a wired or wireless data network, such as a telephone network, or a radio channel.
  • the ISP controller in an ISP system can receive data from the access interface either serially or in parallel.
  • a central processing unit can be provided to control the ISP system.
  • the central processing unit can include a microprocessor, a random access memory for storing control and programming data received over the communication link and an address bus for specifying the memory locations or device accessed.
  • the ISP controller includes a microprocessor for controlling programming of the ISP devices under the ISP controller's control.
  • Each ISP controller can program multiple ISP devices simultaneously. Thus, if multiple ISP controllers are present in the same ISP system under the control of a central processing unit, a large number of ISP devices can be simultaneously programmed by remote access.
  • the ISP system is programmed by remote access by a host programming system which includes one or more programming host computers.
  • Each host computer includes a central processing unit, which may be a personal computer or an engineering workstation, and an access interface for accessing the communication link.
  • These host units can be coupled by a computer network, which may be a local area network or a wide area network.
  • FIG. 1 shows a configuration 100 in a first embodiment of the present invention
  • a programming host system 101 remotely accesses the ISP systems 103 , 104 and 105 over a wired data network 102 .
  • FIG. 2 shows a configuration 200 in a second embodiment of the present invention
  • the wireless link between programming host system 201 and any one of ISP systems 203 , 204 and 205 is provided by a wireless data network 202 .
  • FIG. 3 shows a configuration 300 in a third embodiment of the present invention
  • the wireless link between programming host system 301 and any one of ISP systems 303 , 304 and 305 is provided by a broadcast radio channel 302 .
  • FIG. 4 shows an ISP system 400 , suitable for implementing any of ISP systems 103 , 104 and 105 of configuration 100 of FIG. 1.
  • FIG. 5 shows an ISP system 500 , suitable for implementing any of ISP systems 203 , 204 and 205 of configuration 200 of FIG. 2.
  • FIG. 6 shows an ISP system 600 , suitable for implementing any of ISP systems 303 , 304 and 305 of FIG. 3.
  • FIG. 7 is a programming host system 700 , suitable for implementing any of programming host systems 101 , 201 and 301 of FIGS. 1 - 3 .
  • FIG. 8 shows an ISP controller 800 in one embodiment of the present invention.
  • FIG. 1 illustrates a configuration 100 in a first embodiment of the present invention, in which the programming device remotely accesses ISP systems over a wired data network.
  • a programming device (“host programming system”) 101 is shown coupled by a wired data network (e.g., a wired telephone network) 102 to remote ISP systems 103 , 104 and 105 .
  • a wired data network e.g., a wired telephone network
  • configuration 100 reprogramming of ISP systems 103 , 104 and 105 is initiated when host programming system 101 receives a command, represented by a signal from terminal 106 , and programming data, represented by reprogramming data 107 .
  • programming data 107 can be provided by an ispSTREAM file, which is a file format widely adopted for use with ISP PLDs available from Lattice Semiconductor Corporation.
  • ispSTREAM file programming commands (“control data”) and programming data for an ISP PLD are compiled in a binary format.
  • host programming system 101 and ISP systems 103 , 104 and 105 are interfaced to telephone network 102 via modems.
  • FIG. 2 shows a configuration 200 in a second embodiment of the present invention.
  • the wireless link between programming host system 201 and any one of ISP systems 203 , 204 and 205 is provided by a wireless data network 202 , such as a cellular telephone network.
  • FIG. 3 shows a configuration 300 in a third embodiment of the present invention.
  • the wireless link between programming host system 301 and any one of ISP systems 303 , 304 and 305 is provided by a broadcast radio channel 302 .
  • gateways exist between wired and wireless telephone networks
  • the present invention can be practiced in a configuration in which some ISP systems are reprogrammed over a wired data network, while other ISP systems are reprogrammed over a wireless data network (e.g., a wireless telephone system) through a gateway in the wired data network.
  • a wireless data network e.g., a wireless telephone system
  • ISP systems 103 , 104 and 105 in configuration 100 can be each provided by ISP system 400 of FIG. 4.
  • ISP system 400 includes a remote access interface 401 , which is coupled by a 2-wire serial data interface 403 to an ISP controller 402 .
  • access interface 401 is implemented by a wired telephone modem to allow access to the telephone network over telephone lines 406 .
  • ISP controller 402 which is described in further detail below, performs the actual programming of ISP devices, such as ISP devices 404 and 405 .
  • ISP devices 404 and 405 are daisy-chained to allow shifting control and programming data in and out of each of these ISP devices.
  • serial input data terminal 411 serial input data terminal 411
  • SDO/TDO serial data output terminal 410
  • data shifting is synchronized by a clock signal 407 (“SCLK/TCK”), which is provided by ISP controller 402 to each of ISP devices 404 and 405 in parallel.
  • Control signal 408 (“MODE/TMS”) indicates whether the data currently shifted into or out of the ISP device is control data or programming data.
  • Programming mode is entered when the ISP mode enable signal (“ispEN”) at terminal 409 is asserted.
  • the SDI/TDI, SDO/TDO, ispEN, SCLK/TCK and MODE/TMS signals are referred to as ISP signals.
  • FIG. 8 shows an ISP controller 800 in one embodiment of the present invention.
  • ISP controller 800 can implement ISP controller 402 in each of configurations 100 , 200 and 300 .
  • ISP controller 800 can be provided as an integrated circuit. As shown in FIG. 8, ISP controller 800 provides ISP signals SCLK/TCK, MODE/TMS, ispEN, SDI/TDI and SDO/TDO over a parallel port 803 on terminals 407 , 408 , 409 , 410 and 411 respectively.
  • ISP controller 800 is provided both a parallel port 802 and a serial port 804 , thus allowing sending and receiving control and programming data, at the user's option (i.e., according to a control signal at terminal 808 ), over 8-bit parallel bus 603 or 2-wire serial bus 403 .
  • ISP controller 800 is controlled by a microprocessor core running programs stored in non-volatile program read-only memory (ROM) 807 .
  • ROM non-volatile program read-only memory
  • Random access memory 806 is provided as run time storage.
  • ISP system 500 An example of an ISP system suitable for implementing any of ISP systems 203 , 204 and 205 is illustrated by ISP system 500 of FIG. 5.
  • ISP system 500 is similar to ISP system 400 , except that access interface 501 in ISP system 500 is implemented by a wireless telephone modem, and the programming signals are transmitted through an antenna indicated by reference numeral 502 .
  • ISP system 600 An example of an ISP system suitable for implementing any of ISP systems 303 , 304 and 305 is provided in ISP system 600 .
  • access interface 601 is provided by a transceiver, i.e., a radio communication device having both a transmitter and a receiver.
  • transceiver i.e., a radio communication device having both a transmitter and a receiver.
  • like elements in these ISP systems are provided like reference numerals.
  • ISP system 600 Unlike ISP systems 400 and 500 , which each maintain a 2-wire serial data interface 403 between access interface 401 or 501 and the ISP controller in each of these ISP systems, ISP system 600 provides an 8-bit parallel data bus writable by access interface 601 .
  • ISP system 600 includes a microprocessor 605 , which executes control programs stored in a non-volatile storage element 608 (e.g., an EPROM).
  • programming data received from the transceiver at access interface 601 are stored in random access memory (“RAM”) 607 .
  • RAM 607 and nonvolatile storage element 608 can share a common address space. Further, as shown in FIG.
  • ISP system 600 may contain multiple ISP controllers each assigned an address in the shared common address space.
  • An address in ISP system 600 is decoded by a chip-select decoder 609 to provide a chip select control signal for selecting one of the ISP controllers.
  • the programming data stored in RAM 607 can be provided to ISP controller 402 via data bus 603 under the control of microprocessor 605 , which provides a control signal 610 (“read/write”) for latching the data into ISP controller 402 .
  • the multiple ISP controllers in ISP system 600 can program a large number of ISP devices in parallel, without incurring large latencies due to the long daisy-chains of ISP devices.
  • the microprocessor-based ISP system taught by ISP system 600 can be adapted for use with any of access interfaces, whether implemented by wired or wireless data network interfaces.).
  • FIG. 7 shows programming host system 700 as including host machines 701 and 702 coupled by a computer network 703 .
  • Computer network 703 can be a local area network, a dial-up network or a wide area network.
  • host machine 702 may be physically at the same geographical location as the ISP systems it programs, or host machine 701 can be a machine at a vendor site or a development site which provides updates of control and programming information to ISP devices on demand or periodically.
  • Host machines 701 and 702 are each capable of supporting multiple remote ISP systems, such as any of remote ISP systems 103 - 105 , 203 - 205 and 303 - 305 .
  • host machines 701 and 702 are similarly equipped. Thus, to simplify discussion, corresponding elements in host machines 701 and 702 are provided corresponding reference numerals, with a suffix “a” attached for elements in host machine 701 and a suffix “b” for corresponding elements in host machine 702 .
  • host machine 701 includes a central processing unit (“CPU”) 705 a , which can be implemented by a workstation or a personal computer.
  • CPU 705 a sends control and programming data to a remote ISP system via (a) wired modem 706 a , for such ISP system as ISP system 103 of FIG.
  • host system 701 can be controlled from terminal 709 a and stores control and programming data in ispSTREAM files in storage element 710 .
  • host machine 702 obtains ispSTREAM files over network 703 through a server running on host machine 701 .
  • an ISP system under configuration 100 of FIG. 1 e.g., any one of ISP systems 103 , 104 and 105 .
  • control and programming data arrive from host system 101 at the access interface over wired data network 102 .
  • a wired modem in the ISP system e.g., wired telephone modem 401 in ISP system 400 of FIG. 4, provides the control and programming data serially to the RXD line of the ISP controller's 2-wire serial data port (e.g., serial port 804 in ISP controller 800 of FIG. 8).
  • Control and programming data arrive at the access interface, e.g., received by transceiver 601 from the radio channel.
  • the access interface provides the control and programming data as digital signals on a data bus (e.g., data bus 603 ) under the control of the microprocessor (e.g., microprocessor 605 ).
  • the microprocessor which executes a program stored in the non-volatile memory (e.g., EPROM 608 ), specifies an address on an address bus (e.g., address bus 604 ), so as to store the data on the data bus into memory (e.g., RAM 607 ).
  • Step 2.2 is repeated until all control and programming data are stored into memory.
  • the microprocessor then asserts a control signal to select an ISP controller (e.g., ISP controller 402 ) and begins to retrieve the control and programming data from memory onto the data bus.
  • ISP controller e.g., ISP controller 402
  • the microprocessor asserts a write signal (e.g., read/write signal 610 ) to latch the data into the ISP controller.
  • a write signal e.g., read/write signal 610
  • the ISP controller activates the ISP signals (i.e., ispEN, SDI/TDI, SDO/TDO, SCLK/TCK, MODE/TMS) to program the ISP devices.
  • ISP signals i.e., ispEN, SDI/TDI, SDO/TDO, SCLK/TCK, MODE/TMS
  • the microprocessor directs the access interface to provide the status and response information to the host programming system by transmitting a message over the radio channel.
  • the ISP controller waits in standby mode until arrival of control and programming data.
  • the ISP controller Upon receiving the control and programming data, the ISP controller sets the ISP devices into programming mode by asserting the ispEN control signal.
  • the ISP controller then reads an identification code (ID) from each ISP device in the daisy-chain. Each ID is clocked out of the SDO/TDO pin (i.e., terminal 410 ); during this time, the ISP controller provides a clock signal on the SCLK/TCK pin (i.e., terminal 407 ).
  • ID identification code
  • the ISP controller compares the ID of each ISP device with the ID specified in the programming data, to ensure that the correct ISP device is programmed.
  • the ISP controller then shifts the control and programming data serially into the target ISP device via the SDI/TDI pin (i.e., terminal 411 ).
  • control and programming data are shifted serially into the ISP device, the control and programming data are echoed back to the ISP controller via the SDO/TDO pin.
  • the ISP controller calculates a checksum of the control and programming data echoed back from the ispLSI device.
  • the ISP controller provides at either the serial output (i.e., 2-wire serial data port 403 ) or the parallel data bus 603 , a code indicating whether the ISP device is correctly programmed.
  • the ISP device is set to SHIFT state.
  • the ISP device is set to EXECUTE state.
  • the ISP signals are held steady for 200 milliseconds to erase any pattern from the ISP device.
  • the ISP device is set to SHIFT state.
  • the ISP device is set to EXECUTE state.
  • the ISP device is set to SHIFT state.
  • the ISP device is set to EXECUTE state.
  • the ISP device is set to SHIFT state.
  • the ISP device is set to EXECUTE state.
  • the ISP device is set to SHIFT state.
  • the ISP device is set to the SHIFT state.
  • the ISP device is set to the EXECUTE state.
  • the host programming system e.g., host programming system 701 , performs the following operations:
  • the host programming system retrieves from storage an ispSTREAM file, e.g., from disk storage into the memory of a microcomputer or a workstation.
  • the host programming system accesses the communication channel (e.g. wired data network 102 , wireless data network 202 , or radio channel 302 ) so as to reach the ISP systems.
  • the communication channel e.g. wired data network 102 , wireless data network 202 , or radio channel 302
  • the central processing unit (e.g. CPU 705 a ) of the host programming system activates the access interface (e.g. wired modem 706 a , wireless modem 707 a , or transceiver 704 a ) to send to the remote ISP systems an identity code identifying the host programming system.
  • the access interface e.g. wired modem 706 a , wireless modem 707 a , or transceiver 704 a
  • the host programming system can sign onto a second remote host programming system (e.g. host programming system 702 ) to allow further accesses to ISP systems.
  • a second remote host programming system e.g. host programming system 702
  • the CPU then scans a binary code answer-back (e.g. a 64-bit integer) from each of the ISP systems and compares the binary code received to the binary code of the host programming system.
  • a binary code answer-back e.g. a 64-bit integer

Abstract

An in-system programmable (ISP) system can be programmed by remote access from a host programming system. The remote access can be accomplished over a wired data network, a wireless data network, a radio channel, or any combination of the above. In the ISP system, an ISP controller receives control and programming data through the access interface to program ISP devices in accordance with ISP programming conventions. The ISP controller can be provided by an integrated circuit having a microprocessor core.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to programmable integrated circuits, and in particular, the present invention relates to techniques for remotely programming multiple programmable systems sequentially or simultaneously over wired or wireless links between a programming host device and the programmable systems. [0002]
  • 2. Discussion of the Related Art [0003]
  • Programmable devices that are programmed and reprogrammed without being removed from its application environment are widely preferred. One example of such a device is the “In-System programmable logic device” or “ISP PLD”, available from Lattice Semiconductor Corp. One method for reprogramming ISP PLDs is disclosed in U.S. Pat. No. 5,635,855, entitled “Method for Simultaneous Programming of In-System Programmable Integrated Circuits”, to Tang et al, filed on Jul. 21, 1995 and issued on Jun. 3, 1997. [0004]
  • In the prior art, a reprogrammable system is reprogrammed by a host programming device over a hardwired connection. It is desirable to allow such a reprogrammable system to be reprogrammed over wired or wireless links established at the time of reprogramming, so as to allow reprogramming by a “remotely located” programmer, such as a portable programming device or a programming device physically located at any arbitrary location. [0005]
  • SUMMARY OF THE INVENTION
  • The present invention provides an in-system programmable (ISP) system which can be reprogrammed by remote access. Such a system allows the configurations of ISP devices to be updated in the field without requiring a hardwired connection to a tester or a programmer. [0006]
  • In one embodiment of the present invention, the ISP system includes an access interface for sending and receiving data over a communication link, so as to allow control and programming data used in ISP programming to be downloaded. Each ISP system includes one or more ISP controllers for programming multiple ISP devices according to the control and programming data received by the access interface. In this embodiment, each ISP device is programmed under the control of a programming clock signal and a mode signal. The ISP device receives control and programming data from a serial input signal and provides data output, including status and echoed control and programming data, through a serial data output signal. [0007]
  • The ISP system of the present invention can be coupled to a host programming system through a communication link that may include a wired or wireless data network, such as a telephone network, or a radio channel. [0008]
  • In one embodiment of the present invention, the ISP controller in an ISP system can receive data from the access interface either serially or in parallel. Further, a central processing unit can be provided to control the ISP system. The central processing unit can include a microprocessor, a random access memory for storing control and programming data received over the communication link and an address bus for specifying the memory locations or device accessed. [0009]
  • In one embodiment of the present invention, the ISP controller includes a microprocessor for controlling programming of the ISP devices under the ISP controller's control. Each ISP controller can program multiple ISP devices simultaneously. Thus, if multiple ISP controllers are present in the same ISP system under the control of a central processing unit, a large number of ISP devices can be simultaneously programmed by remote access. [0010]
  • In one embodiment of the present invention, the ISP system is programmed by remote access by a host programming system which includes one or more programming host computers. Each host computer includes a central processing unit, which may be a personal computer or an engineering workstation, and an access interface for accessing the communication link. These host units can be coupled by a computer network, which may be a local area network or a wide area network. [0011]
  • The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.[0012]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a [0013] configuration 100 in a first embodiment of the present invention; in configuration 100, a programming host system 101 remotely accesses the ISP systems 103, 104 and 105 over a wired data network 102.
  • FIG. 2 shows a [0014] configuration 200 in a second embodiment of the present invention; in configuration 200, the wireless link between programming host system 201 and any one of ISP systems 203, 204 and 205 is provided by a wireless data network 202.
  • FIG. 3 shows a [0015] configuration 300 in a third embodiment of the present invention; in configuration 300, the wireless link between programming host system 301 and any one of ISP systems 303, 304 and 305 is provided by a broadcast radio channel 302.
  • FIG. 4 shows an ISP system [0016] 400, suitable for implementing any of ISP systems 103, 104 and 105 of configuration 100 of FIG. 1.
  • FIG. 5 shows an ISP system [0017] 500, suitable for implementing any of ISP systems 203, 204 and 205 of configuration 200 of FIG. 2.
  • FIG. 6 shows an [0018] ISP system 600, suitable for implementing any of ISP systems 303, 304 and 305 of FIG. 3.
  • FIG. 7 is a programming host system [0019] 700, suitable for implementing any of programming host systems 101, 201 and 301 of FIGS. 1-3.
  • FIG. 8 shows an ISP controller [0020] 800 in one embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention is specifically illustrated in this detailed description using configurations for remote accessing and programming an in-system programmable (ISP) system over wired or wireless links. In this description, to simplify discussion, like elements in the drawings are provided like reference numerals. [0021]
  • FIG. 1 illustrates a [0022] configuration 100 in a first embodiment of the present invention, in which the programming device remotely accesses ISP systems over a wired data network. As shown in FIG. 1, a programming device (“host programming system”) 101 is shown coupled by a wired data network (e.g., a wired telephone network) 102 to remote ISP systems 103, 104 and 105. In configuration 100, reprogramming of ISP systems 103, 104 and 105 is initiated when host programming system 101 receives a command, represented by a signal from terminal 106, and programming data, represented by reprogramming data 107. In this embodiment, programming data 107 can be provided by an ispSTREAM file, which is a file format widely adopted for use with ISP PLDs available from Lattice Semiconductor Corporation. In an ispSTREAM file, programming commands (“control data”) and programming data for an ISP PLD are compiled in a binary format. As discussed below, host programming system 101 and ISP systems 103, 104 and 105 are interfaced to telephone network 102 via modems.
  • Alternatively, reprogramming of ISP systems can also be provided under the present invention over wireless links. Wireless links can be provided over a wireless data network (e.g. cellular telephone network) or by a direct broadcast network in which the programming data is directly transmitted over a radio channel and received by the target ISP systems. FIG. 2 shows a [0023] configuration 200 in a second embodiment of the present invention. In configuration 200, the wireless link between programming host system 201 and any one of ISP systems 203, 204 and 205 is provided by a wireless data network 202, such as a cellular telephone network. Similarly, FIG. 3 shows a configuration 300 in a third embodiment of the present invention. In configuration 300, the wireless link between programming host system 301 and any one of ISP systems 303, 304 and 305 is provided by a broadcast radio channel 302.
  • Those skilled in the art would appreciate from [0024] configurations 100, 200 and 300 that many variations and modification of these configuration can be practiced within the scope of the present invention. For example, since gateways exist between wired and wireless telephone networks, the present invention can be practiced in a configuration in which some ISP systems are reprogrammed over a wired data network, while other ISP systems are reprogrammed over a wireless data network (e.g., a wireless telephone system) through a gateway in the wired data network.
  • [0025] ISP systems 103, 104 and 105 in configuration 100 can be each provided by ISP system 400 of FIG. 4. As shown in FIG. 4, ISP system 400 includes a remote access interface 401, which is coupled by a 2-wire serial data interface 403 to an ISP controller 402. In this embodiment, access interface 401 is implemented by a wired telephone modem to allow access to the telephone network over telephone lines 406. ISP controller 402, which is described in further detail below, performs the actual programming of ISP devices, such as ISP devices 404 and 405. As shown in FIG. 4, ISP devices 404 and 405 are daisy-chained to allow shifting control and programming data in and out of each of these ISP devices. Typically, data is shifted in and out of an ISP device through serially, e.g., serial input data terminal 411 (“SDI/TDI”) and serial data output terminal 410 (“SDO/TDO”). In ISP system 400, data shifting is synchronized by a clock signal 407 (“SCLK/TCK”), which is provided by ISP controller 402 to each of ISP devices 404 and 405 in parallel. Control signal 408 (“MODE/TMS”) indicates whether the data currently shifted into or out of the ISP device is control data or programming data. Programming mode is entered when the ISP mode enable signal (“ispEN”) at terminal 409 is asserted. In the following, the SDI/TDI, SDO/TDO, ispEN, SCLK/TCK and MODE/TMS signals are referred to as ISP signals.
  • FIG. 8 shows an ISP controller [0026] 800 in one embodiment of the present invention. ISP controller 800 can implement ISP controller 402 in each of configurations 100, 200 and 300. ISP controller 800 can be provided as an integrated circuit. As shown in FIG. 8, ISP controller 800 provides ISP signals SCLK/TCK, MODE/TMS, ispEN, SDI/TDI and SDO/TDO over a parallel port 803 on terminals 407, 408, 409, 410 and 411 respectively. ISP controller 800 is provided both a parallel port 802 and a serial port 804, thus allowing sending and receiving control and programming data, at the user's option (i.e., according to a control signal at terminal 808), over 8-bit parallel bus 603 or 2-wire serial bus 403. ISP controller 800 is controlled by a microprocessor core running programs stored in non-volatile program read-only memory (ROM) 807. Random access memory 806 is provided as run time storage.
  • Since the programming of ISP devices is known to those skilled in the art, a detailed discussion of the syntax or semantics of any particular ISP “language” is omitted. A discussion regarding ISP programming can be found, for example, U.S. Pat. No. 5,237,218 to G. Josephson, issued on Aug. 19, 1993. [0027]
  • An example of an ISP system suitable for implementing any of [0028] ISP systems 203, 204 and 205 is illustrated by ISP system 500 of FIG. 5. ISP system 500 is similar to ISP system 400, except that access interface 501 in ISP system 500 is implemented by a wireless telephone modem, and the programming signals are transmitted through an antenna indicated by reference numeral 502.
  • An example of an ISP system suitable for implementing any of [0029] ISP systems 303, 304 and 305 is provided in ISP system 600. In ISP system 600, access interface 601 is provided by a transceiver, i.e., a radio communication device having both a transmitter and a receiver. To allow comparison among ISP systems 400, 500 and 600, like elements in these ISP systems are provided like reference numerals.
  • Unlike ISP systems [0030] 400 and 500, which each maintain a 2-wire serial data interface 403 between access interface 401 or 501 and the ISP controller in each of these ISP systems, ISP system 600 provides an 8-bit parallel data bus writable by access interface 601. In addition, ISP system 600 includes a microprocessor 605, which executes control programs stored in a non-volatile storage element 608 (e.g., an EPROM). In ISP system 600, programming data received from the transceiver at access interface 601 are stored in random access memory (“RAM”) 607. RAM 607 and nonvolatile storage element 608 can share a common address space. Further, as shown in FIG. 6, ISP system 600 may contain multiple ISP controllers each assigned an address in the shared common address space. An address in ISP system 600 is decoded by a chip-select decoder 609 to provide a chip select control signal for selecting one of the ISP controllers. The programming data stored in RAM 607 can be provided to ISP controller 402 via data bus 603 under the control of microprocessor 605, which provides a control signal 610 (“read/write”) for latching the data into ISP controller 402. In this manner, the multiple ISP controllers in ISP system 600 can program a large number of ISP devices in parallel, without incurring large latencies due to the long daisy-chains of ISP devices. (Of course, the microprocessor-based ISP system taught by ISP system 600 can be adapted for use with any of access interfaces, whether implemented by wired or wireless data network interfaces.).
  • An example of a programming host system, such as any of [0031] programming host systems 101, 201 and 301, is shown in FIG. 7. FIG. 7 shows programming host system 700 as including host machines 701 and 702 coupled by a computer network 703. Computer network 703 can be a local area network, a dial-up network or a wide area network. For example, host machine 702 may be physically at the same geographical location as the ISP systems it programs, or host machine 701 can be a machine at a vendor site or a development site which provides updates of control and programming information to ISP devices on demand or periodically. Host machines 701 and 702 are each capable of supporting multiple remote ISP systems, such as any of remote ISP systems 103-105, 203-205 and 303-305.
  • As shown in FIG. 7, [0032] host machines 701 and 702 are similarly equipped. Thus, to simplify discussion, corresponding elements in host machines 701 and 702 are provided corresponding reference numerals, with a suffix “a” attached for elements in host machine 701 and a suffix “b” for corresponding elements in host machine 702. As seen in FIG. 7, host machine 701 includes a central processing unit (“CPU”) 705 a, which can be implemented by a workstation or a personal computer. CPU 705 a sends control and programming data to a remote ISP system via (a) wired modem 706 a, for such ISP system as ISP system 103 of FIG. 1, (b) wireless modem 707 a, for such ISP system as ISP system 203 of FIG. 2, and (c) transceiver 704 a, for such ISP system as ISP system 303. In FIG. 7, host system 701 can be controlled from terminal 709 a and stores control and programming data in ispSTREAM files in storage element 710. In FIG. 7, host machine 702 obtains ispSTREAM files over network 703 through a server running on host machine 701.
  • When receiving control and programming data, the operations of an ISP system under [0033] configuration 100 of FIG. 1 (e.g., any one of ISP systems 103, 104 and 105) are as follows:
  • 1.1 control and programming data arrive from [0034] host system 101 at the access interface over wired data network 102.
  • 1.2 A wired modem in the ISP system, e.g., [0035] wired telephone modem 401 in ISP system 400 of FIG. 4, provides the control and programming data serially to the RXD line of the ISP controller's 2-wire serial data port (e.g., serial port 804 in ISP controller 800 of FIG. 8).
  • 1.3 Status and response signals are received serially from the TXD line of the same serial data port to be transmitting by the wired telephone modem back to the host system as acknowledgment. [0036]
  • The operations of an ISP system using a wireless modem, e.g., any of [0037] ISP systems 203, 204 and 205, using a wireless modem such as wireless modem 501, are analogous to steps 1.1 to 1.4 above, except that such an ISP system would be implemented by, for example, ISP system 500 of FIG. 5, substituting the wired modem called for in these steps by a wireless modem.
  • The operations of an ISP system controlled by a microprocessor, e.g., [0038] ISP system 600 of FIG. 6, is slightly more complicated. The following steps illustrate an example of such an ISP system, in which control and programming data are transmitted over a radio channel:
  • 2.1 Control and programming data arrive at the access interface, e.g., received by [0039] transceiver 601 from the radio channel.
  • 2.2 While the control and programming data are received, the access interface provides the control and programming data as digital signals on a data bus (e.g., data bus [0040] 603) under the control of the microprocessor (e.g., microprocessor 605). The microprocessor, which executes a program stored in the non-volatile memory (e.g., EPROM 608), specifies an address on an address bus (e.g., address bus 604), so as to store the data on the data bus into memory (e.g., RAM 607). Step 2.2 is repeated until all control and programming data are stored into memory.
  • 2.3 The microprocessor then asserts a control signal to select an ISP controller (e.g., ISP controller [0041] 402) and begins to retrieve the control and programming data from memory onto the data bus.
  • 2.4 As each byte of data is provided on the data bus, the microprocessor asserts a write signal (e.g., read/write signal [0042] 610) to latch the data into the ISP controller.
  • 2.5 In response to the control and programming data received, the ISP controller activates the ISP signals (i.e., ispEN, SDI/TDI, SDO/TDO, SCLK/TCK, MODE/TMS) to program the ISP devices. [0043]
  • 2.6 When all control and programming data are provided to the selected ISP controller, status and response information are provided by the ISP controller on the data bus, under the microprocessor's control. [0044]
  • 2.7 The microprocessor directs the access interface to provide the status and response information to the host programming system by transmitting a message over the radio channel. [0045]
  • The operations of the ISP controller are as follows: [0046]
  • 3.1 The ISP controller waits in standby mode until arrival of control and programming data. [0047]
  • 3.2 Upon receiving the control and programming data, the ISP controller sets the ISP devices into programming mode by asserting the ispEN control signal. [0048]
  • 3.3 The ISP controller then reads an identification code (ID) from each ISP device in the daisy-chain. Each ID is clocked out of the SDO/TDO pin (i.e., terminal [0049] 410); during this time, the ISP controller provides a clock signal on the SCLK/TCK pin (i.e., terminal 407).
  • 3.4 The ISP controller compares the ID of each ISP device with the ID specified in the programming data, to ensure that the correct ISP device is programmed. [0050]
  • 3.5 The ISP controller then shifts the control and programming data serially into the target ISP device via the SDI/TDI pin (i.e., terminal [0051] 411).
  • 3.6 As the control and programming data are shifted serially into the ISP device, the control and programming data are echoed back to the ISP controller via the SDO/TDO pin. [0052]
  • 3.7 The ISP controller then calculates a checksum of the control and programming data echoed back from the ispLSI device. [0053]
  • 3.8 The calculated checksum from the previous step is compared with a corresponding checksum in the control and programming data received from the access interface. [0054]
  • 3.9 The ISP controller provides at either the serial output (i.e., 2-wire serial data port [0055] 403) or the parallel data bus 603, a code indicating whether the ISP device is correctly programmed.
  • The following is an exemplary sequence of events representative of the programming of an ISP device using the ISP signals: [0056]
  • 4.1 The ISP device is set to SHIFT state. [0057]
  • 4.2 An ERASE command is sent to the ispLSI device. [0058]
  • 4.3 The ISP device is set to EXECUTE state. [0059]
  • 4.4 The ISP signals are held steady for 200 milliseconds to erase any pattern from the ISP device. [0060]
  • 4.5 The ISP device is set to SHIFT state. [0061]
  • 4.6 An ADDRESS SHIFT command is sent to the ISP device. [0062]
  • 4.7 The ISP device is set to EXECUTE state. [0063]
  • 4.8 An address is sent to the ispLSI device. [0064]
  • 4.9 The ISP device is set to SHIFT state. [0065]
  • 4.10 A DATA SHIFT command is sent to ISP device. [0066]
  • 4.11 The ISP device is set to EXECUTE state. [0067]
  • 4.12 The programming data are then provided to the ISP device. [0068]
  • 4.13 The ISP device is set to SHIFT state. [0069]
  • 4.14 A PROGRAM command is sent to the ISP devices. [0070]
  • 4.15 The ISP device is set to EXECUTE state. [0071]
  • 4.16 The ISP signals are held steady for 40 milliseconds to program the new pattern into the ISP device. [0072]
  • 4.17 The ISP device is set to SHIFT state. [0073]
  • 4.18 A VERIFY command is sent to the ISP device. [0074]
  • 4.19 An ISP device is set to EXECUTE state. [0075]
  • 4.20 The ISP signals are held steady for 30 microseconds to verify the new pattern in the ISP device. [0076]
  • 4.21 The ISP device is set to the SHIFT state. [0077]
  • 4.22 A DATA SHIFT command is sent to the ISP device. [0078]
  • 4.23 The ISP device is set to the EXECUTE state. [0079]
  • 4.24 The programming data are shifted out, so that a checksum can be computed by the ISP controller to verify whether the ISP device is properly programmed. [0080]
  • The host programming system, e.g., [0081] host programming system 701, performs the following operations:
  • 5.1 The host programming system retrieves from storage an ispSTREAM file, e.g., from disk storage into the memory of a microcomputer or a workstation. [0082]
  • 5.2 The host programming system accesses the communication channel (e.g. [0083] wired data network 102, wireless data network 202, or radio channel 302) so as to reach the ISP systems.
  • 5.3 The central processing unit (e.g. CPU [0084] 705 a) of the host programming system activates the access interface (e.g. wired modem 706 a, wireless modem 707 a, or transceiver 704 a) to send to the remote ISP systems an identity code identifying the host programming system.
  • 5.4 If applicable, the host programming system can sign onto a second remote host programming system (e.g. host programming system [0085] 702) to allow further accesses to ISP systems.
  • 5.5 The CPU then scans a binary code answer-back (e.g. a 64-bit integer) from each of the ISP systems and compares the binary code received to the binary code of the host programming system. [0086]
  • 5.6 If the binary code received does not match the binary code of the host programming system, the CPU terminates the current access to the ISP systems. [0087]
  • 5.7 If the binary code received matches the binary code of the host programming system, the CPU then transmits over the access interface the control and programming data of the ispSTREAM file. [0088]
  • 5.8 The CPU then wait for a status response from each ISP systems. [0089]
  • 5.9 Upon receiving from an ISP system a status indicating successful programming, the CPU terminates the communication with that ISP system. [0090]
  • The detailed description above is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the invention are possible. The present invention is defined by the appended claims. [0091]

Claims (15)

We claim:
1. An in-system programmable (ISP) system, comprising:
an access interface for sending and receiving data over a communication link;
an ISP device receiving a programming clock signal, a data input signal and providing a data output signal;
an ISP controller, coupled to said access interface and said ISP device, said ISP controller (a) receiving from said access interface control and programming data from said access interface and (b) providing said control and programming data to program said ISP device.
2. An ISP system as in
claim 1
, wherein said communication link includes a portion of a wired data network.
3. An ISP system as in
claim 1
, wherein said communication link includes a portion of a wireless data network.
4. An ISP system as in
claim 1
, wherein said communication link includes a radio channel.
5. An ISP system as in
claim 1
, wherein said access interface provides data received over said communication link to said ISP controller simultaneously over a data bus.
6. An ISP system as in
claim 5
, further a central processing unit coupled to transmit and receive data on said data bus.
7. An ISP system as in
claim 6
, further comprising:
an address bus coupled to receive from said central processing unit a memory address;
a control terminal coupled to said central processing unit to receive a control signal; and
a random access memory coupled to said data bus and said address bus, said random access memory allowing data storage and retrieval in response to said memory address and said control signal specifying whether a read operation or a write operation is to be performed.
8. An ISP system as in
claim 7
further comprising a writable control store for said central processing unit provided in non-volatile memory.
9. An ISP system as in
claim 1
, wherein said ISP controller comprises a microprocessor.
10. An ISP system as in
claim 1
, further comprising a plurality of ISP controllers each controlling the programming of multiple ISP devices.
11. An ISP system as in
claim 1
, further comprising a host programming system coupled to said communication link.
12. An ISP system as in
claim 11
, wherein said host programming system comprises a central processing unit and an access interface receiving said control and programming data from said central processing unit for transmission over said communication link.
13. An ISP system as in
claim 12
, wherein said host programming system further comprises storage means from which said central processing unit retrieves said control and programming data.
14. An ISP system as in
claim 11
, wherein said further comprising a first central processing unit and a second central processing unit coupled by a computer network.
15. An ISP system as in
claim 14
, wherein said computer network includes a wide area network.
US08/964,421 1997-11-04 1997-11-04 Simultaneous wired and wireless remote in-system programming of multiple remote systems Expired - Fee Related US6389321B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US08/964,421 US6389321B2 (en) 1997-11-04 1997-11-04 Simultaneous wired and wireless remote in-system programming of multiple remote systems
GB0013382A GB2346997B (en) 1997-11-04 1998-11-03 Simultaneous wired and wireless remote in-system programming of multiple remote systems
AU13092/99A AU1309299A (en) 1997-11-04 1998-11-03 Simultaneous wired and wireless remote in-system programming of multiple remote systems
PCT/US1998/023562 WO1999023588A1 (en) 1997-11-04 1998-11-03 Simultaneous wired and wireless remote in-system programming of multiple remote systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/964,421 US6389321B2 (en) 1997-11-04 1997-11-04 Simultaneous wired and wireless remote in-system programming of multiple remote systems

Publications (2)

Publication Number Publication Date
US20010041943A1 true US20010041943A1 (en) 2001-11-15
US6389321B2 US6389321B2 (en) 2002-05-14

Family

ID=25508523

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/964,421 Expired - Fee Related US6389321B2 (en) 1997-11-04 1997-11-04 Simultaneous wired and wireless remote in-system programming of multiple remote systems

Country Status (4)

Country Link
US (1) US6389321B2 (en)
AU (1) AU1309299A (en)
GB (1) GB2346997B (en)
WO (1) WO1999023588A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2385438A (en) * 2002-02-19 2003-08-20 Mitel Knowledge Corp Remote programming of serialised semiconductor devices
US6633759B1 (en) * 1999-09-30 2003-10-14 Kabushiki Kaisha Toshiba Communication system, and mobile communication device, portable information processing device, and data communication method used in the system
US20040093109A1 (en) * 2001-01-25 2004-05-13 Dell Products L.P. Method and system for manufacturing and servicing a computing product with the assistance of a wireless communication subsystem attached to a peripheral port
US6954850B1 (en) * 2000-10-30 2005-10-11 Matsushita Electric Works, Ltd. Electronic device that uses a pager network for remote reprogramming of the device
EP2500829A3 (en) * 2005-09-15 2012-11-07 Microchip Technology Incorporated Programming a digital processor with a single connection

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6361944B1 (en) 1996-07-29 2002-03-26 Nanosphere, Inc. Nanoparticles having oligonucleotides attached thereto and uses therefor
US7155711B2 (en) * 1999-12-10 2006-12-26 Sedna Patent Services, Llc Method and apparatus providing remote reprogramming of programmable logic devices using embedded JTAG physical layer and protocol
US6326806B1 (en) 2000-03-29 2001-12-04 Xilinx, Inc. FPGA-based communications access point and system for reconfiguration
US6912601B1 (en) * 2000-06-28 2005-06-28 Cypress Semiconductor Corp. Method of programming PLDs using a wireless link
US7133822B1 (en) 2001-03-29 2006-11-07 Xilinx, Inc. Network based diagnostic system and method for programmable hardware
US6873842B2 (en) * 2001-03-30 2005-03-29 Xilinx, Inc. Wireless programmable logic devices
US7184466B1 (en) 2002-09-12 2007-02-27 Xilinx, Inc. Radio frequency data conveyance system including configurable integrated circuits
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7521960B2 (en) * 2003-07-31 2009-04-21 Actel Corporation Integrated circuit including programmable logic and external-device chip-enable override control
US7138824B1 (en) 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
US7418712B2 (en) * 2004-08-31 2008-08-26 Microsoft Corporation Method and system to support multiple-protocol processing within worker processes
US7099189B1 (en) 2004-10-05 2006-08-29 Actel Corporation SRAM cell controlled by non-volatile memory cell
US7116181B2 (en) * 2004-12-21 2006-10-03 Actel Corporation Voltage- and temperature-compensated RC oscillator circuit
US7119398B1 (en) 2004-12-22 2006-10-10 Actel Corporation Power-up and power-down circuit for system-on-a-chip integrated circuit
US7446378B2 (en) * 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
KR101261022B1 (en) * 2006-01-19 2013-05-06 삼성전자주식회사 Apparatus of data processing and method of setting program data thereof
US10657168B2 (en) 2006-10-24 2020-05-19 Slacker, Inc. Methods and systems for personalized rendering of digital media content
US20100106852A1 (en) * 2007-10-24 2010-04-29 Kindig Bradley D Systems and methods for providing user personalized media content on a portable device
US7884672B1 (en) 2006-11-01 2011-02-08 Cypress Semiconductor Corporation Operational amplifier and method for amplifying a signal with shared compensation components
US8452553B2 (en) * 2006-11-30 2013-05-28 Freescale Semiconductor, Inc. Device and method for testing a circuit
EP2135182A1 (en) 2007-03-08 2009-12-23 Slacker, INC. System and method for personalizing playback content through interaction with a playback device
US9280516B2 (en) 2011-04-07 2016-03-08 The University Of Western Ontario Method and system to validate wired sensors
US10275463B2 (en) 2013-03-15 2019-04-30 Slacker, Inc. System and method for scoring and ranking digital content based on activity of network users

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672529A (en) * 1984-10-26 1987-06-09 Autech Partners Ltd. Self contained data acquisition apparatus and system
US4849928A (en) 1987-01-28 1989-07-18 Hauck Lane T Logic array programmer
US5309351A (en) * 1988-10-27 1994-05-03 Texas Instruments Incorporated Communications, information, maintenance diagnostic and training system
US5237218A (en) * 1991-05-03 1993-08-17 Lattice Semiconductor Corporation Structure and method for multiplexing pins for in-system programming
US5329179A (en) 1992-10-05 1994-07-12 Lattice Semiconductor Corporation Arrangement for parallel programming of in-system programmable IC logical devices
US5457408A (en) 1994-11-23 1995-10-10 At&T Corp. Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA
US5606710A (en) 1994-12-20 1997-02-25 National Semiconductor Corporation Multiple chip package processor having feed through paths on one die
JP2861855B2 (en) * 1995-03-28 1999-02-24 ヤマハ株式会社 Communication karaoke system
US5543730A (en) 1995-05-17 1996-08-06 Altera Corporation Techniques for programming programmable logic array devices
US5635855A (en) 1995-07-21 1997-06-03 Lattice Semiconductor Corporation Method for simultaneous programming of in-system programmable integrated circuits
US5734868A (en) 1995-08-09 1998-03-31 Curd; Derek R. Efficient in-system programming structure and method for non-volatile programmable logic devices
US5751163A (en) 1996-04-16 1998-05-12 Lattice Semiconductor Corporation Parallel programming of in-system (ISP) programmable devices using an automatic tester
US5864486A (en) 1996-05-08 1999-01-26 Lattice Semiconductor Corporation Method and apparatus for in-system programming of a programmable logic device using a two-wire interface
US6134707A (en) * 1996-11-14 2000-10-17 Altera Corporation Apparatus and method for in-system programming of integrated circuits containing programmable elements
US5984498A (en) * 1996-11-21 1999-11-16 Quantum Conveyor Systems, Inc. Device controller with intracontroller communication capability, conveying system using such controllers for controlling conveying sections and methods related thereto

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633759B1 (en) * 1999-09-30 2003-10-14 Kabushiki Kaisha Toshiba Communication system, and mobile communication device, portable information processing device, and data communication method used in the system
US6954850B1 (en) * 2000-10-30 2005-10-11 Matsushita Electric Works, Ltd. Electronic device that uses a pager network for remote reprogramming of the device
US20050272404A1 (en) * 2000-10-30 2005-12-08 Howard Michael L Electronic device that uses a communications network for remote reprogramming of the device
US7181606B2 (en) 2000-10-30 2007-02-20 Matsushita Electric Works, Ltd. Electronic device that uses a communications network for remote reprogramming of the device
US20040093109A1 (en) * 2001-01-25 2004-05-13 Dell Products L.P. Method and system for manufacturing and servicing a computing product with the assistance of a wireless communication subsystem attached to a peripheral port
US6865436B2 (en) * 2001-01-25 2005-03-08 Dell Products L.P. Method and system for manufacturing and servicing a computing product with the assistance of a wireless communication subsystem attached to a peripheral port
GB2385438A (en) * 2002-02-19 2003-08-20 Mitel Knowledge Corp Remote programming of serialised semiconductor devices
US6941178B2 (en) 2002-02-19 2005-09-06 Mitel Knowledge Corporation Remote programming of serialized semiconductor devices using web or internet protocols
EP2500829A3 (en) * 2005-09-15 2012-11-07 Microchip Technology Incorporated Programming a digital processor with a single connection

Also Published As

Publication number Publication date
US6389321B2 (en) 2002-05-14
GB2346997B (en) 2002-12-04
WO1999023588A1 (en) 1999-05-14
AU1309299A (en) 1999-05-24
GB0013382D0 (en) 2000-07-26
GB2346997A (en) 2000-08-23

Similar Documents

Publication Publication Date Title
US6389321B2 (en) Simultaneous wired and wireless remote in-system programming of multiple remote systems
US6023570A (en) Sequential and simultaneous manufacturing programming of multiple in-system programmable systems through a data network
KR950002709B1 (en) Information transfer method and arragnement
US4525865A (en) Programmable radio
US5495593A (en) Microcontroller device having remotely programmable EPROM and method for programming
KR100395706B1 (en) Communication operation system and method
US5901330A (en) In-circuit programming architecture with ROM and flash memory
EP0253530B1 (en) Dynamically reconfigurable array logic
US6684324B2 (en) Method for installing two or more operating systems/user interfaces into an electronic device and an electronic device
EP0806737A2 (en) In-system programming with two wire interface
EP0964338B1 (en) Method and apparatus for operating on a memory unit via a JTAG port
US20050101309A1 (en) Method and apparatus for selective configuration based upon expansion card presence
US6009500A (en) Replacement of erroneous firmware in a redundant non-volatile memory system
JP2001510315A (en) System and method for updating memory in an electronic device by wireless data transfer
US6351638B1 (en) Method and apparatus for accessing a plurality of communication networks
CA2236569A1 (en) Method for installing a wireless network
US20010013540A1 (en) An ic card reading/writing apparatus and an ic card system
US5274765A (en) Multifunctional coupler for connecting a central processing unit of a computer to one or more peripheral devices
CN101091158A (en) Use loader for signaling the system software update service
CN107704285A (en) Field programmable gate array multi version configuration chip, system and method
US7245904B2 (en) Reconfiguration of programmable components in an electronic apparatus
CN110941444A (en) Upgrade configuration logic circuit, method and system and programmable logic device
US6414871B1 (en) Systems and methods for programming programmable devices
US7602729B2 (en) Slow-fast programming of distributed base stations in a wireless network
US6493788B1 (en) Processor with embedded in-circuit programming structures

Legal Events

Date Code Title Description
AS Assignment

Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TANG, HOWARD Y.M.;CHAN, ALBERT;TSUI, CYRUS Y.;REEL/FRAME:008808/0398

Effective date: 19971103

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20100514

AS Assignment

Owner name: JEFFERIES FINANCE LLC, NEW YORK

Free format text: SECURITY INTEREST;ASSIGNORS:LATTICE SEMICONDUCTOR CORPORATION;SIBEAM, INC.;SILICON IMAGE, INC.;AND OTHERS;REEL/FRAME:035225/0352

Effective date: 20150310

AS Assignment

Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326

Effective date: 20190517

Owner name: DVDO, INC., OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326

Effective date: 20190517

Owner name: SILICON IMAGE, INC., OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326

Effective date: 20190517

Owner name: SIBEAM, INC., OREGON

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC;REEL/FRAME:049827/0326

Effective date: 20190517