US20010035572A1 - Stackable flex circuit chip package and method of making same - Google Patents
Stackable flex circuit chip package and method of making same Download PDFInfo
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- US20010035572A1 US20010035572A1 US09/888,785 US88878501A US2001035572A1 US 20010035572 A1 US20010035572 A1 US 20010035572A1 US 88878501 A US88878501 A US 88878501A US 2001035572 A1 US2001035572 A1 US 2001035572A1
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2225/1094—Thermal management, e.g. cooling
Abstract
Description
- The present application is a continuation-in-part of U.S. application Ser. No. 09/305,584 entitled STACKABLE FLEX CIRCUIT IC PACKAGE AND METHOD OF MAKING SAME filed May 5, 1999, the disclosure of which is incorporated herein by reference.
- The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package including a flex circuit which allows multiple chip packages to be quickly, easily and inexpensively assembled into a chip stack having a minimal profile.
- Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
- Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
- In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. Nos. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
- The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages including flex circuits. The inclusion of the flex circuits in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significant increases in the production rate and resultant reductions in cost attributable to the reduced complexity of the assembly process.
- In accordance with a first embodiment of the present invention, there is provided a stackable integrated circuit chip package which comprises a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the flex circuit is a conductive pattern. In addition to the flex circuit, the chip package comprises a frame which is attached to the substrate of the flex circuit. Also included in the chip package is an integrated circuit chip which is at least partially circumvented by the frame and electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit ship package.
- In the first embodiment, the frame preferably has a generally rectangular configuration defining opposed pairs of longitudinal and lateral sides. The frame also defines a central opening for receiving the integrated circuit chip, with the top and bottom surfaces of the frame being attached to the top surface of the substrate. The substrate is preferably wrapped about the frame such that the first portion of the conductive pattern extends over a portion of the bottom surface of the frame, with the second portion of the conductive pattern extending over a portion of the top surface of the frame. More particularly, the substrate is wrapped about the longitudinal sides of the frame such that the first and second portions of the conductive pattern extend in spaced, generally parallel relation to each other over respective portions of the bottom and top surfaces of the frame.
- The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof, with the substrate preferably being wrapped about the longitudinal sides of the frame such that the longitudinal peripheral edge segments of the substrate extend along respective ones of the longitudinal sides of the frame. The substrate is also sized relative to the frame such that the lateral sides of the frame protrude from respective ones of the lateral peripheral edge segments of the substrate, with the longitudinal peripheral edge segments of the substrate also extending to the central opening of the frame. In the chip package of the first embodiment, a pair of heat sinks may be attached to one or both of the lateral sides of the frame which extend beyond the lateral peripheral edge segments of the substrate.
- The conductive pattern of the chip package of the first embodiment preferably comprises a first set of pads which are disposed on the bottom surface of the substrate, and a second set of pads which are disposed on the top surface of the substrate and electrically connected to respective ones of the pads of the first set. The integrated circuit chip is itself electrically connected to the pads of the second set. A plurality of copper bumps or solder bumps may be formed on respective ones of the pads of the first set for facilitating the electrical connection of the chip package to a mother board. The pads of the second set are preferably arranged in an identical pattern to those of the first set such that the pads of the second set are aligned with and electrically connected to respective ones of the pads of the first set. The electrical connection of the pads of the first and second sets to each other is preferably accomplished through the use of vias which are formed in the substrate and extend between respective aligned pairs of the pads of the first and second sets.
- The integrated circuit chip of the chip package of the first embodiment preferably comprises a body having opposed, generally planar top and bottom surfaces. In addition to the body, the integrated circuit chip includes a plurality of conductive contacts which are disposed on the bottom surface of the body. The conductive contacts of the integrated circuit chip are electrically connected to respective ones of the pads of the second set. The conductive contacts are preferably arranged on the bottom surface of the body in an identical pattern to the pads of the second set, and are preferably electrically connected to respective ones of the pads of the second set via solder. The integrated circuit chip is preferably selected from the group consisting of a flip chip device and a fine pitch BGA device.
- In the chip package of the first embodiment, a layer of epoxy is preferably disposed between the bottom surface of the body and the top surface of the substrate. Additionally, the substrate is preferably attached to the frame through the use of an acrylic film adhesive. The substrate is preferably fabricated from a polyamide having a thickness in the range of from about 1 mil to about 8 mils, with the frame preferably being fabricated from either a plastic material filled with a thermal enhancing material or a metal material. The chip package may be combined with a second chip package stacked upon the chip package, with the first portion of the conductive pattern of the second chip package being electrically connected to the second portion of the conductive pattern of the chip package. The electrical connection of the chip packages to each other is preferably accomplished through the use of a Z-axis film material or adhesive.
- In accordance with a second embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising a flex circuit. In the second embodiment, the flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern which is disposed on the flex circuit. The chip package of the second embodiment also includes an integrated circuit chip which is electrically connected to the conductive pattern. The substrate of the chip package of the second embodiment is wrapped about and attached to at least a portion of the integrated circuit chip such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package. In the chip package of the second embodiment, the conductive pattern comprises the first and second sets of pads as described in relation to the chip package of the first embodiment. The electrical connection of the integrated circuit chip to the conductive pattern is accomplished in the chip package of the second embodiment in the same manner previously described in relation to the chip package of the first embodiment.
- In the chip package of the second embodiment, the body of the integrated circuit chip preferably has a generally rectangular configuration defining a pair of longitudinal sides and a pair of lateral sides. The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof. The substrate is wrapped about the longitudinal sides of the body, such that the longitudinal peripheral edge segments of the substrate extend along the top surface of the body in spaced, generally parallel relation to each other. The first and second portions of the conductive pattern also extend in spaced, generally parallel relation to each other over respective portions of the bottom and top surfaces of the body of the integrated circuit chip. The substrate is preferably attached to the integrated circuit chip through the use of an acrylic film adhesive. Additionally, a layer of epoxy is preferably disposed between the bottom surface of the body and top surface of the substrate. The substrate of the chip package of the second embodiment is preferably fabricated from the same material having the same thickness range as previously described in relation to the chip package of the first embodiment.
- In accordance with a third embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern which is disposed thereon. The chip package of the third embodiment further comprises an integrated circuit chip which is electrically connected to the conductive pattern. The substrate is folded and attached to itself such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package. In the chip package of the third embodiment, the conductive pattern comprises the first and second sets of pads as described in relation to the chip package of the first embodiment. Additionally, the electrical connection of the integrated circuit chip to the conductive pattern is preferably accomplished in the same manner as previously described in relation to the chip package of the first embodiment.
- In the chip package of the third embodiment, the body of the integrated circuit chip preferably has a generally rectangular configuration defining a pair of longitudinal sides and a pair of lateral sides. The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof. The substrate is folded such that the longitudinal peripheral edge segments thereof extend along and in substantially parallel relation to respective ones of the longitudinal sides of the body, with the first and second portions of the conductive pattern extending in generally parallel relation to each other. As will be recognized, the total thickness of the substrate at those regions whereat it is folded over itself is preferably such that the second portion of the conductive pattern is substantially flush with or extends along a plane disposed above the top surface of the body of the integrated circuit chip, thus allowing for the electrical connection of the second portion of the conductive pattern of the chip package to another stackable integrated circuit chip package. In the chip package of the third embodiment, the substrate is preferably attached to itself through the use of an acrylic film adhesive, with the chip package further preferably comprising a layer of epoxy disposed between the bottom surface of the body and the top surface of the substrate. The substrate in the chip package of the third embodiment is also preferably fabricated from the same material in the same thickness range as previously described in relation to the chip package of the first embodiment.
- Further in accordance with the present invention, there is provided a method of assembling a stackable integrated circuit chip package constructed in accordance with the first embodiment of the present invention. The method comprises the initial step of electrically connecting an integrated circuit chip to a conductive pattern on a flexible substrate of a flex circuit. This particular step is itself preferably accomplished by first applying a layer of flux to the conductive contacts of the integrated circuit chip, and thereafter positioning the integrated circuit chip upon the substrate such that at least some of conductive contacts abut the conductive pattern. Thereafter, heat is applied to the integrated circuit chip and the substrate to facilitate the reflow of the solder disposed on the conductive contacts and electrical connection thereof to the conductive pattern.
- In the preferred method, the above described initial heat application step is followed by the dispensation of a quantity of an epoxy onto the substrate along a side of the integrated circuit chip to facilitate the wicking of the epoxy between the integrated circuit chip and the substrate. At this time, the substrate preferably resides on a heated stage at a temperature of about 90 degrees Celsius. After the epoxy has been applied to the substrate, the heat applied to the integrated circuit chip and the substrate by the heated stage is then increased to a temperature of about 160 degrees Celsius for a time period of about 5 minutes to facilitate the hardening of the epoxy. The epoxy dispensation and subsequent heating step are preferably completed while a vacuum is being applied to the substrate to maintain the substrate in a generally flat orientation. Thereafter, the integrity of electrical connection of the conductive contacts of the integrated circuit chip to the conductive pattern is tested.
- Upon the completion of the electrical connection of the integrated circuit chip to the conductive pattern, a frame is attached to the flex circuit such that the frame at least partially circumvents the integrated circuit chip. The attachment of the frame to the flex circuit is preferably accomplished by initially bonding two strips of an adhesive to the substrate along opposite sides of the integrated circuit chip. Thereafter, a pair of flex windows are punched through the substrate and respective ones of the adhesive strips, with the frame thereafter being attached to the adhesive strips. The bonding of the adhesive strips to the substrate is preferably completed by heating the adhesive strips and the substrate to a temperature of about 140 degrees Celsius and applying pressure to the adhesive strips for a time period of from about 5 seconds to about 10 seconds. To facilitate the attachment of the frame to the adhesive strips, the frame, adhesive strips, and substrate are preferably heated to a temperature of about 130 degrees Celsius, with pressure of about 20 psi being applied to the frame for a time period of about 5 seconds.
- Following the attachment of the frame to the flex circuit, the flex circuit is wrapped about and secured to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to at least one other stackable integrated circuit chip package. To facilitate such wrapping, the substrate is preferably positioned upon a spaced pair of reciprocally movable wrapping fingers, with pressure then being applied to one side of the frame of the integrated circuit chip to force the frame and the integrated circuit chip between the wrapping fingers and facilitate the folding of the substrate upwardly along each of the opposed sides of the frame. The wrapping fingers are then moved toward each other to facilitate the wrapping of the substrate about the opposed sides of the frame. Heat is applied to the chip package at a temperature about 180 degrees Celsius for a time period of about 5 minutes after the movement of the wrapping fingers toward each other. This 5 minute time period is used to facilitate the curing of the adhesive, with the wrapping fingers being moved away from each other upon the elapse thereof to allow for the removal of the chip package from therebetween.
- The present method may further comprise the additional step of electrically connecting the second portion of the conductive pattern of the chip package to the first portion of the conductive pattern of another stackable integrated circuit chip package to form a chip stack. Such electrical connection between the chip packages is preferably accomplished by first placing a Z-axis film between the first and second portions of the conductive patterns of the chip packages, and thereafter applying heat and pressure to the chip packages for a time period of about 1 minute to cure the Z-axis film. A plurality of copper bumps or solder bumps may then be formed on the first portion of the conductive pattern of the lowermost chip package of the chip stack, with the integrity of the electrical connection of the chip packages to each other than being tested.
- Further in accordance with the present invention, there is provided methods for assembling chip packages constructed in accordance with the second and third embodiments as described above. These assembly methods are substantially similar to assembly method previously described in relation to the chip package of the first embodiment. More particularly, the assembly method related to the chip package of the second embodiment differs only in that the substrate is wrapped about opposed sides of the integrated circuit chip and adhered directly thereto due to the absence of the frame in the chip package of the second embodiment. In the assembly method related to the third embodiment, the substrate is folded over and adhered to itself.
- FIG. 1 is a top perspective view of a four-sided flex circuit chip package constructed in accordance with the teachings of parent application Ser. No. 09/305,584;
- FIG. 2 is a bottom perspective view of the four-sided flex circuit chip package shown in FIG. 1;
- FIG. 3 is a top perspective view of a two-sided flex circuit chip package constructed in accordance with a first embodiment of the present invention;
- FIG. 4 is a bottom perspective view of the chip package shown in FIG. 3;
- FIG. 5 is a bottom plan view of the flex circuit of the chip package of the first embodiment shown in FIGS. 3 and 4;
- FIG. 6 is a partial cross-sectional view of the chip package of the first embodiment shown in FIG. 3;
- FIG. 7 is an exploded, partial cross-sectional view of a chip stack comprising chip packages constructed in accordance with the first embodiment, further illustrating a copper bump formed on the conductive pattern of the flex circuit of the lowermost chip package;
- FIG. 8 is a top perspective view of a chip stack assembled using chip packages constructed in accordance with the first embodiment, further illustrating a pair of heat sinks attached to respective ones of the lateral ends of the frames of the chip packages within the chip stack;
- FIG. 9 is a top perspective view of a chip stack wherein the chip packages thereof include alternatively configured, extended frames;
- FIGS.10-15 illustrate the sequence of steps implemented to facilitate the assembly of the chip package of the first embodiment of the present invention;
- FIG. 16a-16 e illustrate the step-by-step sequence included in the assembly step shown in FIG. 13;
- FIG. 17 is a top perspective view of a two-sided flex circuit chip package constructed in accordance with a second embodiment of the present invention;
- FIG. 18 is a bottom perspective view of the chip package of the second embodiment shown in FIG. 17;
- FIG. 19 is a partial cross-sectional view of the chip package of the second embodiment shown in FIG. 17; and
- FIG. 20 is a partial cross-sectional view of a two-sided flex circuit chip package constructed in accordance with a third embodiment of the present invention.
- Referring now to the drawings wherein the showings are for purposes of illustrating preferred embodiments of the present invention only, and not for purposes of limiting the same, FIGS. 1 and 2 perspectively illustrate a four-sided flex
circuit chip package 10 constructed in accordance with the teachings of parent application Ser. No. 09/305,584 entitled STACKABLE FLEX CIRCUIT IC PACKAGE AND METHOD OF MAKING SAME filed May 5, 1999 of which the present application is a continuation-in-part. In thechip package 10, all four sides of theframe 12 thereof are wrapped by respective portions of theflex circuit 14 of thechip package 10. The need to wrap all four sides of theframe 12 with theflex circuit 14 requires a relatively high level of handling, thus increasing production time and hence cost. In thechip package 10, theconductive pattern 16 of theflex circuit 14 comprises a plurality ofconductive traces 18 which each extend to a respectiveconductive pad 20 on the bottom surface of theflex circuit 14. These conductive traces 20 are segregated into four different sets, with the conductive traces 20 of each set typically being of a 10-20 mil pitch. - Referring now to FIGS. 3 and 4, there is perspectively illustrated a two-sided flex
circuit chip package 22 constructed in accordance with a first embodiment of the present invention. As seen in FIGS. 3-5, thechip package 22 comprises aflex circuit 24 which itself comprises aflexible substrate 26 having a generally planar top surface 28 (shown in FIGS. 6 and 7) and a generally planarbottom surface 30. Thesubstrate 26 preferably has a generally rectangular configuration defining a pair of longitudinalperipheral edge segments 32 and a pair of lateralperipheral edge segments 34. Thesubstrate 26 is preferably fabricated from a polyamide which has a thickness of several mils or less, and may have a thickness down to about 1 mil. - Disposed on the
substrate 26 is aconductive pattern 36 of theflex circuit 24. Theconductive pattern 36 comprises a first set ofconductive pads 38 which are disposed on thebottom surface 30 of thesubstrate 26. In addition to thepads 38 of the first set, theconductive pattern 36 comprises a plurality ofconductive traces 40 which extend along thebottom surface 30 of thesubstrate 26 from respective ones of thepads 38 of the first set to respective ones of the longitudinalperipheral edge segments 32 of thesubstrate 26. As best seen in FIG. 5, thetraces 40 are segregated into two sets, with thetraces 40 of each set preferably being separated by a pitch of 10 to 15 mils. Importantly, the pitch between theconductive traces 40 of each set is such that thetraces 40 may be extended to only the longitudinalperipheral edge segments 32 of thesubstrate 26, and not to the lateralperipheral edge segments 34 thereof. Thus, in thechip package 22, only two sets oftraces 40 are included, as opposed to the four sets oftraces 18 included in theconductive pattern 16 of theflex circuit 14 of thechip package 10 shown in FIGS. 1 and 2. As will be discussed in more detail below, the extension of thetraces 40 to only the longitudinalperipheral edge segments 32 of thesubstrate 26 substantially reduces the complexity, and hence the cost of the assembly method related to thechip package 22, as well as chip stacks including multiple chip packages 22. As will also be discussed below, this “two-sided” approach for thechip package 22 allows for various cooling options which are not practical for a “four-sided” approach. - In addition to the
pads 38 of the first set and thetraces 40, theconductive pattern 36 of theflex circuit 24 comprises a second set ofconductive pads 42 which are disposed on thetop surface 28 of thesubstrate 26 and electrically connected to respective ones of thepads 38 of the first set. In thechip package 22, thepads 42 of the second set are arranged in an identical pattern to thepads 38 of the first set such that thepads 42 of the second set are aligned with and electrically connected to respective ones of thepads 38 of the first set. As best seen in FIGS. 6 and 7, the electrical connection of thepads vias 44 which are formed in thesubstrate 26 and extend between respective aligned pairs of thepads - The
pads pads flex circuit 24 and, as indicated above, allows for the two-sided approach. As also indicated above, thepads conductive pattern 36 of theflex circuit 24. - Referring now to FIGS. 3, 4,6 and 7, the
chip package 22 constructed in accordance with the first embodiment of the present invention further comprises aframe 46 which is attached to thesubstrate 26 of theflex circuit 24 through the use of twostrips 48 of an adhesive in a manner which will be described in more detail below. In thechip package 22, theframe 46 preferably has a generally rectangular configuration defining an opposed pair oflongitudinal sides 50 and an opposed pair of lateral sides 52. The longitudinal andlateral sides frame 46 collectively define a rectangularly configuredcentral opening 54 thereof. As will also be discussed in more detail below, theframe 46 defines top and bottom surfaces, portions of which are attached to thetop surface 28 of thesubstrate 26 via theadhesive strips 48 when thechip package 22 is properly assembled. - A preferred adhesive for the
adhesive strips 48 is an acrylic film adhesive sold by DuPont and available as Pyralux LF which is a non-tacky film at room temperature and becomes tacky at 140 degrees Celsius. This particular acrylic film adhesive punches well, bonds well, withstands solder reflow temperatures, and is commonly used for circuit board lamination. In the first embodiment, theframe 46 is preferably fabricated from either a plastic material filled with a thermal enhancing material, or a metal material made using powder metallurgy. The use of these particular materials provides theframe 46 with thermally conductive properties which are useful for heat dissipation, and thus are preferred to address thermal issues where heat must be removed from the chip stack assembled using the chip packages 22. - The
chip package 22 of the first embodiment further comprises anintegrated circuit chip 56 which is preferably a fine pitch BGA (ball grid array) device, but may alternatively comprise a flip chip device. In thechip package 22, theintegrated circuit chip 56 is electrically connected to thepads 42 of the second set, and hence to thepads 38 of the first set by virtue of their electrical connection to thepads 42 of the second set. Theintegrated circuit chip 56 includes a rectangularly configuredbody 58 defining a generally planartop surface 60, a generally planarbottom surface 62, a pair oflongitudinal sides 64 and a pair of lateral sides 66. Protruding from thebottom surface 62 of thebody 58 are a plurality of generally semi-spherically shapedconductive contacts 68 which normally have a quantity of solder pre-applied thereto. Theconductive contacts 68 are preferably arranged in an identical pattern to each of the first and second sets ofconductive pads conductive contacts 68 being electrically connected to respective ones of thepads 42 of the second set. - In the
chip package 22, the electrical connection of theconductive contacts 68 to respective ones of thepads 42 of the second set is preferably accomplished through the use of solder. More particularly, as will be discussed in more detail below, the solder pre-applied to theconductive contacts 68 is heated to a temperature which facilitates its reflow, thus facilitating the electrical connection of theconductive contacts 68 andpads 42 of the second set to each other. As is also seen in FIGS. 6 and 7, thechip package 22 further comprises alayer 70 of underfill epoxy which is disposed between thebottom surface 62 of thebody 58 of theintegrated circuit chip 56 and thetop surface 28 of thesubstrate 26. A preferred epoxy is available from Dexter Hysol as No. FP4527. This particular epoxy material has been found to dispense and flow very well, and can be cured in stages. - In the
chip package 22 of the first embodiment, thesubstrate 26 is wrapped about and attached to theframe 46 such that theconductive pattern 36 defines a lower,first portion 72 and an upper,second portion 74 which are each electrically connectable to another stackable integrated circuit chip package. More particularly, thesubstrate 26 is wrapped about thelongitudinal sides 50 of theframe 46 such that the first andsecond portions conductive pattern 36 extend in spaced, generally parallel relation to each other, with thefirst portion 72 extending over portions of the bottom surface of theframe 46 and thesecond portion 74 extending over portions of the top surface of theframe 46. Thesubstrate 26 is preferably sized relative to theframe 46 such that the longitudinalperipheral edge segments 32, which extend along respective ones of thelongitudinal sides 50 of the frame, extend to or terminate at approximately thecentral opening 54, with the lateral sides 52 of theframe 46 extending or protruding from respective ones of the lateralperipheral edge segments 34 of thesubstrate 26. - As will be explained in more detail below, each of the
adhesive strips 48 which is attached to thetop surface 28 of thesubstrate 26 has a length substantially equal to the length of eachlongitudinal side 50 of theframe 46, and a width which is about three times the width of eachlongitudinal side 50 of theframe 46. Thus, when the bottom surfaces of thelongitudinal sides 50 of theframe 46 are attached to respective ones of theadhesive strips 48, the inner longitudinal edges of suchadhesive strips 48 preferably terminate at thecentral opening 54, with the outer longitudinal edges of theadhesive strips 48 extending outwardly beyond respective ones of thelongitudinal sides 50 of theframe 46. Thus, as is seen in FIGS. 6 and 7, when thesubstrate 26 is wrapped about thelongitudinal sides 50 of theframe 46, the preferred sizing of theadhesive strips 48 causes the outer edges thereof to also terminate at approximately thecentral opening 54, with each of theadhesive strips 48 extending between thesubstrate 26 and the top and bottom surfaces of a respectivelongitudinal side 50 of theframe 46. - As is further seen in FIG. 6, a
solder mask 76 may be applied to each of thepads 38 of the first set prior to the electrical connection of theconductive contacts 68 to respective ones of thepads 42 of the second set. In this respect, when theintegrated circuit chip 56 is heated to facilitate the reflow of the solder pre-applied to theconductive contacts 68, such solder sometimes has a tendency to wick through thevias 44, thus resulting in an insufficient soldered interconnection between theconductive contacts 68 and thepads 42 of the second set. As will be recognized, the inclusion of thesolder mask 76 on each of thepads 38 of the first set substantially blocks or caps the open bottom end of each of thevias 44, thus preventing such wicking from occurring. Additionally, as seen in FIG. 7, in thechip package 22, acopper bump 78 may be formed on each of thepads 38 of the first set. As will be discussed below, the copper or solder bumps 78 will typically be included on thelowermost chip package 22 of a chip stack to facilitate the electrical connection of suchlowermost chip package 22 to another electrical component such as, for example, a mother board. - FIG. 7 is an exploded view of a
chip stack 80 including twochip stacks 22 of the first embodiment of the present invention. FIG. 8 depicts achip stack 82 including fourchip packages 22 of the first embodiment. It will be recognized that a chip stack may also be constructed to include three or more than four chip packages 22. As indicated above, thelowermost chip package 22 in thechip stack pads 38 of the first set thereof. In thestack first portion 72 of theconductive pattern 36 of anychip package 22 in the stack will be electrically connected to thesecond portion 74 of theconductive pattern 36 of thechip package 22 immediately therebelow. It will be recognized that thefirst portion 72 of theconductive pattern 36 of thelowermost chip package 22 will not be electrically connected to thesecond portion 74 of theconductive pattern 36 of anotherchip package 22, but rather will be electrically connected to a component such as a mother board through the use of the copper or solder bumps 78. - As is seen in FIG. 7, the attachment of any two
chip packages 22 in thechip stack film 84 which will normally be applied to thesecond portion 74 of theconductive pattern 36. Since thesecond portion 74 of eachconductive pattern 36 is segregated into two sections which extend along portions of the top surface of theframe 46 over respective ones of thelongitudinal sides 50 thereof, the Z-axis film 84 is applied to thesecond portion 74 in two strips or sheets. A preferred Z-axis film material is available from the 3M Company as No. 5460. This particular film material contains gold-plated nickel particles of about 7 microns in size, with heat and pressure causing metal contact between thesecond portion 74 of theconductive pattern 36 of onechip package 22 to thefirst portion 72 of theconductive pattern 36 of anotherchip package 22 in thechip stack second portions axis film 84. - Referring again to FIG. 8, once the
chip stack 82 has been assembled, a pair ofheat sinks 86 may be attached to respective ones of thelateral sides 52 of each of theframes 46 of the chip packages 22 within thechip stack 82. As will be recognized, the heat sinks 82 assist in dissipating heat generated by theintegrated circuit chips 56 within thechip stack 82. Though not shown, it will be recognized that one or both of thelateral sides 52 of eachframe 46 may include a separate heat sink attached thereto. - As an alternative to the heat sinks86, FIG. 9 illustrates a
chip stack 88 similar to thechip stack 82 but wherein the frames 46(a) of the chip packages 22 are slightly modified from theframes 46 such that the lateral sides 52(a) thereof protrude outwardly from the lateralperipheral edge segments 34 of thesubstrate 26 further than do the lateral sides 52 of theframe 46. These extended width lateral sides 52(a) of the frame 46(a) serve as heat sinks. The ability of the lateral sides 52(a) to serve as heat sink is, in part, facilitated by the preferred fabrication of the frame 46(a) from either a plastic material filled with a thermal enhancing material or a metal material as discussed above. - Having thus described the preferred configuration of the
chip package 22 of the first embodiment and thechip stack 80, a preferred method of assembling eachchip package 22 and a chip stack including two or more chip packages 22 will now be described with particular reference to FIGS. 10-16. - The preferred assembly method related to the
chip package 22 preferably occurs in a continuous tape format, thus substantially increasing production flow. The assembly method or process as described below is capable of being set-up with universal tooling that can be adjusted for different dimensions without making new tooling. The assembly process is initiated with a continuous tape orstrip 88 which, when punched and cut in the manner described below, will form theflex circuit 24 of each completedchip package 22. Thus, thestrip 88 is preferably fabricated from the polyamide material in the aforementioned thickness range, with second sets of theconductive pads 42 being disposed on the top surface thereof in aligned, spaced relation to each other. Though not shown in FIG. 10, first sets ofconductive pads 38 andconductive traces 40 corresponding to each second set ofpads 42 are disposed on the bottom surface of thestrip 88, thus facilitating the formation of equidistantly spacedconductive patterns 36 on thestrip 88. - In the preferred assembly method, an
integrated circuit chip 56 is picked and placed upon respective ones of the second sets ofconductive pads 42 such that each of theconductive contacts 68 of a particularintegrated circuit chip 56 abut respective ones of thepads 42 of the corresponding second set. Prior to such placement, theconductive contacts 68 of eachintegrated circuit chip 56 preferably have a layer of tacky flux applied thereto, with such application preferably being accomplished by dipping theconductive contacts 68 into a thin layer of flux doctor bladed over a flat surface. It will be recognized that many pick and place machines are capable of completing such dipping operation. As indicated above, theconductive contacts 68 of eachintegrated circuit chip 56 already have solder applied thereto. As also indicated above, subsequent to the flux application, eachintegrated circuit chip 56 is placed or positioned upon thestrip 88 in the above-described manner. - The
strip 88 having the integratedcircuit chip 56 positioned thereon continues through a heated zone which provides the proper atmosphere and a profile suitable for the flux applied to theconductive contacts 68. In this heated zone, a peak temperature of about 220 degrees Celsius is used to reflow the solder disposed upon theconductive contacts 68, thus facilitating the electrical connection thereof to respective ones of thepads 42 of the corresponding second set. Advantageously, the surface tension of the molten solder self-aligns theconductive contacts 68 to thepads 42 of the corresponding second set. During this particular procedure, it is contemplated that a vacuum stage or other mechanism will be included in the heated stage to keep thestrip 88 flat during the operation. It is also preferable that the reflow be completed in a reducing atmosphere such as forming gas which is about 90% nitrogen and about 10% hydrogen. This atmosphere allows for minimal amounts of flux which is desirable for the underfill operation which will be described below. - Referring now to FIG. 11, subsequent to the reflow of the solder, the
strip 88 having the integratedcircuit chip 56 electrically connected thereto, is placed upon a heated stage, the temperature of which is set to about 90 degrees Celsius. Thereafter, the underfill epoxy is dispensed along onelongitudinal side 64 of thebody 58 of theintegrated circuit chip 56 to wick under thebody 58. As a result of such wicking, the epoxy underfill flows between thebottom surface 62 of thebody 58 and the top surface of thestrip 88. The heat generated by the stage is then preferably increased to about 160 degrees Celsius for about five minutes to cure (i.e., gel or harden) the underfill epoxy. It is also preferred that a vacuum hold-down as described above be included in this particular stage to maintain thestrip 88 in a substantially flat orientation during the cure of the underfill epoxy. As will be recognized, this epoxy, when cured, is theepoxy layer 70 described above in relation to thechip package 22. It will be recognized that the epoxy may also be applied along both of thelongitudinal sides 64 of thebody 58 during this stage. - Subsequent to the completion of the underfill epoxy stage, the integrity of the electrical connection (i.e., soldered connections) between the
integrated circuit chip 56 and the correspondingconductive pattern 36 is tested. The testing is preferably completed through the use of test probes which are electrically connected to respective ones of thetraces 40 on the bottom surface of thestrip 88. It is contemplated that each of thetraces 40 may extend to a testing pad which will be removed from theflex circuit 24 upon the completion of the assembly method related to thechip package 22. These test pads can be provided with equal diameters and spacing to allow for the use of a universal probe system for different chip package sizes. - As is further seen in FIG. 11, subsequent to the completion of the initial electrical test, the above-described
adhesive strips 48 are bonded to the top surface of thestrip 88 along opposite sides (i.e., the longitudinal sides 64) of thebody 58 of theintegrated circuit chip 56. The adhesive strips 48 extend in spaced, generally parallel in relation to each other, and in generally parallel relation to thelongitudinal sides 64 of thebody 58. The adhesive strips 48 are adhered or mated to the top surface of thestrip 88, with the assembly thereafter being heated to about 140 degrees Celsius. Pressure is also applied for approximately five to ten seconds to theadhesive strips 48, with the combinedadhesive strips 48 andstrip 88 then being allowed to cool down before a paper backing is removed from the exposed sides of the adhesive strips 48. - Referring now to FIG. 12, subsequent to the bonding of the
adhesive strips 48 to thestrip 88, aflex window 90 is punched into thestrip 88. The punching operation preferably occurs in two steps, with the first step resulting in the formation of four rectangularly configuredopenings 92 which each extend through portions of theadhesive strips 48 and portions of thestrip 88. As seen in FIG. 12, each of theopenings 92 is disposed outwardly beyond a respectivelateral side 66 of thebody 58 of the correspondingintegrated circuit chip 56. In the second step of the punching operation, theopenings 92 extending through acommon adhesive strip 48 are connected by the removal of a small portion of thecommon adhesive strip 48 and a large portion of thestrip 88. Theresultant flex window 90 has a generally U-shaped configuration. In the present method, a universal pattern for theflex window 90 can be adopted to work with anintegrated circuit chip 56 of any size. - Upon the completion of the punching operation, the
strip 88 is registered to a frame locating fixture via registration holes 94 formed within thestrip 88. As is seen in FIGS. 10-13, a pair of registration holes 94 is disposed within thestrip 88 between each adjacent pair of the second sets ofconductive pads 28, and hence between each adjacent pair of integrated circuit chips 56. Theintegrated circuit chips 56 andregistration holes 94 are disposed in linear alignment along the approximate center of thestrip 88. Once thestrip 88 has been registered on the frame locating fixture via the registration holes 94, theframe 46 is dropped into position and bonded to theadhesive strips 48 at a temperature of about 140 degrees Celsius for about five seconds and at a pressure of about 20 psi. As is shown in FIG. 12, the properly positionedframe 46 circumvents and is equidistantly spaced from the longitudinal andlateral sides body 58 of the correspondingintegrated circuit chip 56. - Referring now to FIG. 13, subsequent to the attachment of the
frame 46 to thestrip 88, those portions of theadhesive strips 48 andstrip 88 protruding beyond thelongitudinal sides 50 of theframe 46 are wrapped thereabout. As seen in FIGS. 16(a)-16(e), such wrapping is accomplished by the advancement of thestrip 88 over a spaced pair of reciprocallymoveable wrapping fingers 96. Downward pressure is applied to at least one of theframe 46 and thebody 58 of theintegrated circuit chip 56 to force both theframe 46 and theintegrated circuit chip 56 between the wrappingfingers 96 and facilitate the folding of thestrip 88 andadhesive strips 48 upwardly along each of thelongitudinal sides 50 of theframe 46. The wrappingfingers 96 are then moved inwardly toward each other in the manner shown in FIG. 16(d) to facilitate the wrapping of theadhesive strips 48 andstrip 88 about thelongitudinal sides 50 of theframe 46. The wrappingfingers 96 are preferably maintained in the orientation shown in FIG. 16(d) for a period of about five minutes, with the temperature being raised to about 180 degrees Celsius. This elevated temperature for the five minute duration facilitates the complete curing of the adhesive strips 48. Upon the elapse of such time, the wrappingfingers 96 are moved away from each other in the manner shown in FIG. 16(e). For purposes of clarity, theadhesive strips 48 are shown only in FIG. 16(a) and are not shown in FIGS. 16(b)-16(e). - Referring now to FIG. 14, subsequent to the completion of the wrapping procedure, two
continuous strips 88 containing the completedchip packages 22 are brought together and registered using the registration holes 94 within thestrips 88. The Z-axis film 84 described above is then cut into rectangles and positioned between each pair of vertically aligned chip packages 22 in the above-described manner. Heat and pressure are then applied to eachchip stack 80 for approximately one minute to cure the Z-axis film 84. Upon the cure of the Z-axis film 84, the chip stacks 80 are separated from the remainder of thestrip 88. Thereafter, the copper or solder bumps 78 may be formed on the first set ofconductive pads 38 of thelowermost chip package 22 within eachchip stack 80. This particular step is omitted if thelowermost strip 88 is originally provided with the copper bumps 78 formed on thepads 38 of each of the first sets thereof. Finally, the completedchip stack 80 is subjected to an electrical test to verify the integrity of all the electrical connections therein. The copper or solder bumps 78 are preferably formed during the fabrication of theflex circuit 24 through the use of a plating process. - Referring now to FIGS.17-19, there is depicted a stackable integrated
circuit chip package 100 constructed in accordance with a second embodiment of the present invention. Thechip package 100 comprises aflex circuit 102 which is substantially identical to the previously describedflex circuit 24, and comprises aflexible substrate 104 having aconductive pattern 106 disposed thereon. Thechip package 100 also includes anintegrated circuit chip 108 which is identical to the above-describeintegrated circuit chip 56 and is electrically connected to theconductive pattern 106. Thesubstrate 104 of thechip package 100 is wrapped about and attached to at least a portion of theintegrated circuit chip 108 such that theconductive pattern 106 defines afirst portion 110 and asecond portion 112 which are each electrically connectable to another stackable integrated circuit chip package. In thechip package 100 of the second embodiment, theconductive pattern 106 is substantially identical to theconductive pattern 36 previously described in relation to thechip package 22. Additionally, the electrical connection of theintegrated circuit chip 108 to theconductive pattern 106 is accomplished in thechip package 100 in the same manner previously described in relation to the electrical connection of theintegrated circuit chip 56 to theconductive pattern 36. - In the
chip package 100 of the second embodiment, thebody 114 of theintegrated circuit chip 108 preferably has a general rectangular configuration defining a pair oflongitudinal sides 116 and a pair oflateral sides 118. Thesubstrate 104 itself preferably has a generally rectangular configuration defining a pair of longitudinalperipheral edge segments 120 and a pair of lateralperipheral edge segments 122. Theconductive pattern 106 extends along the bottom surface of thesubstrate 104 to the longitudinalperipheral edge segments 120 thereof. Thesubstrate 104 is wrapped about thelongitudinal sides 116 of thebody 114, such that the longitudinalperipheral edge segments 120 extend along the top surface 115 of thebody 114 in spaced, generally parallel relation to each other. The first andsecond portions conductive pattern 106 also extend in spaced, generally parallel relation to each other, with thefirst portion 110 extending over portions of thebottom surface 117 of thebody 114 and thesecond portion 112 extending over a portion of the top surface 115 of thebody 114. Thesubstrate 104 is preferably attached to thebody 114 of theintegrated circuit chip 108 through the use of a pair ofadhesive strips 124 substantially identical to the above-described adhesive strips 48. Additionally, anepoxy layer 126 substantially identical to the above-describedepoxy layer 70 is preferably disposed between thebottom surface 117 of thebody 108 and the top surface of thesubstrate 104. - The assembly process or method related to the
chip package 100 of the second embodiment is substantially similar to the assembly method previously described in relation to thechip package 22 of the first embodiments. In this respect, the assembly method related to thechip package 100 differs primarily in that thestrip 88 is wrapped about the opposedlongitudinal sides 116 of thebody 114 and adhered directly thereto due to the absence of theframe 46 in thechip package 100 of the second embodiment. - Referring now to FIG. 20, there is depicted a stackable integrated
circuit chip package 200 constructed in accordance with a third embodiment of the present invention. Thechip package 200 comprises aflex circuit 202 which itself comprises aflexible substrate 204 having opposed, generally planar top and bottom surfaces, and aconductive pattern 206 disposed thereon. Thechip package 200 of the third embodiment further comprises anintegrated circuit chip 208 which is electrically connected to theconductive pattern 206. Thesubstrate 204 is folded and attached to itself such that theconductive pattern 206 defines afirst portion 210 and asecond portion 212 which are each electrically connectable to another stackable integrated circuit chip package. In thechip package 200 of the third embodiment, theconductive pattern 206 is substantially identical to the above-describedconductive pattern 36 of thechip package 22. Additionally, the electrical connection of the integrated circuit chip 208 (which is substantially identical to the above-described integrated circuit chip 56) to theconductive pattern 206 is accomplished in the same manner previously described in relation to the electrical connection of theintegrated circuit chip 56 to theconductive pattern 36 in thechip package 22. - In the
chip package 200 of the third embodiment, thebody 214 of theintegrated circuit chip 208 preferably has a generally rectangular configuration defining a pair oflongitudinal sides 216 and a pair of lateral sides. Thesubstrate 204 itself preferably has a generally rectangular configuration defining a pair of longitudinalperipheral edge segments 218 and a pair of lateral peripheral edge segments. Theconductive pattern 206 extends along the bottom surface of thesubstrate 204 to the longitudinalperipheral edge segments 218 thereof. Thesubstrate 204 is folded such that the longitudinalperipheral edge segments 218 thereof extend along and in substantially parallel relation to respective ones of thelongitudinal sides 216 of thebody 214, with the first andsecond portions conductive pattern 206 extending in generally parallel relation to each other. - As seen in FIG. 20, the total thickness of the
substrate 204 at those regions whereat it is folded over itself is preferably such that thesecond portion 212 of theconductive pattern 206 is substantially flush with or extends along a plane disposed above the top surface of thebody 214 of theintegrated circuit chip 208, thus allowing for the electrical connection of thesecond portion 212 to another stackable integrated circuit chip package. In thechip package 200 of the third embodiment, thesubstrate 204 is preferably attached to itself through the use of a pair ofadhesive strips 220 substantially similar to the above-describedadhesive strips 48 of thechip package 22 of the first embodiment. Thechip package 200 of the third embodiment further preferably comprises anepoxy layer 222 which is disposed between the bottom surface of thebody 214 and the top surface of thesubstrate 204, and is substantially identical to the above-describedepoxy layer 70 of thechip package 22 of the first embodiment. The assembly method related to thechip package 200 of the third embodiment is also substantially analogous to the above-described assembly method related to thechip package 22 of the first embodiment, except that thesubstrate 204 is folder over and adhered to itself rather than to either theframe 46 or thebody 214 of theintegrated circuit chip 208. - Additional modifications and improvements of the present invention may also be apparent to those of ordinary skill in the art. Thus, the particular combination of parts and steps described and illustrated herein is intended to represent only certain embodiments of the present invention, and is not intended to serve as limitations or alternative devices and methods within the spirit and scope of the invention.
Claims (74)
Priority Applications (1)
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US09/888,785 US6426240B2 (en) | 1999-05-05 | 2001-06-25 | Stackable flex circuit chip package and method of making same |
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US09/305,584 US6323060B1 (en) | 1999-05-05 | 1999-05-05 | Stackable flex circuit IC package and method of making same |
US09/574,321 US6351029B1 (en) | 1999-05-05 | 2000-05-19 | Stackable flex circuit chip package and method of making same |
US09/888,785 US6426240B2 (en) | 1999-05-05 | 2001-06-25 | Stackable flex circuit chip package and method of making same |
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US09/574,321 Division US6351029B1 (en) | 1999-05-05 | 2000-05-19 | Stackable flex circuit chip package and method of making same |
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US20010035572A1 true US20010035572A1 (en) | 2001-11-01 |
US6426240B2 US6426240B2 (en) | 2002-07-30 |
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US09/888,785 Expired - Lifetime US6426240B2 (en) | 1999-05-05 | 2001-06-25 | Stackable flex circuit chip package and method of making same |
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US09/574,321 Expired - Lifetime US6351029B1 (en) | 1999-05-05 | 2000-05-19 | Stackable flex circuit chip package and method of making same |
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Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005010990A2 (en) * | 2003-07-21 | 2005-02-03 | Staktek Group, L.P. | Memory stack using flexible circuit and low-profile contacts |
US20060090102A1 (en) * | 2004-09-03 | 2006-04-27 | Wehrly James D Jr | Circuit module with thermal casing systems and methods |
US20060091529A1 (en) * | 2004-09-03 | 2006-05-04 | Staktek Group L.P. | High capacity thin module system and method |
US20060129888A1 (en) * | 2004-09-03 | 2006-06-15 | Staktek Group L.P. | Circuit module turbulence enhacement systems and methods |
US20070111400A1 (en) * | 2005-11-15 | 2007-05-17 | Katsumi Terada | Dispensing device and mounting system |
US20070132081A1 (en) * | 2004-03-03 | 2007-06-14 | United Test And Assembly Center Limited | Multiple stacked die window csp package and method of manufacture |
US20070238359A1 (en) * | 2006-04-05 | 2007-10-11 | Gutierrez Aurelio J | Modular electronic header assembly and methods of manufacture |
SG144708A1 (en) * | 2004-02-27 | 2008-08-28 | Ever Technologies Pte Ltd | Apparatus and method for fabricating folded ic packages |
US7485951B2 (en) * | 2001-10-26 | 2009-02-03 | Entorian Technologies, Lp | Modularized die stacking system and method |
US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
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Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5484959A (en) * | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
US6323060B1 (en) * | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
US6660561B2 (en) * | 2000-06-15 | 2003-12-09 | Dpac Technologies Corp. | Method of assembling a stackable integrated circuit chip |
US6627984B2 (en) * | 2001-07-24 | 2003-09-30 | Dense-Pac Microsystems, Inc. | Chip stack with differing chip package types |
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US20050056921A1 (en) * | 2003-09-15 | 2005-03-17 | Staktek Group L.P. | Stacked module systems and methods |
US20050009234A1 (en) * | 2001-10-26 | 2005-01-13 | Staktek Group, L.P. | Stacked module systems and methods for CSP packages |
US7154171B1 (en) * | 2002-02-22 | 2006-12-26 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US7246431B2 (en) * | 2002-09-06 | 2007-07-24 | Tessera, Inc. | Methods of making microelectronic packages including folded substrates |
WO2004025699A2 (en) * | 2002-09-11 | 2004-03-25 | Tessera, Inc. | Assemblies having stacked semiconductor chips |
US7071547B2 (en) * | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
US7089984B2 (en) * | 2002-09-30 | 2006-08-15 | Intel Corporation | Forming folded-stack packaged device using progressive folding tool |
FR2845821B1 (en) * | 2002-10-11 | 2005-12-02 | Thales Sa | ELECTRONIC SUBSTRATE OF A THREE-DIMENSIONAL ELECTRONIC MODULE HAVING A HIGH THERMAL DISSIPATION POWER AND ELECTRONIC MODULE |
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US20040207990A1 (en) * | 2003-04-21 | 2004-10-21 | Rose Andrew C. | Stair-step signal routing |
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US6972482B2 (en) | 2003-09-22 | 2005-12-06 | Intel Corporation | Electronic package having a folded flexible substrate and method of manufacturing the same |
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US7394161B2 (en) * | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
WO2005067044A1 (en) | 2004-01-12 | 2005-07-21 | Infineon Technologies Ag | A method for connecting a die assembly to a substrate in an integrated circuit and a semiconductor device comprising a die assembly |
US20060033187A1 (en) * | 2004-08-12 | 2006-02-16 | Staktek Group, L.P. | Rugged CSP module system and method |
US20060043558A1 (en) * | 2004-09-01 | 2006-03-02 | Staktek Group L.P. | Stacked integrated circuit cascade signaling system and method |
US7289327B2 (en) * | 2006-02-27 | 2007-10-30 | Stakick Group L.P. | Active cooling methods and apparatus for modules |
US7606040B2 (en) * | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Memory module system and method |
US20060049513A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method with thermal management |
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US7816778B2 (en) * | 2007-02-20 | 2010-10-19 | Micron Technology, Inc. | Packaged IC device comprising an embedded flex circuit on leadframe, and methods of making same |
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US9093360B2 (en) | 2013-01-11 | 2015-07-28 | Analog Devices, Inc. | Compact device package |
US9332940B1 (en) | 2015-01-05 | 2016-05-10 | Analog Devices, Inc. | Compact wearable biological sensor modules |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4956694A (en) | 1988-11-04 | 1990-09-11 | Dense-Pac Microsystems, Inc. | Integrated circuit chip stacking |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5313096A (en) | 1992-03-16 | 1994-05-17 | Dense-Pac Microsystems, Inc. | IC chip package having chip attached to and wire bonded within an overlying substrate |
US5612570A (en) | 1995-04-13 | 1997-03-18 | Dense-Pac Microsystems, Inc. | Chip stack and method of making same |
US6323060B1 (en) * | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
-
2000
- 2000-05-19 US US09/574,321 patent/US6351029B1/en not_active Expired - Lifetime
-
2001
- 2001-03-29 WO PCT/US2001/010064 patent/WO2001091173A1/en active Application Filing
- 2001-04-24 TW TW090109731A patent/TW506101B/en not_active IP Right Cessation
- 2001-06-25 US US09/888,785 patent/US6426240B2/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
---|---|
US6426240B2 (en) | 2002-07-30 |
TW506101B (en) | 2002-10-11 |
WO2001091173A1 (en) | 2001-11-29 |
US6351029B1 (en) | 2002-02-26 |
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