US20010020737A1 - Chip scale package - Google Patents
Chip scale package Download PDFInfo
- Publication number
- US20010020737A1 US20010020737A1 US09/853,950 US85395001A US2001020737A1 US 20010020737 A1 US20010020737 A1 US 20010020737A1 US 85395001 A US85395001 A US 85395001A US 2001020737 A1 US2001020737 A1 US 2001020737A1
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- US
- United States
- Prior art keywords
- forming
- metal layer
- patterned metal
- dielectric layer
- terminal pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Definitions
- the present invention generally relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly to a chip scale package and a method for manufacturing the chip scale package at the wafer level, using a redistribution substrate.
- Chip Scale Package or a Chip Size Package
- Wafer Level Chip Scale Packaging which assembles CSPs at the wafer level, rather than separately processing individual chips.
- FIG. 1 schematically shows a semiconductor wafer 10 , which includes integrated circuit chips 20 and scribe lines 14 dividing the chips 20 .
- FIG. 2 which is an enlarged view of part ‘A’ of FIG. 1, chip pads 22 are on each chip 20 , and a passivation layer 24 covers the upper surface of the IC chip 20 except where openings through the passivation layer 24 expose the chip pads 22 .
- a dielectric layer 36 and solder bumps 38 are formed on the surface of the wafer 10 .
- the solder bumps 38 electrically connect to the chip pads 22 of FIG. 2.
- a sawing apparatus separates the wafer 10 along the scribe lines 14 , producing individual CSPs 30 .
- FIG. 4 illustrates the cross-sectional structure of the CSP 30 .
- the solder bump 38 connects to the chip pad 22 through a metal layer 34 , and a first and a second dielectric layers 32 and 36 are respectively on and under the metal layer 34 .
- Integrated circuits (not shown) are under the chip pad 22 and the passivation layer 24 .
- the first dielectric layer 32 is formed and patterned on the wafer 10 such that openings in the first dielectric layer 32 expose the chip pads 22 .
- the metal layer 34 is formed on the first dielectric layer by metal deposition and patterning, so that the metal layer 34 contacts the chip pads 22 .
- the second dielectric layer 36 is formed on the metal layer 34 such that openings in the second dielectric layer 36 expose a portion of the metal layer 34 .
- solder bumps 38 are formed on the exposed portion of the metal layer 34 . As described above, sawing separates individual CSPs 30 .
- the CSPs manufactured by the above-described manufacturing method have several problems.
- First, coating and high-temperature curing of the dielectric layers may apply thermal stress to the integrated circuits below the dielectric layers, damaging the integrated circuits. The thinner the dielectric layers are, the smaller the thermal stress is. However, making the dielectric layer thin increases the capacitance of the CSP.
- the present invention is directed to chip scale packages and methods for manufacturing the chip scale packages.
- the methods fabricate multiple chip scale packages on a semiconductor wafer including integrated circuits, and separate the chip scale packages by sawing.
- a method for manufacturing a chip scale package includes: providing a redistribution substrate which has terminal pads, interconnection bumps, and a patterned metal layer connecting the interconnection bumps to the respective terminal pads; attaching a semiconductor wafer having chip pads to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor wafer; forming external terminals on the respective terminal pads; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits.
- the method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material.
- a method of providing the redistribution substrate includes: forming a first dielectric layer having first openings on a substrate base; forming the terminal pads on the substrate base inside the first openings; forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads; forming a second dielectric layer having second openings on the patterned metal layer and the first dielectric layer; and forming the interconnection bumps on the exposed patterned metal layer through the second openings.
- Another method for manufacturing a chip scale package is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips are attached to the redistribution substrate.
- a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer, the first dielectric layer having first holes through which the patterned metal layer connects to the interconnection bumps; a second dielectric layer overlying the patterned metal layer, the second dielectric layer having second holes which expose the patterned metal layer; and terminal pads connecting to the patterned metal layer through the second holes.
- the semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.
- FIG. 1 is a plan view of a semiconductor wafer
- FIG. 2 is an enlarged view of a part “A” of FIG. 1;
- FIG. 3 is a partial plan view of a wafer conventionally processed to have multiple chip scale packages
- FIG. 4 is a cross-sectional view of a chip scale package of FIG. 3;
- FIGS. 5 to 20 are partial cross-sectional views of a semiconductor wafer and/or a redistribution substrate, illustrating a method for manufacturing chip scale packages according to an embodiment of the present invention, wherein
- FIGS. 5 and 6 show the semiconductor wafer
- FIGS. 7 to 14 show the a redistribution substrate
- FIGS. 15 to 20 show the semiconductor wafer and the redistribution substrate
- FIGS. 21 to 27 are partial cross-sectional views of a semiconductor wafer, illustrating a method for manufacturing chip scale packages according to another embodiment of the present invention.
- FIGS. 28 to 31 are partial cross-sectional views of a semiconductor wafer, illustrating a method for manufacturing wafer level chip scale packages according to still another embodiment of the present invention.
- the present invention is directed to chip scale packages and methods for manufacturing the chip scale packages.
- the methods fabricate multiple chip scale packages on a semiconductor wafer including integrated circuits, and separates the chip scale packages by sawing.
- the individualized chip scale packages can be directly mounted on a circuit board of an electronic device.
- FIGS. 5 to 20 illustrate a method for manufacturing a chip scale package according to an embodiment of the present invention.
- a known wafer fabrication method produces a wafer 100 containing integrated circuits (not shown), chip pads 104 , and a passivation layer 106 on a silicon wafer substrate 102 . Openings of the passivation layer 106 expose chip pads 104 .
- the wafer 100 also includes scribe lines (not shown), which separate the integrated circuits.
- an under barrier metal (UBM) 108 is formed on the chip pad 104 to increase the adhesion strength between the chip pad 104 and a solder bump to be formed on the chip pad 104 .
- the UBM 108 is multilayered and includes nickel (Ni), copper (Cu), gold (Au), titanium (Ti), chromium (Cr), titanium-tungsten (TiW), and/or nickel-vanadium (NiV) layers. Other metal layers also can be a part of the UBM 108 .
- the structure of the UBM 108 and the method of fabricating the UBM 108 are well known in the art. For example, electroplating or electroless-plating can form the UBM 108 .
- the chip pads 104 can be coated with Palladium (Pd) or Zinc (Zn) to facilitate the plating.
- Pd Palladium
- Zn Zinc
- a Pd coating can be formed by dipping the chip pads in PdCl 2 diluted with a small quantity of HCl and H 2 O.
- Zn coating the chip pads are first treated with HNO 3 , dipped in zincate solution for about 1 minute, treated with HNO 3 for about 15 seconds, and again dipped in zincate solution for about 1 minute.
- FIGS. 7 to 14 show a manufacturing process of the redistribution substrate.
- a first dielectric layer 112 is formed on a substrate base 110 , which is a metal sheet or film, preferably a copper (Cu) sheet.
- the first dielectric layer 112 is formed by coating a polymer such as a polyimide or a BenzoCycloButene (BCB) and patterning the coated polymer layer to form openings 114 that expose substrate base 110 .
- a known photo-etch process can pattern the first dielectric layer 112 .
- terminal pads 116 are formed on the substrate base 110 in the openings 114 in the same way that the UBM 108 of FIG. 8 was formed. For instance, when electroplating forms the terminal pads 116 , the substrate base 110 is used as a plating electrode.
- FIG. 9 to 12 show formation of redistributed metal patterns 122 .
- a photoresist layer 118 is formed by known coating and photo-etch processes on the first dielectric layer 112 as shown in FIG. 9.
- a known chemical vapor deposition forms a metal layer 120 on the first dielectric layer 112 and the photoresist layer 118 .
- the redistributed metal patterns 122 are obtained.
- the redistributed metal patterns 122 can be made of Copper (Cu), Aluminum (Al), Zinc (Zn), Iron (Fe), Platinum (Pt), Cobalt (Co), Lead (Pb), Nickel (Ni), or their alloys.
- a second dielectric layer 124 is formed of a polymer, such as polyimide or BCB, on the redistributed metal patterns 122 in the same way that the first dielectric layer 112 of FIG. 7 is formed.
- the second dielectric layer 124 has second openings 126 through which the redistributed metal patterns 122 is exposed. Second openings 126 have positions that coincide with the chip pads 22 .
- FIGS. 13 and 14 illustrate the formation of interconnection bumps 128 on the portion of the redistributed metal patterns 122 exposed through the second openings 126 .
- Electroplating a metal such as solder can form pre-interconnection bumps 128 ′ on the exposed redistributed metal patterns 122 using the substrate base 110 as plating electrode.
- reflowing the pre-interconnection bumps 128 ′ forms the interconnection bumps 128 in ball shape through melting and solidifying of the pre-interconnection bumps 128 ′.
- the processes in FIGS. 7 to 14 manufactures a redistribution substrate 130 .
- the redistribution substrate 130 is manufactured separately from the wafer 100 , and thus the integrated circuit chips of the wafer are not damaged by process conditions associated with forming dielectric layers in the known wafer level chip scale packaging.
- the wafer 100 of FIG. 15, which is identical to the wafer 100 of FIG. 6, is attached to the redistribution substrate 130 as shown in FIG. 16.
- the interconnection bumps 128 of the redistribution substrate 130 connect to the chip pads 104 , through the UBM 108 , of the wafer 100 .
- the wafer 100 is placed on the redistribution substrate 130 with the interconnection bumps 128 aligned with the chip pads 104 .
- a reflow process at 200 ⁇ 250° C. for about 1 to 2 minutes electrically connects the wafer 100 and the redistribution substrate 130 .
- This reflow process is less damaging to the integrated circuits of the wafer 100 than the dielectric layer formation. For example, forming a dielectric layer typically heat the wafer to 300° C. for more than 10 minutes.
- a buffer layer 134 For example, an epoxy resin having viscosity of about 250 poise can fill the gap 132 and be cured at 150° C. for about 60 minutes.
- the buffer layer 134 absorbs the thermal stress caused by the thermal expansion coefficient mismatch between the wafer 100 and the redistribution substrate 130 , preventing failure of the interconnection bumps 128 .
- the buffer layer 134 also serves as an additional dielectric layer, decreasing the capacitance of CSPs.
- the substrate base 110 is removed, for example, by wet-etching, leaving the structure of FIG. 18.
- wet etching in sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) for 2 hours can remove the substrate base 110 , exposing the terminal pads 116 .
- a solder bump formation method well-known in the art forms external terminals 136 on the respective terminal pad 116 , and a conventional sawing separates individual CSPs along scribe lines 138 .
- FIGS. 21 to 27 illustrate a method for manufacturing CSPs according to another embodiment of the present invention. This method is basically the same as the method described with reference to FIGS. 5 to 20 . A difference is that the method of FIGS. 21 to 27 attaches individual integrated circuit chips, not the whole wafer, to the redistributed substrate. Accordingly the processes for preparing the wafer and the redistribution substrate are not explained here.
- sawing separates the wafer 100 of FIG. 6 into individual integrate circuit chips 150 .
- the redistribution substrate 130 of FIG. 22 is the same as the redistribution substrate 130 of FIG. 14.
- the separated individual chips 150 are tested, the chips 150 that pass the test are attached to the redistribution substrate 130 in the same manner described with reference to FIG. 16.
- the interconnection bumps 128 of the redistribution substrate 130 connect to the chip pads 104 , through the UBM 108 , of the wafer 100 .
- FIGS. 25 and 26 illustrate separation of individual chips 150 having a part of the redistribution substrate.
- the first and the second dielectric layers 112 and 124 of the redistribution substrate 130 are partly removed by a conventional wafer sawing between the chips 150 .
- a groove 158 which extends to the substrate base 110 of the redistribution substrate 130 , is formed.
- the present invention further provides another wafer level chip scale packaging method, which is the same as the method described with reference to FIGS. 5 to 20 except for the processes associated with external terminal formation.
- FIGS. 28 to 31 illustrate the new external formation processes. After the wafer 130 is attached to the redistribution substrate 100 , while the method of FIGS. 5 to 20 removes entire substrate base 110 to expose the terminal pads 116 , the method of FIGS. 28 to 31 exposes the terminal pads 116 by partial removal of the substrate base 110 .
- the substrate base should be made of an electrically conductive metal.
- a photoresist pattern 170 is formed on the substrate base 110 by coating and patterning a photoresist layer, such that the photoresist pattern 170 is above the terminal pads 116 . Then, etching the substrate base 110 using the photoresist pattern 170 as a mask results in a patterned substrate base 172 covered with the photoresist pattern 170 as shown in FIG. 30. Finally, as shown in FIG. 31, the photoresist pattern 170 is removed, and then patterned substrate base 172 remains to be used as external terminals 172 of individual CSPs. The individual CSPs are separated in the same way as in the method of FIG. 20.
- FIGS. 21 to 27 also can use the external terminal forming processes of the method of FIGS. 28 to 31 .
Abstract
A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.
Description
- This document is related to and incorporates by reference co-filed U.S. patent application Ser. No. UNKNOWN entitled “Chip Scale Package and Method for Manufacturing the Same Using Rerouting Film and Soldering”.
- 1. Field of the Invention
- The present invention generally relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly to a chip scale package and a method for manufacturing the chip scale package at the wafer level, using a redistribution substrate.
- 2. Description of the Related Arts
- The electronics industry has been progressing with the miniaturization of electronic devices. This trend influences semiconductor packaging technology, which enables the connection between bare IC chips and other components. Typically, a semiconductor package has a footprint much larger than that of the chip. To adapt to the miniaturization trend, the size difference between the package and the chip has been reduced, producing a new package type called a Chip Scale Package (or a Chip Size Package) (CSP). Among the manufacturing technologies for the CSPs is Wafer Level Chip Scale Packaging, which assembles CSPs at the wafer level, rather than separately processing individual chips.
- FIG. 1 schematically shows a
semiconductor wafer 10, which includesintegrated circuit chips 20 and scribelines 14 dividing thechips 20. As shown in FIG. 2 which is an enlarged view of part ‘A’ of FIG. 1,chip pads 22 are on eachchip 20, and apassivation layer 24 covers the upper surface of theIC chip 20 except where openings through thepassivation layer 24 expose thechip pads 22. - Regarding to FIGS. 3 and 4, in conventional wafer level chip scale packaging, a
dielectric layer 36 andsolder bumps 38 are formed on the surface of thewafer 10. Thesolder bumps 38 electrically connect to thechip pads 22 of FIG. 2. Then, a sawing apparatus separates thewafer 10 along thescribe lines 14, producingindividual CSPs 30. - FIG. 4 illustrates the cross-sectional structure of the
CSP 30. Thesolder bump 38 connects to thechip pad 22 through ametal layer 34, and a first and a seconddielectric layers metal layer 34. Integrated circuits (not shown) are under thechip pad 22 and thepassivation layer 24. In the fabrication of theCSPs 30 on thewafer 10, the firstdielectric layer 32 is formed and patterned on thewafer 10 such that openings in the firstdielectric layer 32 expose thechip pads 22. Then, themetal layer 34 is formed on the first dielectric layer by metal deposition and patterning, so that themetal layer 34 contacts thechip pads 22. The seconddielectric layer 36 is formed on themetal layer 34 such that openings in the seconddielectric layer 36 expose a portion of themetal layer 34. Finally,solder bumps 38 are formed on the exposed portion of themetal layer 34. As described above, sawing separatesindividual CSPs 30. - The CSPs manufactured by the above-described manufacturing method have several problems. First, coating and high-temperature curing of the dielectric layers may apply thermal stress to the integrated circuits below the dielectric layers, damaging the integrated circuits. The thinner the dielectric layers are, the smaller the thermal stress is. However, making the dielectric layer thin increases the capacitance of the CSP. Second, when the CSP is mounted on an external circuit board such that the solder bumps contact the circuit board, the connection integrity between the solder bumps and the circuit board is not reliable.
- Third, since defective chips as well as good chips are packaged in wafer level, the manufacturing cost of individual CSPs increases.
- The present invention is directed to chip scale packages and methods for manufacturing the chip scale packages. The methods fabricate multiple chip scale packages on a semiconductor wafer including integrated circuits, and separate the chip scale packages by sawing.
- In accordance with an embodiment of the invention, a method for manufacturing a chip scale package includes: providing a redistribution substrate which has terminal pads, interconnection bumps, and a patterned metal layer connecting the interconnection bumps to the respective terminal pads; attaching a semiconductor wafer having chip pads to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor wafer; forming external terminals on the respective terminal pads; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material.
- A method of providing the redistribution substrate includes: forming a first dielectric layer having first openings on a substrate base; forming the terminal pads on the substrate base inside the first openings; forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads; forming a second dielectric layer having second openings on the patterned metal layer and the first dielectric layer; and forming the interconnection bumps on the exposed patterned metal layer through the second openings.
- Another method for manufacturing a chip scale package is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips are attached to the redistribution substrate.
- In accordance with another embodiment of the invention, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer, the first dielectric layer having first holes through which the patterned metal layer connects to the interconnection bumps; a second dielectric layer overlying the patterned metal layer, the second dielectric layer having second holes which expose the patterned metal layer; and terminal pads connecting to the patterned metal layer through the second holes. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.
- The various features and advantages of the present invention will be readily understood with reference to the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and, in which:
- FIG. 1 is a plan view of a semiconductor wafer;
- FIG. 2 is an enlarged view of a part “A” of FIG. 1;
- FIG. 3 is a partial plan view of a wafer conventionally processed to have multiple chip scale packages;
- FIG. 4 is a cross-sectional view of a chip scale package of FIG. 3;
- FIGS.5 to 20 are partial cross-sectional views of a semiconductor wafer and/or a redistribution substrate, illustrating a method for manufacturing chip scale packages according to an embodiment of the present invention, wherein
- FIGS. 5 and 6 show the semiconductor wafer,
- FIGS.7 to 14 show the a redistribution substrate, and
- FIGS.15 to 20 show the semiconductor wafer and the redistribution substrate;
- FIGS.21 to 27 are partial cross-sectional views of a semiconductor wafer, illustrating a method for manufacturing chip scale packages according to another embodiment of the present invention; and
- FIGS.28 to 31 are partial cross-sectional views of a semiconductor wafer, illustrating a method for manufacturing wafer level chip scale packages according to still another embodiment of the present invention.
- The present invention is directed to chip scale packages and methods for manufacturing the chip scale packages. The methods fabricate multiple chip scale packages on a semiconductor wafer including integrated circuits, and separates the chip scale packages by sawing. The individualized chip scale packages can be directly mounted on a circuit board of an electronic device.
- FIGS.5 to 20 illustrate a method for manufacturing a chip scale package according to an embodiment of the present invention. Referring to FIG. 5, a known wafer fabrication method produces a
wafer 100 containing integrated circuits (not shown),chip pads 104, and apassivation layer 106 on asilicon wafer substrate 102. Openings of thepassivation layer 106 exposechip pads 104. Thewafer 100 also includes scribe lines (not shown), which separate the integrated circuits. - With reference to FIG. 6, an under barrier metal (UBM)108 is formed on the
chip pad 104 to increase the adhesion strength between thechip pad 104 and a solder bump to be formed on thechip pad 104. Typically, the UBM 108 is multilayered and includes nickel (Ni), copper (Cu), gold (Au), titanium (Ti), chromium (Cr), titanium-tungsten (TiW), and/or nickel-vanadium (NiV) layers. Other metal layers also can be a part of theUBM 108. The structure of theUBM 108 and the method of fabricating theUBM 108 are well known in the art. For example, electroplating or electroless-plating can form theUBM 108. Prior to the plating but before forming the passivation, thechip pads 104 can be coated with Palladium (Pd) or Zinc (Zn) to facilitate the plating. A Pd coating can be formed by dipping the chip pads in PdCl2 diluted with a small quantity of HCl and H2O. To form a Zn coating, the chip pads are first treated with HNO3, dipped in zincate solution for about 1 minute, treated with HNO3 for about 15 seconds, and again dipped in zincate solution for about 1 minute. - Apart from the
wafer 100, a redistribution substrate is prepared. FIGS. 7 to 14 show a manufacturing process of the redistribution substrate. With reference to FIG. 7, a firstdielectric layer 112 is formed on asubstrate base 110, which is a metal sheet or film, preferably a copper (Cu) sheet. Thefirst dielectric layer 112 is formed by coating a polymer such as a polyimide or a BenzoCycloButene (BCB) and patterning the coated polymer layer to formopenings 114 that exposesubstrate base 110. A known photo-etch process can pattern thefirst dielectric layer 112. - As shown in FIG. 8, after the patterning,
terminal pads 116 are formed on thesubstrate base 110 in theopenings 114 in the same way that theUBM 108 of FIG. 8 was formed. For instance, when electroplating forms theterminal pads 116, thesubstrate base 110 is used as a plating electrode. - FIG. 9 to12 show formation of redistributed
metal patterns 122. First, aphotoresist layer 118 is formed by known coating and photo-etch processes on thefirst dielectric layer 112 as shown in FIG. 9. Then, as shown in FIG. 10, a known chemical vapor deposition forms ametal layer 120 on thefirst dielectric layer 112 and thephotoresist layer 118. Then, by removing thephotoresist layer 118 and themetal layer 120 on thephotoresist layer 118, the redistributedmetal patterns 122 are obtained. The redistributedmetal patterns 122 can be made of Copper (Cu), Aluminum (Al), Zinc (Zn), Iron (Fe), Platinum (Pt), Cobalt (Co), Lead (Pb), Nickel (Ni), or their alloys. - In FIG. 12, a
second dielectric layer 124 is formed of a polymer, such as polyimide or BCB, on the redistributedmetal patterns 122 in the same way that thefirst dielectric layer 112 of FIG. 7 is formed. Thesecond dielectric layer 124 hassecond openings 126 through which the redistributedmetal patterns 122 is exposed.Second openings 126 have positions that coincide with thechip pads 22. - FIGS. 13 and 14 illustrate the formation of interconnection bumps128 on the portion of the redistributed
metal patterns 122 exposed through thesecond openings 126. Electroplating a metal such as solder can formpre-interconnection bumps 128′ on the exposed redistributedmetal patterns 122 using thesubstrate base 110 as plating electrode. Then, reflowing the pre-interconnection bumps 128′ forms the interconnection bumps 128 in ball shape through melting and solidifying of the pre-interconnection bumps 128′. As a result, the processes in FIGS. 7 to 14 manufactures aredistribution substrate 130. According to the above-described method, theredistribution substrate 130 is manufactured separately from thewafer 100, and thus the integrated circuit chips of the wafer are not damaged by process conditions associated with forming dielectric layers in the known wafer level chip scale packaging. - After the
redistribution substrate 130 is manufactured, thewafer 100 of FIG. 15, which is identical to thewafer 100 of FIG. 6, is attached to theredistribution substrate 130 as shown in FIG. 16. As shown, the interconnection bumps 128 of theredistribution substrate 130 connect to thechip pads 104, through theUBM 108, of thewafer 100. In the attachment, thewafer 100 is placed on theredistribution substrate 130 with the interconnection bumps 128 aligned with thechip pads 104. A reflow process at 200˜250° C. for about 1 to 2 minutes electrically connects thewafer 100 and theredistribution substrate 130. This reflow process is less damaging to the integrated circuits of thewafer 100 than the dielectric layer formation. For example, forming a dielectric layer typically heat the wafer to 300° C. for more than 10 minutes. - Regarding FIG. 17, after the connection of the
wafer 100 to theredistribution substrate 130, dispensing an underfilling encapsulant (liquid polymer) into agap 132 between theredistribution substrate 130 and thewafer 100 and curing the filled encapsulant form abuffer layer 134. For example, an epoxy resin having viscosity of about 250 poise can fill thegap 132 and be cured at 150° C. for about 60 minutes. Thebuffer layer 134 absorbs the thermal stress caused by the thermal expansion coefficient mismatch between thewafer 100 and theredistribution substrate 130, preventing failure of the interconnection bumps 128. Thebuffer layer 134 also serves as an additional dielectric layer, decreasing the capacitance of CSPs. - After the forming of the
buffer layer 134, thesubstrate base 110 is removed, for example, by wet-etching, leaving the structure of FIG. 18. For a 500 μm thickcopper substrate base 110, wet etching in sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) for 2 hours can remove thesubstrate base 110, exposing theterminal pads 116. Then, as shown in FIGS. 19 and 20, a solder bump formation method well-known in the art formsexternal terminals 136 on therespective terminal pad 116, and a conventional sawing separates individual CSPs along scribe lines 138. - FIGS.21 to 27 illustrate a method for manufacturing CSPs according to another embodiment of the present invention. This method is basically the same as the method described with reference to FIGS. 5 to 20. A difference is that the method of FIGS. 21 to 27 attaches individual integrated circuit chips, not the whole wafer, to the redistributed substrate. Accordingly the processes for preparing the wafer and the redistribution substrate are not explained here.
- Regarding to FIG. 21, sawing separates the
wafer 100 of FIG. 6 into individual integratecircuit chips 150. Theredistribution substrate 130 of FIG. 22 is the same as theredistribution substrate 130 of FIG. 14. With reference to FIG. 23, the separatedindividual chips 150 are tested, thechips 150 that pass the test are attached to theredistribution substrate 130 in the same manner described with reference to FIG. 16. As before, the interconnection bumps 128 of theredistribution substrate 130 connect to thechip pads 104, through theUBM 108, of thewafer 100. - Regarding FIG. 24, after the connection of the
chips 150 to theredistribution substrate 130, dispensing an underfilling encapsulant (liquid polymer) into agap 152 between theredistribution substrate 130 and thechips 150 and curing the filled encapsulant forms abuffer layer 156. FIGS. 25 and 26 illustrate separation ofindividual chips 150 having a part of the redistribution substrate. As shown in FIG. 25, the first and the seconddielectric layers redistribution substrate 130 are partly removed by a conventional wafer sawing between thechips 150. As a result, agroove 158, which extends to thesubstrate base 110 of theredistribution substrate 130, is formed. Then, removing thesubstrate base 110 by wet-etch separates thechips 150 having parts of theredistribution substrate 130, exposing theterminal pads 116. Finally, a solder bump formation method well known in the art formsexternal terminals 136 on therespective terminal pads 116, andindividual CSPs 160 have been manufactured. (FIG. 27) - The present invention further provides another wafer level chip scale packaging method, which is the same as the method described with reference to FIGS.5 to 20 except for the processes associated with external terminal formation. FIGS. 28 to 31 illustrate the new external formation processes. After the
wafer 130 is attached to theredistribution substrate 100, while the method of FIGS. 5 to 20 removesentire substrate base 110 to expose theterminal pads 116, the method of FIGS. 28 to 31 exposes theterminal pads 116 by partial removal of thesubstrate base 110. In this embodiment, the substrate base should be made of an electrically conductive metal. - After the
wafer 130 is attached to the redistribution substrate 100 (FIG. 28), as shown in FIG. 29, aphotoresist pattern 170 is formed on thesubstrate base 110 by coating and patterning a photoresist layer, such that thephotoresist pattern 170 is above theterminal pads 116. Then, etching thesubstrate base 110 using thephotoresist pattern 170 as a mask results in a patternedsubstrate base 172 covered with thephotoresist pattern 170 as shown in FIG. 30. Finally, as shown in FIG. 31, thephotoresist pattern 170 is removed, and then patternedsubstrate base 172 remains to be used asexternal terminals 172 of individual CSPs. The individual CSPs are separated in the same way as in the method of FIG. 20. - Although specific embodiments of the present invention have been described in detail hereinabove, it should be understood that many variations and/or modifications of the basic inventive concepts herein taught still fall within the spirit and scope of the present invention as defined in the appended claims. For instance, the method of FIGS.21 to 27 also can use the external terminal forming processes of the method of FIGS. 28 to 31.
Claims (15)
1. A method for manufacturing a semiconductor package, comprising:
providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads;
attaching a semiconductor wafer, on which has a plurality of integrated circuits and a plurality of chip pads are formed, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor wafer;
forming a plurality of external terminals on the respective terminal pads of the redistribution substrate; and
separating the semiconductor wafer and the redistribution substrate into individual semiconductor packages, each semiconductor package including an integrated circuit having a corresponding portion of the redistribution substrate attached thereon.
2. The method of , wherein said providing the redistribution substrate comprises:
claim 1
forming a first dielectric layer having a plurality of first openings on the substrate base;
forming the terminal pads on the substrate base inside the first openings;
forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads;
forming a second dielectric layer on the patterned metal layer and the first dielectric layer, the second dielectric layer including a plurality of second openings; and
forming the interconnection bumps on the patterned metal layer exposed through the second openings, wherein the interconnection bumps electrically connect to the respective terminal pads through the patterned metal layer.
3. The method of , wherein said forming the external terminals comprises:
claim 1
removing the substrate base so as to expose the terminal pads; and
forming a plurality of protruding components on the respective terminal pads.
4. The method of , wherein said forming the external terminals comprises patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals.
claim 1
5. The method of , further comprising forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material.
claim 1
6. A method for manufacturing a semiconductor package, comprising:
providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads;
attaching a plurality of semiconductor integrated circuit chips, each of which has a plurality of chip pads formed thereon, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor chips;
forming a plurality of external terminals on the respective terminal pads of the redistribution substrate; and
separating the redistribution substrate so as to produce individual semiconductor packages, each of which includes an integrated circuit chip having a corresponding portion of the redistribution substrate attached thereon.
7. The method of , wherein said providing the redistribution substrate comprises:
claim 6
forming a first dielectric layer having a plurality of first openings on the substrate base;
forming the terminal pads on the substrate base inside the first openings;
forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads;
forming a second dielectric layer having a plurality of second openings on the patterned metal layer and the first dielectric layer; and
forming the interconnection bumps on the patterned metal layer exposed through the second openings, wherein the interconnection bumps electrically connect to the respective terminal pads through the patterned metal layer.
8. The method of , wherein said forming the external terminals comprises:
claim 6
removing the substrate base so as to expose the terminal pads; and
forming a plurality of protruding components on the respective terminal pads.
9. The method of , wherein said forming the external terminals comprises patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals.
claim 6
10. The method of , further comprising forming a buffer layer by filling a gap between the integrated circuit chips and the redistribution substrate with a dielectric material.
claim 6
11. A semiconductor package comprising:
a semiconductor integrated circuit having a plurality of chip pads formed thereon;
a plurality of interconnection bumps overlying on the chip pads;
a patterned metal layer connecting to the interconnection bumps;
a first dielectric layer under the patterned metal layer, the first dielectric
layer having a plurality of first holes through which the patterned metal layer connects to the interconnection bumps;
a second dielectric layer overlying on the patterned metal layer, the second dielectric layer having a plurality of second holes; and
a plurality of terminal pads connecting to the patterned metal layer through the second holes.
12. The semiconductor package of , further comprising a plurality of external terminals connecting to the terminal pads.
claim 11
13. The semiconductor package of , further comprising a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.
claim 11
14. The semiconductor package of , wherein the semiconductor integrated circuit comprises a passivation layer on a top surface of the semiconductor integrated circuit.
claim 11
15. The semiconductor package of , wherein each of the chip pads comprises a metal layer thereon to improve the connection between the interconnection bumps and the chip pads.
claim 11
Priority Applications (1)
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US09/853,950 US6407459B2 (en) | 1999-07-09 | 2001-05-10 | Chip scale package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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KR1019990027786A KR100298827B1 (en) | 1999-07-09 | 1999-07-09 | Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate |
KR99-27786 | 1999-07-09 | ||
US09/482,160 US6235552B1 (en) | 1999-07-09 | 2000-01-12 | Chip scale package and method for manufacturing the same using a redistribution substrate |
US09/853,950 US6407459B2 (en) | 1999-07-09 | 2001-05-10 | Chip scale package |
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US09/482,216 Division US6376279B1 (en) | 1999-07-12 | 2000-01-12 | method for manufacturing a semiconductor package |
US09/482,160 Division US6235552B1 (en) | 1999-07-09 | 2000-01-12 | Chip scale package and method for manufacturing the same using a redistribution substrate |
Publications (2)
Publication Number | Publication Date |
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US20010020737A1 true US20010020737A1 (en) | 2001-09-13 |
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US09/853,950 Expired - Lifetime US6407459B2 (en) | 1999-07-09 | 2001-05-10 | Chip scale package |
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Application Number | Title | Priority Date | Filing Date |
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US09/482,160 Expired - Lifetime US6235552B1 (en) | 1999-07-09 | 2000-01-12 | Chip scale package and method for manufacturing the same using a redistribution substrate |
Country Status (3)
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US (2) | US6235552B1 (en) |
JP (1) | JP3759689B2 (en) |
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Also Published As
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JP3759689B2 (en) | 2006-03-29 |
JP2001035965A (en) | 2001-02-09 |
US6235552B1 (en) | 2001-05-22 |
KR20010009429A (en) | 2001-02-05 |
KR100298827B1 (en) | 2001-11-01 |
US6407459B2 (en) | 2002-06-18 |
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