US20010017807A1 - Semiconductor memory device allowing static-charge tolerance test between bit lines - Google Patents
Semiconductor memory device allowing static-charge tolerance test between bit lines Download PDFInfo
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- US20010017807A1 US20010017807A1 US09/790,573 US79057301A US2001017807A1 US 20010017807 A1 US20010017807 A1 US 20010017807A1 US 79057301 A US79057301 A US 79057301A US 2001017807 A1 US2001017807 A1 US 2001017807A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
Definitions
- the present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that allows a proper check while it is on a wafer.
- WLBI wafer level burn-in
- bit lines are fixed to the ground level (i.e., the voltage level of the ground-side power supply voltage), and word lines are all selected and placed in the activated state. With the bit lines clamped to the low voltage level, a high gate voltage is applied to all the cell transistors in this manner to place them under stress.
- a semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.
- a clamp-voltage generation circuit is provided to supply the first clamp voltage to the first sense amplifier circuits and to supply the second clamp voltage to the second sense amplifier circuits in the test mode.
- the first and second clamp voltages may be set to voltages varying depending on a code signal supplied from an exterior of the semiconductor memory device. This makes it possible to clamp all the bit lines to LOW, thereby conducting a conventional static-charge tolerance test.
- FIG. 1 is a drawing showing a semiconductor memory device to which the present invention is applied;
- FIG. 2 is a circuit diagram showing a main portion of a core circuit of a twin-storage-type memory
- FIG. 3 is a block diagram showing an entry unit that receives a mode flag signal
- FIGS. 4A through 4C are illustrative drawings for explaining code signal inputs to the entry unit
- FIG. 5 is a table showing settings of bit-line clamp voltages responsive to the code signal inputs
- FIG. 6 is a circuit diagram showing a circuit generating bit-line clamp voltages
- FIG. 7 is a circuit diagram showing a control mechanism for clamping bit lines and selecting all word lines
- FIG. 8 is an illustrative drawing showing a layout of signal lines that supply clamp voltages to sense amplifier units.
- FIG. 9 is an illustrative drawing for explaining a stress applied between storage points.
- FIG. 1 is a drawing showing a semiconductor memory device to which the present invention is applied.
- a semiconductor memory device 10 of FIG. 1 includes a data-control circuitry 11 , a read/write amplifier 12 , a timing circuitry 13 , an address processing circuitry 14 , a column decoder 15 , a main-word decoder 16 , and a core circuit 17 .
- the core circuit 17 is provided with a plurality of memory cells CELL arranged in a matrix form, and includes circuitry and signal lines for address selection, data amplification, and so on in order to read/write 1-bit data from/in each cell.
- the core circuit 17 shown illustratively in FIG. 1 includes a plurality of sense amplifier units 400 - 0 and 400 - 1 , a plurality of sub-word decoder 340 , a plurality of word lines WL, a plurality of main word lines MWL, and a plurality of column lines CL.
- the data-control circuitry 11 includes circuitry such as data buffers.
- the data-control circuitry 11 supplies data to the read/write amplifier 12 at an appropriate timing as the data is provided from the exterior of the device, and supplies data to the exterior of the device at an appropriate timing as the data is read from the core circuit 17 and the read/write amplifier 12 .
- the read/write amplifier 12 amplifies write data, followed by supplying the data to the core circuit 17 , and, also, amplifies data supplied form the core circuit 17 .
- the timing circuitry 13 is comprised of control-signal buffers, a command decoder, and so on.
- the timing circuitry 13 receives control signals and a clock signal from the exterior of the device, and interprets commands represented by the control signals, thereby controlling operation and operation timings of each unit provided in the semiconductor memory device 10 .
- the address processing circuitry 14 includes address buffers, an address pre-decoder, and so on.
- the address processing circuitry 14 receives address signals from the exterior of the device, and supplies them to the column decoder 15 and the main-word decoder 16 at appropriate timings.
- the column decoder 15 decodes a column address supplied from the address processing circuitry 14 , and activates a column line CL corresponding to the specified column address.
- the main-word decoder 16 decodes a row address supplied from the address processing circuitry 14 , and activates a main-word line MWL corresponding to the specified row address.
- a hierarchical word decode scheme is employed. In this configuration, a plurality of word lines correspond to the main-word line MWL selected by the main-word decoder, and one of these word lines WL is selectively activated by a sub-word decoder 340 .
- the semiconductor memory device of FIG. 1 is a twin-storage-type memory, in which a pair of bit lines BL and /BL connected to a sense amplifier unit each have a memory cell CELL connected thereto. One of the pair of memory cells stores given data, and the other stores the inverted data.
- FIG. 2 is a circuit diagram showing a main portion of the core circuit 17 of the twin-storage-type memory.
- the word decoder 20 collectively represents one set of the sub-word decoders 340 shown in FIG. 1. Further, “/” preceding symbols represents logic inversion of the same symbols having no “/”.
- twin-storage-type memory stable data read operation is attainable compared to a conventional DRAM structure in which only one of the pair of bit lines has a memory cell connected thereto. Because of this, a refresh cycle can be elongated, for example, as an advantage.
- a twin-storage-type memory to which the present invention is applied has a configuration in which adjacent bit lines are connected to different sense amplifier units. Namely, for example, the bit line BL 1 shown on the top in FIG. 2 is connected to the sense amplifier unit 400 - 1 , and the next bit line BL 0 is connected to the sense amplifier unit 400 - 0 , followed by the next bit line /BL 1 connected to the sense amplifier unit 400 - 1 . In this manner, the sense amplifier unit 400 - 0 has even-number bit lines connected thereto, and the sense amplifier unit 400 - 1 has odd-number bit lines connected thereto.
- a precharge voltage (i.e., bit-line clamp voltage) VPR 0 supplied to the sense amplifier unit 400 - 0 and a precharge voltage (bit-line clamp voltage) VPR 1 supplied to the sense amplifier unit 400 - 1 may be set to HIGH and LOW, respectively, or vise versa, thereby setting two adjacent bit liens to HIGH and LOW.
- bit-line clamp voltages VPR 0 and VPR 1 are set to different voltages in this manner, so that static-charge tolerance tests can be conducted between bit lines during the WLBI test mode.
- FIG. 3 is a block diagram showing an entry unit that receives a mode flag signal.
- the entry unit is part of the command-control related circuitry of the timing circuitry 13 shown in FIG. 1.
- a mode-flag signal WLBIZ HGH
- a signal name that ends with “Z” or “z” represents a positive logic signal
- a signal name that ends with “X” or “x” represents a negative logic signal.
- An entry unit 100 of FIG. 3 includes a plurality of inverters 101 serving as buffers, switches 102 and 103 , a pulse generation circuit 104 , DFF (delay flip-flops) 105 through 107 , a delay circuit 108 , a register 109 , a register 110 , and a decoder 111 .
- inverters 101 serving as buffers
- switches 102 and 103 switches 102 and 103
- DFF delay flip-flops
- the entry unit 100 receives the mode-flag signal WLBIZ, a clock signal CLK, and a code signal CODE from the exterior of the memory chip.
- the mode-flag signal WLBIZ is supplied to the switches 102 and 103 as a mode-flag signal WLBIZA after passing through a series of inverters 101 .
- the switches 102 and 103 are switched on when the mode-flag signal WLBIZA becomes HIGH.
- the clock signal CLK is supplied to the pulse generation circuit 104
- the code signal CODE is supplied to the DFF 105 .
- the pulse generation circuit 104 generates a pulse signal in response to rising edges of the clock signal.
- the pulse signal is supplied to the DFF 105 through 106 via a series of inverters 101 .
- Each of the DFF 105 through 107 latches input data in response to the pulse signal input, and outputs the latched data when the pulse signal input returns to LOW. This makes the code signal CODE shift through the DFF 105 through 107 where the code signal CODE is entered one bit by one bit in a serial fashion at each cycle of the clock signal CLK.
- the code signal CODE is defined such as to start from “1”.
- the code signals “1”, “X”, and “Y” are stored in the DFF 107 , 106 , and 105 , respectively, the output of the DFF 107 that stores “1” therein becomes HIGH.
- the registers 109 and 110 store the data of the DFF 105 and 106 , respectively. That is, the register 109 stores “Y” therein, and the register 110 stores “X” therein.
- the delay circuit 108 delays the HIGH output of the DFF 107 , thereby resetting each DFF at a timing at which storing of the data in the registers 109 and 110 is completed.
- the data stored in the registers 109 and 110 are decoded by the decoder 111 .
- the decoder 111 produces signals TVPR 0 Z and TVPR 1 Z.
- the signals TVPR 0 Z and TVPR 1 Z are not the same as the bit-line clamp voltages VPR 0 and VPR 1 , but are identical to the bit-line clamp voltages VPR 0 and VPR 1 in terms of their signal logic levels.
- FIGS. 4A through 4C are illustrative drawings for explaining code signal inputs to the entry unit.
- the mode-flag signal WLBIZ is set equal to HIGH so as to enter into the WLBI test mode.
- the code signal CODE is entered one bit by one bit in synchronization with the clock signal CLK.
- the very first bit is a FLAG bit, which is followed by a first bit and a second bit.
- FIG. 5 is a table showing settings of the bit-line clamp voltages responsive to the code signal inputs.
- the switches 102 and 103 of the entry unit 100 of FIG. 3 are not switched on. As a result, the WLBI test mode is not selected, so that normal and routine operation will be performed.
- the mode-flag signal WLBIZ becomes HIGH, the device enters into the WLBI test mode.
- bit lines are clamped to certain voltages in accordance with the contents of the code signal CODE.
- FIG. 6 is a circuit diagram showing a circuit generating bit-line clamp voltages.
- a bit-line clamp voltage generation unit 200 of FIG. 6 receives the signals WLBIZA, TVPR 0 Z, and TVPR 1 Z, and generates bit-line clamp voltages VPR 0 and VPR 1 .
- the bit-line clamp voltage generation unit 200 includes NMOS transistors 201 through 206 , PMOS transistors 207 through 210 , NOR circuits 221 and 222 , NAND circuits 223 and 224 , and inverters 231 through 240 .
- the NMOS transistors 205 and 206 and PMOS transistors 209 and 210 together make up a level shifter circuit.
- the mode-flag signal WLBIZA is LOW during the normal operation, so that NMOS transistors 201 and 202 become conductive.
- an incoming precharge voltage VPR is output through the NMOS transistors 201 and 202 without any change.
- bit lines are precharged to the predetermined precharge voltage VPR.
- the NOR circuit 221 receives a HIGH input from the inverter 237 so as to produce a LOW output, thereby making the PMOS transistor 207 nonconductive.
- the PMOS transistor 208 is also nonconductive.
- the NAND circuit 223 receives a LOW signal from the inverter 236 , so that the output of the NAND circuit 223 becomes HIGH, resulting in the NMOS transistor 203 being nonconductive.
- the NMOS transistor 204 is also nonconductive. It is thus confirmed that the predetermined precharge voltage VPR is output without any interference during the normal operation.
- the mode-flag signal WLBIZA is HIGH, so that NMOS transistors 201 and 202 become nonconductive.
- the bit-line clamp voltages VPR 0 and VPR 1 are thus determined by the signals TVPR 0 and TVPR 1 supplied from the entry unit 100 .
- the NOR circuit 221 receives at one input thereof a LOW signal supplied from the inverter 237 , so that the output of the NOR circuit 221 will be an inverse of the input signal to the other input thereof. In this case, therefore, the output of the NOR circuit 221 is equal to the signal TVPR 0 Z.
- the NAND circuit 223 receives at one input thereof a HIGH signal supplied from the inverter 236 , so that the output of the NAND circuit 223 will be an inverse of the signal input to the other input thereof. Namely, the output of the NAND circuit 223 is equal to the signal TVPR 0 Z.
- bit-line clamp voltages VPR 0 and VPR 1 are generated according to the signals TVPR 0 and TVPR 1 supplied from the entry unit 100 .
- FIG. 7 is a circuit diagram showing a control mechanism for clamping bit lines and selecting all word lines.
- FIG. 7 The configuration of FIG. 7 includes the entry unit 100 , the bit-line clamp voltage generation unit 200 , a word-line selection unit 300 , and the sense amplifier units 400 - 0 and 400 - 1 .
- the entry unit 100 is shown in FIG. 3, and the bit-line clamp voltage generation unit 200 is shown in FIG. 6.
- the word-line selection unit 300 includes a main quarter decoder 310 , a main word decoder 320 , a sub quarter decoder 330 , and a sub-word decoder 340 .
- the main quarter decoder 310 includes NMOS transistors 311 through 313 , a latch 314 comprised of two inverters, an NMOS transistor 315 , and an inverter 316 .
- the main word decoder 320 includes NMOS transistors 321 through 323 , a latch 324 comprised of two inverters, an NMOS transistor 325 , and an inverter 326 .
- the sub quarter decoder 330 includes inverters 331 and 332 .
- the sub-word decoder 340 includes a PMOS transistor 341 and NMOS transistors 342 and 343 .
- the NMOS transistors 311 and 312 receive selection signals at the gates thereof. When the selection signals are all HIGH, the main quarter decoder 310 shown in FIG. 7 is selected among a plurality of main quarter decoders of the same type. Likewise, in the main word decoder 320 , the NMOS transistors 321 and 322 receive selection signals at the gates thereof. When the selection signals are all HIGH, the main word decoder 320 shown in FIG. 7 is selected among a plurality of main word decoders of the same kind. Upon selection of the main quarter decoder 310 and the main word decoder 320 , each of these decoders produces a LOW output, so that the word line WL of the sub-word decoder 340 is activated to HIGH.
- the NMOS transistor 313 of the main quarter decoder 310 and the NMOS transistor 323 of the main word decoder 320 become conductive.
- the word line WL is activated to HIGH regardless of whether the main quarter decoder 310 and the main word decoder 320 are selected. Namely, all word lines are activated without exception.
- the clamp voltages VPR 0 and VPR 1 output from the bit-line clamp voltage generation unit 200 are supplied to the sense amplifier units 400 - 0 and 400 - 1 via signal lines 410 and 420 , respectively.
- the sense amplifier unit 400 - 0 when a signal brsx for clamping (precharging) bit lines BL and /BL becomes HIGH, the transistors 401 and 402 are made conductive, resulting in the bit lines BL and /BL being clamped to the clamp voltage VPR 0 .
- bit lines BL and /BL are clamped to the clamp voltage VPR 1 .
- the clamp voltage VPR 0 is supplied to a plurality of sense amplifier units of this type, which are connected to pairs of even-number bit lines in the memory core circuit, and the clamp voltage VPR 1 is supplied to a plurality of sense amplifier units of this time, which are connected to pairs of odd-number bit lines in the memory core circuit.
- FIG. 8 is an illustrative drawing showing a layout of the signal lines 410 and 420 that supply the clamp voltages to the sense amplifier units.
- each line of the sense amplifier units 400 - 0 and each line of the sense amplifier units 400 - 1 are arranged alternately.
- the sense amplifier units 400 - 0 are connected to even-number bit lines
- the sense amplifier units 400 - 1 are connected to odd-number bit lines.
- the signal lines 410 for supplying the clamp voltage VPR 0 is connected to the sense amplifier units 400 - 0
- the signal lines 420 for supplying the clamp voltage VPR 1 is connected to the sense amplifier units 400 - 1 .
- FIG. 9 is an illustrative drawing for explaining a stress applied between storage points.
- Bit lines BL 1 and BL 2 represent adjacent bit lines, and are clamped to the clamp voltages VPR 0 and VPR 1 , respectively, during the WLBI test. Since the word lines WL 1 and WL 2 are both selected during the test, cell transistors T 1 and T 2 become conductive.
- Storage points S 1 and S 2 are joint points between the cell transistors T 1 and T 2 and cells C 1 and C 2 , respectively. Since the cell transistors T 1 and T 2 are both conductive, the storage point S 1 has the clamp voltage VPR 0 applied thereto, and the storage point S 2 has the clamp voltage VPR 1 applied thereto.
Abstract
Description
- 1. Field of the Invention
- The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that allows a proper check while it is on a wafer.
- 2. Description of the Related Art
- WLBI (wafer level burn-in) is a process of stabilizing characteristics of semiconductor devices by exposing them to a high temperature and high voltage environment for a predetermined time period.
- In the WLBI of DRAMs, a high voltage is applied to predetermined circuitry inside the memory chip, and chips are rejected if they have cell transistors with insufficient static charge tolerance. In detail, a mode flag signal indicative of the WLBI test is input to the chip, thereby entering in the WLBI test mode. In the WLBI test mode, bit lines are fixed to the ground level (i.e., the voltage level of the ground-side power supply voltage), and word lines are all selected and placed in the activated state. With the bit lines clamped to the low voltage level, a high gate voltage is applied to all the cell transistors in this manner to place them under stress.
- If the static charge tolerance of cell transistors is insufficient, they will be destroyed during the test. Chips having broken transistors can be easily identified by checking the chips' electric power consumption, thereby rejecting the chips with destroyed transistors.
- The WLBI test as described above can reject chips only if these chips have insufficient static charge tolerance. In reality, insufficient static charge tolerance surfaces as a problem even between adjacent bit lines or adjacent storage points (i.e., joint points between a memory cell and a cell transistor). It is thus desirable to test such static charge tolerance.
- Accordingly, there is a need for a semiconductor memory device that allows testing of various static charge tolerances in the WLBI test.
- It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
- Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor memory device according to the present invention includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.
- In the semiconductor memory device described above, a clamp-voltage generation circuit is provided to supply the first clamp voltage to the first sense amplifier circuits and to supply the second clamp voltage to the second sense amplifier circuits in the test mode. With this configuration, during test operation, the odd-number bit lines are clamped to the first clamp voltage, and the even-number bit lines are clamped to the second clamp voltage. Accordingly, a voltage difference is generated between bit lines to apply a stress, thereby making it possible to test static-charge tolerance between the bit lines.
- Further, selection of all word lines, if so selected, makes it possible to test static-charge tolerance between storage points.
- Moreover, the first and second clamp voltages may be set to voltages varying depending on a code signal supplied from an exterior of the semiconductor memory device. This makes it possible to clamp all the bit lines to LOW, thereby conducting a conventional static-charge tolerance test.
- FIG. 1 is a drawing showing a semiconductor memory device to which the present invention is applied;
- FIG. 2 is a circuit diagram showing a main portion of a core circuit of a twin-storage-type memory;
- FIG. 3 is a block diagram showing an entry unit that receives a mode flag signal;
- FIGS. 4A through 4C are illustrative drawings for explaining code signal inputs to the entry unit;
- FIG. 5 is a table showing settings of bit-line clamp voltages responsive to the code signal inputs;
- FIG. 6 is a circuit diagram showing a circuit generating bit-line clamp voltages;
- FIG. 7 is a circuit diagram showing a control mechanism for clamping bit lines and selecting all word lines;
- FIG. 8 is an illustrative drawing showing a layout of signal lines that supply clamp voltages to sense amplifier units; and
- FIG. 9 is an illustrative drawing for explaining a stress applied between storage points.
- In the following, embodiments of the present invention will be described with reference to the accompanying drawings.
- FIG. 1 is a drawing showing a semiconductor memory device to which the present invention is applied.
- A
semiconductor memory device 10 of FIG. 1 includes a data-control circuitry 11, a read/writeamplifier 12, atiming circuitry 13, anaddress processing circuitry 14, acolumn decoder 15, a main-word decoder 16, and acore circuit 17. - The
core circuit 17 is provided with a plurality of memory cells CELL arranged in a matrix form, and includes circuitry and signal lines for address selection, data amplification, and so on in order to read/write 1-bit data from/in each cell. Thecore circuit 17 shown illustratively in FIG. 1 includes a plurality of sense amplifier units 400-0 and 400-1, a plurality ofsub-word decoder 340, a plurality of word lines WL, a plurality of main word lines MWL, and a plurality of column lines CL. - The data-
control circuitry 11 includes circuitry such as data buffers. The data-control circuitry 11 supplies data to the read/writeamplifier 12 at an appropriate timing as the data is provided from the exterior of the device, and supplies data to the exterior of the device at an appropriate timing as the data is read from thecore circuit 17 and the read/writeamplifier 12. The read/writeamplifier 12 amplifies write data, followed by supplying the data to thecore circuit 17, and, also, amplifies data supplied form thecore circuit 17. - The
timing circuitry 13 is comprised of control-signal buffers, a command decoder, and so on. Thetiming circuitry 13 receives control signals and a clock signal from the exterior of the device, and interprets commands represented by the control signals, thereby controlling operation and operation timings of each unit provided in thesemiconductor memory device 10. - The
address processing circuitry 14 includes address buffers, an address pre-decoder, and so on. Theaddress processing circuitry 14 receives address signals from the exterior of the device, and supplies them to thecolumn decoder 15 and the main-word decoder 16 at appropriate timings. - The
column decoder 15 decodes a column address supplied from theaddress processing circuitry 14, and activates a column line CL corresponding to the specified column address. The main-word decoder 16 decodes a row address supplied from theaddress processing circuitry 14, and activates a main-word line MWL corresponding to the specified row address. In the configuration of Fgi.1, a hierarchical word decode scheme is employed. In this configuration, a plurality of word lines correspond to the main-word line MWL selected by the main-word decoder, and one of these word lines WL is selectively activated by asub-word decoder 340. - In the case of read operation, data is read from cells CELL connected to the activated word line WL, and the sense amplifier unit400-0 or 400-1 amplifies the read data. The amplified data is then read from a sense amplifier unit corresponding to the activated column line CL, and is supplied to the read/write
amplifier 12. In the case of write operation, which is performed in a reversed manner to the read operation, a sense amplifier unit selected by the activated column line CL receives data from the read/writeamplifier 12, and the data of the sense amplifier unit is stored in a cell CELL connected to the activated word line WL. - The semiconductor memory device of FIG. 1 is a twin-storage-type memory, in which a pair of bit lines BL and /BL connected to a sense amplifier unit each have a memory cell CELL connected thereto. One of the pair of memory cells stores given data, and the other stores the inverted data.
- FIG. 2 is a circuit diagram showing a main portion of the
core circuit 17 of the twin-storage-type memory. - The configuration of FIG. 2 includes a
word decoder 20, the sense amplifier units 400-0 and 400-1, bit lines BLn and /BLn (n=1, 2, 3, . . . ), word lines WL0 through WL5, and memory cell units MCxy and /MCxy each comprised of a transistor and a capacitor (x and y indicate a row position and a column position, respectively). Here, theword decoder 20 collectively represents one set of thesub-word decoders 340 shown in FIG. 1. Further, “/” preceding symbols represents logic inversion of the same symbols having no “/”. - As can be seen from FIG. 2, when the word line WL0 is activated, data of the memory cell unit MC00 appears on the bit line BL0, and data of the memory cell unit /MC00 appears on the bit line /BL0. When the memory cell unit MC00 has HIGH data stored therein, the memory cell unit /MC00 has LOW data stored therein. In this case, the potential of the bit line BL0 shifts toward the HIGH potential, and the potential of the bit line /BL0 shifts toward the LOW potential. A resulting potential difference is amplified by the sense amplifier unit 400-0 connected to the bit lines BL0 and /BL0. The data amplified by the sense amplifier unit 400-0 is supplied to a data bus DB and /DB when a column line CL connected to this sense amplifier unit is activated.
- In the twin-storage-type memory, stable data read operation is attainable compared to a conventional DRAM structure in which only one of the pair of bit lines has a memory cell connected thereto. Because of this, a refresh cycle can be elongated, for example, as an advantage.
- A twin-storage-type memory to which the present invention is applied has a configuration in which adjacent bit lines are connected to different sense amplifier units. Namely, for example, the bit line BL1 shown on the top in FIG. 2 is connected to the sense amplifier unit 400-1, and the next bit line BL0 is connected to the sense amplifier unit 400-0, followed by the next bit line /BL1 connected to the sense amplifier unit 400-1. In this manner, the sense amplifier unit 400-0 has even-number bit lines connected thereto, and the sense amplifier unit 400-1 has odd-number bit lines connected thereto.
- Of given two adjacent bit lines, one is connected to the sense amplifier unit400-0, and the other is connected to the sense amplifier unit 400-1. Accordingly, a precharge voltage (i.e., bit-line clamp voltage) VPR0 supplied to the sense amplifier unit 400-0 and a precharge voltage (bit-line clamp voltage) VPR1 supplied to the sense amplifier unit 400-1 may be set to HIGH and LOW, respectively, or vise versa, thereby setting two adjacent bit liens to HIGH and LOW.
- In the present invention, the bit-line clamp voltages VPR0 and VPR1 are set to different voltages in this manner, so that static-charge tolerance tests can be conducted between bit lines during the WLBI test mode.
- In the following, a configuration that supplies different bit-line clamp voltages will be described.
- FIG. 3 is a block diagram showing an entry unit that receives a mode flag signal. The entry unit is part of the command-control related circuitry of the
timing circuitry 13 shown in FIG. 1. - When the WLBI test mode needs to be activated, a mode-flag signal WLBIZ (HIGH) is input to the entry unit from the exterior of the semiconductor memory device. In the specification of the present application, a signal name that ends with “Z” or “z” represents a positive logic signal, and a signal name that ends with “X” or “x” represents a negative logic signal.
- An
entry unit 100 of FIG. 3 includes a plurality ofinverters 101 serving as buffers, switches 102 and 103, apulse generation circuit 104, DFF (delay flip-flops) 105 through 107, adelay circuit 108, aregister 109, aregister 110, and a decoder 111. - The
entry unit 100 receives the mode-flag signal WLBIZ, a clock signal CLK, and a code signal CODE from the exterior of the memory chip. The mode-flag signal WLBIZ is supplied to theswitches inverters 101. Theswitches pulse generation circuit 104, and the code signal CODE is supplied to theDFF 105. - The
pulse generation circuit 104 generates a pulse signal in response to rising edges of the clock signal. The pulse signal is supplied to theDFF 105 through 106 via a series ofinverters 101. Each of theDFF 105 through 107 latches input data in response to the pulse signal input, and outputs the latched data when the pulse signal input returns to LOW. This makes the code signal CODE shift through theDFF 105 through 107 where the code signal CODE is entered one bit by one bit in a serial fashion at each cycle of the clock signal CLK. - The code signal CODE is defined such as to start from “1”. When the code signals “1”, “X”, and “Y” are stored in the
DFF DFF 107 that stores “1” therein becomes HIGH. In response to the HIGH output of theDFF 107, theregisters DFF register 109 stores “Y” therein, and theregister 110 stores “X” therein. Thedelay circuit 108 delays the HIGH output of theDFF 107, thereby resetting each DFF at a timing at which storing of the data in theregisters - The data stored in the
registers - FIGS. 4A through 4C are illustrative drawings for explaining code signal inputs to the entry unit.
- As shown in FIG. 4A, the mode-flag signal WLBIZ is set equal to HIGH so as to enter into the WLBI test mode. Thereafter, as shown in FIGS. 4B and 4C, the code signal CODE is entered one bit by one bit in synchronization with the clock signal CLK. The very first bit is a FLAG bit, which is followed by a first bit and a second bit.
- FIG. 5 is a table showing settings of the bit-line clamp voltages responsive to the code signal inputs.
- As shown in FIG. 5, different combinations of the mode-flag signal WLBIZA and the code signals CODE define different settings of the bit-line clamp voltages.
- If the mode-flag signal WLBIZ is LOW, the
switches entry unit 100 of FIG. 3 are not switched on. As a result, the WLBI test mode is not selected, so that normal and routine operation will be performed. When the mode-flag signal WLBIZ becomes HIGH, the device enters into the WLBI test mode. - Even in the WLBI test mode, if the FLAG bit, the first bit, and the second bit of the code signal CODE are all LOW, no data is stored in the
registers entry unit 100 shown in FIG. 3. This results in a waiting state. - In response to the code signal CODE having the FLAG bit thereof equal to HIGH, bit lines are clamped to certain voltages in accordance with the contents of the code signal CODE.
- Namely, when the first and second bits of the code signal CODE are both LOW, the clamp voltages VPR0 and VPR1 become LOW, so that all the bit lines are clamped to the LOW voltage level. When the first bit and the second bit of the code signal CODE are LOW and HIGH, respectively, the clamp voltages VPR0 and VPR1 become HIGH and LOW, respectively. As a result, even-number bit lines are clamped to the HIGH voltage level, and the odd-number bit lines are clamped to the LOW voltage level. Conversely, when the first bit and the second bit of the code signal CODE are HIGH and LOW, respectively, the clamp voltages VPR0 and VPR1 become LOW and HIGH, respectively. As a result, even-number bit lines are clamped to the LOW voltage level, and the odd-number bit lines are clamped to the HIGH voltage level.
- FIG. 6 is a circuit diagram showing a circuit generating bit-line clamp voltages.
- A bit-line clamp
voltage generation unit 200 of FIG. 6 receives the signals WLBIZA, TVPR0Z, and TVPR1Z, and generates bit-line clamp voltages VPR0 and VPR1. - The bit-line clamp
voltage generation unit 200 includesNMOS transistors 201 through 206,PMOS transistors 207 through 210, NORcircuits NAND circuits inverters 231 through 240. TheNMOS transistors PMOS transistors - At the circuit of FIG. 6, the mode-flag signal WLBIZA is LOW during the normal operation, so that
NMOS transistors NMOS transistors - As this happens, the NOR
circuit 221 receives a HIGH input from theinverter 237 so as to produce a LOW output, thereby making thePMOS transistor 207 nonconductive. By the same token, thePMOS transistor 208 is also nonconductive. Further, theNAND circuit 223 receives a LOW signal from theinverter 236, so that the output of theNAND circuit 223 becomes HIGH, resulting in theNMOS transistor 203 being nonconductive. By the same token, theNMOS transistor 204 is also nonconductive. It is thus confirmed that the predetermined precharge voltage VPR is output without any interference during the normal operation. - In the WLBI test mode, the mode-flag signal WLBIZA is HIGH, so that
NMOS transistors entry unit 100. - Analysis will be given with respect to the signal TVPR0Z. The NOR
circuit 221 receives at one input thereof a LOW signal supplied from theinverter 237, so that the output of the NORcircuit 221 will be an inverse of the input signal to the other input thereof. In this case, therefore, the output of the NORcircuit 221 is equal to the signal TVPR0Z. TheNAND circuit 223 receives at one input thereof a HIGH signal supplied from theinverter 236, so that the output of theNAND circuit 223 will be an inverse of the signal input to the other input thereof. Namely, the output of theNAND circuit 223 is equal to the signal TVPR0Z. When the signal TVPR0Z is HIGH, therefore, thePMOS transistor 207 becomes conductive, and theNMOS transistor 203 becomes nonconductive. As a result, the bit-line clamp voltage VPR0 is HIGH. When the signal TVPR0Z is LOW, thePMOS transistor 207 becomes nonconductive, and theNMOS transistor 203 becomes conductive. In this case, therefore, the bit-line clamp voltage VPR0 is LOW. - The same applies in the case of the signal TVPR1Z. Namely, when the signal TVPR1Z is HIGH, the bit-line clamp voltage VPR1 becomes HIGH. When the signal TVPR1Z is LOW, the bit-line clamp voltage VPR1 becomes LOW.
- In this manner, during the WLBI test mode, the bit-line clamp voltages VPR0 and VPR1 are generated according to the signals TVPR0 and TVPR1 supplied from the
entry unit 100. - FIG. 7 is a circuit diagram showing a control mechanism for clamping bit lines and selecting all word lines.
- The configuration of FIG. 7 includes the
entry unit 100, the bit-line clampvoltage generation unit 200, a word-line selection unit 300, and the sense amplifier units 400-0 and 400-1. Theentry unit 100 is shown in FIG. 3, and the bit-line clampvoltage generation unit 200 is shown in FIG. 6. - The word-
line selection unit 300 includes amain quarter decoder 310, amain word decoder 320, asub quarter decoder 330, and asub-word decoder 340. Themain quarter decoder 310 includesNMOS transistors 311 through 313, alatch 314 comprised of two inverters, anNMOS transistor 315, and aninverter 316. Themain word decoder 320 includesNMOS transistors 321 through 323, a latch 324 comprised of two inverters, anNMOS transistor 325, and an inverter 326. Thesub quarter decoder 330 includesinverters sub-word decoder 340 includes aPMOS transistor 341 andNMOS transistors 342 and 343. - In the
main quarter decoder 310, theNMOS transistors 311 and 312 receive selection signals at the gates thereof. When the selection signals are all HIGH, themain quarter decoder 310 shown in FIG. 7 is selected among a plurality of main quarter decoders of the same type. Likewise, in themain word decoder 320, theNMOS transistors main word decoder 320 shown in FIG. 7 is selected among a plurality of main word decoders of the same kind. Upon selection of themain quarter decoder 310 and themain word decoder 320, each of these decoders produces a LOW output, so that the word line WL of thesub-word decoder 340 is activated to HIGH. - In the WLBI test mode, i.e., when the mode-flag signal WLBIZA output from the
entry unit 100 is HIGH, theNMOS transistor 313 of themain quarter decoder 310 and theNMOS transistor 323 of themain word decoder 320 become conductive. As a result, the word line WL is activated to HIGH regardless of whether themain quarter decoder 310 and themain word decoder 320 are selected. Namely, all word lines are activated without exception. - The clamp voltages VPR0 and VPR1 output from the bit-line clamp
voltage generation unit 200 are supplied to the sense amplifier units 400-0 and 400-1 viasignal lines transistors - Although not shown in FIG. 7, the clamp voltage VPR0 is supplied to a plurality of sense amplifier units of this type, which are connected to pairs of even-number bit lines in the memory core circuit, and the clamp voltage VPR1 is supplied to a plurality of sense amplifier units of this time, which are connected to pairs of odd-number bit lines in the memory core circuit.
- FIG. 8 is an illustrative drawing showing a layout of the
signal lines - As shown in FIG. 8, each line of the sense amplifier units400-0 and each line of the sense amplifier units 400-1 are arranged alternately. The sense amplifier units 400-0 are connected to even-number bit lines, and the sense amplifier units 400-1 are connected to odd-number bit lines. Here, it is not important which one is connected to even-number bit lines and which one is connected to odd-number bit lines. What is important is that they are connected to bit lines alternately.
- The signal lines410 for supplying the clamp voltage VPR0 is connected to the sense amplifier units 400-0, and the
signal lines 420 for supplying the clamp voltage VPR1 is connected to the sense amplifier units 400-1. - Accordingly, even-number lines of the bit lines BL and /BL are clamped to the clamp voltage VPR0, and odd-number lines thereof are clamped to the clamp voltage VPR1. Namely, they are clamped to the clamp voltages VPR0 and VPR1 alternately in terms of special arrangement.
- In the WLBI test of the present invention, as previously described, different combinations of the clamp voltages VPR0 and VPR1 can be selected. That is, there are three different combinations, the first one with the clamp voltages VPR0 and VPR1 being both LOW, the second one with the clamp voltage VPR0 being HIGH and the clamp voltage VPR1 being LOW, and the third one with the clamp voltage VPR0 being LOW and the clamp voltage VPR1 being HIGH. This makes it possible to apply a stress between adjacent bit lines, thereby testing static-charge tolerance between the bit lines. It is also possible to conduct the conventional WLBI test that sets all the bit lines to LOW.
- FIG. 9 is an illustrative drawing for explaining a stress applied between storage points.
- Bit lines BL1 and BL2 represent adjacent bit lines, and are clamped to the clamp voltages VPR0 and VPR1, respectively, during the WLBI test. Since the word lines WL1 and WL2 are both selected during the test, cell transistors T1 and T2 become conductive. Storage points S1 and S2 are joint points between the cell transistors T1 and T2 and cells C1 and C2, respectively. Since the cell transistors T1 and T2 are both conductive, the storage point S1 has the clamp voltage VPR0 applied thereto, and the storage point S2 has the clamp voltage VPR1 applied thereto.
- As a result, a stress is applied between the adjacent storage points corresponding to the adjacent bit lines. This makes it possible to conduct a static-charge tolerance test between storage points as well as between bit lines.
- Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
- The present application is based on Japanese priority application No. 2000-047803 filed on Feb. 24, 2000, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
Claims (10)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2000-047803 | 2000-02-24 | ||
JP12-047803 | 2000-02-24 | ||
JP2000047803A JP2001243794A (en) | 2000-02-24 | 2000-02-24 | Semiconductor memory |
Publications (2)
Publication Number | Publication Date |
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US20010017807A1 true US20010017807A1 (en) | 2001-08-30 |
US6373764B2 US6373764B2 (en) | 2002-04-16 |
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Application Number | Title | Priority Date | Filing Date |
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US09/790,573 Expired - Lifetime US6373764B2 (en) | 2000-02-24 | 2001-02-23 | Semiconductor memory device allowing static-charge tolerance test between bit lines |
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US (1) | US6373764B2 (en) |
JP (1) | JP2001243794A (en) |
KR (1) | KR100639637B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040124440A1 (en) * | 2002-11-08 | 2004-07-01 | Riichiro Takemura | Semiconductor device |
US20050179349A1 (en) * | 2002-02-14 | 2005-08-18 | Penco Products, Inc. | Electronically-controlled locker system |
US8986283B2 (en) | 2011-05-18 | 2015-03-24 | Solo-Dex, Llc | Continuous anesthesia nerve conduction apparatus, system and method thereof |
US9668654B2 (en) | 2011-05-18 | 2017-06-06 | Sundar Rajendran | Ultrasound monitored continuous anesthesia nerve conduction apparatus and method by bolus injection |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004164765A (en) | 2002-11-14 | 2004-06-10 | Renesas Technology Corp | Semiconductor memory circuit |
KR100464937B1 (en) * | 2003-04-29 | 2005-01-06 | 주식회사 하이닉스반도체 | Test mode flag signal generator of semiconductor memory |
US6992939B2 (en) * | 2004-01-26 | 2006-01-31 | Micron Technology, Inc. | Method and apparatus for identifying short circuits in an integrated circuit device |
US7471588B2 (en) | 2006-05-05 | 2008-12-30 | Altera Corporation | Dual port random-access-memory circuitry |
US7602217B2 (en) * | 2007-08-16 | 2009-10-13 | Globalfoundries Inc. | Level shifter circuit with pre-charge/pre-discharge |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6262928B1 (en) * | 2000-09-13 | 2001-07-17 | Silicon Access Networks, Inc. | Parallel test circuit and method for wide input/output DRAM |
-
2000
- 2000-02-24 JP JP2000047803A patent/JP2001243794A/en active Pending
-
2001
- 2001-02-22 KR KR1020010008930A patent/KR100639637B1/en not_active IP Right Cessation
- 2001-02-23 US US09/790,573 patent/US6373764B2/en not_active Expired - Lifetime
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050179349A1 (en) * | 2002-02-14 | 2005-08-18 | Penco Products, Inc. | Electronically-controlled locker system |
US20040124440A1 (en) * | 2002-11-08 | 2004-07-01 | Riichiro Takemura | Semiconductor device |
US8986283B2 (en) | 2011-05-18 | 2015-03-24 | Solo-Dex, Llc | Continuous anesthesia nerve conduction apparatus, system and method thereof |
US9668654B2 (en) | 2011-05-18 | 2017-06-06 | Sundar Rajendran | Ultrasound monitored continuous anesthesia nerve conduction apparatus and method by bolus injection |
US10238830B2 (en) | 2011-05-18 | 2019-03-26 | Solodex Llc | Continuous anesthesia nerve conduction apparatus, system and method thereof |
US10315003B2 (en) | 2011-05-18 | 2019-06-11 | Solodex Llc | Continuous anesthesia nerve conduction apparatus, system and method thereof |
Also Published As
Publication number | Publication date |
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JP2001243794A (en) | 2001-09-07 |
KR100639637B1 (en) | 2006-10-31 |
KR20010085471A (en) | 2001-09-07 |
US6373764B2 (en) | 2002-04-16 |
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