US20010017416A1 - Device having metal interconnects with reduced or eliminated metal recess in vias - Google Patents
Device having metal interconnects with reduced or eliminated metal recess in vias Download PDFInfo
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- US20010017416A1 US20010017416A1 US09/850,654 US85065401A US2001017416A1 US 20010017416 A1 US20010017416 A1 US 20010017416A1 US 85065401 A US85065401 A US 85065401A US 2001017416 A1 US2001017416 A1 US 2001017416A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Abstract
A semiconductor device having metal interconnects provides for a reduction of the recessing of metal in vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The device includes a via in a device layer of the semiconductor device, a barrier layer formed over the device layer, and a metal layer formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.
Description
- This is a divisional of Ser. No. 09/035,735, filed on Mar. 5, 1998, (VLSI.089PA) to which Applicant claims priority under 35 U.S.C.§120.
- The present invention is, in general, directed to a semiconductor device having overlapping interconnects, in which the production of recesses in the interconnects is prevented or reduced.
- Over the last few decades, the electronics industry has developed semiconductor technology to fabricate small, highly integrated electronic devices. Many semiconductor devices are now formed by vertical stacking of device layers, including multiple layers of conductive lines with interconnects between layers. As these devices become smaller, there is a need for increasingly narrow conductive lines and interconnects to form circuit pathways within these devices. These conductive lines and interconnects are typically formed using metals, including, for example, aluminum, tungsten, and copper.
- In a multilevel architecture, layers of metal conductive lines which define circuit pathways are separated from each other by interlevel dielectrics. In a typical process scheme, a first metal layer is deposited and patterned to form a first set of conductive lines. This is followed by deposition of a dielectric layer over the first set of conductive lines. Vias are etched through the dielectric layer to the underlying conductive lines and then filled with metal to establish interlayer conduction. In conventional processing methods, the metal which fills the vias typically extends beyond the via when deposited. This excess metal is removed by, for example, chemical-mechanical polishing or etch back. A second metal layer may then be formed over the dielectric layer and patterned into a second set conductive lines.
- With current aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. This typically leaves at least a portion of the vias exposed during the etch process in which second set of conductive lines are patterned. A recess in the exposed portion of the vias may be formed during this process. For example, if an aluminum conductive line is formed over the via and the aluminum conductive line does not completely overlap the underlying via, then there is a possibility that a portion of the via may be etched during the formation of the conductive lines, which typically includes one or more metal etching steps.
- Tungsten is used to fill the vias in order to reduce the amount of recessing during subsequent processing steps. Tungsten-filled vias provide adequate selectivity during metal etching steps. However, the presence of tungsten in the path of current flow may lead to flux divergence in the metal lines at the tungsten/metal interfaces resulting in the degradation of the electromigration resistance.
- To address this issue, aluminum and aluminum alloys have been suggested for incorporation in the vias. In addition to reducing via resistance, aluminum vias may also show better electromigration resistance. The use of aluminum in vias is expected to become more important as the device dimensions become smaller. Conventional techniques include filling the vias with tungsten or aluminum, polishing or etching back the tungsten or aluminum to remove excess deposits outside of the via, and then depositing a second metal layer for making the conductive lines.
- When aluminum is incorporated in the vias, a conventional metal etch technique cannot be used to form the conductive lines, which are also typically aluminum, because the aluminum in the vias may be exposed to metal etchants which may create recessing in the vias. This recessing can lead to electromigration failure. Furthermore, recesses in the vias may trap chemicals or gases during subsequent processing steps. These chemicals and gases may lead to device degradation over time. In addition, the effective thinning of the via due to the presence of the recess increases the current density through that portion of the via which may lead to local overheating and electromigration. Thus, there is a need for an improved method for forming vias and conductive lines in a semiconductor device to prevent the formation of recesses in non-overlapping portions of the via during processing.
- Generally, the present invention relates to a semiconductor device having metal interconnects, where the recessing of metal in the vias is reduced or eliminated, particularly when the vias are formed using aluminum or an aluminum alloy. One example is directed to a semiconductor device having a device layer and a via in the device layer. Metallic material is disposed in the via. A conductive structure is formed over the via and in contact with the metallic material. The conductive structure has a sidewall extending form the device layer. During processing the metallic material in the via is protected by a spacer formed on the sidewall of the conductive structure during the removal of a portion of a conducting barrier adjacent the via and over the device layer.
- The above summary of the present invention is not intended to describe each disclosed embodiment or every implementation of the present invention. The Figures and the detailed description which follow more particularly exemplify these embodiments.
- The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
- FIGS.1A-1H illustrate, in cross-section, an exemplary fabrication process according to one example embodiment of the invention;
- FIG. 2 is a cross-section of another example embodiment of the structure illustrated in FIG. 1A; and
- FIG. 3 is a cross-section of another example embodiment of the process step illustrated in FIG. 1F.
- While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
- The present invention is believed to be applicable to a number of semiconductor devices having metal interconnect structures. While the present invention may not be so limited, an appreciation of various aspects of the invention will be gained through discussion of an exemplary fabrication process in connection with the examples provided below.
- FIGS.1A-1H illustrate an exemplary process for forming metal interconnects. The process begins by forming at least one via 102 in a
device layer 104 of asemiconductor device 100. Typically, thedevice layer 104 is made from a dielectric material. Examples of dielectric materials include silicon dioxide, silicon oxynitride, silicon oxyfluoride, silicon nitride, other oxides and nitrides, amorphous carbon, spin-on glasses (e.g., silicates, siloxanes, hydrogen silsesquioxane, and alkyl silsesquioxanes), polymers (e.g., polyimides and fluoropolymers), and other non-conductive materials. The device layer may, however, be any other layer of a semiconductor device through which avia 102 is formed. - The
vias 102 may be formed by a variety of techniques. Examples of a suitable techniques include etching processes, such as, for example, wet etching, dry etching and plasma etching. Plasma etching techniques are particularly useful because of their anisotropic behavior. These techniques are well known for formingvias 102 or other trench-like structures in asemiconductor device 100. One example of such a technique includes applying a photoresist over the device layer and patterning the photoresist according to the desired via pattern. Material from thedevice layer 104 may then be removed by, for example, an etching process, such as an anisotropic plasma etch, to form thevias 102. The particular etchant that is used typically depends on the material of thedevice layer 104 and the etching process. - Often, a conductive layer (not shown) is formed prior to the
device layer 104. Thevias 102 typically connect conductive lines (not shown) of this underlying conductive layer to conductive lines in ametal layer 108 formed over thedielectric layer 104, as described below. Thus, thevias 102 typically extend through thedevice layer 104 to the underlying conductive lines. -
Typical vias 102 have a diameter of, for example, 0.3 to 2.5 μm, however, vias of other sizes may also be used. The vias also typically have a cylindrical or rectangular cross-section, however, other cross-sections, including, for example, square, or ovoid, may also be used. The length of the vias varies depending on the thickness of thedevice layer 104 and the height of the underlying conductive lines. In some case, this length may be, for example, 0.3 to 5 μm. However, vias that are longer or shorter may also be used. - After formation of the
vias 102, abarrier layer 106 may be formed over the surface of thedevice layer 104, as well as over the sidewalls and on the bottom surface of thevias 102. Thebarrier layer 106 typically protects the device layer from interaction with a subsequently depositedmetal layer 108. Such interaction may include, for example, chemical reactions between thedevice layer 104 and themetal layer 108, as well as diffusion of metal atoms from themetal layer 108 into thedevice layer 104. In addition, by providing a more easily wetted surface for themetal layer 108, the use of thebarrier layer 106 may improve the filling of thevias 102 by asubsequent metal layer 108, the adhesion between thedevice layer 104 and the subsequently formedmetal layer 108, and/or the grain structure of themetal layer 108. - A variety of materials may be used to form the
barrier layer 106. For example, titanium, titanium nitride (TiN), tantalum, tantalum nitride, tungsten nitride, or combinations thereof are common materials for use in forming thebarrier layer 106. Other materials which are compatible with thedevice layer 104 andmetal layer 108 may also be used. Thebarrier layer 106 is often formed using a material which is conductive; although typically the material of thebarrier layer 106 is not as conductive as the material of themetal layer 108. If thebarrier layer 106 is conductive then current can also be carried by thebarrier layer 106 if themetal layer 108 formed in thevias 102 acting as conductive lines should fail. - The thickness of the
barrier layer 106 may vary over a wide range. Typical values for the thickness of thebarrier layer 106 range from 50 to 1000 angstroms. - One alternative to this structure is illustrated in FIG. 2. In this embodiment, the via202 is formed in the
device layer 204 subsequent to the formation of thebarrier layer 206 over thedevice layer 204. Therefore, in this case, thebarrier layer 206 is not formed along the sidewalls or the bottom surface of thevia 202. Subsequent processing for this structure is similar to that for the structure depicted in FIG. 1A. - In another alternative embodiment, one or more additional layers may be formed between the barrier layer and the device layer. Such layers may include, for example, passivation layers or layers which provide structural support for the subsequently deposited layers.
- Returning to FIG. 1A, a
metal layer 108 is formed over thebarrier layer 106. Themetal layer 108 also fills the via 102 to form a viastructure 109. Themetal layer 108 formed over thebarrier layer 106 and within the via 102 may be formed in a single step. Alternatively, the via 102 may first be filled with a metal material and then, using the same or different formation conditions (e.g., deposition rate or temperature), themetal layer 108 may be formed over thebarrier layer 106. - The
metal layer 108 may be formed using a variety of materials. Examples of suitable materials for themetal layer 108 include metals and alloys, such as, for example, aluminum, copper, tungsten, or aluminum/copper alloys. Other conductive metals and alloys may also be used. - The
metal layer 108 may be formed using a variety of techniques. Examples of suitable techniques include cold or hot physical vapor deposition (PVD), sequential CVD/PVD, low pressure PVD, and PVD followed by high pressure and/or high temperature reflow to fill thevias 102. Themetal layer 108 has a thickness of, for example, 2000 to 10,000 angstroms above thedevice layer 104 andbarrier layer 106. The thickness of themetal layer 108 over the vias will be correspondingly larger. - One advantage to this process is that the metal which fills the vias and the metal which forms the conductive lines above the vias may be sequentially deposited without an intervening polishing or etch-back step. This may reduce the number of process steps needed to form the desired structure. Conventional methods typically require that the metal for the vias and the metal for the conductive lines over the vias be deposited in different steps with an intervening polish or etch-back step.
- An anti-reflective coating (ARC)
layer 110 is formed over themetal layer 108 to reduce the reflection of light during a subsequent photolithographic patterning process, described below. Metals, such as aluminum, tungsten, and copper, typically have a relatively high reflectivity. Therefore, it is often necessary to provide an ARC layer with reduced reflectivity, otherwise the patterned features may be excessively broadened or narrowed. For example, in the absence of theARC layer 110, “reflective notching” occurs when the topography of the underlying surface (e.g., a slope in the topography) causes the reflection of light at angles which are not perpendicular to the surface of the photoresist. TheARC layer 110 may also protect themetal layer 108 during subsequent processing steps, as well as provide a barrier between themetal layer 108 and subsequently deposited layers, such as a dielectric layer. In addition, the ARC layer may enhance adhesion of subsequently deposited dielectric layers. - Materials suitable for the
ARC layer 110 typically have low reflectivity of light for the wavelength or wavelength range that will be used to form the pattern. Therefore, the particular materials useful for forming theARC layer 110 depend on the size of the features and the design rules. For current 0.25 μm design rules, titanium nitride is a useful material for theARC layer 110. Other suitable materials for theARC layer 110 include, for example, silicon oxynitride, silicon nitride, silicon dioxide, and organic ARC materials. Although the ARC material may be non-conductive, it is often desirable to use a conductive ARC. Otherwise, the ARC material will likely need to be removed to allow connection between the conductive structures 114 (see FIG. 1C) formed from themetal layer 108 and subsequently formed interconnects or contacts. - The thickness of the
ARC layer 110 is about 200 to 3000 angstroms. Often, theARC layer 110 has an increased thickness (an additional 50 to 1000 angstroms) relative to a similar ARC layer used in conventional techniques because later processing steps typically remove portions of theARC layer 110, as described below. - In some embodiments, an
ARC layer 110 is not formed, particularly if the size of the device features is not critical or if the reflectivity of themetal layer 108 is otherwise controlled. In these embodiments, the thickness of themetal layer 108 may be increased by 50 to 1000 angstroms because subsequent processing steps may remove additional portions of themetal layer 108. - After the formation of the
ARC layer 110, aphotoresist layer 112 is formed over the ARC layer 110 (ormetal layer 108, if an ARC layer is not used). Thephotoresist layer 112 is patterned, as shown in FIG. 1A, according to a desired conductive line or via pattern using, for example, photolithographic techniques. Once patterned, a portion of thephotoresist layer 112 is removed according to the pattern. - After the
photoresist layer 112 has been patterned, a portion of themetal layer 108 andARC layer 110 may be removed according to the pattern, as shown in FIG. 1B. The removal of the portion of themetal layer 108 and theARC layer 110 may be accomplished by a variety of techniques, including, for example, wet etching, dry etching, and plasma etching. It may be desirable to use an anisotropic etching technique, such as dry plasma etching, to leave relatively straight sidewalls. Typically, the removal of the portions of themetal layer 108 andARC layer 110 continues until thebarrier layer 106 is exposed, as shown in FIG. 1B. In some embodiments, the removal process continues until all or nearly all of thebarrier layer 106 between the remainingportions 114 of themetal layer 108 andARC layer 110 is exposed. In these embodiments, thebarrier layer 106 may be treated as an etch stop so that an end of the removal process is indicated when a threshold amount of the material of thebarrier layer 106 is detected. - The
photoresist layer 112 is subsequently removed, as shown in FIG. 1C. Removal of thephotoresist layer 112 may be accomplished by a variety of techniques including, for example, selective etching or ashing (particularly if the photoresist layer is made using an organic photoresist). The remaining portions of themetal layer 108 and theARC layer 110 formconductive structures 114 which may be used as conductive lines or vias. If an anisotropic etching technique is used to remove the portion of themetal layer 108 and theARC layer 110, then the sidewalls of theconductive structures 114 may be covered by a protective layer formed during the etching process. This protective layer may include polymers formed by the etchant material. The protective layer can often be removed during an ashing process or by a solvent strip process. - The
conductive structures 114 may or may not be aligned with the underlying viastructures 109, as illustrated in FIG. 1C. It is the non-overlapping portions of the viastructures 109 which are particularly susceptible to recess formation during subsequent processing in conventional fabrication processes. - To reduce or eliminate recess formation, a
spacer material 116 is subsequently deposited over thedevice layer 104,barrier layer 106, andconductive structures 114, as shown in FIG. 1D. Thespacer material 116 is typically formed as a conformal layer over the underlying structures. Thespacer material 116 may be formed by a variety of techniques including chemical vapor deposition (CVD), physical vapor deposition, or spin-on techniques. In particular, CVD is a commonly used method for forming a conformal layer over a surface having structure. Thespacer material 116 may be made using a variety of materials. Oxides and nitrides, such as silicon oxide, silicon nitride, and silicon oxynitride, are often used asspacer materials 116. Photoresist compounds may also be aconvenient spacer material 116 as these compound can be easily formed on the structures by a CVD process and easily removed by techniques, such as ashing. - Typically, the
spacer material 116 is formed to a thickness which is at least as large as the expected maximum width of an exposed portion of the via structure 109 (i.e., the portion of the viastructure 109 which does not overlap with the conductive structures 114). This maximum width may be, for example, 0.5 μm or less. Therefore, thespacer material 116 has a thickness of, for example, 0.1 μm to 0.8 μm, although larger or smaller thicknesses may also be used. An extra thickness of thespacer material 116 may be provided to compensate for the removal of portions of thespacer material 116 during the formation of one ormore spacers 118, as described below and depicted in FIG. 1E. However, the thickness of the spacer is generally limited by the minimum spacing between conductive lines. - A portion of the
spacer material 116 is then removed to expose the portions of thebarrier layer 106 between theconductive structures 114 according to the pattern and to formspacers 118 along the sidewall of theconductive structures 114 that extends from thebarrier layer 106. Thespacers 118 protect the sidewall of theconductive structures 114 and the exposed portions of the viastructures 109 during subsequent processing. The formation of thespacers 118 from thespacer material 116 may be accomplished by a variety of techniques including, for example, wet etching, dry etching, or plasma etching. In some embodiments, an etchant selective to thebarrier layer 106 and/ordevice layer 104 is used. Moreover, in some embodiments, anisotropic etching methods are used to reduce etching of thespacer material 116 along the sidewalls of theconductive structures 114. - After formation of the
spacers 118, a portion of thebarrier layer 106, which is between or adjacent to theconductive structures 114 and not covered by thespacers 118, is removed, as shown in FIG. 1F. This electrically isolates theconductive structures 114, except at desired connecting points according to the pattern. The removal of these portions of thebarrier layer 106 may be accomplished by a variety of techniques including wet etching, dry etching, or plasma etching. These techniques may use selective etchants to remove the material of thebarrier layer 106. In some embodiments, thebarrier layer 106 is overetched to aid in isolating theconductive structures 114 from each other (unless a connection is desired). - Often this process also removes a portion of the
ARC layer 110, especially if theARC layer 110 and thebarrier layer 106 are made of the same material, such as titanium nitride. It may be desirable that at least a portion of theARC layer 110 remains to protect themetal layer 108 during subsequent processing steps as well as to enhance adhesion between themetal layer 108 and subsequently deposited layers. Therefore, the thickness of theARC layer 110 may be large enough that at least a portion of theARC layer 110 remains after the removal of thebarrier layer 106 from between theconductive structures 114. In these embodiments, the thickness of the ARC layer prior to the removal step is, for example, 300 to 5000 angstroms. The thickness of the ARC layer after this removal step is, for example, 200 to 3000 angstroms. - In some embodiments, illustrated in FIG. 3, the removal of the
barrier layer 306 is allowed to proceed so that those portions of thebarrier layer 306 beneath thespacer structures 318 are also removed. A portion of the conductive structure which extends beyond thedevice layer 304 and adjacent to the conductive structures 314 (formed from themetal layer 308 and ARC layer 310) may also be removed in this procedure, as depicted by the opening above theARC layer 310 in FIG. 3. - Returning to FIGS.1A-1H, the
spacers 118 are subsequently removed, as shown in FIG. 1G. The removal of the spacer structures may be accomplished by a variety of techniques including, for example, selective etching and/or ashing. If thespacers 118 are made using an oxide or nitride material, then the spacers are typically removed using a selective etching process. If thespacers 118 are made using a photoresist material then thespacers 118 may be removed by ashing because many photoresist materials are organic compounds. - Removal of the
spacers 118 may leave aportion 107 of thebarrier layer 106 exposed, as shown in FIG. 1G. Thisportion 107 was protected from removal by thespacers 118. Optionally, thisportion 107 of thebarrier layer 106 may be removed by, for example, a timed etching process in which thesemiconductor device 100 is exposed to an etchant for a period of time sufficient to remove some or all of theportion 107, as depicted in FIG. 1H. In some embodiments, this etchant is selective to the material of thedevice layer 104 or etches the material of thebarrier layer 106 at a faster rate than the material of thedevice layer 104. - A portion105 (see FIG. 1G) of the via
structure 109 which extends above the device layer may be optionally removed during the same or a different timed etching process, as shown in FIG. 1H. In this embodiment, the etchant may etch themetal layer 108 andbarrier layer 106 at similar rates. - The via
structures 109 obtained as a result of the above-described process are formed in such a way as to avoid or reduce the appearance of recesses within the via structure. Accordingly, the present invention is applicable to semiconductor devices which have metal interconnects. The present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art to which the present invention is directed upon review of the instant specification. The claims are intended to cover such modifications and devices.
Claims (12)
1. A semiconductor device having a device layer, the semiconductor device comprising:
a via in the device layer of the semiconductor device;
a barrier layer over the device layer and over the barrier layer and in the via;
metallic material disposed in the via;
a conductive structure formed over the device layer and in contact with the metallic material, the conductive structure having a sidewall extending from a surface of the barrier layer;
a spacer on the sidewall of the conductive structure; and
wherein the metallic material in the via is protected by a spacer on the sidewall of the conductive structure during a removal of a portion of a conducting barrier adjacent to the via and over the device layer.
2. The semiconductor device of , wherein the barrier layer extends above and laterally beyond the via.
claim 1
3. The semiconductor device of , wherein the metal layer is adapted and configured as a single metal layer that is characterized as contiguously formed in a single deposition step.
claim 2
4. The semiconductor device of , wherein the via has a sidewall and a bottom surface and the barrier layer is over the device layer and on the sidewall and the bottom surface of the via.
claim 1
5. The semiconductor device of , wherein the barrier layer comprises a conductive material.
claim 1
6. The semiconductor device of , wherein the device layer comprises a dielectric material.
claim 1
7. The semiconductor device of , wherein the metal layer comprises a metallic material, the metallic material being at least one of aluminum, copper, tungsten, or alloys thereof.
claim 1
8. The semiconductor device of , wherein the metal layer comprises an aluminum alloy.
claim 7
9. The semiconductor device of , wherein the aluminum alloy comprises an aluminum/copper alloy.
claim 8
10. The semiconductor device of , further comprising forming an anti-reflective coating layer over the metal layer.
claim 1
11. The semiconductor device of , wherein the anti-reflective coating layer comprises a conductive material.
claim 10
12. The semiconductor device of , wherein the conductive structure is formed directly over the via structure.
claim 1
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/850,654 US20010017416A1 (en) | 1998-03-05 | 2001-05-07 | Device having metal interconnects with reduced or eliminated metal recess in vias |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/035,735 US6228757B1 (en) | 1998-03-05 | 1998-03-05 | Process for forming metal interconnects with reduced or eliminated metal recess in vias |
US09/850,654 US20010017416A1 (en) | 1998-03-05 | 2001-05-07 | Device having metal interconnects with reduced or eliminated metal recess in vias |
Related Parent Applications (1)
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US09/035,735 Division US6228757B1 (en) | 1998-03-05 | 1998-03-05 | Process for forming metal interconnects with reduced or eliminated metal recess in vias |
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US20010017416A1 true US20010017416A1 (en) | 2001-08-30 |
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US09/035,735 Expired - Lifetime US6228757B1 (en) | 1998-03-05 | 1998-03-05 | Process for forming metal interconnects with reduced or eliminated metal recess in vias |
US09/850,654 Abandoned US20010017416A1 (en) | 1998-03-05 | 2001-05-07 | Device having metal interconnects with reduced or eliminated metal recess in vias |
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Application Number | Title | Priority Date | Filing Date |
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US09/035,735 Expired - Lifetime US6228757B1 (en) | 1998-03-05 | 1998-03-05 | Process for forming metal interconnects with reduced or eliminated metal recess in vias |
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US (2) | US6228757B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050250314A1 (en) * | 2004-05-10 | 2005-11-10 | Park Chang-Soo | Method for fabricating metal interconnection line with use of barrier metal layer formed in low temperature |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000133710A (en) * | 1998-10-26 | 2000-05-12 | Tokyo Electron Ltd | Semiconductor device and its manufacture |
KR100382730B1 (en) * | 2000-12-14 | 2003-05-09 | 삼성전자주식회사 | Metal contact structure in semiconductor device and forming method thereof |
US6440809B1 (en) * | 2001-03-13 | 2002-08-27 | United Microelectronics Corp. | Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide |
US6815337B1 (en) * | 2004-02-17 | 2004-11-09 | Episil Technologies, Inc. | Method to improve borderless metal line process window for sub-micron designs |
US7833692B2 (en) * | 2007-03-12 | 2010-11-16 | Brewer Science Inc. | Amine-arresting additives for materials used in photolithographic processes |
KR100861644B1 (en) * | 2007-12-27 | 2008-10-07 | 주식회사 동부하이텍 | Image sensor and method for manufacturing the same |
KR20130007378A (en) * | 2011-07-01 | 2013-01-18 | 삼성전자주식회사 | Semiconductor device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH04359518A (en) * | 1991-06-06 | 1992-12-11 | Nec Corp | Manufacture of semiconductor device |
US5656543A (en) * | 1995-02-03 | 1997-08-12 | National Semiconductor Corporation | Fabrication of integrated circuits with borderless vias |
JPH104092A (en) * | 1996-06-14 | 1998-01-06 | Nec Corp | Method of fabricating semiconductor device |
-
1998
- 1998-03-05 US US09/035,735 patent/US6228757B1/en not_active Expired - Lifetime
-
2001
- 2001-05-07 US US09/850,654 patent/US20010017416A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050250314A1 (en) * | 2004-05-10 | 2005-11-10 | Park Chang-Soo | Method for fabricating metal interconnection line with use of barrier metal layer formed in low temperature |
US7375024B2 (en) * | 2004-05-10 | 2008-05-20 | Hynix Semiconductor Inc. | Method for fabricating metal interconnection line with use of barrier metal layer formed in low temperature |
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US6228757B1 (en) | 2001-05-08 |
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