US20010015012A1 - Structure of conductive bump in wiring board - Google Patents
Structure of conductive bump in wiring board Download PDFInfo
- Publication number
- US20010015012A1 US20010015012A1 US09/079,857 US7985798A US2001015012A1 US 20010015012 A1 US20010015012 A1 US 20010015012A1 US 7985798 A US7985798 A US 7985798A US 2001015012 A1 US2001015012 A1 US 2001015012A1
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- Prior art keywords
- bump
- conductive
- insulating base
- wiring board
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/51—Fixed connections for rigid printed circuits or like structures
- H01R12/55—Fixed connections for rigid printed circuits or like structures characterised by the terminals
- H01R12/57—Fixed connections for rigid printed circuits or like structures characterised by the terminals surface mounting terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0382—Continuously deformed conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
- H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
Definitions
- This invention relates to a structure of a wiring board used for contact or connection with a given electronic part such as an IC or the like, and more particularly to a conductive bump in a wiring board to be subjected to the above contact or connection.
- connection refers to an electrical connection disconnectably joined through solder or the like.
- the conductive bump is formed on the lead forming the wiring pattern of one of the wiring boards and contacted with or connected to a terminal formed on an end of the lead of the other wiring board.
- a structure of a conductive bump in a wiring board having a wiring pattern on a surface of an insulating base characterized in that a local portion of the insulating base is raised from the surface of the insulating base to form a projection and a surface of the projection is covered with a part of a lead forming the wiring pattern to form a conductive bump.
- a structure of a conductive bump in a wiring board characterized in that a bump is formed by a part of a lead forming the wiring pattern and a cavity is formed in the bump.
- FIG. 1 is a perspective view of a wiring board according to the present invention with a given electronic part such as an IC loaded thereon;
- FIG. 2A is a sectional view of the wiring board of FIG. 1, showing a structure of a bump in which a conductive bump is backed up with an insulating projection
- FIG. 2B is a sectional view of FIG. 2A, showing a structure of a bump in which the conductive bump is backed up by a cavity
- FIG. 3A is an enlarged sectional view of FIG. 2A and FIG. 3B is an enlarged sectional view of FIG. 2B;
- FIGS. 4A to 4 E are sectional views showing the first example of a method of manufacturing a wiring board having the structure of a bump of FIG. 2A in the sequential order of processes;
- FIGS. 5A to 5 E are sectional views showing the second example of a method of manufacturing a wiring board having the structure of a bump of FIG. 2A in the sequential order of processes;
- FIGS. 6A and 6B are sectional views showing the third example of a process of manufacturing a wiring board having a structure of a bump of FIG. 2A;
- FIG. 7A is a sectional view of a wiring board showing a structure of a bump in which the conductive bump is of a hollow structure and backed up by the cavity and FIG. 7B is a plan view of FIG. 7A;
- FIGS. 8A to 8 E are sectional views showing one example of a method of manufacturing a wiring board of FIG. 7 in the sequential order of processes;
- FIG. 9 is an enlarged sectional view of a bump portion, showing an example in which the conductive bump is made of hard metal;
- FIG. 10 is a sectional view showing a tool for forming the conductive bump forming recesses in the transfer plate.
- FIGS. 11 A and 11B are side views showing another example of a tool for forming the conductive bump forming recesses in the transfer plate
- FIG. 11C is a perspective view showing still another example thereof.
- the wiring board 1 has a wiring pattern.
- This wiring pattern is formed by a lead 3 integrally attached to the surface of the insulating base 2 and extending in that condition. On end of the lead 3 is concentrated in a loading area of the IC 4 so the a conductive bump 3 a is formed by one end of the lead.
- the pump 3 a thus formed is subjected to contact or connection with a pad (terminal) 5 intimately contacted with the surface of the IC 4 .
- a local portion of the insulating base 2 is raised from the surface of the insulating base 2 to form an insulating projection 6 .
- This projection 6 is covered with a part of the lead 3 . That is, the lead 3 is wired in such a manner as to cover the projection, thereby forming the conductive bump 3 a on an end portion of the lead 3 .
- This conductive bump 3 a is a bump which is formed by a known technique for forming the lead 3 on the surface of the insulating base 2 .
- This bump 3 a has a bump structure in which an internal cavity, which can be formed when a part of the lead 3 is given with a chevron-like configuration, is filled by the projection 6 formed by locally raising the insulating base 2 and backed up.
- the above conductive bump 3 a can be realized, for example, by a lead forming method of FIG. 4.
- a transfer plate 8 formed of a metal plate as represented by SUS and provided with a chevron-like bump forming recess 7 opening at the surface, is prepared.
- a conductive film 10 is integrally overlain on the surface of the transfer plate 8 .
- This conductive film 10 covers the entire surface of the transfer plate 8 .
- the conductive film 10 is intimately contacted with the bottom surface in the recess 7 and given with a chevron-like configuration thereby to form the conductive bump 3 a and further to form the recess 7 inwardly of the conductive bump 3 a.
- an insulating layer is formed on the surface of the conductive film 10 , thereby forming the insulating base 2 having a uniform thickness.
- This insulating layer i.e., the insulating layer 2 is partly filled in the recess 7 and locally raised to form the insulating projection 6 and further to form the conductive bump 3 a which is integrally intimately contacted with the surface of the projection 6 to cover thereof.
- the insulating base 2 is removed from the transfer plate 8 .
- the surface of the insulating base 2 thus removed is subjected to etching treatment so that the wiring pattern is formed.
- the bump 3 a covering the projection 16 is formed by a part of the lead 3 forming the wiring pattern.
- the bump 3 a covering the projection 6 by a part of the lead 3 is formed on an end portion of the lead 3 or at an intermediate part of the lead 3 .
- FIG. 5 shows another method for forming the bump 3 a of FIGS. 2A, 3A and 3 B.
- the transfer sheet 8 made of a metal plate as represented by SUS and provided with the chevron-like bump forming recesses 7 opening at the surface thereof is prepared.
- a photoresist is applied to the surface of the transfer plate 8 , or a photoresist is laminated on the surface of the transfer plate 8 and subjected to patterning treatment through exposure and development so that resist patterns 11 are formed.
- the wiring pattern (lead 3 ) is grown on the surface of the transfer plate 8 between the resist patterns 11 through plating.
- One end or an intermediate part of the lead 3 thus grown is integrally contacted with the bottom surface in the recess 7 at its area where the bump forming recess 7 exists and given with the chevron-like configuration, thereby forming the conductive bump 3 a and further forming the recess 7 in the inner surface of the conductive bump 3 a.
- an insulating layer having a uniform thickness is formed in such a manner as to cover the surface of the wiring pattern.
- this insulating layer i.e., the insulating base 2 is partly filled in the bump forming recess 7 to raise a local portion of the insulating base 2 so that the insulating projection 6 is formed.
- the conductive bump 3 a which is integrally intimately contacted with the surface of the insulating projection 6 to cover the surface.
- the insulating base 2 is removed from the transfer plate 8 to obtain the wiring board 1 having a structure of a conductive bump of FIGS. 2A, 3A and 3 B.
- FIG. 6 shows a method of manufacturing a wiring board having a structure in which the conductive bump 3 a is backed up by the insulating projection 6 .
- a transfer plate 6 made of metal having bump forming recesses 7 as in the abovementioned example is prepared. Then, the transfer plate 8 , a conductive film 14 of a copper foil or the like, and an insulating base 2 are superimposed with a conductive film 14 disposed between the transfer plate 8 and the insulating base 2 . The resultant is thermally welded together under pressure with use of a vacuum heat pressing machine or the like to form an integral layer structure. At the same time, a part of the insulating base 2 and a part of the conductive film 14 are pushed into the bump forming recesses 7 altogether and the resultant is removed to obtain a board with bumps as shown in FIG. 6B.
- a chevron-like insulating projection 6 is formed in each recess 7 .
- a chevron-like conductive film 14 is formed in the recess 7 to form the conductive bump 3 a.
- the conductive film 14 is subjected to patterning treatment through a photo-etching process or the like so that a wiring pattern is obtained.
- the insulating bumps 15 are provided on the surface of the insulating base 2 , i.e., the surface on the other side of the recesses 7 . Then, by flatly compressing the insulating bumps 15 through a thermal pressure welding, a part of the base is tightly filled in the recesses 7 so that the wholesome insulating projections 6 can be formed.
- each conductive bump 3 a is small and the pitch is very small, too, the bumps 15 made of comparatively harder insulating material than the base 2 are formed on the insulating base 2 by printing or the like and then hot pressed. By doing so, the insulating base 2 and the conductive film 14 can more effectively be pushed into the recesses 7 and the conductive bumps 3 a can be formed into a predetermined configuration copying the inner surface of each conductive bump 3 a.
- a rubber material is used as a material of the insulating base 2 .
- a bump structure in which the conductive pumps 3 a are backed up with the insulating projections 6 made of rubber material can be formed.
- the conductive bumps 3 a are brought into contact with another wiring board or a given electronic part such as an IC or the like, as shown in FIG. 1, it becomes possible that an appropriate elastic force is applied to the conductive bumps 3 a to increase the contacting pressure.
- another wiring pattern may be formed on the surface of the insulating base 2 on the other side of the wiring pattern.
- both the wiring patterns can be electrically connected together through the insulating base 2 .
- FIGS. 2B, 7A and 7 B show a structure of a conductive bump in a wiring board, in which the wiring board 1 has a wiring pattern on the surface of the insulating base 2 and in such a wiring board 1 , the bump 3 a is formed by a part of the lead 3 forming the wiring pattern and the cavity 12 is formed in the bump 3 a.
- the lead 3 When the lead 3 is formed, a part of the lead 3 is locally applied with a chevron configuration and the same is intimately contacted with the insulating base 2 . By doing so, the conductive bump 3 a having a cavity 12 formed between the projection and the insulating base by the chevron-like projection can be obtained.
- the conductive bump 3 a is backed up by the cavity 12 and the cavity applies an elasticity to the conductive bump 3 a .
- the foregoing arrangement serves as means for increasing the contacting pressure with respect to the terminal 5 of the electronic part such as the IC 4 or the like.
- an air hole 13 leading to the cavity 12 may be formed in the insulating base 2 in such a manner that the air hole 13 extends through the insulating base 2 .
- a transfer plate 8 made of a metal plate as represented by SUS and provided with chevron-like bump forming recesses 7 opening at the surface thereof is prepared.
- the conductive film 10 is integrally overlain on the surface of the transfer plate 8 .
- This conductive film 10 covers the entire surface of the transfer plate 8 .
- the conductive film 10 is intimately contacted with the bottom surface in the recess 7 and given with a chevron-like configuration thereby to form the conductive bump 3 a and further to form the recess 7 inwardly of the conductive bump 3 a.
- an insulating base 2 is integrally overlain on the surface of the conductive surface 8 .
- the recess 7 is tightly closed to form the cavity 12 .
- the insulating base 2 is removed from the transfer plate 8 .
- the surface of the insulating base 2 thus removed is subjected to etching treatment so that the wiring pattern is formed.
- the bump 3 a backed up by the cavity 12 is formed on a part of the lead 3 forming the wiring pattern, for example, on an end portion of the lead 3 or at an intermediate part of the lead 3 .
- the conductive bumps 3 a are often so small as 10 to 50 ⁇ m in height and 20 to 100 ⁇ m in bottom side length and arranged at so small pitches as 30 to 200 ⁇ m.
- the bump for the test use desirably has a generally conical configuration and is required to be uniform in configuration and pitch with precision.
- a tool 16 having a conical or generally conical tip 17 and made of ultra hard metal is vertically hammered on to the surface of the transfer plate 8 to give hammering traces thereon.
- Those hammering traces each have a conical or a generally conical configuration depending on the configuration of the tool tip 1 and provided as the bump forming recesses 7 .
- FIG. 10 shows an example in which the tool tip 17 has a conical configuration and the recesses having the same configuration are formed on the surface of the transfer plate 8 .
- the tool tip 17 has a conical configuration with a cutting head.
- the top surface of the cutting head is flat, and in FIG. 11B, the top surface of the cutting head is formed with a plurality of teeth 18 each having a sharpened tip portion.
- the recesses 7 each having a trigonal prism like configuration are formed with use of a tool 16 having a tool tip 17 of the same configuration as the recesses 7 .
- the conductive bumps 3 a formed by the recesses 7 exhibit a trigonal prism like configuration.
- the sharpened ridge lines of the conductive bumps 3 a are subjected to contact with or connected to the terminals of the electronic part such as the IC 4 or the like.
- the conductive bumps 3 a may be made of harder metal than other lead 3 portion, such as Ni, Cr or the like, as shown in FIG. 9.
- the conductive bumps 3 a made of hard metal are formed on the inner surfaces of the recesses 7 and then, the soft conductive film 10 , 14 made of copper or copper alloy or the like is overlain or the leads 3 are formed by growth of plating.
- the leads made of copper or copper alloy are partly (conductive bumps 3 a ) formed of a hard metal as shown in FIG.
- the abovementioned wiring board may include a case where a plurality of leads 3 are arranged in array on the surface of the insulating base 2 and the conductive bumps 3 a having any one of the abovementioned bump structures are provided on the end portions of the leads 3 and thereafter, the conductive bumps 3 a are brought into contact, under pressure, with the terminals (electronic pads) of a given electronic part such as a liquid crystal display unit or the like.
- a conductive bump when a wiring pattern is formed on a wiring pattern, a conductive bump can be formed by a part of the conductive lead forming the wiring pattern and the conductive bumps can be formed at small pitches utilizing the technique for forming the wiring patterns at small pitches.
Abstract
Description
- This invention relates to a structure of a wiring board used for contact or connection with a given electronic part such as an IC or the like, and more particularly to a conductive bump in a wiring board to be subjected to the above contact or connection.
- In this embodiment, the term “contact” refers to an electrical connection through free contact surface which comes into and out of connection freely, and the term “connection” refers to an electrical connection disconnectably joined through solder or the like.
- Conventionally, when a given electronic part such as an IC is to be loaded on a wiring board for electrical connection, a wiring pattern is formed on the surface of the wiring board and an unlike metal such as a conductive paste or the like is bulged to form a conductive bump on the surface of a lead forming this wiring pattern, so that a terminal of the electrical part is contacted with or connected to the conductive bump.
- Also, for achieving an electrical connection between a wiring board and another wiring board, according to another conventional method, the conductive bump is formed on the lead forming the wiring pattern of one of the wiring boards and contacted with or connected to a terminal formed on an end of the lead of the other wiring board.
- However, the above conventional method for forming the conductive bump on the conductive lead of the wiring board by raising an unlike metal such as a solder paste or the like has such problems that the method for forming thereof is complicated, a positional accuracy is difficult to obtain, the configuration of the height of the conductive bumps is irregular, and so forth. Although this conventional technique can effectively cope with the requirement for a smaller pitch arrangement of terminals, actual practice thereof is jeopardized because of the above problems.
- The present invention has been accomplished in view of the above situation.
- It is, therefore, a general object of the present invention to provide a structure of a conductive bump in a wiring board which is capable of properly solving the above problems and enhancing the actual practice thereof.
- To achieve the above object, there is essentially provided a structure of a conductive bump in a wiring board having a wiring pattern on a surface of an insulating base, characterized in that a local portion of the insulating base is raised from the surface of the insulating base to form a projection and a surface of the projection is covered with a part of a lead forming the wiring pattern to form a conductive bump.
- From another aspect of the present invention, there is also provided a structure of a conductive bump in a wiring board characterized in that a bump is formed by a part of a lead forming the wiring pattern and a cavity is formed in the bump.
- A more complete application of the present invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.
- FIG. 1 is a perspective view of a wiring board according to the present invention with a given electronic part such as an IC loaded thereon;
- FIG. 2A is a sectional view of the wiring board of FIG. 1, showing a structure of a bump in which a conductive bump is backed up with an insulating projection, and FIG. 2B is a sectional view of FIG. 2A, showing a structure of a bump in which the conductive bump is backed up by a cavity;
- FIG. 3A is an enlarged sectional view of FIG. 2A and FIG. 3B is an enlarged sectional view of FIG. 2B;
- FIGS. 4A to4E are sectional views showing the first example of a method of manufacturing a wiring board having the structure of a bump of FIG. 2A in the sequential order of processes;
- FIGS. 5A to5E are sectional views showing the second example of a method of manufacturing a wiring board having the structure of a bump of FIG. 2A in the sequential order of processes;
- FIGS. 6A and 6B are sectional views showing the third example of a process of manufacturing a wiring board having a structure of a bump of FIG. 2A;
- FIG. 7A is a sectional view of a wiring board showing a structure of a bump in which the conductive bump is of a hollow structure and backed up by the cavity and FIG. 7B is a plan view of FIG. 7A;
- FIGS. 8A to8E are sectional views showing one example of a method of manufacturing a wiring board of FIG. 7 in the sequential order of processes;
- FIG. 9 is an enlarged sectional view of a bump portion, showing an example in which the conductive bump is made of hard metal;
- FIG. 10 is a sectional view showing a tool for forming the conductive bump forming recesses in the transfer plate; and
- FIGS. 11 A and 11B are side views showing another example of a tool for forming the conductive bump forming recesses in the transfer plate, and FIG. 11C is a perspective view showing still another example thereof.
- As shown in FIG. 1, the
wiring board 1 has a wiring pattern. This wiring pattern is formed by alead 3 integrally attached to the surface of theinsulating base 2 and extending in that condition. On end of thelead 3 is concentrated in a loading area of theIC 4 so the aconductive bump 3 a is formed by one end of the lead. Thepump 3 a thus formed is subjected to contact or connection with a pad (terminal) 5 intimately contacted with the surface of theIC 4. - As means for forming the
conductive bump 3 a, as shown in FIGS. 2A, 3A and 3B, a local portion of theinsulating base 2 is raised from the surface of theinsulating base 2 to form aninsulating projection 6. Thisprojection 6 is covered with a part of thelead 3. That is, thelead 3 is wired in such a manner as to cover the projection, thereby forming theconductive bump 3 a on an end portion of thelead 3. - This
conductive bump 3 a is a bump which is formed by a known technique for forming thelead 3 on the surface of theinsulating base 2. Thisbump 3 a has a bump structure in which an internal cavity, which can be formed when a part of thelead 3 is given with a chevron-like configuration, is filled by theprojection 6 formed by locally raising theinsulating base 2 and backed up. - The above
conductive bump 3 a can be realized, for example, by a lead forming method of FIG. 4. - As shown in FIG. 4A, a
transfer plate 8 formed of a metal plate as represented by SUS and provided with a chevron-likebump forming recess 7 opening at the surface, is prepared. - Then, as shown in FIG. 4B, a
conductive film 10 is integrally overlain on the surface of thetransfer plate 8. Thisconductive film 10 covers the entire surface of thetransfer plate 8. However, where thebump forming recess 7 exists, theconductive film 10 is intimately contacted with the bottom surface in therecess 7 and given with a chevron-like configuration thereby to form theconductive bump 3 a and further to form therecess 7 inwardly of theconductive bump 3 a. - Then, as shown in FIG. 4C, an insulating layer is formed on the surface of the
conductive film 10, thereby forming theinsulating base 2 having a uniform thickness. - This insulating layer, i.e., the
insulating layer 2 is partly filled in therecess 7 and locally raised to form theinsulating projection 6 and further to form theconductive bump 3 a which is integrally intimately contacted with the surface of theprojection 6 to cover thereof. - Then, as shown in FIG. 4D, the insulating
base 2 is removed from thetransfer plate 8. Then, as shown in FIG. 4E, the surface of the insulatingbase 2 thus removed is subjected to etching treatment so that the wiring pattern is formed. Thus, thebump 3 a covering theprojection 16 is formed by a part of thelead 3 forming the wiring pattern. In other words, thebump 3 a covering theprojection 6 by a part of thelead 3 is formed on an end portion of thelead 3 or at an intermediate part of thelead 3. - FIG. 5 shows another method for forming the
bump 3 a of FIGS. 2A, 3A and 3B. - As shown in FIG. 5A, the
transfer sheet 8 made of a metal plate as represented by SUS and provided with the chevron-likebump forming recesses 7 opening at the surface thereof is prepared. - Then, as shown in FIG. 5B, a photoresist is applied to the surface of the
transfer plate 8, or a photoresist is laminated on the surface of thetransfer plate 8 and subjected to patterning treatment through exposure and development so that resistpatterns 11 are formed. - Then, as shown in FIG. 5C, the wiring pattern (lead3) is grown on the surface of the
transfer plate 8 between the resistpatterns 11 through plating. - One end or an intermediate part of the
lead 3 thus grown is integrally contacted with the bottom surface in therecess 7 at its area where thebump forming recess 7 exists and given with the chevron-like configuration, thereby forming theconductive bump 3 a and further forming therecess 7 in the inner surface of theconductive bump 3 a. - As shown in FIG. 5D, an insulating layer having a uniform thickness is formed in such a manner as to cover the surface of the wiring pattern. this insulating layer, i.e., the insulating
base 2 is partly filled in thebump forming recess 7 to raise a local portion of the insulatingbase 2 so that the insulatingprojection 6 is formed. By doing so, there can be formed theconductive bump 3 a which is integrally intimately contacted with the surface of the insulatingprojection 6 to cover the surface. - Then, as shown in FIG. 5E, the insulating
base 2 is removed from thetransfer plate 8 to obtain thewiring board 1 having a structure of a conductive bump of FIGS. 2A, 3A and 3B. - FIG. 6 shows a method of manufacturing a wiring board having a structure in which the
conductive bump 3 a is backed up by the insulatingprojection 6. - As shown in FIG. 6A, a
transfer plate 6 made of metal havingbump forming recesses 7 as in the abovementioned example is prepared. Then, thetransfer plate 8, aconductive film 14 of a copper foil or the like, and aninsulating base 2 are superimposed with aconductive film 14 disposed between thetransfer plate 8 and the insulatingbase 2. The resultant is thermally welded together under pressure with use of a vacuum heat pressing machine or the like to form an integral layer structure. At the same time, a part of the insulatingbase 2 and a part of theconductive film 14 are pushed into thebump forming recesses 7 altogether and the resultant is removed to obtain a board with bumps as shown in FIG. 6B. - By pushing a local portion of the insulating
base 2 and a local portion of theconductive film 14 into thebump forming recesses 7, a chevron-likeinsulating projection 6 is formed in eachrecess 7. At the same time, a chevron-likeconductive film 14 is formed in therecess 7 to form theconductive bump 3 a. - Then, as in the same manner as in FIG. 4E, the
conductive film 14 is subjected to patterning treatment through a photo-etching process or the like so that a wiring pattern is obtained. - In the embodiment of FIG. 6, as means for tightly and positively pushing the local portions of the insulating
base 2 and theconductive film 14 into thebump forming recesses 7, as shown in FIG. 6A, the insulatingbumps 15 are provided on the surface of the insulatingbase 2, i.e., the surface on the other side of therecesses 7. Then, by flatly compressing the insulatingbumps 15 through a thermal pressure welding, a part of the base is tightly filled in therecesses 7 so that the wholesomeinsulating projections 6 can be formed. - In case the configuration of each
conductive bump 3 a is small and the pitch is very small, too, thebumps 15 made of comparatively harder insulating material than thebase 2 are formed on the insulatingbase 2 by printing or the like and then hot pressed. By doing so, the insulatingbase 2 and theconductive film 14 can more effectively be pushed into therecesses 7 and theconductive bumps 3 a can be formed into a predetermined configuration copying the inner surface of eachconductive bump 3 a. - As one preferred example, in a
wiring board 1 having a structure of a bump in which theconductive bumps 3 a are bucked up with the insulatingprojections 6, a rubber material is used as a material of the insulatingbase 2. By doing so, a bump structure in which theconductive pumps 3 a are backed up with the insulatingprojections 6 made of rubber material can be formed. In case theconductive bumps 3 a are brought into contact with another wiring board or a given electronic part such as an IC or the like, as shown in FIG. 1, it becomes possible that an appropriate elastic force is applied to theconductive bumps 3 a to increase the contacting pressure. - In the
wiring board 1 obtained by FIGS. 4, 5 and 6, a local portion of the insulatingbase 2 is raised from the surface of thebase 2 to form theprojections 6. When the wiring patterns are to be formed, the surface of eachprojection 6 is covered with a part of thelead 3 to form theconductive bump 3. - In FIGS. 2A, 3A,4, 5 and 6, another wiring pattern may be formed on the surface of the insulating
base 2 on the other side of the wiring pattern. In this case, both the wiring patterns can be electrically connected together through the insulatingbase 2. - FIGS. 2B, 7A and7B show a structure of a conductive bump in a wiring board, in which the
wiring board 1 has a wiring pattern on the surface of the insulatingbase 2 and in such awiring board 1, thebump 3 a is formed by a part of thelead 3 forming the wiring pattern and thecavity 12 is formed in thebump 3 a. - When the
lead 3 is formed, a part of thelead 3 is locally applied with a chevron configuration and the same is intimately contacted with the insulatingbase 2. By doing so, theconductive bump 3 a having acavity 12 formed between the projection and the insulating base by the chevron-like projection can be obtained. - The
conductive bump 3 a is backed up by thecavity 12 and the cavity applies an elasticity to theconductive bump 3 a. The foregoing arrangement serves as means for increasing the contacting pressure with respect to theterminal 5 of the electronic part such as theIC 4 or the like. In order to ensure the elastic contacting pressure by thecavity 12, anair hole 13 leading to thecavity 12 may be formed in the insulatingbase 2 in such a manner that theair hole 13 extends through the insulatingbase 2. - One example of a method of forming the
conductive bump 3 a backed up by thecavity 12 will now be described with reference to FIG. 8. - As shown in FIG. 8A, a
transfer plate 8 made of a metal plate as represented by SUS and provided with chevron-likebump forming recesses 7 opening at the surface thereof is prepared. - Then, as shown in FIG. 8B, the
conductive film 10 is integrally overlain on the surface of thetransfer plate 8. Thisconductive film 10 covers the entire surface of thetransfer plate 8. However, where thebump forming recess 7 exists, theconductive film 10 is intimately contacted with the bottom surface in therecess 7 and given with a chevron-like configuration thereby to form theconductive bump 3 a and further to form therecess 7 inwardly of theconductive bump 3 a. - Then, as shown in FIG. 8C, an insulating
base 2 is integrally overlain on the surface of theconductive surface 8. By doing so, therecess 7 is tightly closed to form thecavity 12. - Then, as shown in FIG. 8D, the insulating
base 2 is removed from thetransfer plate 8. Then, as shown in FIG. 8E, the surface of the insulatingbase 2 thus removed is subjected to etching treatment so that the wiring pattern is formed. Thus, thebump 3 a backed up by thecavity 12 is formed on a part of thelead 3 forming the wiring pattern, for example, on an end portion of thelead 3 or at an intermediate part of thelead 3. - A method of forming the
bump forming recesses 7 in thetransfer plate 8 of FIGS. 4, 5, 6 and 8 will now be described with reference to FIGS. 10 and 11. Theconductive bumps 3 a are often so small as 10 to 50 μm in height and 20 to 100 μm in bottom side length and arranged at so small pitches as 30 to 200 μm. The bump for the test use desirably has a generally conical configuration and is required to be uniform in configuration and pitch with precision. - In a method of forming
such recesses 7 in thetransfer plate 8, as shown in FIGS. 10, 11A and 11B, atool 16 having a conical or generallyconical tip 17 and made of ultra hard metal is vertically hammered on to the surface of thetransfer plate 8 to give hammering traces thereon. Those hammering traces each have a conical or a generally conical configuration depending on the configuration of thetool tip 1 and provided as thebump forming recesses 7. - FIG. 10 shows an example in which the
tool tip 17 has a conical configuration and the recesses having the same configuration are formed on the surface of thetransfer plate 8. - In FIGS. 11A and 11B, the
tool tip 17 has a conical configuration with a cutting head. In FIG. 11A, the top surface of the cutting head is flat, and in FIG. 11B, the top surface of the cutting head is formed with a plurality ofteeth 18 each having a sharpened tip portion. In the example of FIG. 11C, therecesses 7 each having a trigonal prism like configuration are formed with use of atool 16 having atool tip 17 of the same configuration as therecesses 7. Accordingly, theconductive bumps 3 a formed by therecesses 7 exhibit a trigonal prism like configuration. The sharpened ridge lines of theconductive bumps 3 a are subjected to contact with or connected to the terminals of the electronic part such as theIC 4 or the like. - In any of the bump structure in which the
conductive bumps 3 a are backed up by theconductive bumps 3 a as shown in FIG. 3 and of the bump structure in which theconductive bumps 3 a are backed up by thecavities 12 as shown in FIG. 7, only theconductive bumps 3 a may be made of harder metal thanother lead 3 portion, such as Ni, Cr or the like, as shown in FIG. 9. - As a method of forming thereof, prior to formation of the
conductive film leads 3 of FIGS. 4B, SC, 6A and 8B, theconductive bumps 3 a made of hard metal are formed on the inner surfaces of therecesses 7 and then, the softconductive film leads 3 are formed by growth of plating. In that case, as shown in FIG. 9, the leads made of copper or copper alloy are partly (conductive bumps 3 a) formed of a hard metal as shown in FIG. 9 or theleads 3 are partly applied with a chevron-like configuration by therecesses 7 to form theconductive bumps 3 a and the surfaces of theconductive bumps 3 a are covered with a harder conductive metal than the bumps, so that a composite structure is obtained. Those can be realized by the embodiments of the manufacturing methods of FIGS. 4, 5, 6 and 8. - The abovementioned wiring board may include a case where a plurality of
leads 3 are arranged in array on the surface of the insulatingbase 2 and theconductive bumps 3 a having any one of the abovementioned bump structures are provided on the end portions of theleads 3 and thereafter, theconductive bumps 3 a are brought into contact, under pressure, with the terminals (electronic pads) of a given electronic part such as a liquid crystal display unit or the like. - According to the present invention, when a wiring pattern is formed on a wiring pattern, a conductive bump can be formed by a part of the conductive lead forming the wiring pattern and the conductive bumps can be formed at small pitches utilizing the technique for forming the wiring patterns at small pitches.
- Furthermore, when the wiring pattern is formed through application of the known technique for forming the wiring pattern, merely by employing an additional means for providing the bump forming recesses in a local area of the pattern forming surface, uniform conductive bumps can be formed at equal pitches with precision.
- Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described herein.
Claims (2)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9051951A JP2934202B2 (en) | 1997-03-06 | 1997-03-06 | Method for forming conductive bumps on wiring board |
JP9-51951 | 1997-03-06 |
Publications (2)
Publication Number | Publication Date |
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US20010015012A1 true US20010015012A1 (en) | 2001-08-23 |
US6351885B2 US6351885B2 (en) | 2002-03-05 |
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Application Number | Title | Priority Date | Filing Date |
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US09/079,857 Expired - Fee Related US6351885B2 (en) | 1997-03-06 | 1998-05-15 | Method of making conductive bump on wiring board |
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US (1) | US6351885B2 (en) |
JP (1) | JP2934202B2 (en) |
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US20080012592A1 (en) * | 2006-07-13 | 2008-01-17 | Samsung Electronics Co., Ltd. | Device and method for testing semiconductor packages |
US20190157238A1 (en) * | 2015-06-30 | 2019-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices |
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US5914613A (en) | 1996-08-08 | 1999-06-22 | Cascade Microtech, Inc. | Membrane probing system with local contact scrub |
US6256882B1 (en) | 1998-07-14 | 2001-07-10 | Cascade Microtech, Inc. | Membrane probing system |
US6838890B2 (en) * | 2000-02-25 | 2005-01-04 | Cascade Microtech, Inc. | Membrane probing system |
DE20114544U1 (en) | 2000-12-04 | 2002-02-21 | Cascade Microtech Inc | wafer probe |
WO2003052435A1 (en) | 2001-08-21 | 2003-06-26 | Cascade Microtech, Inc. | Membrane probing system |
WO2004006178A1 (en) * | 2002-07-03 | 2004-01-15 | Quelis Id Systems Inc. | Wire positioning and mechanical attachment for a radio-frequency identification device |
JP2004221502A (en) * | 2003-01-17 | 2004-08-05 | Nec Electronics Corp | Wiring board with bump electrode and its manufacturing method |
US6948940B2 (en) * | 2003-04-10 | 2005-09-27 | Formfactor, Inc. | Helical microelectronic contact and method for fabricating same |
US7005751B2 (en) * | 2003-04-10 | 2006-02-28 | Formfactor, Inc. | Layered microelectronic contact and method for fabricating same |
US7057404B2 (en) | 2003-05-23 | 2006-06-06 | Sharp Laboratories Of America, Inc. | Shielded probe for testing a device under test |
JP2007517231A (en) | 2003-12-24 | 2007-06-28 | カスケード マイクロテック インコーポレイテッド | Active wafer probe |
JP4980903B2 (en) * | 2004-07-07 | 2012-07-18 | カスケード マイクロテック インコーポレイテッド | Probe head with membrane suspension probe |
DE202005021435U1 (en) | 2004-09-13 | 2008-02-28 | Cascade Microtech, Inc., Beaverton | Double-sided test setups |
US7656172B2 (en) | 2005-01-31 | 2010-02-02 | Cascade Microtech, Inc. | System for testing semiconductors |
US7535247B2 (en) | 2005-01-31 | 2009-05-19 | Cascade Microtech, Inc. | Interface for testing semiconductors |
US7764072B2 (en) | 2006-06-12 | 2010-07-27 | Cascade Microtech, Inc. | Differential signal probing system |
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US7723999B2 (en) | 2006-06-12 | 2010-05-25 | Cascade Microtech, Inc. | Calibration structures for differential signal probing |
KR100761706B1 (en) * | 2006-09-06 | 2007-09-28 | 삼성전기주식회사 | Fabrication method for printed circuit board |
US7876114B2 (en) | 2007-08-08 | 2011-01-25 | Cascade Microtech, Inc. | Differential waveguide probe |
KR101542478B1 (en) * | 2007-08-15 | 2015-08-06 | 테세라, 인코포레이티드 | A method of fabricating an interconnection element having conductive posts |
US7888957B2 (en) | 2008-10-06 | 2011-02-15 | Cascade Microtech, Inc. | Probing apparatus with impedance optimized interface |
US8410806B2 (en) | 2008-11-21 | 2013-04-02 | Cascade Microtech, Inc. | Replaceable coupon for a probing apparatus |
KR101022912B1 (en) * | 2008-11-28 | 2011-03-17 | 삼성전기주식회사 | A printed circuit board comprising a metal bump and a method of manufacturing the same |
CN105097758B (en) * | 2014-05-05 | 2018-10-26 | 日月光半导体制造股份有限公司 | Substrate, its semiconductor packages and its manufacturing method |
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US5207887A (en) * | 1991-08-30 | 1993-05-04 | Hughes Aircraft Company | Semi-additive circuitry with raised features using formed mandrels |
JPH07105420B2 (en) | 1991-08-26 | 1995-11-13 | ヒューズ・エアクラフト・カンパニー | Electrical connection with molded contacts |
US5245750A (en) * | 1992-02-28 | 1993-09-21 | Hughes Aircraft Company | Method of connecting a spaced ic chip to a conductor and the article thereby obtained |
US5245135A (en) * | 1992-04-20 | 1993-09-14 | Hughes Aircraft Company | Stackable high density interconnection mechanism (SHIM) |
US5390412A (en) * | 1993-04-08 | 1995-02-21 | Gregoire; George D. | Method for making printed circuit boards |
EP0971405A3 (en) * | 1994-09-23 | 2000-05-10 | Siemens S.A. | Method for manufacturing a substrate for a polymer stud grid array |
US6085414A (en) * | 1996-08-15 | 2000-07-11 | Packard Hughes Interconnect Company | Method of making a flexible circuit with raised features protruding from two surfaces and products therefrom |
US5790377A (en) * | 1996-09-12 | 1998-08-04 | Packard Hughes Interconnect Company | Integral copper column with solder bump flip chip |
US5831832A (en) * | 1997-08-11 | 1998-11-03 | Motorola, Inc. | Molded plastic ball grid array package |
US6166333A (en) | 1998-01-14 | 2000-12-26 | Packard Hughes Interconnect Company | Bumps with plural under-bump dielectric layers |
-
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US20080012592A1 (en) * | 2006-07-13 | 2008-01-17 | Samsung Electronics Co., Ltd. | Device and method for testing semiconductor packages |
US20190157238A1 (en) * | 2015-06-30 | 2019-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices |
US11329022B2 (en) * | 2015-06-30 | 2022-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices |
Also Published As
Publication number | Publication date |
---|---|
JPH10256416A (en) | 1998-09-25 |
JP2934202B2 (en) | 1999-08-16 |
US6351885B2 (en) | 2002-03-05 |
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Owner name: YAMAICHI ELECTRONICS CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, ETSUJI;YONEZAWA, AKIRA;OKUNO, TOSHIO;REEL/FRAME:009311/0873 Effective date: 19980525 Owner name: SHOSHOTECH CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, ETSUJI;YONEZAWA, AKIRA;OKUNO, TOSHIO;REEL/FRAME:009311/0873 Effective date: 19980525 |
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