US20010014541A1 - Method of sealing an epitaxial silicon layer on a substrate - Google Patents

Method of sealing an epitaxial silicon layer on a substrate Download PDF

Info

Publication number
US20010014541A1
US20010014541A1 US09/350,805 US35080599A US2001014541A1 US 20010014541 A1 US20010014541 A1 US 20010014541A1 US 35080599 A US35080599 A US 35080599A US 2001014541 A1 US2001014541 A1 US 2001014541A1
Authority
US
United States
Prior art keywords
chamber
wafer
loadlock
ozone
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/350,805
Other versions
US6376387B2 (en
Inventor
David K. Carlson
Paul B. Comita
Norma B. Riley
Dale R. Du Bois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/350,805 priority Critical patent/US6376387B2/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CARLSON, DAVID K., COMITA, PAUL B., DU BOIS, DALE R., RILEY, NORMA B.
Priority to EP00114548A priority patent/EP1067585A3/en
Priority to TW089113475A priority patent/TW504730B/en
Priority to KR1020000039068A priority patent/KR100746380B1/en
Priority to JP2000208618A priority patent/JP4640879B2/en
Publication of US20010014541A1 publication Critical patent/US20010014541A1/en
Priority to US10/076,250 priority patent/US6685779B2/en
Publication of US6376387B2 publication Critical patent/US6376387B2/en
Application granted granted Critical
Priority to KR1020060128514A priority patent/KR100713264B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • CCHEMISTRY; METALLURGY
    • C01INORGANIC CHEMISTRY
    • C01BNON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B13/00Oxygen; Ozone; Oxides or hydroxides in general
    • C01B13/10Preparation of ozone
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/005Oxydation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67201Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S414/00Material or article handling
    • Y10S414/135Associated with semiconductor wafer handling
    • Y10S414/139Associated with semiconductor wafer handling including wafer charging or discharging means for vacuum chamber

Definitions

  • This invention relates to a method of and a system for sealing an epitaxial silicon layer formed on a semiconductor wafer.
  • Integrated circuits are formed in and on silicon and other semiconductor wafers. Wafers are made by extruding an ingot from a silicon bath and sawing the ingot into multiple wafers. In the case of silicon, the material of the wafers is monocrystalline. An epitaxial silicon layer is then formed on the monocrystalline material of the wafer. The epitaxial silicon layer is typically doped with boron and has a dopant concentration of about 1 ⁇ 10 16 atoms per centimeter cube. A typical epitaxial silicon layer is about five microns thick. The material of the epitaxial silicon layer has better controlled properties than the monocrystalline silicon for purposes of forming semiconductor devices therein and thereon.
  • the wafer is removed from the wafer processing chamber and exposed to ambient air.
  • the air oxidizes the exposed epitaxial silicon layer to form a native oxide layer thereon.
  • the epitaxial silicon layer and the native oxide layer are exposed to contaminants in the air and are usually filled with impurities and particles.
  • the electronic devices often fail.
  • a method of processing a wafer is provided.
  • the wafer is located in a wafer processing chamber of a system for processing a wafer.
  • An epitaxial silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber.
  • the wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off.
  • the wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.
  • FIG. 1 is a plan view of a system for processing a wafer
  • FIG. 2 is a diagram of a loadlock assembly forming part of the system and illustrates a loadlock chamber thereof in sectioned side view;
  • FIG. 3 is a flow chart of how the system is operated
  • FIG. 4 is a time chart of how the system operates
  • FIG. 5 is a cross-sectional side view of a wafer which is processed according to the invention.
  • FIG. 6 is a cross-sectional end view of an ozone generator which is used in the loadlock assembly
  • FIG. 7 is a cross-sectional side view of the ozone generator
  • FIG. 8 is a graph of ozone concentration against backfill rate
  • FIG. 9 is a graph of oxide formation against ozone concentration.
  • the present invention relates to a method whereby a epitaxial silicon layer formed on a silicon wafer is sealed with an oxide formed due to exposure to ozone gas.
  • a plurality of the wafers are located in a batch in a loadlock chamber and exposed to ozone gas under controlled conditions.
  • the ozone gas forms a stable and clean oxide layer on the epitaxial silicon layer of each wafer.
  • the oxide layer can later be removed to leave the epitaxial silicon layer exposed and containing substantially no impurities.
  • One advantage is that another chamber which is designated for a step in an existing process does not have to be dedicated for exposing the wafers to ozone gas.
  • Another advantage is that such a system is relatively safe because there is a substantially reduced likelihood that the ozone gas will mix with hydrogen gas within the system and cause an explosion, in particular because the pressure within the loadlock chamber is lower than a chamber in the system where hydrogen gas is used.
  • the system is also safe because the pressure within the loadlock chamber is always below atmospheric pressure of an area around the loadlock chamber when ozone gas is within the loadlock chamber so that there is reduced likelihood that the ozone gas will escape to a surrounding area and cause an explosion.
  • Another advantage is that the overall time taken to process wafers is maintained.
  • FIG. 1 of the accompanying drawings illustrates a system 10 for processing a semiconductor wafer.
  • the system 10 includes a factory integration unit 12 , first and second batch loadlock assemblies 14 A and 14 B, a transfer chamber 18 , first, second, and third wafer processing chambers 20 A, 20 B, and 20 C, and a cooldown chamber 22 .
  • FIG. 2 illustrates one of the loadlock assemblies 14 in more detail.
  • the loadlock assembly 14 includes a loadlock chamber 24 , a cassette elevator 26 , a wafer cassette 28 , a pump 30 , and apparatus 32 for supplying gasses into the loadlock chamber 24 .
  • the loadlock chamber 24 defines an enclosure 34 and has a door opening 36 on one side thereof and a slitvalve opening 38 on an opposing side thereof.
  • the factory integration unit 12 mates with the loadlock chamber 24 over the door opening 36 .
  • a door 40 is mounted to the loadlock chamber 24 for movement between a position as shown in FIG. 2 wherein the door 40 closes the door opening 36 , and a position wherein the door opening 36 is open so that the confines of the factory integration unit 12 are in communication with the enclosure 34 .
  • the transfer chamber 18 mates with the loadlock chamber 24 over the slitvalve opening 38 .
  • a slitvalve 42 is mounted to the loadlock chamber 24 for movement between a position as shown in FIG. 2 wherein the slitvalve 42 closes the slitvalve opening 38 , and a position wherein the slitvalve opening 38 is open so that the enclosure 34 is in communication with the confines of the transfer chamber 18 .
  • the cassette elevator 26 includes a shaft 44 and a support plate 46 .
  • the shaft 44 extends through an opening in a base of the loadlock chamber 24 .
  • a seal (not shown) is located between the shaft 44 and the base of the loadlock chamber 24 .
  • the support plate 46 is secured to an upper end of the shaft 44 .
  • the wafer cassette 28 includes a frame 48 with a plurality of fins 50 located on the frame.
  • the fins 50 are positioned relative to one another so as to be jointly capable of supporting a total of twenty-five wafers above one another.
  • the wafer cassette 28 is located on the support plate 46 .
  • the wafer cassette 28 can be elevated by extending the shaft 44 into the loadlock chamber 24 , and lowered by retracting the shaft 44 from the loadlock chamber 24 .
  • a respective one of the wafers 52 can be aligned with the slitvalve opening 38 and can be removed from the loadlock chamber 24 through the slitvalve opening 38 .
  • the pump 30 has a low-pressure side 54 and a high-pressure side 56 .
  • An exhaust line 58 has one end that extends into an opening in a base of the loadlock chamber 24 , and an opposed end connected to the low-pressure side 54 of the pump 30 .
  • the pump 30 can therefore be used for pumping a gas from the enclosure 34 .
  • the apparatus 32 includes a source of nitrogen 60 , a source of oxygen 62 , an ozone generator 64 , a nitrogen supply valve 68 , and an ozone supply valve 70 .
  • the source of nitrogen 60 is connected to the nitrogen supply valve 68 .
  • the nitrogen supply valve 68 is, in turn, connected to a nitrogen supply line 74 .
  • An opposing end of the nitrogen supply line 74 extends into an opening in an upper wall of the loadlock chamber 24 .
  • a diffuser (not shown) is located in the nitrogen supply line 74 to reduce the speed of the nitrogen gas.
  • the source of oxygen 62 may, for example, be substantially pure oxygen gas or may be air. It has been found that even filtered air is not as free of impurities as substantially pure oxygen.
  • the oxygen is typically about 99.999% pure. Substantially pure oxygen may thus be preferred.
  • the ozone generator 64 is connected to the source of oxygen 62 .
  • the ozone generator 64 When oxygen gas from the source of oxygen 62 is supplied to the ozone generator the ozone generator 64 generates ozone gas.
  • the ozone generator 64 is, in turn, connected to the ozone supply valve 70 .
  • An ozone supply line 76 is connected to the ozone supply valve 70 .
  • An opposing end of the ozone supply line 76 extends into an opening in the upper wall of the loadlock chamber 24 .
  • a diffuser (not shown) is located in the ozone supply line 76 to reduce the speed of the ozone gas.
  • a pressure detector 72 is connected to the exhaust line 58 .
  • the pressure detector 72 can detect the pressure within the exhaust line 58 , and therefore also the pressure within the enclosure 34 .
  • a controller 80 is used for controlling various components of the system 10 shown in FIG. 1, including the pump 30 , the ozone generator 64 , and the valves 68 and 70 shown in FIG. 2.
  • the controller 80 receives input from the pressure detector 72 and controls all the components based on the pressure detected by the pressure detector 72 and other variables as will be described hereinbelow.
  • the controller 80 is typically a computer having a processor which is programmed to execute a program which controls all the components of the system 10 .
  • the program includes processor executable code and is typically stored on a disk or other computer readable medium and then loaded into memory of the computer from where the processor of the computer reads and executes the program to control the components of the system 10 . Particular features of the program and how it is constructed will be evident to one skilled in the art from the discussion that follows.
  • each wafer processing chamber 20 A, 20 B, or 20 C leads directly off the transfer chamber 18 .
  • a respective slitvalve 82 A, 82 B, and 82 C is mounted to open or close communication between the transfer chamber 18 and a respective one of the wafer processing chambers 20 A, 20 B or 20 C.
  • the cooldown chamber 22 also leads off the transfer chamber 18 but no slitvalve is provided to open and close communication between the transfer chamber 18 and the cooldown chamber 22 .
  • a robot 84 is located within the transfer chamber 18 .
  • the robot 84 has a blade 86 which, when the robot 84 is operated, can transfer a wafer from one of the chambers 20 , 22 , or 24 to another.
  • a susceptor 88 is located in each one of the chambers 20 and 22 , on which the wafer can be located by the blade 86 .
  • the slitvalves 82 and the robot 84 are also under control of the controller 80 shown in FIG. 2.
  • FIG. 3 is a flow chart which assists in illustrating how the system 10 is operated.
  • the slitvalves 42 are initially closed so that the confines of the transfer chamber 18 are not in communication with the loadlock chambers 24 .
  • the loadlock chamber 18 is initially evacuated to remove contamination.
  • the loadlock chamber 18 is then backfilled with an inert gas such as nitrogen.
  • the slitvalves 82 are open so that the wafer processing chambers 20 are in communication with the transfer chamber 18 .
  • the transfer chamber 18 , the wafer processing chamber 20 , and the cooldown chamber 22 are filled with an inert gas such as nitrogen gas and are at atmospheric pressure.
  • the door 40 of the first loadlock assembly 14 A is open.
  • a robot located within the factory integration unit 12 then loads a total of twenty-five wafers on the wafer cassette 28 of the first loadlock assembly 14 A. (Step 1 ). The door 40 is then closed so that the wafers 52 are isolated within the loadlock chamber 24 . (Step 2 ).
  • the pump 30 is then switched on so that air passes from the enclosure 34 through the exhaust line 58 through the pump 30 . (Step 3 ).
  • the valves 68 , and 70 are closed so that the enclosure 34 is pumped down to a pressure of about 5 Torr.
  • the pump 30 is then switched off. (Step 4 ).
  • the valve 68 is then opened.
  • Nitrogen then flows into the enclosure 34 until the pressure within the enclosure 34 is substantially the same as the pressure within the transfer chamber 18 .
  • the valve 68 is then closed. (Step 6 ).
  • the slitvalve 42 is then opened. (Step 7 ).
  • the robot 84 then removes three wafers consecutively from the wafer cassette 28 and locates one wafer within the first wafer processing chamber 20 A, another wafer within the second wafer processing chamber 20 B, and a further wafer within the third wafer processing chamber 20 C.
  • the slitvalves 82 are then closed so that the wafer processing chambers 20 are isolated from the transfer chamber 18 .
  • An epitaxial silicon layer is then formed on the wafer in each processing chamber 20 .
  • a mixture of gasses is introduced into each one of the wafer processing chambers 20 .
  • One of these gasses typically includes hydrogen.
  • Another one of the gasses is a source of silicon such as silane, dichlorosilane, or trichlorosilane.
  • the source of silicon reacts with the hydrogen to form an epitaxial layer.
  • Another one of the gasses is typically B 2 H 6 which provides boron for purposes of doping the epitaxial silicon layer.
  • Heat lamps (not shown) heat the wafers within the wafer processing chambers 20 to a temperature of between 600° C. and 1300° C.
  • the processing gasses within the respective chambers 20 are replaced by pure hydrogen gas to purge the chambers 20 .
  • the respective slitvalve 82 is then opened.
  • the respective wafer is transferred, utilizing the robot 84 , to the cooldown chamber 22 .
  • Step 13 Transfer of the wafer takes about twenty seconds.
  • the wafer remains within the cooldown chamber 22 for about sixty seconds.
  • the robot 84 then transfers the wafer from the cooldown chamber 22 back to the wafer cassette 28 .
  • the wafer is thus transferred from the chambers 20 to the wafer cassette 28 without ever being exposed to oxygen or any other gas that can form an oxide on the epitaxial silicon layer.
  • the slitvalve 38 thereof is closed. (Step 16 ).
  • the wafers 52 are then typically at a temperature of less than 100° C., but this temperature can vary depending on the time spent in the cooldown chamber 22 .
  • the pump 30 is then again switched on so that nitrogen gas then flows out of the enclosure 34 .
  • the enclosure 34 is pumped down to a pressure of about 5 Torr.
  • the pump 30 is then switched off.
  • the ozone generator 64 is then switched on and the valve 70 is opened so that an ozone gas and oxygen gas mixture flows into the top of the enclosure 34 .
  • the ozone gas and oxygen mixture continues to flow into the enclosure 34 until the pressure within the enclosure 34 reaches about 600 Torr.
  • the valve 70 is then closed and the ozone generator 64 is switched off. (Step 20 ).
  • the wafers 52 are then simultaneously exposed to the ozone gas within the enclosure 34 . Exposure of the epitaxial silicon layer on the wafer 52 results in oxidation of the epitaxial silicon layer.
  • the wafers 52 are exposed to the ozone gas for a period from one to fifteen minutes.
  • the wafers 52 are simply “soaked” in the ozone gas i.e., there are no additional sources of excitation which, for example, create a plasma or create certain photo effects.
  • An oxide layer forms over the epitaxial silicon layer of each wafer and has a thickness of about 10 ⁇ to about 15 ⁇ , as measured by a multiple wavelength ellipsometry technique, for exposure to ozone gas of about fifteen minutes.
  • the oxide layer that forms on the wafer is extremely pure because of the controlled conditions to which the wafers 52 are exposed, including the purity of the ozone gas and oxygen gas mixture to which the wafers 52 are exposed.
  • Hydrogen is used within the wafer processing chamber 20 .
  • Hydrogen is highly explosive when mixed with ozone or oxygen.
  • the system 10 has to fail simultaneously in a number of respects.
  • Second, the hydrogen should leak past a respective slitvalve 82 of the relevant wafer processing chamber 20 . Leakage of hydrogen past the slitvalve 82 would only occur if the slitvalve 82 does not seal sufficiently on the wafer processing chamber or when the slitvalve 82 is not closed when hydrogen is introduced into the wafer processing chamber 20 .
  • ozone should leak from the enclosure 34 into the transfer chamber 18 . Because the enclosure 34 is maintained at a pressure below that of the transfer chamber 18 , it is highly unlikely that there would be any flow of gasses from the enclosure 34 into the transfer chamber 18 .
  • ozone is only present within the apparatus 32 when generated by the ozone generator 64 which is only while the enclosure 34 is being filled with ozone. There is therefore no contained source of ozone (other than in the loadlock chambers 24 ) which may leak and cause exposure to personnel or other reactive gasses. Ozone gas is thus generated at the point of use.
  • the pump 30 is then again switched on so that the pressure within the enclosure 34 reduces to about 5 Torr. (Step 21 ).
  • the ozone gas flowing through the pump 30 is pumped to a location distant from the system 10 , where the ozone gas is neutralized.
  • the ozone gas may for example be neutralized by treatment with a chemical to form oxygen, be scrubbed in a fluidized bed of silica, or be scrubbed in another liquid system.
  • the valve 68 is then opened so that the enclosure 34 is filled with nitrogen gas. (Step 22 ).
  • the door 40 is then opened and the wafers 52 are transferred from the enclosure 34 into the factory integration unit 12 .
  • the factory integration unit 12 is filled with air. (Step 23 ).
  • the air within the factory integration unit 12 does not form an oxide layer on the epitaxial silicon layer because of the oxide layer which is already formed thereon due to exposure to ozone.
  • the first loadlock assembly 14 A can thus be used in an epitaxial silicon cycle wherein wafers are transferred to the wafer processing chamber 20 and the cooldown chamber 22 .
  • the first loadlock assembly 14 A can then be used in a oxide cycle wherein the wafer is exposed to ozone gas.
  • the second loadlock assembly 14 B can be used for a epitaxial silicon cycle, whereafter the second loadlock assembly 14 B can be used for an oxide cycle.
  • the first loadlock assembly 14 A can be used in a epitaxial silicon cycle. It can thus be seen that, because the oxide cycles are shorter than the epitaxial silicon cycles, there is no lapse in time from one epitaxial silicon cycle to a next epitaxial silicon cycle.
  • FIG. 5 illustrates a wafer 100 which is processed in accordance with the invention.
  • the wafer includes a monocrystalline substrate 102 on which an epitaxial silicon layer 104 is formed.
  • a silicon dioxide layer 106 is formed on the epitaxial silicon layer 104 .
  • the silicon dioxide layer can later be removed to leave the expitaxial silicon layer 104 exposed and containing substantially no impurities.
  • the silicon dioxide layer can, for example, be removed in a aqueous solution of hydrogen fluoride.
  • FIG. 6 and FIG. 7 illustrate the ozone generator 64 in more detail.
  • the ozone generator 64 includes a housing 120 , two ultraviolet lamps 122 , four quartz tubes 124 , an inlet pipe 126 , and an outlet pipe 128 .
  • the housing 120 is leak tight and dust proof.
  • a mirror 126 is located on a lower surface of the housing 120 .
  • the ultraviolet lamps 122 are located within the housing 120 on a side thereof opposing the mirror 126 . Electrical connectors 128 extend into the housing 120 to the ultraviolet lamps 122 . The ultraviolet lamps 122 can be energized by supplying electricity through the cables 128 . A leak tight interface exists between the housing 120 and the cables 128 where the cables extend into the housing 120 .
  • Each pipe 126 or 128 extends into the housing 120 .
  • a leak tight interface also exists between each pipe 126 or 128 and the housing 120 where the pipe 126 or 128 extends into the housing 120 .
  • the pipes 126 and 128 are located on opposing sides of the housing 120 as can be seen in FIG. 7.
  • the inlet pipe 126 has an inlet opening therein.
  • the pipe 126 interconnects ends of the tubes 124 to one another.
  • the pipe 128 extends through ends of the tubes 124 opposing the ends that are interconnected by the pipe 126 .
  • Small openings 130 are formed in the pipe 128 within the tubes 124 .
  • Each opening 130 is typically about 2 mm in diameter.
  • the openings 130 are located facing away from a flow passage of a gas flowing through the tubes 126 so as to avoid a flow channel within each tube 126 and to ensure mixing of a gas flowing through each tube 126 .
  • the oxygen source 62 is connected to the inlet tube 126 through a regulator valve 132 .
  • the regulator valve 132 can be adjusted so as to control flow to the inlet tube 126 .
  • a nitrogen source 132 is connected to the housing 120 .
  • a purge gas outlet 134 is also provided out of the housing 120 .
  • Nitrogen from the nitrogen source 132 flows through the housing 120 in an area around the tubes 124 .
  • the ultraviolet lamps 122 are switched on by providing electricity through the cables 128 .
  • Oxygen from the oxygen source 62 flows through the regulator valve 132 and the pipe 126 to the tubes 124 .
  • Ultraviolet light is transmitted by the ultraviolet lamps 122 .
  • the quartz of the tubes 124 is transmissive so that the ultraviolet light enters the tubes 124 .
  • One of the ultraviolet lamps is located above two of the tubes 124 and another one of the ultraviolet lamps 122 is located above another two of the tubes 124 .
  • a substantially equal amount of ultraviolet light enters the tubes 124 because of substantially equal spacing of the lamps 122 over the tubes 124 .
  • More ultraviolet light reflects from the mirror 126 and enters the tubes 124 from an opposing side.
  • the ultraviolet light results in a change of some of the oxygen gas within the tubes 124 to ozone gas.
  • a mixture of oxygen gas and ozone gas flows around the pipe 128 and leaves the tubes 124 through the openings 130 , from where the mixture flows through the pipe 128 out of the housing 120 .
  • While ozone is formed within the tubes 124 the nitrogen in the area around the tubes 124 suppresses ozone generation outside of the tubes 124 . This reduces exposure of ozone to people, thereby making the ozone generator 64 safe to operate, and reduces the chance of ozone degradation of components of the ozone generator 64 located externally of the tubes 124 .
  • the openings 130 are restrictions in the path of the mixture of oxygen and ozone leaving the tubes 124 . Because of the restrictions provided by the openings 120 , free flow of gas through the tubes 124 is restricted. Because of restrictions provided by the openings 120 , the gas remains within the tubes 124 for longer and the flow thereof is more evenly distributed between the tubes 124 . The residence time of the mixture within the tubes 124 is also increased.
  • FIG. 8 is a graph of ozone generation.
  • a horizontal axis of FIG. 8 is the rate at which the loadlock chamber is filled in Torr per minute. The higher the valve on the horizontal axis, the faster the loadlock chamber will be filled.
  • a backfill rate of 60 Torr per minute, for example, means that the loadlock chamber is filled to 600 Torr within 10 minutes.
  • the loadlock is preferably filled to 600 Torr within 20 minutes to maintain throughput, i.e. the rate on the horizontal axis is preferably at least 30.
  • a vertical axis of the FIG. 8 graph is ozone concentration in parts per million. It can be seen from the graph that the ozone concentration is higher for lower filling rates of the load lock chamber. Furthermore, there is an appreciable increase in ozone concentration for filling rates below 50 (i.e. a filling time of more than 12 minutes). The filling rate is therefore preferably between 20 Torr per minutes and 50 Torr per minute for purposes discussed with reference to FIG. 8 alone.
  • FIG. 9 is a graph of encapsulation of a wafer with an oxide formed with ozone gas.
  • a horizontal axis of the FIG. 9 graph is the ozone concentration in parts per million and the vertical axis is oxide thickness as measured with a single wavelength ellipsometry technique.
  • the wafer is maintained at about room temperature and is exposed to the air and ozone gas mixture for 12 minutes.
  • the ozone concentration is preferably at least 250 parts per million. From FIG. 9 can thus be gathered that the ozone concentration is preferably between 250 parts per million and 350 parts per million. Referring again to FIG.
  • the loadlock is preferably filled at a rate of about 45 Torr per minute.
  • an ozone source may, for example, be a contained source of ozone located externally of a loadlock chamber.
  • an ozone source such as an ozone generator may, for example, be located within a loadlock chamber.

Abstract

According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates to a method of and a system for sealing an epitaxial silicon layer formed on a semiconductor wafer. [0002]
  • 2. Discussion of Related Art [0003]
  • Integrated circuits are formed in and on silicon and other semiconductor wafers. Wafers are made by extruding an ingot from a silicon bath and sawing the ingot into multiple wafers. In the case of silicon, the material of the wafers is monocrystalline. An epitaxial silicon layer is then formed on the monocrystalline material of the wafer. The epitaxial silicon layer is typically doped with boron and has a dopant concentration of about 1×10[0004] 16 atoms per centimeter cube. A typical epitaxial silicon layer is about five microns thick. The material of the epitaxial silicon layer has better controlled properties than the monocrystalline silicon for purposes of forming semiconductor devices therein and thereon.
  • Once the epitaxial silicon layer is formed, the wafer is removed from the wafer processing chamber and exposed to ambient air. The air oxidizes the exposed epitaxial silicon layer to form a native oxide layer thereon. The epitaxial silicon layer and the native oxide layer are exposed to contaminants in the air and are usually filled with impurities and particles. When semiconductor devices are formed on a surface which is filled with impurities, the electronic devices often fail. [0005]
  • It has been suggested that exposure of an epitaxial silicon layer to ozone gas will provide an efficient process for forming a very pure oxide layer on the epitaxial silicon layer. [0006]
  • SUMMARY OF THE INVENTION
  • According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. An epitaxial silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system. [0007]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention is further described by way of example with reference to the accompanying drawings wherein: [0008]
  • FIG. 1 is a plan view of a system for processing a wafer; [0009]
  • FIG. 2 is a diagram of a loadlock assembly forming part of the system and illustrates a loadlock chamber thereof in sectioned side view; [0010]
  • FIG. 3 is a flow chart of how the system is operated; [0011]
  • FIG. 4 is a time chart of how the system operates; [0012]
  • FIG. 5 is a cross-sectional side view of a wafer which is processed according to the invention; [0013]
  • FIG. 6 is a cross-sectional end view of an ozone generator which is used in the loadlock assembly; [0014]
  • FIG. 7 is a cross-sectional side view of the ozone generator; [0015]
  • FIG. 8 is a graph of ozone concentration against backfill rate; and [0016]
  • FIG. 9 is a graph of oxide formation against ozone concentration. [0017]
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention relates to a method whereby a epitaxial silicon layer formed on a silicon wafer is sealed with an oxide formed due to exposure to ozone gas. A plurality of the wafers are located in a batch in a loadlock chamber and exposed to ozone gas under controlled conditions. The ozone gas forms a stable and clean oxide layer on the epitaxial silicon layer of each wafer. The oxide layer can later be removed to leave the epitaxial silicon layer exposed and containing substantially no impurities. There are certain advantages for processing the wafers in the loadlock chamber. One advantage is that another chamber which is designated for a step in an existing process does not have to be dedicated for exposing the wafers to ozone gas. Another advantage is that such a system is relatively safe because there is a substantially reduced likelihood that the ozone gas will mix with hydrogen gas within the system and cause an explosion, in particular because the pressure within the loadlock chamber is lower than a chamber in the system where hydrogen gas is used. The system is also safe because the pressure within the loadlock chamber is always below atmospheric pressure of an area around the loadlock chamber when ozone gas is within the loadlock chamber so that there is reduced likelihood that the ozone gas will escape to a surrounding area and cause an explosion. Another advantage is that the overall time taken to process wafers is maintained. [0018]
  • FIG. 1 of the accompanying drawings illustrates a [0019] system 10 for processing a semiconductor wafer. The system 10 includes a factory integration unit 12, first and second batch loadlock assemblies 14A and 14B, a transfer chamber 18, first, second, and third wafer processing chambers 20A, 20B, and 20C, and a cooldown chamber 22.
  • FIG. 2 illustrates one of the [0020] loadlock assemblies 14 in more detail. The loadlock assembly 14 includes a loadlock chamber 24, a cassette elevator 26, a wafer cassette 28, a pump 30, and apparatus 32 for supplying gasses into the loadlock chamber 24.
  • The [0021] loadlock chamber 24 defines an enclosure 34 and has a door opening 36 on one side thereof and a slitvalve opening 38 on an opposing side thereof. The factory integration unit 12 mates with the loadlock chamber 24 over the door opening 36. A door 40 is mounted to the loadlock chamber 24 for movement between a position as shown in FIG. 2 wherein the door 40 closes the door opening 36, and a position wherein the door opening 36 is open so that the confines of the factory integration unit 12 are in communication with the enclosure 34.
  • The [0022] transfer chamber 18 mates with the loadlock chamber 24 over the slitvalve opening 38. A slitvalve 42 is mounted to the loadlock chamber 24 for movement between a position as shown in FIG. 2 wherein the slitvalve 42 closes the slitvalve opening 38, and a position wherein the slitvalve opening 38 is open so that the enclosure 34 is in communication with the confines of the transfer chamber 18.
  • The [0023] cassette elevator 26 includes a shaft 44 and a support plate 46. The shaft 44 extends through an opening in a base of the loadlock chamber 24. A seal (not shown) is located between the shaft 44 and the base of the loadlock chamber 24. The support plate 46 is secured to an upper end of the shaft 44.
  • The [0024] wafer cassette 28 includes a frame 48 with a plurality of fins 50 located on the frame. The fins 50 are positioned relative to one another so as to be jointly capable of supporting a total of twenty-five wafers above one another. The wafer cassette 28 is located on the support plate 46. The wafer cassette 28 can be elevated by extending the shaft 44 into the loadlock chamber 24, and lowered by retracting the shaft 44 from the loadlock chamber 24. By elevating or lowering the wafer cassette 28, a respective one of the wafers 52 can be aligned with the slitvalve opening 38 and can be removed from the loadlock chamber 24 through the slitvalve opening 38.
  • The [0025] pump 30 has a low-pressure side 54 and a high-pressure side 56. An exhaust line 58 has one end that extends into an opening in a base of the loadlock chamber 24, and an opposed end connected to the low-pressure side 54 of the pump 30. The pump 30 can therefore be used for pumping a gas from the enclosure 34.
  • The [0026] apparatus 32 includes a source of nitrogen 60, a source of oxygen 62, an ozone generator 64, a nitrogen supply valve 68, and an ozone supply valve 70.
  • The source of [0027] nitrogen 60 is connected to the nitrogen supply valve 68. The nitrogen supply valve 68 is, in turn, connected to a nitrogen supply line 74. An opposing end of the nitrogen supply line 74 extends into an opening in an upper wall of the loadlock chamber 24. When the valve 68 is open, nitrogen gas from the source of nitrogen 60 can therefore be supplied to the enclosure 34. A diffuser (not shown) is located in the nitrogen supply line 74 to reduce the speed of the nitrogen gas.
  • The source of [0028] oxygen 62 may, for example, be substantially pure oxygen gas or may be air. It has been found that even filtered air is not as free of impurities as substantially pure oxygen. The oxygen is typically about 99.999% pure. Substantially pure oxygen may thus be preferred. The ozone generator 64 is connected to the source of oxygen 62.
  • When oxygen gas from the source of [0029] oxygen 62 is supplied to the ozone generator the ozone generator 64 generates ozone gas. The ozone generator 64 is, in turn, connected to the ozone supply valve 70. An ozone supply line 76 is connected to the ozone supply valve 70. An opposing end of the ozone supply line 76 extends into an opening in the upper wall of the loadlock chamber 24. When the valve 70 is open, ozone gas generated by the ozone generator 64 can be supplied to the enclosure 34. A diffuser (not shown) is located in the ozone supply line 76 to reduce the speed of the ozone gas.
  • A [0030] pressure detector 72 is connected to the exhaust line 58. The pressure detector 72 can detect the pressure within the exhaust line 58, and therefore also the pressure within the enclosure 34.
  • A [0031] controller 80 is used for controlling various components of the system 10 shown in FIG. 1, including the pump 30, the ozone generator 64, and the valves 68 and 70 shown in FIG. 2. The controller 80 receives input from the pressure detector 72 and controls all the components based on the pressure detected by the pressure detector 72 and other variables as will be described hereinbelow. The controller 80 is typically a computer having a processor which is programmed to execute a program which controls all the components of the system 10. The program includes processor executable code and is typically stored on a disk or other computer readable medium and then loaded into memory of the computer from where the processor of the computer reads and executes the program to control the components of the system 10. Particular features of the program and how it is constructed will be evident to one skilled in the art from the discussion that follows.
  • Referring again to FIG. 1, it can be seen that each [0032] wafer processing chamber 20A, 20B, or 20C leads directly off the transfer chamber 18. A respective slitvalve 82A, 82B, and 82C is mounted to open or close communication between the transfer chamber 18 and a respective one of the wafer processing chambers 20A, 20B or 20C.
  • The [0033] cooldown chamber 22 also leads off the transfer chamber 18 but no slitvalve is provided to open and close communication between the transfer chamber 18 and the cooldown chamber 22.
  • A [0034] robot 84 is located within the transfer chamber 18. The robot 84 has a blade 86 which, when the robot 84 is operated, can transfer a wafer from one of the chambers 20, 22, or 24 to another. A susceptor 88 is located in each one of the chambers 20 and 22, on which the wafer can be located by the blade 86. The slitvalves 82 and the robot 84 are also under control of the controller 80 shown in FIG. 2.
  • One example of how the [0035] controller 80 controls the system 10 is now described with reference to FIGS. 1 and 2 jointly. FIG. 3 is a flow chart which assists in illustrating how the system 10 is operated.
  • The [0036] slitvalves 42 are initially closed so that the confines of the transfer chamber 18 are not in communication with the loadlock chambers 24. The loadlock chamber 18 is initially evacuated to remove contamination. The loadlock chamber 18 is then backfilled with an inert gas such as nitrogen. The slitvalves 82 are open so that the wafer processing chambers 20 are in communication with the transfer chamber 18. The transfer chamber 18, the wafer processing chamber 20, and the cooldown chamber 22 are filled with an inert gas such as nitrogen gas and are at atmospheric pressure. The door 40 of the first loadlock assembly 14A is open.
  • A robot (not shown) located within the [0037] factory integration unit 12 then loads a total of twenty-five wafers on the wafer cassette 28 of the first loadlock assembly 14A. (Step 1). The door 40 is then closed so that the wafers 52 are isolated within the loadlock chamber 24. (Step 2).
  • The [0038] pump 30 is then switched on so that air passes from the enclosure 34 through the exhaust line 58 through the pump 30. (Step 3). The valves 68, and 70 are closed so that the enclosure 34 is pumped down to a pressure of about 5 Torr.
  • The [0039] pump 30 is then switched off. (Step 4). The valve 68 is then opened. (Step 5). Nitrogen then flows into the enclosure 34 until the pressure within the enclosure 34 is substantially the same as the pressure within the transfer chamber 18. The valve 68 is then closed. (Step 6).
  • The [0040] slitvalve 42 is then opened. (Step 7). The robot 84 then removes three wafers consecutively from the wafer cassette 28 and locates one wafer within the first wafer processing chamber 20A, another wafer within the second wafer processing chamber 20B, and a further wafer within the third wafer processing chamber 20C. (Step 8). The slitvalves 82 are then closed so that the wafer processing chambers 20 are isolated from the transfer chamber 18. (Step 9). An epitaxial silicon layer is then formed on the wafer in each processing chamber 20. (Step 10). A mixture of gasses is introduced into each one of the wafer processing chambers 20. One of these gasses typically includes hydrogen. Another one of the gasses is a source of silicon such as silane, dichlorosilane, or trichlorosilane. The source of silicon reacts with the hydrogen to form an epitaxial layer. Another one of the gasses is typically B2H6 which provides boron for purposes of doping the epitaxial silicon layer. Heat lamps (not shown) heat the wafers within the wafer processing chambers 20 to a temperature of between 600° C. and 1300° C.
  • Once the formation of the epitaxial silicon layer on one of the wafers is finalized, the processing gasses within the [0041] respective chambers 20 are replaced by pure hydrogen gas to purge the chambers 20. (Step 11). The respective slitvalve 82 is then opened. (Step 12). The respective wafer is transferred, utilizing the robot 84, to the cooldown chamber 22. (Step 13). Transfer of the wafer takes about twenty seconds. The wafer remains within the cooldown chamber 22 for about sixty seconds. (Step 14). The robot 84 then transfers the wafer from the cooldown chamber 22 back to the wafer cassette 28. (Step 15). The wafer is thus transferred from the chambers 20 to the wafer cassette 28 without ever being exposed to oxygen or any other gas that can form an oxide on the epitaxial silicon layer.
  • The process of forming an expitaxial silicon layer on each wafer is continued until all the wafers are processed in a similar manner and all the wafers are located back on the [0042] wafer cassette 28. It takes between one and two hours to process twenty-five wafers when forming a 5 micron thick epitaxial silicon layer on each wafer. While the wafers from the first loadlock assembly 14A are processed, more wafers can be located on the wafer cassette 28 of the second loadlock assembly 14B.
  • Once the wafers are located on the [0043] wafer cassette 28 of the first loadlock assembly 14A, the slitvalve 38 thereof is closed. (Step 16). The wafers 52 are then typically at a temperature of less than 100° C., but this temperature can vary depending on the time spent in the cooldown chamber 22.
  • The [0044] pump 30 is then again switched on so that nitrogen gas then flows out of the enclosure 34. (Step 17). The enclosure 34 is pumped down to a pressure of about 5 Torr. The pump 30 is then switched off. (Step 18). The ozone generator 64 is then switched on and the valve 70 is opened so that an ozone gas and oxygen gas mixture flows into the top of the enclosure 34. (Step 19). The ozone gas and oxygen mixture continues to flow into the enclosure 34 until the pressure within the enclosure 34 reaches about 600 Torr. The valve 70 is then closed and the ozone generator 64 is switched off. (Step 20).
  • The [0045] wafers 52 are then simultaneously exposed to the ozone gas within the enclosure 34. Exposure of the epitaxial silicon layer on the wafer 52 results in oxidation of the epitaxial silicon layer. The wafers 52 are exposed to the ozone gas for a period from one to fifteen minutes. The wafers 52 are simply “soaked” in the ozone gas i.e., there are no additional sources of excitation which, for example, create a plasma or create certain photo effects. An oxide layer forms over the epitaxial silicon layer of each wafer and has a thickness of about 10Å to about 15Å, as measured by a multiple wavelength ellipsometry technique, for exposure to ozone gas of about fifteen minutes. The oxide layer that forms on the wafer is extremely pure because of the controlled conditions to which the wafers 52 are exposed, including the purity of the ozone gas and oxygen gas mixture to which the wafers 52 are exposed.
  • As mentioned previously, hydrogen is used within the [0046] wafer processing chamber 20. Hydrogen is highly explosive when mixed with ozone or oxygen. However, for the hydrogen in the processing chambers 20 to mix with the ozone within the enclosure 34, the system 10 has to fail simultaneously in a number of respects. First, there should be hydrogen within one of the wafer processing chambers 20. Second, the hydrogen should leak past a respective slitvalve 82 of the relevant wafer processing chamber 20. Leakage of hydrogen past the slitvalve 82 would only occur if the slitvalve 82 does not seal sufficiently on the wafer processing chamber or when the slitvalve 82 is not closed when hydrogen is introduced into the wafer processing chamber 20. Third, it is required that ozone be present within the enclosure 34. Fourth, ozone should leak from the enclosure 34 into the transfer chamber 18. Because the enclosure 34 is maintained at a pressure below that of the transfer chamber 18, it is highly unlikely that there would be any flow of gasses from the enclosure 34 into the transfer chamber 18.
  • Furthermore, it should be noted that the pressure within the enclosure [0047] 34 never goes over atmospheric pressure so that there is a substantially reduced likelihood that ozone gas can escape from the enclosure 34 to a surrounding area and cause exposure of personnel.
  • It should also be noted that, in the embodiment described, ozone is only present within the [0048] apparatus 32 when generated by the ozone generator 64 which is only while the enclosure 34 is being filled with ozone. There is therefore no contained source of ozone (other than in the loadlock chambers 24) which may leak and cause exposure to personnel or other reactive gasses. Ozone gas is thus generated at the point of use.
  • The [0049] pump 30 is then again switched on so that the pressure within the enclosure 34 reduces to about 5 Torr. (Step 21). The ozone gas flowing through the pump 30 is pumped to a location distant from the system 10, where the ozone gas is neutralized. The ozone gas may for example be neutralized by treatment with a chemical to form oxygen, be scrubbed in a fluidized bed of silica, or be scrubbed in another liquid system.
  • The [0050] valve 68 is then opened so that the enclosure 34 is filled with nitrogen gas. (Step 22). The door 40 is then opened and the wafers 52 are transferred from the enclosure 34 into the factory integration unit 12. The factory integration unit 12 is filled with air. (Step 23). The air within the factory integration unit 12 does not form an oxide layer on the epitaxial silicon layer because of the oxide layer which is already formed thereon due to exposure to ozone.
  • It takes about twenty-five minutes to process the wafers within the first loadlock assembly [0051] 14A, as measured from when the slitvalve 42 is closed until the wafers 52 are removed from the loadlock chamber 24. The time taken to process twenty-five wafers by the first loadlock assembly 14A is less than the time taken to process twenty-five wafers within the wafer processing chambers 20 and cooling the wafer down in the cooldown chamber 22, because the wafers are processed in batch. As illustrated in FIG. 4 the first loadlock assembly 14A can thus be used in an epitaxial silicon cycle wherein wafers are transferred to the wafer processing chamber 20 and the cooldown chamber 22. The first loadlock assembly 14A can then be used in a oxide cycle wherein the wafer is exposed to ozone gas. At the same time when the first loadlock assembly 14A is used for an oxide cycle, the second loadlock assembly 14B can be used for a epitaxial silicon cycle, whereafter the second loadlock assembly 14B can be used for an oxide cycle. When the second loadlock assembly 14B is used in the oxide cycle, the first loadlock assembly 14A can be used in a epitaxial silicon cycle. It can thus be seen that, because the oxide cycles are shorter than the epitaxial silicon cycles, there is no lapse in time from one epitaxial silicon cycle to a next epitaxial silicon cycle.
  • FIG. 5 illustrates a [0052] wafer 100 which is processed in accordance with the invention. The wafer includes a monocrystalline substrate 102 on which an epitaxial silicon layer 104 is formed. A silicon dioxide layer 106 is formed on the epitaxial silicon layer 104. The silicon dioxide layer can later be removed to leave the expitaxial silicon layer 104 exposed and containing substantially no impurities. The silicon dioxide layer can, for example, be removed in a aqueous solution of hydrogen fluoride.
  • FIG. 6 and FIG. 7 illustrate the [0053] ozone generator 64 in more detail. The ozone generator 64 includes a housing 120, two ultraviolet lamps 122, four quartz tubes 124, an inlet pipe 126, and an outlet pipe 128.
  • The [0054] housing 120 is leak tight and dust proof. A mirror 126 is located on a lower surface of the housing 120.
  • The [0055] ultraviolet lamps 122 are located within the housing 120 on a side thereof opposing the mirror 126. Electrical connectors 128 extend into the housing 120 to the ultraviolet lamps 122. The ultraviolet lamps 122 can be energized by supplying electricity through the cables 128. A leak tight interface exists between the housing 120 and the cables 128 where the cables extend into the housing 120.
  • Each [0056] pipe 126 or 128 extends into the housing 120. A leak tight interface also exists between each pipe 126 or 128 and the housing 120 where the pipe 126 or 128 extends into the housing 120. The pipes 126 and 128 are located on opposing sides of the housing 120 as can be seen in FIG. 7. The inlet pipe 126 has an inlet opening therein. The pipe 126 interconnects ends of the tubes 124 to one another. The pipe 128 extends through ends of the tubes 124 opposing the ends that are interconnected by the pipe 126. Small openings 130 are formed in the pipe 128 within the tubes 124. Each opening 130 is typically about 2 mm in diameter. The openings 130 are located facing away from a flow passage of a gas flowing through the tubes 126 so as to avoid a flow channel within each tube 126 and to ensure mixing of a gas flowing through each tube 126.
  • The [0057] oxygen source 62 is connected to the inlet tube 126 through a regulator valve 132. The regulator valve 132 can be adjusted so as to control flow to the inlet tube 126.
  • A [0058] nitrogen source 132 is connected to the housing 120. A purge gas outlet 134 is also provided out of the housing 120.
  • Nitrogen from the [0059] nitrogen source 132 flows through the housing 120 in an area around the tubes 124. The ultraviolet lamps 122 are switched on by providing electricity through the cables 128. Oxygen from the oxygen source 62 flows through the regulator valve 132 and the pipe 126 to the tubes 124. Ultraviolet light is transmitted by the ultraviolet lamps 122. The quartz of the tubes 124 is transmissive so that the ultraviolet light enters the tubes 124. One of the ultraviolet lamps is located above two of the tubes 124 and another one of the ultraviolet lamps 122 is located above another two of the tubes 124. A substantially equal amount of ultraviolet light enters the tubes 124 because of substantially equal spacing of the lamps 122 over the tubes 124. More ultraviolet light reflects from the mirror 126 and enters the tubes 124 from an opposing side. The ultraviolet light results in a change of some of the oxygen gas within the tubes 124 to ozone gas. A mixture of oxygen gas and ozone gas flows around the pipe 128 and leaves the tubes 124 through the openings 130, from where the mixture flows through the pipe 128 out of the housing 120. While ozone is formed within the tubes 124, the nitrogen in the area around the tubes 124 suppresses ozone generation outside of the tubes 124. This reduces exposure of ozone to people, thereby making the ozone generator 64 safe to operate, and reduces the chance of ozone degradation of components of the ozone generator 64 located externally of the tubes 124.
  • The [0060] openings 130 are restrictions in the path of the mixture of oxygen and ozone leaving the tubes 124. Because of the restrictions provided by the openings 120, free flow of gas through the tubes 124 is restricted. Because of restrictions provided by the openings 120, the gas remains within the tubes 124 for longer and the flow thereof is more evenly distributed between the tubes 124. The residence time of the mixture within the tubes 124 is also increased.
  • FIG. 8 is a graph of ozone generation. A horizontal axis of FIG. 8 is the rate at which the loadlock chamber is filled in Torr per minute. The higher the valve on the horizontal axis, the faster the loadlock chamber will be filled. A backfill rate of 60 Torr per minute, for example, means that the loadlock chamber is filled to 600 Torr within 10 minutes. The loadlock is preferably filled to 600 Torr within 20 minutes to maintain throughput, i.e. the rate on the horizontal axis is preferably at least 30. [0061]
  • A vertical axis of the FIG. 8 graph is ozone concentration in parts per million. It can be seen from the graph that the ozone concentration is higher for lower filling rates of the load lock chamber. Furthermore, there is an appreciable increase in ozone concentration for filling rates below 50 (i.e. a filling time of more than 12 minutes). The filling rate is therefore preferably between 20 Torr per minutes and 50 Torr per minute for purposes discussed with reference to FIG. 8 alone. [0062]
  • FIG. 9 is a graph of encapsulation of a wafer with an oxide formed with ozone gas. A horizontal axis of the FIG. 9 graph is the ozone concentration in parts per million and the vertical axis is oxide thickness as measured with a single wavelength ellipsometry technique. The wafer is maintained at about room temperature and is exposed to the air and ozone gas mixture for 12 minutes. There is an increase in oxide thickness with ozone concentration up to an ozone concentration of about 400 parts per million. In order to obtain an oxide thickness which is sufficiently thick the ozone concentration is preferably at least 250 parts per million. From FIG. 9 can thus be gathered that the ozone concentration is preferably between 250 parts per million and 350 parts per million. Referring again to FIG. 8, it can be seen that such an ozone concentration requires a filling rate of between 33 Torr per minute and 45 Torr per minute. In order to maintain an ozone concentration of at least 250 parts per million and an appreciable oxide thickness, the loadlock is preferably filled at a rate of about 45 Torr per minute. [0063]
  • While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described, since modifications may occur to those ordinarily skilled in the art. In another embodiment an ozone source may, for example, be a contained source of ozone located externally of a loadlock chamber. In another embodiment, an ozone source such as an ozone generator may, for example, be located within a loadlock chamber. [0064]

Claims (53)

What is claimed:
1. A method of processing a wafer, which includes:
(a) locating a wafer in a wafer processing chamber of a system for processing a wafer;
(b) forming a silicon layer on the wafer while located in the wafer processing chamber;
(c) transferring the wafer from the wafer processing chamber to a loadlock chamber of the system;
(d) closing off communication between the processing chamber and the loadlock chamber;
(e) exposing the wafer to ozone gas while located in the loadlock chamber; and
(f) removing the wafer from the loadlock chamber out of the system.
2. A method according to
claim 1
wherein the system includes a transfer chamber leading off the loadlock chamber, and a plurality of wafer processing chambers leading off the transfer chamber, the wafer being transferred from the wafer processing chamber through the transfer chamber to the loadlock chamber.
3. A method according to
claim 1
which includes:
(g) loading a plurality of wafers in the loadlock chamber, wherein:
step (a) includes transferring a respective wafer from the loadlock chamber into a respective one of the processing chambers;
step (b) includes forming a silicon layer on each one of the respective wafers, wherein a silicon layer is formed on one of the wafers in one of the chambers while a silicon layer is formed on another wafer in another one of the chambers;
step (c) includes transferring the plurality of wafers to the loadlock chamber;
step (d) includes closing off communication between the loadlock chamber and the transfer chamber;
step (e) includes exposing the wafers together to ozone gas while located in the loadlock chamber; and
step (f) includes removing the plurality of wafers from the loadlock chamber out of the system.
4. A method according to
claim 3
wherein the time taken from when step (a) is started until step (d) is completed is at least twice as long as the time from when step (d) is completed until step (f) is completed.
5. A method according to
claim 3
wherein the loadlock chamber is a first loadlock chamber and the plurality of wafers is a first plurality of wafers, the method including:
(h) locating a second plurality of wafers in a second loadlock chamber;
(i) transferring a respective wafer from the second loadlock chamber into a respective one of the processing chambers;
(j) forming a silicon layer on each one of the wafers of the second plurality of wafers located in one of the chambers;
(k) transferring the second plurality of wafers the second loadlock chamber;
(1) closing off communication between the second loadlock chamber and the transfer chamber;
(m) exposing the second plurality of wafers together to ozone gas while located in the second loadlock chamber; and
(n) removing the second plurality of wafers from the second loadlock chamber out of the system.
6. A method according to
claim 5
wherein steps (d), (e) and (f) are carried out entirely within a time period from when step (i) is started until step (l) is completed.
7. A method according to
claim 5
wherein, when step (e) is carried out, the pressure within the first loadlock chamber is below the pressure in the transfer chamber.
8. A method according to
claim 2
wherein the pressure within the loadlock chamber remains below the pressure within the transfer chamber while the wafer is exposed to the ozone gas.
9. A method according to
claim 1
wherein the system includes a cooldown chamber, the wafer being transferred from the wafer processing chamber to the cooldown chamber and from the cooldown chamber to the loadlock chamber.
10. A method according to
claim 1
wherein a plurality of wafers, each having a silicon layer formed thereon, are located in the loadlock chamber and the plurality of wafers are simultaneously exposed to the ozone gas.
11. A method according to
claim 1
which includes introducing the ozone gas from outside the loadlock chamber into the loadlock chamber.
12. A method according to
claim 1
which includes generating the ozone gas.
13. A method of processing a wafer, which includes:
(a) locating a wafer in a wafer processing chamber of a system from processing a wafer;
(b) forming a silicon layer on the wafer while located in the wafer processing chamber;
(c) transferring the wafer processing chamber to a loadlock chamber of the system;
(d) closing off communication between the processing chamber and the loadlock chamber;
(e) exposing the wafer to ozone gas while located in the loadlock chamber;
(f) removing ozone from the loadlock chamber, the pressure in the loadlock chamber during (e) and (f) remaining below the pressure in the processing chamber; and
(g) removing the wafer from the loadlock chamber out of the system.
14. A method according to
claim 13
wherein hydrogen gas is present within the processing chamber of any given time between when (f) is started and (g) ends.
15. A method according to
claim 13
wherein the pressure within the loadlock chamber remains below atmospheric pressure during (e) and (f).
16. A method according to
claim 1
wherein substantially no oxide layer forms on the silicon layer before exposure to the ozone gas.
17. A loadlock assembly which includes:
a loadlock chamber having a first opening for inserting a wafer and a second opening for removing the wafer;
a holder within the loadlock chamber which is capable of holding the wafer;
a pump having a low-pressure side connected to the loadlock chamber; and
an ozone source which provides ozone gas to which the wafer is exposed when held by the holder.
18. A loadlock assembly according to
claim 17
wherein the ozone source includes a ozone generator.
19. A loadlock assembly according to
claim 18
wherein the ozone generator is located externally of the loadlock chamber and is connected thereto.
20. A loadlock assembly according to
claim 19
wherein the ozone generator includes an ultraviolet lamp and a vessel wherein ultraviolet light from the lamp passes into the vessel where ozone is created.
21. A loadlock assembly according to
claim 19
wherein the ozone source is located externally of the loadlock chamber and connected thereto.
22. A loadlock assembly according to
claim 21
wherein the ozone source includes an ozone generator including at least one ultraviolet lamp, at least one container having a wall which is transmissive to ultraviolet light the ultraviolet lamp being positioned so that ultraviolet light radiated thereby enters the container through the wall, an inlet through which an oxygen containing gas can enter the container where the oxygen containing gas is at least partially converted to ozone gas by the ultraviolet light, and an outlet from which the ozone gas can leave the container and flow to the loadlock chamber.
23. A loadlock assembly according to
claim 22
wherein the container is a tube, the ozone generator including a plurality of tubes, each tube having a wall which is transmissive to ultraviolet light so that ultraviolet light can enter the tube, the inlet allows the oxygen containing gas into each tube and the outlet allows ozone gas out of each tube.
24. A loadlock assembly according to
claim 23
wherein the ozone generator includes a means for restricting the flow of gas out of the plurality of tubes so that the residence time of the gases in the tubes is increased.
25. A loadlock assembly according to
claim 24
wherein the restricting means includes a plurality of restrictions, each restriction being located between a respective tube and the outlet.
26. A loadlock assembly according to
claim 22
wherein the ozone generator includes a housing around the container.
27. A loadlock assembly according to
claim 26
which includes a purge gas source connected to the housing so that the purge gas source is capable of providing purge gas to an area within the housing and around the container.
28. A loadlock assembly according to
claim 17
wherein the holder is a cassette capable of holding a plurality of wafers.
29. A system for processing a semiconductor wafer, which includes:
a loadlock chamber;
a wafer holder in the loadlock chamber;
a wafer processing chamber;
a closure member which is movable between a first position which allows for a wafer to be transferred from the wafer processing chamber into the loadlock chamber, and a second position wherein the closure member substantially closes off communication between the loadlock chamber and the wafer processing chamber;
a pump having a low-pressure side connected to the loadlock chamber; and
an ozone source which produces ozone gas to which a wafer is exposed when located in the loadlock chamber.
30. A system according to
claim 29
which includes a transfer chamber leading off the loadlock chamber, and a plurality of wafer processing chambers leading off the transfer chamber, the wafer being transferred from the wafer processing chamber through the transfer chamber to the loadlock chamber.
31. A system according to
claim 30
wherein the loadlock chamber is a first loadlock chamber, the wafer holder is a first wafer cassette capable of holding a plurality of wafers, and the closure member is a first closure member, the system including:
a second loadlock chamber;
a second wafer cassette in the second loadlock chamber and capable of holding a plurality of wafers; and
a second closure members which is movable between a first position which allows for a wafer to be transferred from the wafer processing chamber through the transfer chamber to the second loadlock chamber, and a second position wherein the second closure member substantially closes off communication between the second loadlock chamber and the transfer chamber.
32. A system according to
claim 31
wherein the number of wafers that can be located on each wafer cassette is at least three times the total number of chambers.
33. A system according to
claim 32
which includes a cooldown chamber, a wafer being transferable from the wafer processing chamber via the cooldown chamber to the loadlock chamber.
34. A system according to
claim 29
wherein the ozone source is located externally of the loadlock chamber and connected thereto.
35. A system according to
claim 34
wherein the ozone source includes an ozone generator including at least one ultraviolet lamp, at least one container having a wall which is transmissive to ultraviolet light the ultraviolet lamp being positioned so that ultraviolet light radiated thereby enters the container through the wall, an inlet through which an oxygen containing gas can enter the container where the oxygen containing gas is at least partially converted to ozone gas by the ultraviolet light, and an outlet from which the ozone gas can leave the container and flow to the loadlock chamber.
36. A system according to
claim 35
wherein the container is a tube, the ozone generator including a plurality of tubes, each tube having a wall which is transmissive to ultraviolet light so that ultraviolet light can enter the tube, the inlet allows the oxygen containing gas into each tube and the outlet allows ozone gas out of each tube.
37. A system according to
claim 36
wherein the ozone generator includes at least one restriction so that the pressure of the ozone gas is higher before the restriction than after the restriction.
38. A system according to
claim 37
which includes a plurality of restrictions, each restriction being located between a respective tube and the outlet.
39. A system according to
claim 38
wherein the ozone generator includes a housing around the tubes.
40. A system according to
claim 39
which includes a purge gas source connected to the housing so that the purge gas source is capable of providing purge gas to an area within the housing and around the container.
41. A system according to
claim 29
which includes a cassette, located within the loadlock chamber, capable of holding a plurality of wafers.
42. A system according to
claim 29
which includes a controller which has processor executable code which controls the pump and the ozone source.
43. A system according to
claim 42
wherein the processor executable code maintains the loadlock at a lower pressure than on a side of the closure member opposing the loadlock at all times when the wafer is exposed to the ozone gas.
44. A system according to
claim 43
wherein the processor executable code maintains the loadlock below atmospheric pressure at all times when the wafer is exposed to ozone gas.
45. A system according to
claim 43
wherein the processor executable code:
(i) controls the closure member by opening the closure member;
(ii) controls a robot so that the robot then transfers the wafer from the wafer processing chamber into the loadlock chamber;
(iii) then closes the closure member; and
(iv) controls the ozone source by then exposing the wafer to the ozone gas when located in the wafer processing chamber.
46. An ozone generator, which includes:
a plurality of tubes that are transmissive to ultraviolet light;
an inlet through which oxygen gas can be provided into the tubes;
an ultraviolet lamp, located externally of the tubes, which can radiate ultraviolet light, the ultraviolet lamp being positioned so that the ultraviolet light enters the tubes and generates ozone gas from the oxygen gas in the tubes; and
an outlet through which the ozone gas can flow out of the tubes.
47. An ozone generator according to
claim 46
which includes at least one restriction in a flow path of the ozone gas which ensures more even distribution of flow of gas between the tubes.
48. An ozone generator according to
claim 46
which includes a plurality of restrictions, each restriction being located in a flow path of the ozone gas between a respective one of the tubes and the outlet.
49. An ozone generator according to
claim 46
which includes a housing around the tubes, a purge gas inlet into the housing, and a purge gas outlet out of the housing.
50. An ozone generator according to
claim 46
wherein the tubes are made of quartz.
51. An ozone generator, which includes:
a housing;
a container, located within the housing, which is transmissive to ultraviolet light;
an inlet into the housing to the container so that oxygen gas can be provided into the housing to the container;
a lamp which generates ozone gas from the oxygen gas to the container; and
an outlet from the container out of the housing through which the ozone gas can flow from the container out of the housing.
52. An ozone generator according to
claim 51
wherein some of the ultraviolet light is transmitted directly from the ultraviolet lamp into the container, the ozone generator further including a mirror on a side of the container opposing the ultraviolet lamp from which more of the ultraviolet light reflects before entering the container.
53. An ozone generator, which includes:
a housing having a purge gas inlet and a purge gas outlet;
a container, located within the housing, which is transmissive to ultraviolet light;
an inlet into the housing to the container so that oxygen gas can be provided into the housing to the container, the inlet having a leak tight interface with the housing;
an ultraviolet lamp located within the housing;
electrical wiring extending into the housing to the ultraviolet lamp, the electrical wiring having a leak tight interface with the housing, wherein electrical power can be supplied through the wiring to the ultraviolet lamp so that the ultraviolet lamp can be energized and radiate ultraviolet light, the ultraviolet lamp being positioned so that the ultraviolet light can enter the container and generate ozone gas from the oxygen gas; and
an outlet from the container out of the housing through which the ozone gas can flow from the container out of the housing, the outlet having a leak tight interface with the housing.
US09/350,805 1999-07-09 1999-07-09 Method of sealing an epitaxial silicon layer on a substrate Expired - Fee Related US6376387B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US09/350,805 US6376387B2 (en) 1999-07-09 1999-07-09 Method of sealing an epitaxial silicon layer on a substrate
EP00114548A EP1067585A3 (en) 1999-07-09 2000-07-06 Method and a system for sealing an epitaxial silicon layer on a substrate
TW089113475A TW504730B (en) 1999-07-09 2000-07-07 Method and a system for processing a wafer
KR1020000039068A KR100746380B1 (en) 1999-07-09 2000-07-08 Method and a system for sealing an epitaxial silicon layer on a substrate
JP2000208618A JP4640879B2 (en) 1999-07-09 2000-07-10 Method for processing a wafer and system for processing a semiconductor wafer
US10/076,250 US6685779B2 (en) 1999-07-09 2002-02-11 Method and a system for sealing an epitaxial silicon layer on a substrate
KR1020060128514A KR100713264B1 (en) 1999-07-09 2006-12-15 Method and a system for sealing an epitaxial silicon layer on a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/350,805 US6376387B2 (en) 1999-07-09 1999-07-09 Method of sealing an epitaxial silicon layer on a substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/076,250 Division US6685779B2 (en) 1999-07-09 2002-02-11 Method and a system for sealing an epitaxial silicon layer on a substrate

Publications (2)

Publication Number Publication Date
US20010014541A1 true US20010014541A1 (en) 2001-08-16
US6376387B2 US6376387B2 (en) 2002-04-23

Family

ID=23378260

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/350,805 Expired - Fee Related US6376387B2 (en) 1999-07-09 1999-07-09 Method of sealing an epitaxial silicon layer on a substrate
US10/076,250 Expired - Lifetime US6685779B2 (en) 1999-07-09 2002-02-11 Method and a system for sealing an epitaxial silicon layer on a substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/076,250 Expired - Lifetime US6685779B2 (en) 1999-07-09 2002-02-11 Method and a system for sealing an epitaxial silicon layer on a substrate

Country Status (5)

Country Link
US (2) US6376387B2 (en)
EP (1) EP1067585A3 (en)
JP (1) JP4640879B2 (en)
KR (2) KR100746380B1 (en)
TW (1) TW504730B (en)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1344243A1 (en) * 2000-12-23 2003-09-17 Aixtron AG Method and device for treating semiconductor substrates
US6436194B1 (en) * 2001-02-16 2002-08-20 Applied Materials, Inc. Method and a system for sealing an epitaxial silicon layer on a substrate
KR100421036B1 (en) * 2001-03-13 2004-03-03 삼성전자주식회사 Wafer processing apparatus and wafer processing method using the same
JP2002338390A (en) * 2001-05-17 2002-11-27 Shin Etsu Handotai Co Ltd Method of producing silicon epitaxial wafer and vapor growth device
KR100863782B1 (en) * 2002-03-08 2008-10-16 도쿄엘렉트론가부시키가이샤 Substrate processing apparatus and substrate processing method
JP3999059B2 (en) * 2002-06-26 2007-10-31 東京エレクトロン株式会社 Substrate processing system and substrate processing method
US20040060899A1 (en) * 2002-10-01 2004-04-01 Applied Materials, Inc. Apparatuses and methods for treating a silicon film
US6833322B2 (en) * 2002-10-17 2004-12-21 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
US6790777B2 (en) * 2002-11-06 2004-09-14 Texas Instruments Incorporated Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
JP4344886B2 (en) * 2004-09-06 2009-10-14 東京エレクトロン株式会社 Plasma processing equipment
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US8454750B1 (en) * 2005-04-26 2013-06-04 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8137465B1 (en) 2005-04-26 2012-03-20 Novellus Systems, Inc. Single-chamber sequential curing of semiconductor wafers
US8282768B1 (en) 2005-04-26 2012-10-09 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
KR100706790B1 (en) * 2005-12-01 2007-04-12 삼성전자주식회사 Oxidation treatment apparatus and method
US8398816B1 (en) 2006-03-28 2013-03-19 Novellus Systems, Inc. Method and apparatuses for reducing porogen accumulation from a UV-cure chamber
KR100682756B1 (en) * 2006-03-17 2007-02-15 주식회사 아이피에스 Epitaxy apparatus and method of growing epitaxial layer using the same
US7867403B2 (en) * 2006-06-05 2011-01-11 Jason Plumhoff Temperature control method for photolithographic substrate
US20080072820A1 (en) * 2006-06-30 2008-03-27 Applied Materials, Inc. Modular cvd epi 300mm reactor
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US8465991B2 (en) * 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US8008166B2 (en) * 2007-07-26 2011-08-30 Applied Materials, Inc. Method and apparatus for cleaning a substrate surface
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
US8426778B1 (en) 2007-12-10 2013-04-23 Novellus Systems, Inc. Tunable-illumination reflector optics for UV cure system
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
US20100096569A1 (en) * 2008-10-21 2010-04-22 Applied Materials, Inc. Ultraviolet-transmitting microwave reflector comprising a micromesh screen
US10388546B2 (en) 2015-11-16 2019-08-20 Lam Research Corporation Apparatus for UV flowable dielectric
US10347547B2 (en) 2016-08-09 2019-07-09 Lam Research Corporation Suppressing interfacial reactions by varying the wafer temperature throughout deposition
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
CN110592666A (en) * 2019-08-27 2019-12-20 长江存储科技有限责任公司 Polycrystalline silicon film deposition system and method
CN111621758B (en) * 2020-05-28 2022-03-29 中国电子科技集团公司第四十八研究所 Wafer cooling device

Family Cites Families (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1037500A (en) * 1911-11-23 1912-09-03 Michael John Fritz Ozonizer.
US3766051A (en) * 1971-09-22 1973-10-16 Pollution Control Ind Inc Liquid cooled ozone generator
US3776023A (en) * 1971-12-22 1973-12-04 Monitor Labs Inc Calibration system for gas analyzers
US4341592A (en) 1975-08-04 1982-07-27 Texas Instruments Incorporated Method for removing photoresist layer from substrate by ozone treatment
US4409260A (en) 1979-08-15 1983-10-11 Hughes Aircraft Company Process for low-temperature surface layer oxidation of a semiconductor substrate
US5259881A (en) * 1991-05-17 1993-11-09 Materials Research Corporation Wafer processing cluster tool batch preheating and degassing apparatus
NL8603111A (en) 1986-12-08 1988-07-01 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE APPLYING A SILICONE SURFACE ON ITS SURFACE WITH FIELD OXIDE AREAS.
US4872947A (en) 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
US5292393A (en) * 1986-12-19 1994-03-08 Applied Materials, Inc. Multichamber integrated process system
EP0289246A1 (en) 1987-04-27 1988-11-02 Seiko Instruments Inc. Method of manufacturing MOS devices
US4908189A (en) * 1988-07-15 1990-03-13 Henkel Corporation Concentric tube ozonator
JPH038331A (en) * 1989-06-06 1991-01-16 Nec Corp Method and apparatus for forming silicon oxide
JPH03104341A (en) 1989-09-18 1991-05-01 Fujitsu Ltd Connection system between local area networks
JPH03201427A (en) 1989-12-28 1991-09-03 Nec Corp Formation of semiconductor thin film
US5057463A (en) 1990-02-28 1991-10-15 Sgs-Thomson Microelectronics, Inc. Thin oxide structure and method
JPH03287767A (en) * 1990-04-04 1991-12-18 Nec Corp Loading chamber for film forming device
US5089441A (en) 1990-04-16 1992-02-18 Texas Instruments Incorporated Low-temperature in-situ dry cleaning process for semiconductor wafers
US5067218A (en) * 1990-05-21 1991-11-26 Motorola, Inc. Vacuum wafer transport and processing system and method using a plurality of wafer transport arms
US5229334A (en) 1990-08-24 1993-07-20 Seiko Epson Corporation Method of forming a gate insulating film involving a step of cleaning using an ammonia-peroxide solution
JPH07118522B2 (en) 1990-10-24 1995-12-18 インターナショナル・ビジネス・マシーンズ・コーポレイション Method and semiconductor structure for oxidizing a substrate surface
JPH04196119A (en) * 1990-11-26 1992-07-15 Matsushita Electron Corp Manufacture of semiconductor device
US5271732A (en) * 1991-04-03 1993-12-21 Tokyo Electron Sagami Kabushiki Kaisha Heat-treating apparatus
JPH04332130A (en) * 1991-05-07 1992-11-19 Ricoh Co Ltd Manufacture of semiconductor element
US5228208A (en) * 1991-06-17 1993-07-20 Applied Materials, Inc. Method of and apparatus for controlling thermal gradient in a load lock chamber
US5258165A (en) * 1991-06-26 1993-11-02 Osmonics, Inc. Multi-tube ozone generator and method of making same
US5766360A (en) * 1992-03-27 1998-06-16 Kabushiki Kaisha Toshiba Substrate processing apparatus and substrate processing method
JP3154793B2 (en) * 1992-03-27 2001-04-09 株式会社東芝 Substrate processing equipment
US5294571A (en) 1992-07-22 1994-03-15 Vlsi Technology, Inc. Rapid thermal oxidation of silicon in an ozone ambient
JPH0684802A (en) * 1992-08-31 1994-03-25 Nec Corp Vapor phase epitaxy method
US5316981A (en) 1992-10-09 1994-05-31 Advanced Micro Devices, Inc. Method for achieving a high quality thin oxide using a sacrificial oxide anneal
JP3330166B2 (en) * 1992-12-04 2002-09-30 東京エレクトロン株式会社 Processing equipment
US5360769A (en) 1992-12-17 1994-11-01 Micron Semiconductor, Inc. Method for fabricating hybrid oxides for thinner gate devices
JPH0786271A (en) * 1993-09-17 1995-03-31 Fujitsu Ltd Manufacture of silicon oxide film
US5672539A (en) * 1994-01-14 1997-09-30 Micron Technology, Inc. Method for forming an improved field isolation structure using ozone enhanced oxidation and tapering
JP3486821B2 (en) * 1994-01-21 2004-01-13 東京エレクトロン株式会社 Processing apparatus and method of transporting object to be processed in processing apparatus
JPH09508494A (en) * 1994-01-27 1997-08-26 インシンク・システムズ・インコーポレーテッド Method of improving semiconductor process
US5580419A (en) * 1994-03-23 1996-12-03 Trw Inc. Process of making semiconductor device using focused ion beam for resistless in situ etching, deposition, and nucleation
JPH0831763A (en) * 1994-07-13 1996-02-02 Nissin Electric Co Ltd Surface treatment device
JP3036366B2 (en) * 1994-08-10 2000-04-24 三菱マテリアル株式会社 Processing method of semiconductor silicon wafer
JP3453223B2 (en) * 1994-08-19 2003-10-06 東京エレクトロン株式会社 Processing equipment
JPH08134649A (en) * 1994-11-14 1996-05-28 Fujitsu Ltd Pressure control method and pressure controller of apparatus for producing semiconductor
US5981399A (en) * 1995-02-15 1999-11-09 Hitachi, Ltd. Method and apparatus for fabricating semiconductor devices
US5578280A (en) * 1995-04-28 1996-11-26 Americal Environmental Technologies, Inc. Ozone generator with a generally spherical corona chamber
JPH0945597A (en) * 1995-05-25 1997-02-14 Kokusai Electric Co Ltd Semiconductor manufacturing apparatus and method for controlling load lock chamber oxygen concentration and method for producing natural oxide film
US5604298A (en) * 1995-12-07 1997-02-18 In Usa, Inc. Gas measurement system
JP4015210B2 (en) * 1996-05-30 2007-11-28 富士電機システムズ株式会社 Ozone generator
US5944940A (en) * 1996-07-09 1999-08-31 Gamma Precision Technology, Inc. Wafer transfer system and method of using the same
US6143081A (en) * 1996-07-12 2000-11-07 Tokyo Electron Limited Film forming apparatus and method, and film modifying apparatus and method
JP3589801B2 (en) * 1996-07-29 2004-11-17 松下電器産業株式会社 Method of forming oxide film on semiconductor substrate surface
US5879461A (en) * 1997-04-21 1999-03-09 Brooks Automation, Inc. Metered gas control in a substrate processing apparatus
US6193852B1 (en) * 1997-05-28 2001-02-27 The Boc Group, Inc. Ozone generator and method of producing ozone
JP3670451B2 (en) * 1997-07-24 2005-07-13 三菱電機株式会社 Ozone supply device
JP4851647B2 (en) 1998-01-09 2012-01-11 エーエスエム アメリカ インコーポレイテッド In situ growth of oxide and silicon layers
US6077751A (en) * 1998-01-29 2000-06-20 Steag Rtp Systems Gmbh Method of rapid thermal processing (RTP) of ion implanted silicon
US6168961B1 (en) * 1998-05-21 2001-01-02 Memc Electronic Materials, Inc. Process for the preparation of epitaxial wafers for resistivity measurements
US6338756B2 (en) 1998-06-30 2002-01-15 Seh America, Inc. In-situ post epitaxial treatment process
US6375746B1 (en) * 1998-07-10 2002-04-23 Novellus Systems, Inc. Wafer processing architecture including load locks
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
JP4176236B2 (en) * 1999-06-07 2008-11-05 東京エレクトロン株式会社 Method and apparatus for measuring light quantity of ultraviolet lamp in processing apparatus
US6166509A (en) * 1999-07-07 2000-12-26 Applied Materials, Inc. Detection system for substrate clamp
US6436194B1 (en) * 2001-02-16 2002-08-20 Applied Materials, Inc. Method and a system for sealing an epitaxial silicon layer on a substrate

Also Published As

Publication number Publication date
US6685779B2 (en) 2004-02-03
JP4640879B2 (en) 2011-03-02
KR20070007004A (en) 2007-01-12
TW504730B (en) 2002-10-01
JP2001077039A (en) 2001-03-23
KR100746380B1 (en) 2007-08-03
US20020148563A1 (en) 2002-10-17
KR100713264B1 (en) 2007-05-04
EP1067585A2 (en) 2001-01-10
EP1067585A3 (en) 2006-07-26
US6376387B2 (en) 2002-04-23
KR20010015244A (en) 2001-02-26

Similar Documents

Publication Publication Date Title
US6685779B2 (en) Method and a system for sealing an epitaxial silicon layer on a substrate
US5961323A (en) Dual vertical thermal processing furnace
US8791031B2 (en) Method of manufacturing semiconductor device, method of processing substrate and substrate processing apparatus
US8716147B2 (en) Manufacturing method of semiconductor device and substrate processing apparatus
KR100918005B1 (en) Semiconductor Device Manufacturing Method and Substrate Treatment Device
JP5303510B2 (en) Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus
US5928428A (en) Apparatus and method for manufacturing a semiconductor device
KR20050074964A (en) Apparatus and method for depositing an oxide film
US20040038487A1 (en) Method for improving nitrogen profile in plasma nitrided gate dielectric layers
KR20020031384A (en) A method of forming a silicon nitride layer on a semiconductor wafer
JP2010067788A (en) Substrate processing apparatus
JP2004533722A (en) Doped silicon deposition process in a resistively heated single wafer chamber
JP2002525886A (en) Method and apparatus for producing polycrystalline and amorphous silicon films
US5016567A (en) Apparatus for treatment using gas
US6489220B2 (en) Method and a system for sealing an epitaxial silicon layer on a substrate
JP2012054393A (en) Substrate processing apparatus and semiconductor manufacturing method
US20060003542A1 (en) Method of oxidizing object to be processed and oxidation system
KR20020041299A (en) Semiconductor manufacturing system and method for cleaning the same
EP1422316B1 (en) Method for cleaning reaction container
JP5792972B2 (en) Semiconductor device manufacturing method and substrate processing apparatus
JP2008171958A (en) Method of manufacturing semiconductor device
JPH04188721A (en) Vertical heat treatment apparatus
JP2007305798A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CARLSON, DAVID K.;COMITA, PAUL B.;RILEY, NORMA B.;AND OTHERS;REEL/FRAME:010350/0831

Effective date: 19990720

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20100423