US20010008482A1 - Integrated device and method for routing a signal through the device - Google Patents
Integrated device and method for routing a signal through the device Download PDFInfo
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- US20010008482A1 US20010008482A1 US09/173,538 US17353898A US2001008482A1 US 20010008482 A1 US20010008482 A1 US 20010008482A1 US 17353898 A US17353898 A US 17353898A US 2001008482 A1 US2001008482 A1 US 2001008482A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
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- H01L2924/3011—Impedance
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Abstract
Description
- The invention relates generally to electronic circuits, and more particularly to an integrated device that routes a signal through the device and to other devices in an integrated-circuit module.
- In today's marketplace, consumers are pressuring manufacturers of electronic products to squeeze more functionality into a smaller space. For example, consumers want smaller and lighter personal computers, such as laptops, that have faster, more powerful processors and greater memory capacity.
- FIG. 1 is a side view of an integrated-circuit (IC) module10, which allows manufactures to reduce the circuit-board area, and thus the overall size, of electronic products such as personal computers. The module 10 includes a number of integrated
devices 12, which are stacked one atop the other, and is mounted to acircuit board 14. Therefore, no matter howmany devices 12 it includes, the module 10 occupies the circuit-board area of only onedevice 12. This is a significant reduction in occupied area as compared to a scheme where thedevices 12 are laid out side by side on theboard 14. - More specifically, each of the
devices 12 in the module 10 has a conventional package that allows coupling of signals between theboard 14 and all of thedevices 12. In the illustrated embodiment, thedevices 12 each have a ball-grid-array (BGA) package, although other packages may be used as long as they allow stacking of thedevices 12 to form the module 10. Eachdevice 12 includes a number of connection balls 16, which are each coupled to a respective terminal 18. A respective conductor 19 couples each of the terminals 18 to arespective terminal 20 that is aligned with the terminal 18. For example, in thedevice 12 0, the conductor 19 0 couples the terminal 18 0 to theterminal 20 0. When thedevices 12 are stacked to form the module 10, respective conductive paths are formed by the connection balls 16, theterminals 18 and 20, and the conductors 19. It is these conductive paths that couple respective signals between thecircuit board 14 and all of thedevices 12 in the module 10. For example, one such conductive path is formed by the ball 16 0, terminal 18 0, conductor 19 0,terminal 20 0, ball 16 1, and so on up to theterminal 20 n. Therefore, so that the module 10 works properly, all of thedevices 12 have the same pin out, i.e., receive the same signals on the same respective terminals 18 and provide the same signals on the samerespective terminals 20. - Unfortunately, referring to FIG. 2, which is a top view of one of the
devices 12 of FIG. 1, the size of eachdevice 12 is increased to accommodate signals that are not common to all of thedevices 12. For example, eachdevice 12 is enabled by a respective chip-select signal CS0-CSn, which is received on a respective chip-select terminal 18 CS0-18 CSn. If they were laid out side by side on the board 14 (FIG. 1), then each of thedevices 12 would need only one chip-select terminal 18 CS. But because they are stacked, eachdevice 12 has the same number of chip-select terminals 18 CS0-18 CSn as there aredevices 12 in the module 10 (FIG. 1). - More specifically, for each unique signal such as a chip-select signal that they receive, the
devices 12 each need n terminals, where n is the number ofdevices 12 in the module 10 (FIG. 1). Thus, just one or two unique signals may cause a significant increase in the sizes of thedevices 12. For example, the device 12 0 (FIG. 1) responds only to CS0, and thus needs only the terminal 18 CS0 to function properly. That is, thedevice 12 0 has no need for CS1-CSn, and thus can function properly without the terminals 18 CS1-18 CSn But because theother devices 12, - 12 n in the module 10 respond to CS1-CSn, respectively, thedevice 12 0 must also include the terminals 18 CS1-18 CSn to form conductive paths that couple CS1-CSn to the devices 12 1-12 n. For reasons including that the relative position of adevice 12 in the module 10 is unknown during manufacture of thedevice 12, each of the devices 12 1-12 n also includes a respective set of terminals 18 CS0-18 CSn - Following is a brief description of the drawing where like numerals are used to reference like elements.
- FIG. 1 is a side view of a known IC module.
- FIG. 2 is a top view of one of the devices that composes the IC module of FIG. 1.
- FIG. 3 is a side view of an embodiment of an IC module according to the invention.
- FIG. 4 is a coupling diagram for the devices that compose the IC module of FIG. 3.
- FIG. 5 is a side view of another embodiment of an IC module according to the invention.
- FIG. 6 is a coupling diagram for the devices that compose the IC module of FIG. 5.
- FIG. 7 is a side view of another embodiment of the IC module of FIG. 5.
- FIG. 8 is a side view of another embodiment of the IC module of FIG. 5.
- FIG. 9 is a side view of another embodiment of the IC module of FIG. 5.
- FIG. 10 is a schematic block diagram of a memory circuit that can be incorporated into one or more of the devices that compose the IC modules of FIGS. 3, 5,7, 8, and 9.
- FIG. 11 is a block diagram of an electronic computer system that can incorporate one or more of the IC modules of FIGS. 3, 5,7, 8, and 9.
- In one aspect of the invention, an integrated device includes a package having first and second sides, a first package terminal disposed on the first side of the package, and a second package terminal disposed on the second side of the package in alignment with the first package terminal. An integrated circuit is mounted to the package and has an input terminal coupled to the first package terminal and has an output terminal coupled to the second package terminal. In operation, the first package terminal receives a signal and couples the signal to the input terminal of the integrated circuit, the integrated circuit couples the signal from its input terminal to its output terminal, and the signal leaves the device via the second package terminal.
- Such a device allows the coupling of multiple signals to multiple devices in an IC module over only one single path. For example, such a device may allow multiple devices in the module to share one chip-select signal path. Sharing the same signal path allows each device in the module to have only one terminal for a unique signal, and thus allows the devices and module to have smaller sizes than they might otherwise have.
- FIG. 3 is a side view of an embodiment of an
IC module 20 according to the invention. Themodule 20 is mounted to thecircuit board 14 and includes one or more integrated devices 22 0-22 n, which are coupled together by connectingballs 21 and which share the same signal path for signals, such as chip-select signals, that are respectively unique to each of thedevices 22. Therefore, where thedevices 22 are similar to thedevices 12 of FIG. 1 except for the signal path sharing, eachdevice 20 includes fewer terminals and occupies a smaller area than adevice 12, and thus themodule 20 occupies a smaller area than the module 10 of FIG. 1. - More specifically, each of the
devices 22 of themodule 20 includes apackage 24 having a sides 26 and 28.Terminals 30 are disposed on the side 26, andterminals 32, which are each aligned with arespective terminal 30, are disposed on the side 28. For example, theterminals device 22 0 are aligned with one another. Aconductive pad 34 is disposed on the side 28 and is coupled to theterminal 30 via aconductive path 36. Similarly, a pad 38 is disposed on the side 28 and is coupled to theterminal 32 via aconductive path 40. Although thepath 40 is shown routed through thepackage 24, in other embodiments it is routed along the surface of the side 28. Anintegrated circuit 42, such as a memory circuit, is mounted to thepackage 24. In one embodiment, thecircuit 42 is in die form. In another embodiment, thecircuit 42 includes a Sync-Link Dynamic Random Access Memory (SLDRAM) that operates at clock speeds up to 800 MHZ. In still another embodiment, thepackage 24 encapsulates thecircuit 42 to protect it from the environment. In yet another embodiment, the package includes a substrate, such as a circuit board, to which thecircuit 42 is mounted. Thecircuit 42 has an input terminal 44, which is coupled to thepad 36, and has anoutput terminal 46, which is coupled to the pad 38. In the illustrated embodiment, theterminals 44 and 46 are wire bonded to thepads 36 and 38, respectively, although other coupling techniques may be used. - During operation of the
module 20, theintegrated circuit 42 0 of thedevice 22 0 receives a signal from thecircuit board 14 via theconnection ball 21 0,terminal 30 0,path 36 0,pad 34 0, and input terminal 44 0, and provides the signal to theconnection ball 21 1 via theoutput terminal 46 0, pad 38 0,path 40 0, andterminal 32 0. The other devices 22 1-22 n−1 operate in a similar manner such that the signal is serially coupled all the way to thedevice 22 n. Arrows in FIG. 3 show the direction of the signal flow along this serial path. - Each of the
devices 22 may, however, respond only to a respective one of the signals, even though all of the signals are coupled through the same serial path. For example, if the signals transmitted along this path are chip-select signals, then each of theintegrated circuits 42 may be constructed or programmed to recognize a unique voltage drop across itsterminals 44 and 46. That is, acircuit 42 will not be enabled until the appropriate chip-select voltage is applied to the signal path. Thus, by providing chip-select signals of differing voltage levels, the desired one of thedevices 22 can be selected. Alternatively, the chip-select signals may be digital, and each circuit 44 programmed to recognize a unique digital value. Furthermore, signals other than chip-select signals may be routed according to these techniques. - Still referring to FIG. 3, in high-frequency applications, it may be desirable to terminate the serial path at its end to prevent undesirable transmission-line effects. Therefore, the
module 20 may include a termination circuit, such as atermination impedance 50, which is coupled between the end of the signal path, here theconnection ball 21 n+1, and ground or another termination node. Theimpedance 50 may include e.g., a resistor, capacitor, or transmission-line stub. In one embodiment, a conductive path to theboard 14 is formed by terminals 52 and 54, conductors 56, and connection balls 58, and thetermination impedance 50 is coupled between theconnection balls 21 n+1, and 58 n+1. If this conductive path is required whether or not theimpedance 50 is present (for example, if it is a ground path), then the addition of theimpedance 50 does not require thedevices 22 to have additional terminals. Alternatively, if this path is a dedicated termination path, then theconnection balls 21 n+1 and 58 n+1 can be shorted together so that thetermination impedance 50 can be located on thecircuit board 14. - Although the
module 20 is shown having BGA connections between thedevices 22, other types of connections may be used. Furthermore, although the input andoutput terminals 44 and 46 are shown on opposite sides of the respectiveintegrated circuits 42, they may have different locations. Additionally, the input terminals 44 may be wire bonded directly to therespective terminals 30, and theoutput terminals 46 may be wire bonded directly to therespective terminals 32, thus eliminating the need for thepads 34 and 38 and theconductive paths - FIG. 4 is a top view of one embodiment of the
device 22 0 and the coupling between thecircuit 42 0 and theterminals 44 0 and 46 0. In this embodiment, theterminals 44 0 and 46 0 are arranged side by side, and theterminals conductive paths other devices 22 can have a similar coupling scheme. - FIG. 5 is a side view of an
IC module 60 according to another embodiment of the invention. Themodule 60 includes twostacks devices 22, and is useful in high-frequency applications. Because of its larger surface area, themodule 60 often allows greater heat-dissipation than themodule 20 of FIG. 3. Also, themodule 60 may provide shorter signal paths including shorter serial paths that are terminated at their respective ends. - The
stack 62 of themodule 60 is similar to the single stack of thedevices 22 in themodule 20 of FIG. 3. Thus, the serial signal path of thestack 62 begins at the ball 21 0 and ends at theball 21 n+1. Themodule 60 also includes a shunt coupler 66 having a conductor 68 for coupling theball 21 n+1 to theball 21 n+2, which is the input ball of thestack 64. - The
stack 64 is similar to thestack 62, except that the signal flow along the serial path is in the opposite direction, i.e., top to bottom instead of bottom to top. To accommodate this reversed signal flow, the connections to theintegrated circuits 42 are reversed. For example, in thedevice 22 2n, the input terminal 44 2n is coupled to the pad 38 2n instead of thepad 34 2n. Likewise, theoutput terminal 46 2n is coupled to thepad 34 2n instead of the pad 38 2n. Thus, theintegrated circuit 42 2n receives the signal from theball 21 2n+1 via the terminal 32 2n,path 40 2n, pad 38 2n, and input terminal 44 2n, and provides the signal to theconnection ball 21 2(n+1) via theoutput terminal 46 2n,pad 34 2n,path 36 2n, andterminal 30 2n. The other devices 22 n+1-22 2n-1 of thestack 64 are similarly constructed such that thestack 64 receives the signal from thestack 62 and couples the signal back to theboard 14 for termination by a termination circuit such as thetermination impedance 50. Again, the arrows show the direction of the signal flow along the serial path. It is clear that for the same number n ofdevices 22 in themodules stacks module 20. Therefore, for the same number n ofdevices 22, the terminated serial path of themodule 60 is approximately one half the length of the terminated serial path of themodule 20 of FIG. 3. - The
module 60 also includes a path for a signal, such as an address signal, that thedevices 22 of bothstacks first stack 62, aconductor 70 of the coupler 66, thestack 64, and to the ball 58 2(n+1), and thus can be terminated on the board 14. - In one embodiment, whether the signals are serially routed like the chip-select signals or parallel routed like an address signal, they are routed up from the
board 14 via the left and right sides of thestack 62 and back down to thecircuit board 14 via the left and right sides of thestack 64, respectively. - FIG. 6 is a top view of one embodiment of a
device 22 of themodule 60 of FIG. 5 and the coupling options between thecircuit 42 and theballs 21. Thepackage 24 includes arouting scheme 72 having two connection options, a first one for thedevices 22 of the stack 62 (shown in solid line and with solid arrows) and a second one for thedevices 22 of the stack 64 (shown in broken line with broken arrows). Having this connection scheme allows thesame packages 24 to be used for thedevices 22 in both of thestacks pads 34 and 38, respectively, of thedevices 22 in thestack 62. Thus, as shown by the solid arrows, the signal flow is from the lower ball 21 (for example, 21 1) into the input terminal 44 via the pad A, and out of theoutput terminal 46 to the upper ball 21 (for example, 21 1) via the pad B. In the second option, the pads B and C correspond to thepads 38 and 34, respectively, of thedevices 22 in thestack 64. Thus, as shown by the broken arrows, the signal flow is from the upper ball 21 (for example, 21 1) into the input terminal 44 via the pad B, and out of theoutput terminal 46 to the lower ball 21 (for example, 21 0) via the pad C. - FIG. 7 is a side view of another embodiment of the
IC module 60 according to the invention. Here,identical devices 22 are used in both of thestacks devices 22 need be manufactured and tested. This is advantageous because it is often easier and less expensive to manufacture and test one version of a part than it is to manufacture and test multiple versions. To allow the use ofidentical devices 22 in bothstacks integrated circuits 42 are conventionally designed to recognize which of theterminals 44 and 46 is being used as an input terminal and which is being used as an output terminal, and to then configure these terminals appropriately. For example, in one embodiment, theintegrated circuit 42 0 measures the voltage drop across theterminals 44 0 and 46 0 and configures the terminal at the higher voltage as the input terminal and configures the terminal at the lower voltage as the output terminal. Theother circuits 42 operate in a similar manner. Thus, because the connections of theterminals 44 and 46 in thestack 64 are not reversed with respect to the connections of theterminals 44 and 46 in thestack 62 as in the embodiment of FIG. 5, only one version of thedevices 22 needs to be manufactured and tested. - FIG. 8 is a side view of another embodiment of the
IC module 60 of FIG. 5. In this embodiment, not only can both of thestacks identical devices 22, but unlike the embodiment of FIG. 7, theintegrated circuits 42 need not dynamically configure theterminals 44 and 46. Therefore, theintegrated circuits 42 used in this embodiment can be less complex and smaller because they do not need the dynamic configuration circuitry like thecircuits 42 in the FIG. 7 embodiment. More specifically, thestack 62 in this embodiment is similar to thestacks 62 of FIGS. 5 and 7. In thestack 64, however, thedevices 22 are flipped such that they are upside down with respect to thedevices 22 in thestack 62. Therefore, a signal routed along the serial path enters adevice 22 in thestack 64 via the terminal 30 and exits the device via the terminal 32 just as it enters and exits adevice 22 in thestack 62. - FIG. 9 is a side view of yet another embodiment of the
IC module 60 in which some signal paths between thestacks - More specifically, the
module 60 of FIG. 9 is similar to themodule 60 of FIG. 8, except that in the FIG. 9 embodiment, thestack 64 is oriented as if its left side were “hinged” to the right side of thestack 62. Therefore, all of the signals that are routed along the right side of thestack 62 are also routed along the left side of the stack 54, and all of the signals routed along the left side of thestack 62 are also routed along the right side of thestack 64. Because the right side of the stack 52 and the left side of the stack 54 are adjacent, the distance between them is much less than for the right-side-to-right-side and left-side-to-left-side routing of themodules 60 in FIGS. 5, 7, and 8. Although it is true that now the signal paths along the left side of thestack 62 and right side of thestack 64 are longer than the signal paths in FIGS. 5, 7, and 8, thedevices 22 can be designed so that lower frequency signals are routed along these paths so that the additional distance does not cause undesirable transmission line effects. Thus, besides the different orientations of thedevices 22 in thestack 64, the only major structural difference between themodules 60 of FIGS. 8 and 9 is that in the FIG. 9 embodiment, the coupler 66 couples the terminals on the left side of thestack 62 to the respective terminals on the right side of the stack 54, and couples the terminals on the right side of thestack 62 to those on the left side of thestack 64. - FIG. 10 is a block diagram of a
memory circuit 70, which can compose one or more of theintegrated circuits 42 of FIGS. 3-9. - The
memory circuit 70 includes anaddress register 72, which receives an address from an ADDRESS bus. Acontrol logic circuit 74 receives a clock (CLK) signal, and receives clock enable (CKE), chip select ({overscore (CS)}), row address strobe ({overscore (RAS)}), column address strobe ({overscore (CAS)}), and write enable ({overscore (WE)}) signals from the COMMAND bus, and communicates with the other circuits of thememory circuit 70. Arow address multiplexer 76 receives the address signal from theaddress register 72 and provides the row address to the row-address latch-and-decode circuits 78 a and 78 b for the memory bank 80 a or 80 b, respectively. During read and write cycles, the row-address latch-and-decode circuits 78 a and 78 b activate the work lines of the addressed rows of memory cells in the memory banks 80 a and 80 b, respectively. Read/write circuits 82 a and 82 b read data from the addressed memory cells in the memory banks 80 a and 80 b, respectively, during a read cycle, and write data to the addressed memory cells during a write cycle. A column-address latch-and-decode circuit 84 receives the address from theaddress register 72 and provides the column address of the selected memory cells to the read/write circuits 82 a and 82 b. For clarity, theaddress register 72, the row-address multiplexer 76, and row-address latch-and-decode circuits 78 a and 78 b, and the column-address latch-and-decode circuit 84 can be collectively referred to as an address decoder. - A data input/output (I/O) circuit86 includes a plurality of input buffers 88. During a write cycle, the buffers 88 receive and store data from the DATA bus, and the read/write circuits 82 a and 82 b provide the stored data to the memory banks 80 a and 80 b, respectively. The data I/O circuit 86 also includes a plurality of
output drivers 90. During a read cycle, the read/write circuits 82 a and 82 b provide data from the memory banks 80 a and 80 b, respectively, to thedrivers 90, which in turn provide this data to the DATA bus. - A refresh counter92 stores the address of the row of memory cells to be refreshed either during a conventional auto-refresh mode or self-refresh mode. After the row is refreshed, a refresh controller 94 updates the address in the
refresh counter 92, typically by either incrementing or decrementing the contents of therefresh counter 92 by one. Although shown separately, the refresh controller 94 may be part of thecontrol logic 74 in other embodiments of thememory circuit 70. - The
memory device 70 may also include anoptional charge pump 96, which steps up the power-supply voltage VDD to a voltage VDDP. In one embodiment, thepump 96 generates VDDP approximately 1-1.5 V higher than VDD. Thememory circuit 70 may also use VDDP to conventionally overdrive selected internal transistors. - FIG. 11 is a block diagram of an
electronic system 100, such as a computer system, the can incorporate one or more of themodules 20 of FIG. 3 or themodules 60 of FIGS. 5, 7, 8, and 9. Thesystem 100 includes computer circuitry 102 for performing computer functions, such as executing software to perform desired calculations and tasks. The circuitry 102 typically includes a processor 104 and a memory section 105, which may include one or more of thememory circuits 70. The memory section 105 is coupled to the processor 104. One ormore input devices 106, such as a keyboard or a mouse, are coupled to the computer circuitry 102 and allow an operator (not shown) to manually input data thereto. One ormore output devices 168 are coupled to the computer circuitry 102. Examples of such output devices 108 include a printer and a video display unit. One or more data-storage devices 110 are coupled to the computer circuitry 102 to store data on or retrieve data from external storage media (not shown). Examples of thestorage devices 110 and the corresponding storage media include drives that accept hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). Typically, the computer circuitry 102 includes address data and command buses and a clock line that are respectively coupled to the ADDRESS, DATA, and COMMAND buses, and the CLK line of thememory circuit 70. The computer circuitry 102, processor 104,input devices 106, output devices 108, and storage devices 170 may each include one or more of themodules 20 of FIG. 3 or themodules 60 of FIGS. 5, 7, 8, and 9. - From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.
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US09/173,538 US6381141B2 (en) | 1998-10-15 | 1998-10-15 | Integrated device and method for routing a signal through the device |
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US09/173,538 US6381141B2 (en) | 1998-10-15 | 1998-10-15 | Integrated device and method for routing a signal through the device |
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US20010008482A1 true US20010008482A1 (en) | 2001-07-19 |
US6381141B2 US6381141B2 (en) | 2002-04-30 |
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US20060049504A1 (en) * | 1998-06-30 | 2006-03-09 | Corisis David J | Module assembly and method for stacked BGA packages |
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US20060049504A1 (en) * | 1998-06-30 | 2006-03-09 | Corisis David J | Module assembly and method for stacked BGA packages |
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