US20010003379A1 - Semiconductor device and method of fabricating the same - Google Patents
Semiconductor device and method of fabricating the same Download PDFInfo
- Publication number
- US20010003379A1 US20010003379A1 US09/216,874 US21687498A US2001003379A1 US 20010003379 A1 US20010003379 A1 US 20010003379A1 US 21687498 A US21687498 A US 21687498A US 2001003379 A1 US2001003379 A1 US 2001003379A1
- Authority
- US
- United States
- Prior art keywords
- layer
- semiconductor substrate
- insulating
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of fabricating the same.
- the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a parasitic capacitance between data lines. Accordingly, a DRAM (Dynamic Random Access Memory) device having a stable performance and an improved data sensing capability is fabricated in the present invention.
- DRAM Dynamic Random Access Memory
- aluminum is a choice of material for interconnection between gate electrodes, source/drain regions, and electrical contacts.
- a wiring characteristic is deteriorated with a reduction in a device dimension or a power source.
- a signal transmission is delayed due to a resistance increase. An operation speed is thus decreased.
- a current intensity of an electrical contact is increased due to the resistance increase, thereby degrading a reliability of a wiring in the device.
- the increases in resistance and the current intensity cause an electromigration, which significantly degrades the reliability of the wiring in the device.
- a RC (resistance-capacitance) transmission is delayed because a wiring resistance and a capacitance are increased due to micronization and reduction in a wiring pitch.
- FIG. 1 is a cross-sectional view illustrating the background art semiconductor device.
- FIGS. 2A to 2 E are cross-sectional views showing the process steps of fabricating method of the background art semiconductor device.
- FIG. 3 is a circuit diagram of the background art semiconductor device.
- bitlines applying driving signals to cell transistors and bitlines applying data signals to cell capacitors are arranged to cross each other to have a higher integration.
- the background art semiconductor device will be explained with an emphasis on a conductive layer pattern (bitline).
- the background art semiconductor device is provided with a conductive layer pattern 12 on a semiconductor substrate 10 having cell transistors.
- the conductive layer pattern 12 is connected to source/drain of the cell transistors or another conductive layers.
- a first insulating layer 13 is formed on the semiconductor substrate 10 including the conductive layer pattern 12 , and a second insulating layer 14 for planarizing the device.
- An insulating layer 11 such as oxide, is provided between the conductive layer pattern 12 and the semiconductor substrate 10 for insulating the conductive pattern 12 from other regions.
- an insulating layer 11 a is formed on a semiconductor substrate 10 having cell transistors or another conductive layers formed thereon.
- a conductive layer 12 a is formed on the insulating layer 11 a for a metal line.
- the conductive layer 12 a and the insulating layer 11 a are selectively etched to form a conductive layer pattern 12 and a first insulating layer pattern 11 , respectively.
- a second insulating layer 13 such as oxide, is formed on the semiconductor substrate 10 including the conductive layer pattern 12 and the first insulating layer 11 .
- the layer 14 a is formed to completely fill the spaces between each conductive layer pattern 12 on the second insulating layer 13 .
- the layer 14 a is subjected to an anisotropic etching to expose an upper surface of the second insulating layer 13 , thereby completing a semiconductor device having a third insulating layer 14 , as shown in FIG. 2E.
- the semiconductor device fabricated by the aforementioned method has a parasitic capacitance Cb between the second and third insulating layers 13 and 14 .
- the second and third insulating layers 13 and 14 such as oxide, have a dielectric constant of about 3.85.
- a unit cell of a DRAM is provided with a cell transistor T 1 , a cell capacitor Cs having one electrode connected to a ground terminal and another electrode connected to one of electrodes of source/drain in the cell transistor T 1 .
- An S/A sensing amplifier
- bitline BL connected to one of the electrode of the source/drain in the cell transistor T 1 to output signals.
- the aforementioned unit cell generates a parasitic capacitance Cb (bitline parasitic capacitance) during reading operation in the second and third insulating layers 13 and 14 between one side of the cell transistor T 1 and the S/A.
- Vd/2 is also applied to the parasitic capacitance Cb.
- the sensing amplifier S/A compares voltages of the bitline B/L and a bitbarline ⁇ overscore (B) ⁇ / ⁇ overscore (L) ⁇ to output the compared value after amplifying the value.
- Vd, Cb, and Cs denote a voltage of a power source, a parasitic capacitance of the bitline, and a capacitance of the cell capacitor C 1 , respectively.
- both the Vd and the Cs should be increased, while the Cb should be decreased.
- a dielectric constant of the second and third insulating layers 13 and 14 such as oxide, between the conductive layer patterns 12 (bitlines) in the background art is about 3.85.
- a parasitic capacitance by the oxide layer between bitlines degrades a data sensing capability of the device. Since the parasitic capacitance is generated from a dielectric constant of oxide itself, it can be reduced by increasing both the source power voltage Vd and the capacitance of the cell capacitor Cs.
- the present invention is directed to a semiconductor device and a method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a wiring in a semiconductor device and a method of fabricating the same, in which a parasitic capacitance between conductive patterns is reduced for providing a stable operation of the device.
- a wiring in a semiconductor device includes a semiconductor substrate, a plurality of conductive layer patterns on the semiconductor substrate, an insulating film on the semiconductor substrate and the conductive layer pattern, and at least one void in the insulating film between the conductive layer patterns adjacent to each other.
- a method for fabricating a wiring in a semiconductor device includes the steps of providing a semiconductor substrate, forming a plurality of conductive layer patterns on the semiconductor substrate, and forming an insulating film having at least one void therein on the semiconductor substrate and the conductive layer pattern and between the conductive layer patterns adjacent to each other.
- a semiconductor device in another aspect of the present invention, includes a semiconductor substrate, a plurality of conductive layers on the semiconductor substrate, and an insulating layer on the semiconductor substrate including the conductive layers, the insulating layer having at least one void between each adjacent conductive layer.
- a method of fabricating a semiconductor device having a semiconductor substrate includes the steps of forming a plurality of conductive layers on the semiconductor substrate, and forming an insulating layer on the semiconductor substrate including the conductive layers, the insulating layer having at least one void between each adjacent conductive layer.
- a method of fabricating a semiconductor device having a semiconductor substrate includes the steps of forming a plurality of conductive layers on the semiconductor substrate, forming an insulating layer on the semiconductor substrate including the conductive layers, forming a nitride layer on the insulating layer, forming an insulating interlayer on the nitride layer, removing the insulating interlayer to expose an upper surface of the nitride layer, forming a hemi-spherical grain silicon layer on the insulating interlayer including the upper surface of the nitride layer, selectively removing the insulating interlayer using the hemi-spherical grain silicon layer as a mask to form a plurality of void in the insulating interlayer, and forming a planarization layer on the insulating interlayer including the nitride layer.
- FIG. 1 is a cross-sectional view illustrating a semiconductor device in accordance with a background art
- FIGS. 2A to 2 E are cross-sectional views showing the process steps of fabricating method of the background art semiconductor device
- FIG. 3 is an equivalent circuit diagram of the background art semiconductor device during a reading operation
- FIG. 4 is a cross-sectional view of a semiconductor device in accordance with a first embodiment of the present invention.
- FIGS. 5A to 5 E are cross-sectional views showing the process steps of fabricating method of a semiconductor device in accordance with the first embodiment of the present invention
- FIG. 6 is a cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention.
- FIGS. 7A to 7 F are cross-sectional views showing the process steps of fabricating method of a semiconductor device in accordance with the second embodiment of the present invention.
- FIG. 4 is a cross-sectional view of a semiconductor device in accordance with a first embodiment of the present invention while FIGS. 5A to 5 E are cross-sectional views showing the process steps of fabricating method of the semiconductor device in accordance with the first embodiment of the present invention.
- a parasitic capacitance generated in the insulating layers between conductive lines is suppressed in the semiconductor device of the present invention.
- the parasitic capacitance in the semiconductor device of the present invention is much more reduced by lowering a dielectric constant itself than that of the background art semiconductor where insulating layer are filled in the spaces between conductive line patterns.
- a semiconductor device in accordance with the first embodiment of the present invention includes a first insulating film 41 on a semiconductor substrate 40 having cell transistors.
- a conductive layer pattern 42 is formed on the first insulating film 41 .
- a second insulating film 43 is formed on the semiconductor substrate 40 including the conductive layer pattern 42 .
- the second insulating film 43 has overhangs between the conductive layer patterns 42 to form a void 44 below the overhangs.
- a third insulating film 45 is formed on the second insulating film 43 to planarize the semiconductor device.
- the void 44 formed in the second insulating film 43 between the conductive layer patterns 42 below the overhangs is filled with air.
- an insulating material layer 41 a is formed on an semiconductor substrate 40 having cell transistors and other conductive layers. Then, a conductive material layer 42 a (a bitline in a DRAM) for a metal line is formed on the insulating material layer 41 a.
- the conductive material layer 42 a and the insulating material layer 41 a are subjected to selective etching to form a conductive layer pattern 42 and a first insulating film 41 .
- a second insulating film 43 such as oxide, is formed on the semiconductor substrate 40 having the conductive layer pattern 42 including the first insulating film 41 , as shown in FIG. 5C.
- the second insulating film 43 is formed to have overhangs between the adjacent conductive layer patterns, thereby forming a void 44 below the overhangs. Air is naturally trapped in the void 44 .
- an oxide film is formed by a delta-N 2 O process to have a poor side step coverage.
- the delta-N 2 O process is used for improving a flatness of an interlayer insulating film for a device with a dimension below 0.35 ⁇ m.
- an insulating film with overhangs is formed, so that the side step coverages of metal lines become poor.
- the spaces between the metal lines are filled with a material having an excellent fluidity, such as SOG.
- SOG a material having an excellent fluidity
- the delta-N 2 O process is an oxide film formation process by a thermal decomposition using TEOS (Tetra-Ethyl-Ortho-Silicate)/O 2 /N 2 O in stead of TEOS/O 2 for forming an oxide film on the wiring lines.
- TEOS Tetra-Ethyl-Ortho-Silicate
- the overhangs are prone to be formed at the upper portion of the hole due to a poor side step coverage created by N 2 O gas.
- a void 44 is formed in the second insulating film 43 and air having a dielectric constant 1 is trapped in the void 44 .
- a third insulating material layer 45 a is formed on the surface over the semiconductor substrate 40 to an enough thickness to fill the spaces between the conductive lines 42 .
- the third insulating material layer 45 a is subjected to anisotropic etching, so that the third insulating material layer 45 a remains only on the recesses of the second insulating film 43 to form a third insulating film 45 , thereby planarizing the semiconductor device.
- the third insulating material layer 45 a are mainly formed on the overhung portions of the second insulating film 43 .
- a tilt deposition process instead of the delta-N 2 O process may be used in forming the second insulating film 43 .
- FIG. 6 illustrates a cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention.
- FIGS. 7A to 7 F are cross-sectional views showing the process steps of fabricating method for a semiconductor device in accordance with the second preferred embodiment of the present invention.
- a HSG hemi-spherical grain
- the semiconductor device in accordance with the second embodiment of the present invention includes a first oxide film 62 a formed on a semiconductor substrate 60 having cell transistors.
- a conductive layer pattern 61 is formed on the first oxide film 62 a.
- a second oxide film 62 b and a nitride film 63 formed in this order on the conductive layer pattern 61 including the semiconductor substrate 60 .
- a third oxide film 62 c having a plurality of vertical pass-through voids 65 between the conductive layer patterns 61 are formed on the nitride film 63 a except for the top surface.
- a fourth oxide film 62 d formed on the entire surface including the third oxide film 62 c for planarizing the device.
- the vertical pass-through holes in the third oxide film 62 c are formed to have irregular sizes and positions.
- the holes are sealed by the nitride film 63 at the lower side of the holes and the fourth oxide film 62 d at the upper side.
- the inside of the holes is naturally filled with air.
- the voids 65 has a diameter in the range of 250 to 1000 ⁇ .
- a first oxide film 62 a is initially formed on a semiconductor substrate 60 having cell transistors or other conductive layers.
- a conductive material layer (bitline in a DRAM) for a metal line is then formed on the first oxide film 62 a.
- the conductive material layer and the first oxide film 62 a are subjected to selective etching to form a conductive layer pattern 61 .
- a second oxide film 62 b and a nitride film 63 are successively formed on the semiconductor substrate 60 including the conductive layer pattern 61 and the first oxide film 62 a.
- FIG. 7C shows that a third oxide film 62 c is formed on the nitride film 63 including the conductive layer pattern 61 to have an enough thickness to fill the gap between the adjacent conductive layer patterns 61 .
- the third oxide film 62 c is subjected to anisotropic etching to expose an upper surface of the nitride film 63 on the conductive layer pattern 61 .
- the third oxide film 62 c between the conductive layer patterns 61 is planarized, as shown in FIG. 7D.
- a HSG silicon layer 64 is formed on the planarized surface at about 550 to 600° C. to have a thickness of 500 ⁇ 2000 ⁇ .
- the entire surface of the HSG silicon layer 64 is subjected to anisotropic etching in FIG. 7F.
- the HSG silicon layer 64 which has irregular size hemispheres and scattered irregularly, is used as a mask in the anisotropic etching.
- the third oxide film 62 c is etched only at the portions corresponding to the recessed portions of the HSG silicon layer 64 due to different etching rates between the convex portions and the recessed portions of the HSG silicon layer 64 .
- the nitride film 63 acts as an etch stop detection point in the etching process. Accordingly, the third oxide film 62 c is vertically etched until the nitride film 63 is exposed, thereby forming a plurality of holes through the third oxide film 62 c.
- a fourth oxide film 62 d is formed on the entire surface by chemical vapor deposition to seal the holes in the third oxide film 62 c.
- voids 65 filled with air are formed in the insulating layer between the conductive layer patterns 61 , surrounded by the nitride film 63 , the third oxide film 62 c with holes, and the fourth oxide film 62 d.
- the voids 65 have a diameter in the range of 250 to 1000 ⁇ .
- the signal voltage of the present invention Vs′ has a value 3.85 times greater than the signal value of the background art Vs. As a result, a sensing capability of the present invention is improved as a shown result.
- a wiring in a semiconductor device and a method of fabricating the same in the present invention has the following advantages.
- the semiconductor device in the present invention can be operated with a cell capacitor a few times smaller than a current semiconductor device with a cell capacitor due to a reduced parasitic capacitance.
- steps or chip size of the semiconductor device is decrease, so that a higher integration is achieved in the present invention.
Abstract
Description
- This application claims the benefit of Korean Application No. 97-80698 filed Dec. 31, 1997, which is hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a parasitic capacitance between data lines. Accordingly, a DRAM (Dynamic Random Access Memory) device having a stable performance and an improved data sensing capability is fabricated in the present invention.
- 2. Discussion of the Related Art
- In a semiconductor device, aluminum is a choice of material for interconnection between gate electrodes, source/drain regions, and electrical contacts.
- Generally, a wiring characteristic is deteriorated with a reduction in a device dimension or a power source. For example, in a gate electrode, a signal transmission is delayed due to a resistance increase. An operation speed is thus decreased. Also, a current intensity of an electrical contact is increased due to the resistance increase, thereby degrading a reliability of a wiring in the device. As a result, the increases in resistance and the current intensity cause an electromigration, which significantly degrades the reliability of the wiring in the device. Particularly in submicron devices, a RC (resistance-capacitance) transmission is delayed because a wiring resistance and a capacitance are increased due to micronization and reduction in a wiring pitch.
- A metal wiring in a semiconductor device according to a background art will be explained with reference to the attached drawings. FIG. 1 is a cross-sectional view illustrating the background art semiconductor device. FIGS. 2A to2E are cross-sectional views showing the process steps of fabricating method of the background art semiconductor device. FIG. 3 is a circuit diagram of the background art semiconductor device.
- In the DRAM, wordlines applying driving signals to cell transistors and bitlines applying data signals to cell capacitors are arranged to cross each other to have a higher integration. The background art semiconductor device will be explained with an emphasis on a conductive layer pattern (bitline).
- Initially referring to FIG. 1, the background art semiconductor device is provided with a
conductive layer pattern 12 on asemiconductor substrate 10 having cell transistors. Theconductive layer pattern 12 is connected to source/drain of the cell transistors or another conductive layers. A firstinsulating layer 13 is formed on thesemiconductor substrate 10 including theconductive layer pattern 12, and a secondinsulating layer 14 for planarizing the device. Aninsulating layer 11, such as oxide, is provided between theconductive layer pattern 12 and thesemiconductor substrate 10 for insulating theconductive pattern 12 from other regions. - A method of forming the aforementioned background art semiconductor device will be explained as follows.
- Initially referring to FIG. 2A, an
insulating layer 11 a is formed on asemiconductor substrate 10 having cell transistors or another conductive layers formed thereon. Aconductive layer 12 a is formed on theinsulating layer 11 a for a metal line. - As shown in FIG. 2B, the
conductive layer 12 a and theinsulating layer 11 a are selectively etched to form aconductive layer pattern 12 and a firstinsulating layer pattern 11, respectively. - In FIG. 2C, a second
insulating layer 13, such as oxide, is formed on thesemiconductor substrate 10 including theconductive layer pattern 12 and the firstinsulating layer 11. - A layer14 a having a good insulating characteristic and a fluidity, such as an SOG (spin on glass) layer, is formed over the semiconductor substrate in FIG. 2D. In this process, the layer 14 a is formed to completely fill the spaces between each
conductive layer pattern 12 on the secondinsulating layer 13. - Thereafter, the layer14 a is subjected to an anisotropic etching to expose an upper surface of the second
insulating layer 13, thereby completing a semiconductor device having a thirdinsulating layer 14, as shown in FIG. 2E. - However, the semiconductor device fabricated by the aforementioned method has a parasitic capacitance Cb between the second and third
insulating layers insulating layers - A reading operation of the background art semiconductor device will be explained with reference to FIG. 3.
- A unit cell of a DRAM is provided with a cell transistor T1, a cell capacitor Cs having one electrode connected to a ground terminal and another electrode connected to one of electrodes of source/drain in the cell transistor T1. An S/A (sensing amplifier) for sensing and amplifying data in the cell through a bitline BL connected to one of the electrode of the source/drain in the cell transistor T1 to output signals. As shown in FIG. 3, the aforementioned unit cell generates a parasitic capacitance Cb (bitline parasitic capacitance) during reading operation in the second and third
insulating layers - In reading data from the DRAM, when a voltage is applied to a wordline W/L through a gate of the cell transistor T1 after a Vd/2 is precharged to the bitline B/L, the Vd/2 is also applied to the parasitic capacitance Cb. Upon applying the voltage to the wordline W/L to turn on the cell transistor T1, a charge in the cell capacitor Cs changes a voltage of the bitline B/L by Vs=(Vd/2)/(1+Cb/Cs). Thereafter, the sensing amplifier S/A compares voltages of the bitline B/L and a bitbarline {overscore (B)}/{overscore (L)} to output the compared value after amplifying the value. Vd, Cb, and Cs denote a voltage of a power source, a parasitic capacitance of the bitline, and a capacitance of the cell capacitor C1, respectively.
- In order to have the Vs at least higher than 100 mV, both the Vd and the Cs should be increased, while the Cb should be decreased. However, there is a maximum value for Vd due to limitations in a transistor size and a low power consumption. Therefore, by reducing the Cb value, a data sensing capability can be much improved in the device. For instance, a dielectric constant of the second and third
insulating layers - In a wiring in a semiconductor device according to the background art, a parasitic capacitance by the oxide layer between bitlines degrades a data sensing capability of the device. Since the parasitic capacitance is generated from a dielectric constant of oxide itself, it can be reduced by increasing both the source power voltage Vd and the capacitance of the cell capacitor Cs.
- However, an increase in the source power voltage Vd is limited by size of the device and power consumption. Also, an increase in a cell capacitance is problematic because a fabricating process becomes complicated. Further, a reduction of the parasitic capacitance Cb is also practically impossible because of a dielectric constant of oxide.
- Accordingly, the present invention is directed to a semiconductor device and a method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a wiring in a semiconductor device and a method of fabricating the same, in which a parasitic capacitance between conductive patterns is reduced for providing a stable operation of the device.
- Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
- To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a wiring in a semiconductor device includes a semiconductor substrate, a plurality of conductive layer patterns on the semiconductor substrate, an insulating film on the semiconductor substrate and the conductive layer pattern, and at least one void in the insulating film between the conductive layer patterns adjacent to each other.
- In another aspect of the present invention, there is provide a method for fabricating a wiring in a semiconductor device includes the steps of providing a semiconductor substrate, forming a plurality of conductive layer patterns on the semiconductor substrate, and forming an insulating film having at least one void therein on the semiconductor substrate and the conductive layer pattern and between the conductive layer patterns adjacent to each other.
- In another aspect of the present invention, a semiconductor device includes a semiconductor substrate, a plurality of conductive layers on the semiconductor substrate, and an insulating layer on the semiconductor substrate including the conductive layers, the insulating layer having at least one void between each adjacent conductive layer.
- In another aspect of the present invention, a method of fabricating a semiconductor device having a semiconductor substrate includes the steps of forming a plurality of conductive layers on the semiconductor substrate, and forming an insulating layer on the semiconductor substrate including the conductive layers, the insulating layer having at least one void between each adjacent conductive layer.
- In a further aspect of the present invention, a method of fabricating a semiconductor device having a semiconductor substrate includes the steps of forming a plurality of conductive layers on the semiconductor substrate, forming an insulating layer on the semiconductor substrate including the conductive layers, forming a nitride layer on the insulating layer, forming an insulating interlayer on the nitride layer, removing the insulating interlayer to expose an upper surface of the nitride layer, forming a hemi-spherical grain silicon layer on the insulating interlayer including the upper surface of the nitride layer, selectively removing the insulating interlayer using the hemi-spherical grain silicon layer as a mask to form a plurality of void in the insulating interlayer, and forming a planarization layer on the insulating interlayer including the nitride layer.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention:
- In the drawings:
- FIG. 1 is a cross-sectional view illustrating a semiconductor device in accordance with a background art;
- FIGS. 2A to2E are cross-sectional views showing the process steps of fabricating method of the background art semiconductor device;
- FIG. 3 is an equivalent circuit diagram of the background art semiconductor device during a reading operation;
- FIG. 4 is a cross-sectional view of a semiconductor device in accordance with a first embodiment of the present invention;
- FIGS. 5A to5E are cross-sectional views showing the process steps of fabricating method of a semiconductor device in accordance with the first embodiment of the present invention;
- FIG. 6 is a cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention; and
- FIGS. 7A to7F are cross-sectional views showing the process steps of fabricating method of a semiconductor device in accordance with the second embodiment of the present invention.
- Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 4 is a cross-sectional view of a semiconductor device in accordance with a first embodiment of the present invention while FIGS. 5A to5E are cross-sectional views showing the process steps of fabricating method of the semiconductor device in accordance with the first embodiment of the present invention.
- A parasitic capacitance generated in the insulating layers between conductive lines is suppressed in the semiconductor device of the present invention. The parasitic capacitance in the semiconductor device of the present invention is much more reduced by lowering a dielectric constant itself than that of the background art semiconductor where insulating layer are filled in the spaces between conductive line patterns. Now, a semiconductor device according to a first embodiment of the present invention will be explained as follows.
- Referring to FIG. 4, a semiconductor device in accordance with the first embodiment of the present invention includes a first insulating
film 41 on asemiconductor substrate 40 having cell transistors. Aconductive layer pattern 42 is formed on the first insulatingfilm 41. A second insulatingfilm 43 is formed on thesemiconductor substrate 40 including theconductive layer pattern 42. The second insulatingfilm 43 has overhangs between theconductive layer patterns 42 to form a void 44 below the overhangs. A third insulatingfilm 45 is formed on the second insulatingfilm 43 to planarize the semiconductor device. The void 44 formed in the second insulatingfilm 43 between theconductive layer patterns 42 below the overhangs is filled with air. - A method of fabricating the semiconductor device having the aforementioned wiring in accordance with the first embodiment of the present invention will be explained with reference with the attached drawings.
- Initially referring to FIG. 5A, an insulating material layer41 a is formed on an
semiconductor substrate 40 having cell transistors and other conductive layers. Then, aconductive material layer 42 a (a bitline in a DRAM) for a metal line is formed on the insulating material layer 41 a. - As shown in FIG. 5B, the
conductive material layer 42 a and the insulating material layer 41 a are subjected to selective etching to form aconductive layer pattern 42 and a first insulatingfilm 41. - Thereafter, a second insulating
film 43, such as oxide, is formed on thesemiconductor substrate 40 having theconductive layer pattern 42 including the first insulatingfilm 41, as shown in FIG. 5C. In this process, the second insulatingfilm 43 is formed to have overhangs between the adjacent conductive layer patterns, thereby forming a void 44 below the overhangs. Air is naturally trapped in thevoid 44. - In the process of forming the second insulating
film 43, an oxide film is formed by a delta-N2O process to have a poor side step coverage. Generally, the delta-N2O process is used for improving a flatness of an interlayer insulating film for a device with a dimension below 0.35 μm. By using the delta-N2O process, an insulating film with overhangs is formed, so that the side step coverages of metal lines become poor. The spaces between the metal lines are filled with a material having an excellent fluidity, such as SOG. The process is used mostly in improving a flatness by preventing formation of recesses in the SOG layer in the middle of metal wiring when the metal wiring has a large gap. The delta-N2O process is an oxide film formation process by a thermal decomposition using TEOS (Tetra-Ethyl-Ortho-Silicate)/O2/N2O in stead of TEOS/O2 for forming an oxide film on the wiring lines. When an oxide film is formed by thermal decomposition using TEOS/O2/N2O, the overhangs are prone to be formed at the upper portion of the hole due to a poor side step coverage created by N2O gas. In the first embodiment of the present invention, because of the overhangs at the upper portion of the hole, a void 44 is formed in the second insulatingfilm 43 and air having a dielectric constant 1 is trapped in thevoid 44. - After forming the second insulating
film 43 with a void 44, as shown in FIG. 5D, a thirdinsulating material layer 45 a is formed on the surface over thesemiconductor substrate 40 to an enough thickness to fill the spaces between theconductive lines 42. - In FIG. 5E, the third insulating
material layer 45 a is subjected to anisotropic etching, so that the third insulatingmaterial layer 45 a remains only on the recesses of the second insulatingfilm 43 to form a third insulatingfilm 45, thereby planarizing the semiconductor device. The thirdinsulating material layer 45 a are mainly formed on the overhung portions of the second insulatingfilm 43. Alternatively, a tilt deposition process instead of the delta-N2O process may be used in forming the second insulatingfilm 43. - A second embodiment of the present invention will be described with reference to the attached drawings. FIG. 6 illustrates a cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention. FIGS. 7A to7F are cross-sectional views showing the process steps of fabricating method for a semiconductor device in accordance with the second preferred embodiment of the present invention. In the second embodiment, a HSG (hemi-spherical grain) process is used to form a void filled with air in an insulating film between the conductive layer patterns.
- Initially referring to FIG. 6, the semiconductor device in accordance with the second embodiment of the present invention includes a
first oxide film 62 a formed on asemiconductor substrate 60 having cell transistors. Aconductive layer pattern 61 is formed on thefirst oxide film 62 a. Asecond oxide film 62 b and anitride film 63 formed in this order on theconductive layer pattern 61 including thesemiconductor substrate 60. Athird oxide film 62 c having a plurality of vertical pass-through voids 65 between theconductive layer patterns 61 are formed on the nitride film 63 a except for the top surface. Afourth oxide film 62 d formed on the entire surface including thethird oxide film 62 c for planarizing the device. - The vertical pass-through holes in the
third oxide film 62 c are formed to have irregular sizes and positions. The holes are sealed by thenitride film 63 at the lower side of the holes and thefourth oxide film 62 d at the upper side. The inside of the holes is naturally filled with air. The voids 65 has a diameter in the range of 250 to 1000 Å. - A method of fabricating the semiconductor device in accordance with the second embodiment of the present invention will be described as follows.
- Referring to FIG. 7A, a
first oxide film 62 a is initially formed on asemiconductor substrate 60 having cell transistors or other conductive layers. A conductive material layer (bitline in a DRAM) for a metal line is then formed on thefirst oxide film 62 a. The conductive material layer and thefirst oxide film 62 a are subjected to selective etching to form aconductive layer pattern 61. - As shown in FIG. 7B, a
second oxide film 62 b and anitride film 63 are successively formed on thesemiconductor substrate 60 including theconductive layer pattern 61 and thefirst oxide film 62 a. - FIG. 7C shows that a
third oxide film 62 c is formed on thenitride film 63 including theconductive layer pattern 61 to have an enough thickness to fill the gap between the adjacentconductive layer patterns 61. - Thereafter, the
third oxide film 62 c is subjected to anisotropic etching to expose an upper surface of thenitride film 63 on theconductive layer pattern 61. Thus, thethird oxide film 62 c between theconductive layer patterns 61 is planarized, as shown in FIG. 7D. - As shown in FIG. 7E, a
HSG silicon layer 64 is formed on the planarized surface at about 550 to 600° C. to have a thickness of 500˜2000 Å. - The entire surface of the
HSG silicon layer 64 is subjected to anisotropic etching in FIG. 7F. TheHSG silicon layer 64, which has irregular size hemispheres and scattered irregularly, is used as a mask in the anisotropic etching. Thethird oxide film 62 c is etched only at the portions corresponding to the recessed portions of theHSG silicon layer 64 due to different etching rates between the convex portions and the recessed portions of theHSG silicon layer 64. Thenitride film 63 acts as an etch stop detection point in the etching process. Accordingly, thethird oxide film 62 c is vertically etched until thenitride film 63 is exposed, thereby forming a plurality of holes through thethird oxide film 62 c. - As shown FIG. 7F, a
fourth oxide film 62 d is formed on the entire surface by chemical vapor deposition to seal the holes in thethird oxide film 62 c. Thus, voids 65 filled with air are formed in the insulating layer between theconductive layer patterns 61, surrounded by thenitride film 63, thethird oxide film 62 c with holes, and thefourth oxide film 62 d. The voids 65 have a diameter in the range of 250 to 1000 Å. - A parasitic capacitance of the semiconductor device in the present invention can be expressed as Cb=S/d because the dielectric constant of air is unity (where Cb=(εS)/d,, ε= 1). When the spaces between the conductive pattern layers are filled with the oxide film, a parasitic capacitance is Cb= (3.85S)/d because the dielectric constant of the oxide is 3.85. Setting that parasitic capacitances of the present invention and the background art are Cb′ and Cb, respectively, and signal voltages of the present invention and the background art are Vs′=(Vd/2)/(1+Cb′/Cs) and Vs= (Vd/2)/(1+Cb/Cs),
- Where, Cb= 3.85 and Cb′=1, the signal voltage of the present invention Vs′ has a value 3.85 times greater than the signal value of the background art Vs. As a result, a sensing capability of the present invention is improved as a shown result.
- A wiring in a semiconductor device and a method of fabricating the same in the present invention has the following advantages.
- By forming the insulating film having a void in the data line, a parasitic capacitance Cb is much reduced, thereby improving a data sensing capability without increasing a source power voltage Vd and cell capacitance Cs.
- In addition, the semiconductor device in the present invention can be operated with a cell capacitor a few times smaller than a current semiconductor device with a cell capacitor due to a reduced parasitic capacitance.
- Further, steps or chip size of the semiconductor device is decrease, so that a higher integration is achieved in the present invention.
- It will be apparent to those skilled in the art that various modifications and variations can be made in the wiring in a semiconductor device and a method for fabricating the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (15)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1997/80698 | 1997-12-31 | ||
KR19970080698 | 1997-12-31 | ||
KR1998/30314 | 1998-07-28 | ||
KR1019980030314A KR100351888B1 (en) | 1997-12-31 | 1998-07-28 | Metaline of Semiconductor Device and Method for Manufacturing the Same |
KR80698/1997 | 1998-07-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010003379A1 true US20010003379A1 (en) | 2001-06-14 |
US6380607B2 US6380607B2 (en) | 2002-04-30 |
Family
ID=26633337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/216,874 Expired - Lifetime US6380607B2 (en) | 1997-12-31 | 1998-12-21 | Semiconductor device and method for reducing parasitic capacitance between data lines |
Country Status (2)
Country | Link |
---|---|
US (1) | US6380607B2 (en) |
JP (2) | JP3964066B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004107352A2 (en) * | 2003-05-21 | 2004-12-09 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
US20090096109A1 (en) * | 2007-10-11 | 2009-04-16 | Akihisa Iwasaki | Semiconductor device and method for fabricating the same |
US20090115060A1 (en) * | 2007-11-01 | 2009-05-07 | Infineon Technologies Ag | Integrated circuit device and method |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1146567A1 (en) * | 2000-04-14 | 2001-10-17 | Infineon Technologies AG | Diode and process for manufacturing it |
JP4493182B2 (en) * | 2000-08-23 | 2010-06-30 | 株式会社ルネサステクノロジ | Semiconductor device |
US6908806B2 (en) * | 2003-01-31 | 2005-06-21 | Infineon Technologies Ag | Gate metal recess for oxidation protection and parasitic capacitance reduction |
KR100583965B1 (en) | 2004-12-31 | 2006-05-26 | 삼성전자주식회사 | Method of fabricating a semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby |
DE102005039323B4 (en) * | 2005-08-19 | 2009-09-03 | Infineon Technologies Ag | Guideway arrangement and associated production method |
US7396757B2 (en) * | 2006-07-11 | 2008-07-08 | International Business Machines Corporation | Interconnect structure with dielectric air gaps |
JP4827639B2 (en) * | 2006-07-12 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
JP2010153904A (en) * | 2010-03-04 | 2010-07-08 | Renesas Technology Corp | Semiconductor device |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0464567B1 (en) * | 1990-06-25 | 1997-08-06 | Matsushita Electronics Corporation | Cold cathode element |
JP2960538B2 (en) * | 1990-11-30 | 1999-10-06 | 関西日本電気株式会社 | Method for manufacturing semiconductor device |
US5641711A (en) * | 1994-04-28 | 1997-06-24 | Texas Instruments Incorporated | Low dielectric constant insulation in VLSI applications |
US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
JP3597885B2 (en) * | 1994-06-06 | 2004-12-08 | テキサス インスツルメンツ インコーポレイテツド | Semiconductor device |
US5691573A (en) * | 1995-06-07 | 1997-11-25 | Advanced Micro Devices, Inc. | Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines |
US5776834A (en) * | 1995-06-07 | 1998-07-07 | Advanced Micro Devices, Inc. | Bias plasma deposition for selective low dielectric insulation |
US5835987A (en) * | 1995-10-31 | 1998-11-10 | Micron Technology, Inc. | Reduced RC delay between adjacent substrate wiring lines |
US5677241A (en) * | 1995-12-27 | 1997-10-14 | Micron Technology, Inc. | Integrated circuitry having a pair of adjacent conductive lines and method of forming |
US5872401A (en) * | 1996-02-29 | 1999-02-16 | Intel Corporation | Deposition of an inter layer dielectric formed on semiconductor wafer by sub atmospheric CVD |
JP3085231B2 (en) * | 1997-02-20 | 2000-09-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JP3102382B2 (en) * | 1997-05-30 | 2000-10-23 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
-
1998
- 1998-12-21 US US09/216,874 patent/US6380607B2/en not_active Expired - Lifetime
- 1998-12-28 JP JP37326798A patent/JP3964066B2/en not_active Expired - Fee Related
-
2007
- 2007-03-29 JP JP2007087378A patent/JP4657237B2/en not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004107352A2 (en) * | 2003-05-21 | 2004-12-09 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
WO2004107352A3 (en) * | 2003-05-21 | 2005-02-03 | Sandisk Corp | Use of voids between elements in semiconductor structures for isolation |
US7045849B2 (en) | 2003-05-21 | 2006-05-16 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
CN100428440C (en) * | 2003-05-21 | 2008-10-22 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
US7569465B2 (en) | 2003-05-21 | 2009-08-04 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
US20090096109A1 (en) * | 2007-10-11 | 2009-04-16 | Akihisa Iwasaki | Semiconductor device and method for fabricating the same |
US7843073B2 (en) | 2007-10-11 | 2010-11-30 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US20110092068A1 (en) * | 2007-10-11 | 2011-04-21 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US7977239B2 (en) | 2007-10-11 | 2011-07-12 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US20090115060A1 (en) * | 2007-11-01 | 2009-05-07 | Infineon Technologies Ag | Integrated circuit device and method |
US20100099223A1 (en) * | 2007-11-01 | 2010-04-22 | Infineon Technologies Ag | Integrated circuit device and method |
US8187964B2 (en) | 2007-11-01 | 2012-05-29 | Infineon Technologies Ag | Integrated circuit device and method |
Also Published As
Publication number | Publication date |
---|---|
US6380607B2 (en) | 2002-04-30 |
JP3964066B2 (en) | 2007-08-22 |
JP4657237B2 (en) | 2011-03-23 |
JPH11251428A (en) | 1999-09-17 |
JP2007173879A (en) | 2007-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6744091B1 (en) | Semiconductor storage device with self-aligned opening and method for fabricating the same | |
US6395599B1 (en) | Method for fabricating semiconductor storage device | |
KR100821451B1 (en) | Method of forming memory arrays, method of forming contacts to bitlines, and method of forming storage nodes | |
JP4657237B2 (en) | Wiring formation method of semiconductor device | |
US5300814A (en) | Semiconductor device having a semiconductor substrate with reduced step between memory cells | |
KR0151866B1 (en) | Semiconductor apparatus and its manufacturing method | |
US6235583B1 (en) | Non-volatile semiconductor memory and fabricating method therefor | |
KR100545865B1 (en) | Semiconductor device and manufacturing method thereof | |
US6291335B1 (en) | Locally folded split level bitline wiring | |
KR100327123B1 (en) | A method of fabricating dram cell capacitor | |
US5606189A (en) | Dynamic RAM trench capacitor device with contact strap | |
US6620685B2 (en) | Method for fabricating of semiconductor memory device having a metal plug or a landing pad | |
US6140174A (en) | Methods of forming wiring layers on integrated circuits including regions of high and low topography | |
KR100351888B1 (en) | Metaline of Semiconductor Device and Method for Manufacturing the Same | |
KR100479815B1 (en) | A method of forming a bitline and bitline contact and a dynamic memory cell | |
US6670711B2 (en) | Semiconductor device including low dielectric constant insulating film formed on upper and side surfaces of the gate electrode | |
US6429478B1 (en) | Semiconductor device which increases the capacity of a capacitor without deepening the contact hole | |
US20040140496A1 (en) | Bitline structure for DRAM and method of forming the same | |
US20020130343A1 (en) | Semiconductor device which increases the capacity without deepening the contact hole | |
KR19990055805A (en) | Capacitor Formation Method of Semiconductor Device | |
JPH09266291A (en) | Semiconductor memory | |
KR19990041755A (en) | Contact hole formation method of semiconductor device | |
KR19990065079A (en) | Capacitor Manufacturing Method of Semiconductor Device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: LG SEMICON CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEO, WON CHEUL;REEL/FRAME:009669/0916 Effective date: 19980828 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:LG SEMICON CO., LTD.;REEL/FRAME:026837/0725 Effective date: 20110329 |
|
AS | Assignment |
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED ON REEL 026837 FRAME 0725. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:LG SEMICON CO., LTD.;REEL/FRAME:026855/0660 Effective date: 20010329 |
|
AS | Assignment |
Owner name: 658868 N.B. INC., CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR INC.;REEL/FRAME:027234/0549 Effective date: 20110822 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, CANADA Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196 Effective date: 20111223 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: CHANGE OF NAME;ASSIGNOR:658868 N.B. INC.;REEL/FRAME:032439/0547 Effective date: 20140101 |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT IP N.B. 276 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001 Effective date: 20140611 Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:033707/0001 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CONVERSANT IP N.B. 868 INC.;REEL/FRAME:036159/0386 Effective date: 20150514 |
|
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054371/0884 Effective date: 20201028 |