US20010001084A1 - Novel zero insertion force sockets using negative thermal expansion materials - Google Patents

Novel zero insertion force sockets using negative thermal expansion materials Download PDF

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Publication number
US20010001084A1
US20010001084A1 US09/740,751 US74075100A US2001001084A1 US 20010001084 A1 US20010001084 A1 US 20010001084A1 US 74075100 A US74075100 A US 74075100A US 2001001084 A1 US2001001084 A1 US 2001001084A1
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United States
Prior art keywords
layer
socket device
thermal expansion
socket
connection pad
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US09/740,751
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Tongbi Jiang
Zhiqiang Wu
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Micron Technology Inc
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Micron Technology Inc
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Priority to US09/740,751 priority Critical patent/US20010001084A1/en
Publication of US20010001084A1 publication Critical patent/US20010001084A1/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WU, ZHIQIANG, JIANG, TONGBI
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70Coupling devices
    • H01R12/82Coupling devices connected with low or zero insertion force
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/50Fixed connections
    • H01R12/51Fixed connections for rigid printed circuits or like structures
    • H01R12/55Fixed connections for rigid printed circuits or like structures characterised by the terminals
    • H01R12/58Fixed connections for rigid printed circuits or like structures characterised by the terminals terminals for insertion into holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0195Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06Thermal details
    • H05K2201/068Thermal details wherein the coefficient of thermal expansion is important
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09472Recessed pad for surface mounting; Recessed electrode of component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S439/00Electrical connectors
    • Y10S439/932Heat shrink material

Definitions

  • This invention relates generally to the field of integrated circuits, and, more particularly, to integrated circuit devices having offset junctions to protect circuits from an electrostatic discharge (ESD) and methods for their manufacture.
  • ESD electrostatic discharge
  • sockets comprising spring contacts. These sockets allow easy installation and replacement of electrical elements. With conventional sockets, the terminal pins of an integrated circuit (IC) are pressed into a socket and deflect the spring contacts.
  • IC integrated circuit
  • Modern integrated circuits are often complex and may have a large number of pins. While the force required to insert an individual pin into a socket receptacle is modest, simultaneously inserting a large number of pins into their respective sockets can require a significant insertion force. The insertion force can damage the integrated circuit or bend the pins when the force is significant or when the sockets and pins are not properly aligned.
  • ZIF zero insertion force
  • a widely used conventional zero insertion force socket substantially includes a socket housing having a plurality of metallic conductive contacts disposed in the insertion holes.
  • the insertion holes of the socket are adapted to receive multiple terminal pins of an IC.
  • an operation lever is moved to push a movable plate disposed over the socket housing. The plate then slides a small distance (usually 1 mm) relative to the socket housing, whereby the terminal pins are urged to move toward the contacts and squeeze into a space between two opposite conductive elastic plates comprising the contacts.
  • Typical ZIF sockets are advantageously used to receive large dies or packages, for example a PentiumTM chip.
  • a PentiumTM chip for example a PentiumTM chip.
  • the dies or packages are too small to be mechanically processed practically with a through-hole type ZIF socket employing the offset method discussed above.
  • the proximity of the pins to one another becomes so close that the pins sometimes come into contact with one another and short the circuit.
  • the present invention is directed to overcoming, or at least reducing the effects of, one or more of the issues set forth above.
  • a socket device for receiving an IC terminal pin or solder ball.
  • the socket device includes a substrate having an upper surface, a connection pad disposed on the upper surface of the substrate and a first layer disposed on the upper surface and on the connection pad.
  • the first layer includes material having an overall positive coefficient of thermal expansion.
  • the socket device includes a second layer disposed on the first layer.
  • the second layer includes material having an overall negative coefficient of thermal expansion.
  • the socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad which is receptive of a pin.
  • the socket device only includes the negative coefficient of thermal expansion layer.
  • FIG. 1 is a cross-sectional view of the socket device at room temperature
  • FIG. 2 a is a cross-sectional view of the socket device at an elevated temperature with a pin inserted into the socket;
  • FIG. 2 b is a cross-sectional view of the socket device at normal operating temperature with the pin inserted into the socket;
  • FIG. 3 is a cross-sectional view of the socket device at normal operating temperature with a solder ball/die inserted into the socket.
  • the zero insertion force socket 10 comprises a substrate 12 with an upper surface 14 , a connection pad 16 , a first layer 18 disposed on the substrate 12 and connection pad 16 , and a second layer 20 disposed on the first layer 18 .
  • Substrate 12 for example a ceramic or organic substrate, comprises a base of the socket device 10 upon which the socket is built. Substrate 12 may also comprise a die/package of the another socket assembly upon which the next socket is built.
  • Connection pad 16 is disposed on the upper surface of substrate 12 and attached thereto by a photo define/etch method. Also disposed on the upper surface of substrate 12 and on connection pad 16 is first layer 18 .
  • First layer 18 is bonded to substrate 12 in a way similar to the connection pad by a spin-on and photo define/etch method or drilling.
  • first layer 18 comprises material with an overall positive coefficient of thermal expansion, indicating that the material will expand as temperature is elevated and contract as temperature decreases.
  • first layer 18 comprises silicon oxide SiO 2 , silicon nitride Si 3 N 4 , a polyimide, or similar materials.
  • first layer 18 preferably comprises polyimide or other organic material.
  • first layer 18 preferably comprises silicon oxide or silicon nitride.
  • first layer 18 may be absent from the socket device.
  • second layer 20 Disposed on the upper surface of first layer 18 is second layer 20 .
  • second layer 20 comprises materials with an overall negative coefficient of thermal expansion, indicating that the second layer contracts with a temperature elevation and expands with a temperature decrease.
  • the second layer material preferably has a wide temperature range for which the material exhibits the negative expansion behavior, in order to accommodate use of the socket device in apparatuses with various operation temperatures.
  • One material exhibiting the behavior desirable for the purposes of practicing the present invention is zirconium tungstate ZrW 2 O 8 .
  • the zirconium tungstate may be a single crystal ZrW 2 O 8 , an amorphous ZrW 2 O 8 , or a polymer bound ZrW 2 O 8 .
  • zirconium tungstate exhibits a negative coefficient of thermal expansion over the desired wide range of temperatures, from near absolute zero to 1050° K., its decomposition temperature.
  • Second layer 20 is bonded to first layer 18 with a compliant interfacial layer 22 that allows first layer 18 and second layer 20 to remain bonded to one another despite the opposite tendencies of the layers to contract and expand with temperature changes.
  • the interfacial layer 22 material for example Hitachi's HF-X20, is such that it absorbs the stress between the first and second layers as the opposing movement between layers occurs.
  • connection hole 24 is etched using current technologies, such as photo lithography or laser drilling. Connection hole 24 is receptive of an integrated circuit pin 26 with zero insertion force at elevated temperatures.
  • FIG. 2 a shows the socket in an elevated temperature condition with pin 26 inserted into connection hole 24 .
  • the portion of connection hole 24 formed in first layer 18 has a linear dimension that is larger than the portion of connection hole 24 formed in second layer 20 , the advantage of which being discussed in further detail below.
  • Connection hole 24 through both layers 18 and 20 is substantially larger in dimension than pin 26 when the socket is at elevated temperatures.
  • Connection hole 24 being larger than pin 26 ensures that as pin 26 is inserted or retracted there are no forces required that could potentially damage the pin or the associated integrated circuit.
  • Connection hole 24 is chamfered at the point designated with reference numeral 28 , around the upper perimeter of second layer 20 to act as self-guidance during pin insertion.
  • Chamfer 28 may be accomplished by facet etching or other methods, as would be appreciated by those of ordinary skill in the art.
  • socket device 10 Operation of socket device 10 is as follows: socket device 10 is raised to an elevated temperature in anticipation of receiving pin 26 .
  • the temperature to which the socket device is elevated is such that it is substantially higher than the temperature at which the device will ultimately be operated. For example, if the socket device is intended to be used in a CPU that has a normal operating temperature of 100° C., the temperature to which the socket might be brought prior to insertion of the pin might be 200-250° C.
  • second layer 20 contracts, enlarging connection hole 24 through second layer 20 .
  • the elevated temperature has the opposite effect for connection hole 24 through first layer 18 of the device. The higher temperature causes first layer 18 to expand and therefore decreases the size of connection hole 24 through the first layer.
  • connection hole 24 through first layer 18 becomes smaller with elevated temperatures, connection hole 24 through first layer 18 has a larger dimension at operating temperatures than connection hole 24 through second layer 20 , to ensure a hole through both layers 18 and 20 large enough to accommodate receipt of pin 26 without any insertion force at elevated temperatures. This larger dimension of connection hole 24 through first layer 18 may continue to be exhibited at elevated temperatures if the mounting temperature is greater than the operating temperature.
  • FIG. 2 a exhibits socket device 10 with pin 26 inserted while the device is in an elevated temperature condition.
  • the insertion of pin 26 in this elevated temperature environment leaves pin 26 in substantially close proximity to connection pad 16 , but short of full contact, as shown in FIG. 2 a.
  • Second layer 20 which has a surface in direct contact with the lower temperature medium, begins to cool.
  • Second layer 20 is subject to cooling by two modes of heat transfer: Conduction via direct contact with the cooler environment, and convection, as natural or forced convection currents are established.
  • First layer 18 will also begin to cool by the conduction mode of heat transfer as second layer 20 , with which first layer 18 is bonded, continues to dissipate heat.
  • first layer 18 will not be cooled by convection since it is insulated from the lower temperature environment by a boundary layer comprising second layer 20 .
  • connection hole 24 through second layer 20 becomes smaller, due to the negative coefficient of thermal expansion behavior exhibited by the second layer material.
  • connection hole 24 through second layer 20 will make contact with the circumferential surface of pin 26 .
  • the shrinking of connection hole 24 through second layer 20 continues and pin 26 is secured within socket 10 .
  • Connection hole 24 is sized so as to secure pin 26 in place at temperatures substantially near or below the normal operating temperature of the equipment into which the IC and socket are placed.
  • First layer 18 which has been slower to cool than second layer 20 , begins to contract in accordance with a material having a positive coefficient of thermal expansion in a cooler environment.
  • the results of first layer 18 contraction are a larger connection hole 24 through first layer 18 , an increase in the annular space between the circumferential surface of pin 26 and the inner surface of connection hole 24 , and a reduction in the thickness of first layer 18 .
  • second layer 20 moves into closer proximity with substrate 12 . This occurs because second layer 20 is bonded to first layer 18 .
  • the movement of second layer 20 toward the upper surface of substrate 14 concurrently urges pin 26 , which is secured within connection hole 24 , into contact with connection pad 16 . Socket insertion is complete upon contact between pin 26 and connection pad 16 .
  • connection hole 24 in second layer 20 enlarges and releases pin 26 .
  • Pin 26 can then be retracted from the socket with zero retraction force.
  • the cycle of heating and cooling to allow for insertion and retraction pins is indefinitely repeatable.
  • a socket device 10 ′ is receptive of a solder ball 30 connected to a die 32 instead of a pin.
  • solder ball 30 comprises the same operation as for pin 26 described above.

Abstract

A socket device for receiving a connection pin is disclosed, the socket device including a substrate having an upper surface. The socket device includes a connection pad disposed on the upper surface and a first layer disposed on the upper surface and on the connection pad. The first layer includes material having an overall positive coefficient of thermal expansion. The socket device includes a second layer disposed on the first layer. The second layer includes material having an overall negative coefficient of thermal expansion. The socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad.

Description

    BACKGROUND OF THE INVENTION
  • 1. 1. Field of the Invention
  • 2. This invention relates generally to the field of integrated circuits, and, more particularly, to integrated circuit devices having offset junctions to protect circuits from an electrostatic discharge (ESD) and methods for their manufacture.
  • 3. 2. Description of the Related Art
  • 4. Electrical components are often mounted in sockets comprising spring contacts. These sockets allow easy installation and replacement of electrical elements. With conventional sockets, the terminal pins of an integrated circuit (IC) are pressed into a socket and deflect the spring contacts.
  • 5. Modern integrated circuits are often complex and may have a large number of pins. While the force required to insert an individual pin into a socket receptacle is modest, simultaneously inserting a large number of pins into their respective sockets can require a significant insertion force. The insertion force can damage the integrated circuit or bend the pins when the force is significant or when the sockets and pins are not properly aligned.
  • 6. To avoid the problem of damaging the IC or the pins, various kinds of zero insertion force (ZIF) sockets have been developed, whereby the terminal pins of an IC can be inserted into and withdrawn from such sockets with minimal or no insertion and withdrawal force. This facilitates easy change or replacement of the IC, which is often necessary.
  • 7. A widely used conventional zero insertion force socket substantially includes a socket housing having a plurality of metallic conductive contacts disposed in the insertion holes. The insertion holes of the socket are adapted to receive multiple terminal pins of an IC. According to the zero insertion force arrangement, during the insertion and withdrawal of the IC from the socket, the IC will suffer little or no resistant force from the contacts of the socket. After the pins are inserted into the insertion holes, an operation lever is moved to push a movable plate disposed over the socket housing. The plate then slides a small distance (usually 1 mm) relative to the socket housing, whereby the terminal pins are urged to move toward the contacts and squeeze into a space between two opposite conductive elastic plates comprising the contacts.
  • 8. Several shortcomings may be perceived in the conventional structure. Typical ZIF sockets are advantageously used to receive large dies or packages, for example a Pentium™ chip. For smaller-scale socket devices, for example a “flip chip” assembly, the dies or packages are too small to be mechanically processed practically with a through-hole type ZIF socket employing the offset method discussed above. In addition, as the package size becomes smaller, the proximity of the pins to one another becomes so close that the pins sometimes come into contact with one another and short the circuit.
  • 9. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the issues set forth above.
  • SUMMARY OF INVENTION
  • 10. In accordance with one aspect of the present invention, a socket device for receiving an IC terminal pin or solder ball is provided. The socket device includes a substrate having an upper surface, a connection pad disposed on the upper surface of the substrate and a first layer disposed on the upper surface and on the connection pad. The first layer includes material having an overall positive coefficient of thermal expansion. The socket device includes a second layer disposed on the first layer. The second layer includes material having an overall negative coefficient of thermal expansion. The socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad which is receptive of a pin. In an alternative embodiment the socket device only includes the negative coefficient of thermal expansion layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • 11. The foregoing and other features and aspects of the invention will become further apparent upon reading the following detailed description and upon reference to the drawings in which:
  • 12.FIG. 1 is a cross-sectional view of the socket device at room temperature;
  • 13.FIG. 2a is a cross-sectional view of the socket device at an elevated temperature with a pin inserted into the socket;
  • 14.FIG. 2b is a cross-sectional view of the socket device at normal operating temperature with the pin inserted into the socket;
  • 15.FIG. 3 is a cross-sectional view of the socket device at normal operating temperature with a solder ball/die inserted into the socket.
  • 16. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
  • DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
  • 17. Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, that will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
  • 18. Turning now to the drawings, and in particular to FIG. 1, one embodiment of the socket device in accordance with the present invention is disclosed. The zero insertion force socket 10 comprises a substrate 12 with an upper surface 14, a connection pad 16, a first layer 18 disposed on the substrate 12 and connection pad 16, and a second layer 20 disposed on the first layer 18.
  • 19. Substrate 12, for example a ceramic or organic substrate, comprises a base of the socket device 10 upon which the socket is built. Substrate 12 may also comprise a die/package of the another socket assembly upon which the next socket is built. Connection pad 16 is disposed on the upper surface of substrate 12 and attached thereto by a photo define/etch method. Also disposed on the upper surface of substrate 12 and on connection pad 16 is first layer 18. First layer 18 is bonded to substrate 12 in a way similar to the connection pad by a spin-on and photo define/etch method or drilling. In accordance with one aspect of the invention first layer 18 comprises material with an overall positive coefficient of thermal expansion, indicating that the material will expand as temperature is elevated and contract as temperature decreases. In one embodiment, first layer 18 comprises silicon oxide SiO2, silicon nitride Si3N4, a polyimide, or similar materials. When substrate 12 comprises ceramic or organic material, first layer 18 preferably comprises polyimide or other organic material. However, when substrate 12 is comprises a die or package, first layer 18 preferably comprises silicon oxide or silicon nitride. In an alternative embodiment, first layer 18 may be absent from the socket device.
  • 20. Disposed on the upper surface of first layer 18 is second layer 20. In accordance with another aspect of the invention second layer 20 comprises materials with an overall negative coefficient of thermal expansion, indicating that the second layer contracts with a temperature elevation and expands with a temperature decrease. The second layer material preferably has a wide temperature range for which the material exhibits the negative expansion behavior, in order to accommodate use of the socket device in apparatuses with various operation temperatures. One material exhibiting the behavior desirable for the purposes of practicing the present invention is zirconium tungstate ZrW2O8. The zirconium tungstate may be a single crystal ZrW2O8, an amorphous ZrW2O8, or a polymer bound ZrW2O8. Those of ordinary skill in the art will appreciate that zirconium tungstate exhibits a negative coefficient of thermal expansion over the desired wide range of temperatures, from near absolute zero to 1050° K., its decomposition temperature. Second layer 20 is bonded to first layer 18 with a compliant interfacial layer 22 that allows first layer 18 and second layer 20 to remain bonded to one another despite the opposite tendencies of the layers to contract and expand with temperature changes. The interfacial layer 22 material, for example Hitachi's HF-X20, is such that it absorbs the stress between the first and second layers as the opposing movement between layers occurs.
  • 21. Both first and second layers 18 and 20, respectively, exhibit a connection hole 24 therethrough to expose a portion of the surface of connection pad 16. Connection hole 24 is etched using current technologies, such as photo lithography or laser drilling. Connection hole 24 is receptive of an integrated circuit pin 26 with zero insertion force at elevated temperatures. FIG. 2a shows the socket in an elevated temperature condition with pin 26 inserted into connection hole 24. The portion of connection hole 24 formed in first layer 18 has a linear dimension that is larger than the portion of connection hole 24 formed in second layer 20, the advantage of which being discussed in further detail below. Connection hole 24 through both layers 18 and 20 is substantially larger in dimension than pin 26 when the socket is at elevated temperatures. Connection hole 24 being larger than pin 26 ensures that as pin 26 is inserted or retracted there are no forces required that could potentially damage the pin or the associated integrated circuit. Connection hole 24 is chamfered at the point designated with reference numeral 28, around the upper perimeter of second layer 20 to act as self-guidance during pin insertion. Chamfer 28 may be accomplished by facet etching or other methods, as would be appreciated by those of ordinary skill in the art.
  • 22. Operation of socket device 10 is as follows: socket device 10 is raised to an elevated temperature in anticipation of receiving pin 26. The temperature to which the socket device is elevated is such that it is substantially higher than the temperature at which the device will ultimately be operated. For example, if the socket device is intended to be used in a CPU that has a normal operating temperature of 100° C., the temperature to which the socket might be brought prior to insertion of the pin might be 200-250° C. When socket 10 is raised to an elevated temperature, second layer 20 contracts, enlarging connection hole 24 through second layer 20. The elevated temperature has the opposite effect for connection hole 24 through first layer 18 of the device. The higher temperature causes first layer 18 to expand and therefore decreases the size of connection hole 24 through the first layer. Because connection hole 24 through first layer 18 becomes smaller with elevated temperatures, connection hole 24 through first layer 18 has a larger dimension at operating temperatures than connection hole 24 through second layer 20, to ensure a hole through both layers 18 and 20 large enough to accommodate receipt of pin 26 without any insertion force at elevated temperatures. This larger dimension of connection hole 24 through first layer 18 may continue to be exhibited at elevated temperatures if the mounting temperature is greater than the operating temperature.
  • 23. When an elevated temperature for the socket device 10 has been achieved, the socket can receive pin 26 with zero insertion force. FIG. 2a exhibits socket device 10 with pin 26 inserted while the device is in an elevated temperature condition. The insertion of pin 26 in this elevated temperature environment leaves pin 26 in substantially close proximity to connection pad 16, but short of full contact, as shown in FIG. 2a.
  • 24. Following the insertion of pin 26, the socket and pin combination are removed from the elevated temperature condition. As the environment temperature decreases, second layer 20, which has a surface in direct contact with the lower temperature medium, begins to cool. Second layer 20 is subject to cooling by two modes of heat transfer: Conduction via direct contact with the cooler environment, and convection, as natural or forced convection currents are established. First layer 18 will also begin to cool by the conduction mode of heat transfer as second layer 20, with which first layer 18 is bonded, continues to dissipate heat. However, first layer 18 will not be cooled by convection since it is insulated from the lower temperature environment by a boundary layer comprising second layer 20. Thus second layer 20 will cool more quickly than first layer 18 because first layer 18 only cools as it transfers heat conductively to relatively cooler second layer 20. As second layer 20 cools, connection hole 24 through second layer 20 becomes smaller, due to the negative coefficient of thermal expansion behavior exhibited by the second layer material. When second layer 20 cools sufficiently, the inner diameter of connection hole 24 through second layer 20 will make contact with the circumferential surface of pin 26. The shrinking of connection hole 24 through second layer 20 continues and pin 26 is secured within socket 10. Connection hole 24 is sized so as to secure pin 26 in place at temperatures substantially near or below the normal operating temperature of the equipment into which the IC and socket are placed.
  • 25. After pin 26 has been secured in place, as shown in FIG. 2b, the cooling of socket device 10 continues. First layer 18, which has been slower to cool than second layer 20, begins to contract in accordance with a material having a positive coefficient of thermal expansion in a cooler environment. The results of first layer 18 contraction are a larger connection hole 24 through first layer 18, an increase in the annular space between the circumferential surface of pin 26 and the inner surface of connection hole 24, and a reduction in the thickness of first layer 18. When the dimensions of first layer 18 reduce, second layer 20 moves into closer proximity with substrate 12. This occurs because second layer 20 is bonded to first layer 18. The movement of second layer 20 toward the upper surface of substrate 14 concurrently urges pin 26, which is secured within connection hole 24, into contact with connection pad 16. Socket insertion is complete upon contact between pin 26 and connection pad 16.
  • 26. If it becomes desirable to remove pin 26 from the socket, the socket/pin assembly need only be re-elevated to a temperature such that connection hole 24 in second layer 20 enlarges and releases pin 26. Pin 26 can then be retracted from the socket with zero retraction force. The cycle of heating and cooling to allow for insertion and retraction pins is indefinitely repeatable.
  • 27. In an alternative embodiment depicted in FIG. 3, a socket device 10′ is receptive of a solder ball 30 connected to a die 32 instead of a pin. Those of ordinary skill in the art having the benefit of the present disclosure will appreciate that the insertion and retraction of solder ball 30 comprises the same operation as for pin 26 described above.
  • 28. While the present invention has been particularly shown and described with reference to various illustrative embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. The above-described embodiments are intended to be merely illustrative, and should not be considered as limiting the scope of the present invention.

Claims (17)

What is claimed is:
1. A socket device for receiving a connection pin or solder ball, said socket device comprising:
a substrate having an upper surface;
a connection pad disposed on said upper surface;
a layer disposed on said upper surface and on said connection pad, said layer including material having an overall negative coefficient of thermal expansion;
a contact hole formed in said layer exposing a portion of said connection pad.
2. A socket device for receiving a connection pin or solder ball, said socket device comprising:
a substrate having an upper surface;
a connection pad disposed on said upper surface;
a first layer disposed on said upper surface and on said connection pad, said first layer including material having an overall positive coefficient of thermal expansion;
a second layer disposed on said first layer, said second layer including material having an overall negative coefficient of thermal expansion; and
a contact hole formed in said first and second layers exposing a portion of said connection pad.
3. The socket device of
claim 2
, including a bonding layer disposed between said first and second layers, said bonding layer bonding said first and second layers together.
4. The socket device of
claim 2
, wherein said contact hole includes a first portion formed in said first layer having a first linear dimension and a second portion formed in said second layer having a second linear dimension smaller than said first linear dimension.
5. The socket device of
claim 1
, wherein said layer includes zirconium tungstate.
6. The socket device of
claim 2
, wherein said second layer includes zirconium tungstate.
7. The socket device of
claim 5
, wherein said layer including zirconium tungstate has a substantially isotropic negative thermal expansion behavior.
8. The socket device of
claim 6
, wherein said second layer including zirconium tungstate has a substantially isotropic negative thermal expansion behavior.
9. The socket device of
claim 7
or
8
, wherein said substantially isotropic negative thermal expansion behavior is exhibited at least in a temperature range of from about 100° C. to about 200° C.
10. The socket device of
claim 9
, wherein said substantially isotropic negative thermal expansion behavior is exhibited at least at a temperature of about 150°C.
11. The socket device of
claim 1
, wherein said contact hole includes a chamfer formed in said layer.
12. The socket device of
claim 2
, wherein said contact hole includes a chamfer formed in said second layer.
13. The socket device of
claim 3
, wherein said contact hole includes a first portion formed in said first layer having a first linear dimension and a second portion formed in said second layer having a second linear dimension smaller than said first linear dimension.
14. The socket device of
claim 3
, wherein said second layer includes zirconium tungstate.
15. The socket device of
claim 14
, wherein said second layer including zirconium tungstate has a substantially isotropic negative thermal expansion behavior.
16. The socket device of
claim 15
, wherein said substantially isotropic negative thermal expansion behavior is exhibited at least in a temperature range of from about 100° C. to about 200° C.
17. The socket device of
claim 16
, wherein said substantially isotropic negative thermal expansion behavior is exhibited at least at a temperature of about 150° C.
US09/740,751 1999-02-12 2000-12-19 Novel zero insertion force sockets using negative thermal expansion materials Abandoned US20010001084A1 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004005190A1 (en) * 2002-07-05 2004-01-15 The University Of Sydney Anomalous expansion materials
US20060204776A1 (en) * 2005-03-09 2006-09-14 Jyh-Chen Chen Structure and method of thermal stress compensation
US20080197166A1 (en) * 2004-02-20 2008-08-21 Black & Decker Inc. Adjustable Exhaust Assembly For Pneumatic Fasteners
US20170101518A1 (en) * 2013-08-16 2017-04-13 Berry Plastics Corporation Polymeric material for an insulated container
US9633955B1 (en) * 2016-08-10 2017-04-25 United Microelectronics Corp. Semiconductor integrated circuit structure including dielectric having negative thermal expansion
CN109674139A (en) * 2019-01-23 2019-04-26 宁波市中迪鞋业有限公司 A kind of self-interacting type breathable shoes

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642476B2 (en) * 2001-07-23 2003-11-04 Siemens Automative Corporation Apparatus and method of forming orifices and chamfers for uniform orifice coefficient and surface properties by laser
US6603095B2 (en) * 2001-07-23 2003-08-05 Siemens Automotive Corporation Apparatus and method of overlapping formation of chamfers and orifices by laser light
US6635847B2 (en) 2001-07-31 2003-10-21 Siemens Automotive Corporation Method of forming orifices and chamfers by collimated and non-collimated light
US6600132B2 (en) 2001-07-31 2003-07-29 John James Horsting Method and apparatus to generate orifice disk entry geometry
US6740847B1 (en) 2003-03-10 2004-05-25 Siemens Vdo Automotive Corporation Method of forming multiple machining spots by a single laser
US20050110168A1 (en) * 2003-11-20 2005-05-26 Texas Instruments Incorporated Low coefficient of thermal expansion (CTE) semiconductor packaging materials
CN101414715B (en) * 2007-10-19 2011-01-19 财团法人工业技术研究院 Miniature connector and preparation method thereof
JP5880428B2 (en) * 2012-12-28 2016-03-09 株式会社オートネットワーク技術研究所 Card edge connector

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602635A (en) * 1970-06-30 1971-08-31 Ibm Micro-circuit device
US4513055A (en) * 1981-11-30 1985-04-23 Trw Inc. Controlled thermal expansion composite and printed circuit board embodying same
US4590539A (en) * 1985-05-15 1986-05-20 Westinghouse Electric Corp. Polyaramid laminate
US4642160A (en) * 1985-08-12 1987-02-10 Interconnect Technology Inc. Multilayer circuit board manufacturing
US4916808A (en) * 1988-02-22 1990-04-17 Harris Corporation Process for fabricating a sculptured stripling interface conductor
US4950173A (en) * 1983-06-15 1990-08-21 Hitachi, Ltd. Service temperature connector and packaging structure of semiconductor device employing the same
US5123849A (en) * 1990-11-15 1992-06-23 Amp Incorporated Conductive gel area array connector
US5387121A (en) * 1993-09-13 1995-02-07 Kurz; Edward A. Zero insertion force socket
US5433778A (en) * 1993-05-11 1995-07-18 The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Negative thermal expansion material
US5466169A (en) * 1994-08-03 1995-11-14 Lai; Kuang-Chih Zero insertion force socket
US5497545A (en) * 1992-03-19 1996-03-12 Hitachi, Ltd. Method of making electrical connections in the manufacture of wiring sheet assemblies
US5514360A (en) * 1995-03-01 1996-05-07 The State Of Oregon, Acting By And Through The Oregon State Board Of Higher Education, Acting For And On Behalf Of Oregon State University Negative thermal expansion materials
US5557066A (en) * 1993-04-30 1996-09-17 Lsi Logic Corporation Molding compounds having a controlled thermal coefficient of expansion, and their uses in packaging electronic devices
US5607313A (en) * 1995-02-27 1997-03-04 Autosplice Systems, Inc. Surface mounted holes for printed circuit boards
US5641291A (en) * 1993-12-13 1997-06-24 Japan Solderless Terminal Mfg. Co., Ltd. Printed circuit board connector
US5919720A (en) * 1997-04-15 1999-07-06 State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Materials with low or negative thermal expansion
US5935638A (en) * 1998-08-06 1999-08-10 Dow Corning Corporation Silicon dioxide containing coating
US5966803A (en) * 1996-05-31 1999-10-19 International Business Machines Corporation Ball grid array having no through holes or via interconnections
US6187700B1 (en) * 1998-05-19 2001-02-13 Corning Incorporated Negative thermal expansion materials including method of preparation and uses therefor
US6195193B1 (en) * 1998-09-21 2001-02-27 Gentex Corporation Seal for electrochromic devices
US6274932B1 (en) * 1994-08-30 2001-08-14 Nec Corporation Semiconductor device having metal interconnection comprising metal silicide and four conductive layers
US6555414B1 (en) * 2000-02-09 2003-04-29 Interuniversitair Microelektronica Centrum, Vzw Flip-chip assembly of semiconductor devices using adhesives

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602635A (en) * 1970-06-30 1971-08-31 Ibm Micro-circuit device
US4513055A (en) * 1981-11-30 1985-04-23 Trw Inc. Controlled thermal expansion composite and printed circuit board embodying same
US4950173A (en) * 1983-06-15 1990-08-21 Hitachi, Ltd. Service temperature connector and packaging structure of semiconductor device employing the same
US4590539A (en) * 1985-05-15 1986-05-20 Westinghouse Electric Corp. Polyaramid laminate
US4642160A (en) * 1985-08-12 1987-02-10 Interconnect Technology Inc. Multilayer circuit board manufacturing
US4916808A (en) * 1988-02-22 1990-04-17 Harris Corporation Process for fabricating a sculptured stripling interface conductor
US5123849A (en) * 1990-11-15 1992-06-23 Amp Incorporated Conductive gel area array connector
US5497545A (en) * 1992-03-19 1996-03-12 Hitachi, Ltd. Method of making electrical connections in the manufacture of wiring sheet assemblies
US5557066A (en) * 1993-04-30 1996-09-17 Lsi Logic Corporation Molding compounds having a controlled thermal coefficient of expansion, and their uses in packaging electronic devices
US5433778A (en) * 1993-05-11 1995-07-18 The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Negative thermal expansion material
US5387121A (en) * 1993-09-13 1995-02-07 Kurz; Edward A. Zero insertion force socket
US5641291A (en) * 1993-12-13 1997-06-24 Japan Solderless Terminal Mfg. Co., Ltd. Printed circuit board connector
US5466169A (en) * 1994-08-03 1995-11-14 Lai; Kuang-Chih Zero insertion force socket
US6274932B1 (en) * 1994-08-30 2001-08-14 Nec Corporation Semiconductor device having metal interconnection comprising metal silicide and four conductive layers
US5607313A (en) * 1995-02-27 1997-03-04 Autosplice Systems, Inc. Surface mounted holes for printed circuit boards
US5514360A (en) * 1995-03-01 1996-05-07 The State Of Oregon, Acting By And Through The Oregon State Board Of Higher Education, Acting For And On Behalf Of Oregon State University Negative thermal expansion materials
US5966803A (en) * 1996-05-31 1999-10-19 International Business Machines Corporation Ball grid array having no through holes or via interconnections
US5919720A (en) * 1997-04-15 1999-07-06 State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University Materials with low or negative thermal expansion
US6187700B1 (en) * 1998-05-19 2001-02-13 Corning Incorporated Negative thermal expansion materials including method of preparation and uses therefor
US5935638A (en) * 1998-08-06 1999-08-10 Dow Corning Corporation Silicon dioxide containing coating
US6195193B1 (en) * 1998-09-21 2001-02-27 Gentex Corporation Seal for electrochromic devices
US6555414B1 (en) * 2000-02-09 2003-04-29 Interuniversitair Microelektronica Centrum, Vzw Flip-chip assembly of semiconductor devices using adhesives

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004005190A1 (en) * 2002-07-05 2004-01-15 The University Of Sydney Anomalous expansion materials
US20050228166A1 (en) * 2002-07-05 2005-10-13 Kepert Cameron J Anomalous expansion materials
US20080197166A1 (en) * 2004-02-20 2008-08-21 Black & Decker Inc. Adjustable Exhaust Assembly For Pneumatic Fasteners
US20060204776A1 (en) * 2005-03-09 2006-09-14 Jyh-Chen Chen Structure and method of thermal stress compensation
US20170101518A1 (en) * 2013-08-16 2017-04-13 Berry Plastics Corporation Polymeric material for an insulated container
US9633955B1 (en) * 2016-08-10 2017-04-25 United Microelectronics Corp. Semiconductor integrated circuit structure including dielectric having negative thermal expansion
CN109674139A (en) * 2019-01-23 2019-04-26 宁波市中迪鞋业有限公司 A kind of self-interacting type breathable shoes

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US6164993A (en) 2000-12-26

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