EP2249351A1 - Method for multilevel programming of phase change memory cells using a percolation algorithm - Google Patents
Method for multilevel programming of phase change memory cells using a percolation algorithm Download PDFInfo
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- EP2249351A1 EP2249351A1 EP10173621A EP10173621A EP2249351A1 EP 2249351 A1 EP2249351 A1 EP 2249351A1 EP 10173621 A EP10173621 A EP 10173621A EP 10173621 A EP10173621 A EP 10173621A EP 2249351 A1 EP2249351 A1 EP 2249351A1
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/009—Write using potential difference applied between cell electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Definitions
- Phase change can be obtained by locally increasing the temperature. Below 150°C, both phases are stable. Starting from an amorphous state, and raising the temperature above 200°C, there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600°C) and then rapidly cool off the chalcogenide.
Abstract
Description
- The present invention relates to a method for multilevel programming of phase change memory cells and to a multilevel phase change memory device.
- As is known, phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated with two different crystallographic structures of the material: an amorphous, disorderly phase, and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
- Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has been also proposed for mass storage.
- In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
- Phase change can be obtained by locally increasing the temperature. Below 150°C, both phases are stable. Starting from an amorphous state, and raising the temperature above 200°C, there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600°C) and then rapidly cool off the chalcogenide.
- Memory devices exploiting the properties of chalcogenic materials. (also called phase change memory devices) have been already proposed.
- The composition of chalcogenides suitable for the use in a phase change memory device and a possible structure of a phase change element is disclosed in a number of documents (see, e.g. ,
US 5,825,046 ). - As discussed in
EP-A-1 326 254 (corresponding toUS-A-2003/0185047 ) a memory element of a phase change memory device comprises a chalcogenic material and a resistive electrode, also called a heater. - In fact, from an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or close proximity with the chalcogenic material and thus heating the chalcogenic material by Joule effect.
- In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the reset state), it is necessary to apply a voltage/current pulse of a suitable length and amplitude and allow the chalcogenic material to cool slowly. In this condition, the chalcogenic material changes its state and switches from a high resistivity to a low resistivity state (also called the set state).
- Vice versa, when the chalcogenic material is in the set state, it is necessary to apply a voltage/current pulse of suitable length and high amplitude so as to cause the chalcogenic material to switch to the amorphous phase.
- As already mentioned, the resistivity of phase change materials may vary several orders of magnitude upon switching between the fully set (crystalline) state to the fully reset (amorphous) state. A typical range, for example, is 1 mΩ*cm in the set state to 1000 mΩ*cm in the reset state. However, the resistivity of the amorphous chalcogenic material is not stable and continuously increases according to a sub-linear law after phase transition. Thus, a quite rapid resistivity drift may take place, especially when large extensions of chalcogenic material are brought to the amorphous state.
- The resistivity drift would not normally cause major problems in conventional two-level phase change memory cells, since the gap between the set state and the reset state is increased as well. Multilevel programming, instead, is not compatible with the resistivity drift, at present. According to conventional programming methods, in fact, every time a programming cycle is started, phase change memory cells are first brought to the fully crystalline state and then partially amorphized through a single voltage or current pulse, which lasts until a desired intermediate resistivity level is achieved. In this manner, however, large amorphous regions are still created, which are subjected to resistivity drift. The gap between the intermediate programming levels may not be kept constant and is narrowed on account of the resistivity drift. Thus, a sense amplifier associated to multilevel cells would fail to distinguish adjacent levels in a relatively short time after each phase transition. Moreover, the configuration of the large amorphous regions that are every time created greatly affects the resistivity level, but is not predictable. Thus, repeating identical programming cycles on the same phase memory change cell may lead to different resistivity levels.
- The object of the invention is to provide a method for multilevel programming of phase change memory cells and a multilevel phase change memory device, which are free from the above-described drawbacks.
- According to the present invention, there is provided a method for programming a phase change memory cell and a phase change memory device, as defined respectively in
claims - For the understanding of the present invention, preferred embodiments thereof are now described, purely as a non-limitative example, with reference to the enclosed drawings, wherein:
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Figure 1 shows a simplified block diagram of a phase change memory device implementing a programming method according to the present invention; -
figure 2 is a cross section through a memory cell of the phase change memory device offigure 1 ; -
figure 3 is a top plan view, taken along the line III-III offigure 2 ; -
figure 4 is a cross section taken along the lines IV-IV offigures 2 andfigure 3 ; -
figure 5 is a plot showing read current levels -
figure 6 is a flowchart of a method for programming a multi-level phase change memory element. -
figure 7 is a plot showing the linear relationship between percolation programming current and read current of a percolated bit; -
figure 8 is a plot showing a comparison between a drift exponent of homogenous bits and parallel percolated bits; -
figure 9 is a system depiction of one embodiment of the present invention. -
Figure 1 shows a phase change memory ("PCM" hereinafter)device 1. A plurality ofPCM cells 2 are arranged in rows and columns to form anarray 3. Arow decoder 4 and acolumn decoder 5 are coupled to a read/writeunit 7, which includes aprogramming circuit 7a and averify circuit 7b.Word lines 8 andbit lines 9 run parallel to rows and columns, respectively, and are selectively connectable to the read/writeunit 7 through therow decoder 4 and thecolumn decoder 5, in a known manner. -
PCM cells 2 are connected at a cross-point of aword line 8 and abit line 9 and include amemory element 10, of the phase change type, and aselection element 11. Thememory element 10 has a first terminal connected to itsrespective bit line 9 and a second terminal connected to a first terminal of theselection element 11. Theselection element 11 has a second terminal grounded and a control terminal connected to aword line 8. According to alternative solutions, thememory element 10 and theselection element 11 of eachPCM cell 2 may be exchanged in position; moreover, theselection elements 11 may have two terminals only (e.g. diodes). - The
programming circuit 7a is configured for providing initialization pulses PI and programming pulses PR, PP0, PPK (either current or voltage pulses) to selectedPCM cells 2, according to a programming method described below. Theverify circuit 7b is connected to theselected PCM cells 2 for reading the information stored therein (e.g., after each programming pulse). - A cross-section of a
PCM cell 2 is illustrated infigure 2 . In the embodiment herein described, theselection element 11 is a MOS transistor, but other selection elements may be used (e.g., a bipolar transistor). TheMOS transistor 11 includes adrain region 12a, asource region 12b, agate region 12c, and drain andsource contacts drain 12a andsource 12b are formed with N+ implants. Thegate 12c is made of polysilicon and extends above a semiconductor substrate 18 (of P-type) and is isolated there from. Thegate 12c is connected toword line 8 and, when activated, turns the transistor on by creating a conductive channel between thedrain 12a andsource 12b. The MOS transistor may be in saturation and used as a voltage-controlled current-source selector. - A cup-
shaped heating element 16 is formed on thedrain contact 14a. An upper portion of the heating element is defined by a circular or oval wall having sublithographic thickness, as also shown infigure 3 . Here, the term "sublithographic" means a linear dimension smaller than the minimum dimension achievable with current optical (UV) lithographic techniques, and hence smaller than 100 nm, preferably 50-60 nm, down to approximately 5-20 nm. Astrip 17 of a chalcogenic material, e.g. GST, runs parallel to thebit lines 9 and is separated from theheating element 16 by a minitrench layer 19 (e.g., nitride). Additionally, acap layer 21 and abarrier layer 22 are positioned between and parallel to thestrip 17 andbit lines 9. An elongated minitrench 20 (see alsofigure 3 ) is formed through theminitrench layer 19 above and across theheating element 16 in a direction parallel to the bit lines 9. Thus, athin portion 17a of thestrip 17 fills theminitrench 20 and contacts theheating element 16, as shown infigure 4 . Downwardly, theminitrench 20 has a sublithographic width in a direction parallel to theword lines 8, so that a contact area between thethin portion 17a of thestrip 17 and theheating element 16 has sublithographic extension as well. Thememory element 10 of thePCM cell 2 is formed in thethin portion 17a of thestrip 17 at the contact area. On account of the sublithographic extension of the contact area, even relatively small currents flowing through thestrip 17 and theheating element 16 will provide sufficient heating by Joule effect to cause phase transitions in a volume corresponding to thememory element 10. - In particular, a small amount of current can be used to create a
percolation path 25 having an average diameter D within theminitrench 20. Thepercolation path 25 is a crystalline path that passes through thephase change material 27, which is in an amorphous state. Thus, thepercolation path 25 passes within thethin portion 17a and continuously from theheating element 16 to thestrip 17. Once apercolation path 25 is formed, a pulse with increased amplitude can be used to increase the diameter of the path, as further described below. Information stored inPCM cells 2 is associated to predetermined resistance levels (programming states) of the chalcogenic material forming thememory elements 10. Thus, by changing the diameter of thepercolation path 25, the resistance levels can be correspondingly changed. The particular resistance levels and ranges will vary depending on the application. For example, isotropic scaling of devices will reduce the dimensions of thememory elements 10 and will correspondingly increase their resistance levels. - All the
PCM cells 2 may be initialized once after manufacturing, in order to minimize the variability of their programming characteristics. To this end, theprogram circuit 7a supplies thePCM cells 2 with a single initialization pulse PT having such amplitude and duration as to bring the chalcogenic material of thememory elements 10 first to the fully reset state and then to the fully set state. The chalcogenic material is thus made uniform and possible irregularities are removed. The initialization pulse PI may be a current or voltage sloped pulse that allows slow cool off of the chalcogenic material. As an alternative, a decreasing stepped ramp would be acceptable as well. -
Figure 5 shows a plot of the probability density versus current for a four-state PCM cell (additional states may be added by further sub-dividing the current ranges as is well-known in the art). It is desirable to use the full programming range including the "00" (amorphous) and "11" (crystalline) to allow more margin for the intermediate levels "01" and "10". In this case, "00" is an amorphous state associated with reset bits. Reset is typically obtained with a single square pulse (e.g., 50 ns) that drives the chalcogenide material to a melting point of approximately 600°C and then rapidly cools it. Level "11" is associated to set bits in an all crystalline state. Set is typically obtained with a single square pulse that drives the chalcogenide material up to crystallization temperature (e.g. 400°C) and maintains it there until long-range order is reconstructed. Alternatively, set can be obtained by driving the chalcogenide material to the melting point and then cooling it slowly enough for the crystals to reorganize. - The two intermediate states "01", "10" generally require additional programming pulses and the creation of a percolation path. The programming of the intermediate states is described more fully with respect to
figure 6 . Turning tofigure 6 , inprocess block 70, a reset pulse PR is applied to place the PCM in the amorphous state '00". Then theprogram circuit 7a is configured to provide a start programming pulse PP0 and one or more adjust programming pulses PPK. Inprocess block 72, a start programming pulse PP0 creates a percolation path of estimated diameter D to bring the current levels to either the start of the "01" range as shown at 50 (seefigure 5 ) or the start of the "10" range as shown at 52 (figure 5 ), depending on the desired programming. This first percolation pulse is applied with a fixed current about five-times lower than typical crystallization currents. However, thecurrent levels process block 74, the verifycircuit 7b reads the current of the PCM cell to see if the current is within the desired ranges as indicated at 54, 56 infigure 5 . To accomplish this, the verifycircuit 7b applies a predetermine voltage and compares the currents that flow through the selectedPCM cells 2. - In
decision block 76, a determination is made whether the read current is within the desired range (i.e., 54 for "01" or 56 for "10"). If the current reading is below the desired level, inprocess block 78, theprogramming circuit 7a applies a pulse having an increased amplitude and the same width as the previous pulse applied. A pulse of increased amplitude will result in an increase in the diameter of the percolation path. As shown atarrow 79, process blocks 74, 76, and 78 are repeated with pulses of increasing amplitude and fixed width until the verifycircuit 7b determines that the current readings are within the desired tolerances. If so,decision block 76 is answered in the affirmative and the programming is completed atprocess block 80. An alternative approach is to use pulses of fixed amplitude and increasing width. -
Figure 7 is a plot showing the linear relationship between the programming current and the read current. Thus, increasing amplitude of the programming current results in a percolation path with a larger diameter or width and a correspondingly increased read current. -
Figure 8 shows one of the advantages of the present invention. Specifically, the percolation path provides a reduced resistance drift. The percolation path is a parallel current path through the chalcogenic material that effectively hides any series current components. The plot of the drift component for the percolation path is shown with the triangular plot points, whereas a series path, shown by diamonds, has higher resistance drift. - In
Figure 9 , a portion of asystem 500 in accordance with an embodiment of the present invention is described.System 500 may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly.System 500 may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, or a cellular network, although the scope of the present invention is not limited in this respect. -
System 500 may include acontroller 510, an input/output (I/O) device 520 (e.g. a keypad, display), the phasechange memory device 1, awireless interface 540, and a static random access memory (SRAM) 560 and coupled to each other via abus 550. Abattery 580 may supply power to thesystem 500 in one embodiment. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components. -
Controller 510 may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. The phasechange memory device 1 may be used to store messages transmitted to or bysystem 500. The phasechange memory device 1 may also optionally be used to store instructions that are executed bycontroller 510 during the operation ofsystem 500, and may be used to store user data. The instructions may be stored as digital information and the user data, as disclosed herein, may be stored in one section of the memory as digital data and in another section as analog memory. As another example, a given section at one time may be labeled as such and store digital information, and then later may be relabeled and reconfigured to store analog information. - The I/
O device 520 may be used to generate a message. Thesystem 500 may use thewireless interface 540 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of thewireless interface 540 may include an antenna, or a wireless transceiver, such as a dipole antenna, although the scope of the present invention is not limited in this respect. Also, the I/O device 520 may deliver a voltage reflecting what is stored as either a digital output (if digital information was stored), or as analog information (if analog information was stored). - While an example in a wireless application is provided above, embodiments of the present invention may also be used in non-wireless applications as well.
- Finally, it is clear that numerous variations and modifications may be made to programming method and to the phase change memory device described and illustrated herein, all falling within the scope of the invention as defined in the attached claims. In particular, the invention is not limited to the PCM cell structure as described above. Any kind of selecting elements and memory elements may be used, as well as any suitable shape of heating elements (wall heating elements, lance heating elements or other).
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- A. A method for programming a phase change memory cell (2), wherein the phase change memory cell (2) includes a memory element (10) of a phase change material having a first state ("11"), in which said phase change material is crystalline and has a minimum resistance level (RMIN), a second state ("00") in which said phase change material is amorphous and has a maximum resistance level (RMAX), and a plurality of intermediate states ("01", "10") having associated resistance levels between RMIN and RMAX;
the method comprising providing a plurality of programming pulses to the phase change memory cell (2);
characterised in that a first programming pulse (Pp0) creates a crystalline percolation path (25) having an average diameter (D) through the phase change material in the amorphous state (27) and one or more additional programming pulses (Ppx) modify the diameter (D) of the crystalline percolation path (25) to program the phase change memory cell (2) in one of the intermediate states ("01", "10"). - B. The method as described in statement A, further including applying a reset programming pulse (PR) to place the phase change material in the second state ("00") prior to applying the first programming pulse (PP0).
- C. The method according to statements A or B, wherein the one or more additional programming pulses (PPK) increase the average diameter (D) of the crystalline percolation path (25).
- D. The method according to anyone of the foregoing statements, wherein each of the one or more additional programming pulses (PPK) has an increasing amplitude and the same width as the previous programming pulse.
- E. The method according to anyone of the foregoing statements, wherein each of the one or more additional programming pulses (PPK) have a fixed amplitude and an increasing width with respect to the previous programming pulse.
- F. The method according to anyone of the foregoing statements, further including:
- (a) reading the current level of the phase change memory cell (2);
- (b) if the current level is below a target current level (54, 56) for programming one of the intermediate states ("01", "10"), then applying an additional programming pulse (PPK) having a larger amplitude than a previous programming pulse;
- (c)repeating (a) and (b) until the target current level (54, 56) is obtained.
- G. A method according to any one of the foregoing statements, wherein said phase change memory cell (2) is initialized before providing any programming pulses (PR, PP0, PPK).
- H. A method according to statement G, wherein initializing said phase change memory cell (2) comprises providing an initialization pulse (P1) having such amplitude and duration as to bring said chalcogenic material to said second state (reset) and then to said first state (set).
- I. A phase change memory device, comprising:
- a plurality of phase change memory cells (2), wherein a phase change memory cell (2) includes a memory element (10) of a phase change material having a first state ("11"), in which said phase change material is crystalline and has a minimum resistance level (RMIN), a second state ("00") in which said phase change material is amorphous and has a maximum resistance level (RMAX), and a plurality of intermediate states ("01", "10") having associated resistance levels between RMIN and Rmax;
- a program circuit (7a) for providing a plurality of programming pulses (PP0, PPK) to said phase change memory cells (2);
characterised in that a first programming pulse (PP0) generated by the programming circuit (7a) creates a crystalline percolation path (25) having an average diameter (D) through the phase change material in the amorphous state (27) and one or more additional programming pulses (PPK) modify the diameter (D) of the crystalline percolation path (25) to program the phase change memory cell in one of the intermediate states ("01", "10").
- J. The phase change memory device of statement I, further including a verify circuit (7b) coupled to the programming circuit (7a) for reading a current from the phase change memory cell (2) to determine if it reached the desired intermediate state ("01", "10").
- K. The phase change memory device of statements I or J wherein the phase change memory cell (2) includes a selector (11).
- L. The phase change memory device of statement K, wherein the selector (11) includes either a MOS or bipolar transistor.
- M. The phase change memory device of any of the preceding statements I to L, wherein the phase change memory cell (2) includes a heating element (16).
- N. A system (500) comprising:
- a processing unit (510);
- an interface (540) coupled to said processing unit; and
- a nonvolatile phase change memory device (1) according to any of statements I to M, coupled to said processing unit.
- O. A system according to statement N, wherein said interface (540) is a wireless interface.
Claims (14)
- A method, comprising: programming a phase change memory cell(2) to an intermediate state between a first state (11), in which said phase change material is crystalline and has a first resistance level (R1) and a second state (00) in which said phase change material is amorphous and has a second resistance level (R2), the intermediate state having an intermediate resistance level between R1 and R2, the programming including: providing to the phase change memory cell a first programming pulse (PPO) that creates a crystalline percoladon path (25) within the phase change material in the amorphous state; and providing to the phase change memory cell one or more additional programming pulses (PPK) that modify an average diameter (D) of the crystalline percolation path to program the phase change memory cell in the intermediate state.
- The method as claimed in claim 1, further including applying a reset programming pulse (PR) to place the phase change material in the second state prior to applying the frst programming pulse.
- The method according to claim 1, wherein the one or more additional programming pulses increase the average diameter of the crystalline percolation path.
- The method according to claim 1, wherein each of the one or more additional programming pulses has an increasing amplitude and a width equal to a width of an immediately previous programming pulse of the programming pulses.
- The method according to claim 1, wherein each of the one or more additional programming pulses have a fixed amplitude and an increasing width with respect to the previous programming pulse.
- The method according to claim 1, further including: (a) reading a current level of the phase change memory cell; (b) if the current level is below a target current level for programming to the intermediate state, then applying an additional programming pulse having a larger amplitude than a previous programming pulse; (c) repeating (a) and (b) until the target current level is obtained.
- A method according to claim 1, wherein said phase change memory cell is initialized before providing any programming pulses by providing an initialization pulse having such amplitude and duration as to bring said chalcogenic phase change material to said second state and then to said first state.
- A phase change memory device, comprising:a phase change memory cell (2) that includes a phase change material; anda means for programming the phase change memory cell(2) to an intermediate state between a first state (11), in which said phase change material is crystalline and has a first resistance level (R1) and a second state (00) in which said phase change material is amorphous and has a second resistance level (R2), the intermediate state having an intermediate resistance level between R1 and R2, wherein the means for programming including:providing to the phase change memory cell a first programming pulse (PPO) that creates a crystalline percolation path (25) within the phase change material in the amorphous state; andproviding to the phase change memory cell one or more additional programming pulses (PPK) that modify an average diameter (D) of the crystalline percolation path to program the phase change memory cell in the intermediate state.
- The phase change memory device as claimed in claim 8, wherein the means for programming further includes applying a reset programming pulse (PR) to place the phase change material in the second state prior to applying the first programming pulse.
- The phase change memory device according to claim 8, wherein the one or more additional programming pulses increase the average diameter of the crystalline percolation path.
- The phase change memory device according to claim 8, wherein each of the one or more additional programming pulses has an increasing amplitude and a width equal to a width of an immediately previous programming pulse of the programming pulses.
- The phase change memory device according to claim 8, wherein each of the one or more additional programming pulses have a fixed amplitude and an increasing width with respect to the previous programming pulse.
- The phase change memory device according to claim 8, wherein the means for programming further including: (a) reading a current level of the phase change memory cell; (b) if the current level is below a target current level for programming to the intermediate state, then applying an additional programming pulse having a larger amplitude than a previous programming pulse; (c) repeating (a) and (b) until the target current level is obtained.
- A phase change memory device according to claim 8, wherein said phase change memory cell is initialized before providing any programming pulses by providing an initialization pulse having such amplitude and duration as to bring said chalcogenic phase change material to said second state and then to said first state.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11164628B2 (en) | 2020-02-21 | 2021-11-02 | International Business Machines Corporation | Compensating PCM drift for neuromorphic applications |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070025166A1 (en) * | 2005-07-27 | 2007-02-01 | Spansion Llc | Program/erase waveshaping control to increase data retention of a memory cell |
DE602006012825D1 (en) | 2006-07-27 | 2010-04-22 | St Microelectronics Srl | Phase change memory device |
US8116117B2 (en) | 2006-11-29 | 2012-02-14 | Samsung Electronics Co., Ltd. | Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device |
KR100801082B1 (en) * | 2006-11-29 | 2008-02-05 | 삼성전자주식회사 | Operating method of multi-level memory device using variable resistive element and multi-level memory device using variable resistive element |
JP2008218492A (en) * | 2007-02-28 | 2008-09-18 | Elpida Memory Inc | Phase change memory device |
US7577023B2 (en) * | 2007-05-04 | 2009-08-18 | Qimonda North America Corp. | Memory including write circuit for providing multiple reset pulses |
KR100909770B1 (en) * | 2007-08-10 | 2009-07-29 | 주식회사 하이닉스반도체 | Driving Method of Phase Change Memory Device |
KR100905170B1 (en) * | 2007-08-10 | 2009-06-29 | 주식회사 하이닉스반도체 | Method for driving phase change memory device |
JP5172269B2 (en) * | 2007-10-17 | 2013-03-27 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US7961507B2 (en) | 2008-03-11 | 2011-06-14 | Micron Technology, Inc. | Non-volatile memory with resistive access component |
JP2009266316A (en) * | 2008-04-25 | 2009-11-12 | Semiconductor Technology Academic Research Center | Memory device, electronic equipment, recording method for phase change memory device |
US8134857B2 (en) * | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US8076208B2 (en) * | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8031517B2 (en) | 2008-07-30 | 2011-10-04 | Samsung Electronics Co., Ltd. | Memory device, memory system having the same, and programming method of a memory cell |
IT1392578B1 (en) * | 2008-12-30 | 2012-03-09 | St Microelectronics Rousset | MULTILEVEL PROGRAMMING METHOD OF MEMORY CELLS AT USING PHASE OF CHANGING ADAPTIVE RESET PULSES |
KR101057725B1 (en) * | 2008-12-31 | 2011-08-18 | 주식회사 하이닉스반도체 | Multi-level cell data sensing device and method thereof |
US8107283B2 (en) * | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US7929338B2 (en) * | 2009-02-24 | 2011-04-19 | International Business Machines Corporation | Memory reading method for resistance drift mitigation |
US8331168B2 (en) * | 2009-04-30 | 2012-12-11 | International Business Machines Corporation | Increased capacity heterogeneous storage elements |
US8470635B2 (en) * | 2009-11-30 | 2013-06-25 | Micron Technology, Inc. | Keyhole-free sloped heater for phase change memory |
US8908414B2 (en) * | 2009-12-18 | 2014-12-09 | Micron Technology, Inc. | Modified reset state for enhanced read margin of phase change memory |
US9196530B1 (en) | 2010-05-19 | 2015-11-24 | Micron Technology, Inc. | Forming self-aligned conductive lines for resistive random access memories |
US9224496B2 (en) | 2010-08-11 | 2015-12-29 | Shine C. Chung | Circuit and system of aggregated area anti-fuse in CMOS processes |
US8488359B2 (en) | 2010-08-20 | 2013-07-16 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices |
US9818478B2 (en) | 2012-12-07 | 2017-11-14 | Attopsemi Technology Co., Ltd | Programmable resistive device and memory using diode as selector |
US9460807B2 (en) | 2010-08-20 | 2016-10-04 | Shine C. Chung | One-time programmable memory devices using FinFET technology |
US9236141B2 (en) | 2010-08-20 | 2016-01-12 | Shine C. Chung | Circuit and system of using junction diode of MOS as program selector for programmable resistive devices |
US10249379B2 (en) | 2010-08-20 | 2019-04-02 | Attopsemi Technology Co., Ltd | One-time programmable devices having program selector for electrical fuses with extended area |
US8830720B2 (en) | 2010-08-20 | 2014-09-09 | Shine C. Chung | Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices |
US10923204B2 (en) | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
US9711237B2 (en) | 2010-08-20 | 2017-07-18 | Attopsemi Technology Co., Ltd. | Method and structure for reliable electrical fuse programming |
US10229746B2 (en) | 2010-08-20 | 2019-03-12 | Attopsemi Technology Co., Ltd | OTP memory with high data security |
US9431127B2 (en) | 2010-08-20 | 2016-08-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices |
US9025357B2 (en) | 2010-08-20 | 2015-05-05 | Shine C. Chung | Programmable resistive memory unit with data and reference cells |
US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
US9042153B2 (en) | 2010-08-20 | 2015-05-26 | Shine C. Chung | Programmable resistive memory unit with multiple cells to improve yield and reliability |
US8804398B2 (en) | 2010-08-20 | 2014-08-12 | Shine C. Chung | Reversible resistive memory using diodes formed in CMOS processes as program selectors |
US9251893B2 (en) | 2010-08-20 | 2016-02-02 | Shine C. Chung | Multiple-bit programmable resistive memory using diode as program selector |
US9496033B2 (en) | 2010-08-20 | 2016-11-15 | Attopsemi Technology Co., Ltd | Method and system of programmable resistive devices with read capability using a low supply voltage |
US8559208B2 (en) | 2010-08-20 | 2013-10-15 | Shine C. Chung | Programmably reversible resistive device cells using polysilicon diodes |
US9070437B2 (en) | 2010-08-20 | 2015-06-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink |
US9824768B2 (en) | 2015-03-22 | 2017-11-21 | Attopsemi Technology Co., Ltd | Integrated OTP memory for providing MTP memory |
US9019742B2 (en) | 2010-08-20 | 2015-04-28 | Shine C. Chung | Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory |
US9076513B2 (en) | 2010-11-03 | 2015-07-07 | Shine C. Chung | Low-pin-count non-volatile memory interface with soft programming capability |
US9019791B2 (en) | 2010-11-03 | 2015-04-28 | Shine C. Chung | Low-pin-count non-volatile memory interface for 3D IC |
US8988965B2 (en) | 2010-11-03 | 2015-03-24 | Shine C. Chung | Low-pin-count non-volatile memory interface |
US8913449B2 (en) | 2012-03-11 | 2014-12-16 | Shine C. Chung | System and method of in-system repairs or configurations for memories |
CN102544011A (en) * | 2010-12-08 | 2012-07-04 | 庄建祥 | Anti-fuse memory and electronic system |
US10192615B2 (en) | 2011-02-14 | 2019-01-29 | Attopsemi Technology Co., Ltd | One-time programmable devices having a semiconductor fin structure with a divided active region |
US8848423B2 (en) | 2011-02-14 | 2014-09-30 | Shine C. Chung | Circuit and system of using FinFET for building programmable resistive devices |
US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
US9324849B2 (en) | 2011-11-15 | 2016-04-26 | Shine C. Chung | Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC |
US8912576B2 (en) | 2011-11-15 | 2014-12-16 | Shine C. Chung | Structures and techniques for using semiconductor body to construct bipolar junction transistors |
US9136261B2 (en) | 2011-11-15 | 2015-09-15 | Shine C. Chung | Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection |
US9007804B2 (en) | 2012-02-06 | 2015-04-14 | Shine C. Chung | Circuit and system of protective mechanisms for programmable resistive memories |
US8861249B2 (en) | 2012-02-06 | 2014-10-14 | Shine C. Chung | Circuit and system of a low density one-time programmable memory |
US8917533B2 (en) | 2012-02-06 | 2014-12-23 | Shine C. Chung | Circuit and system for testing a one-time programmable (OTP) memory |
WO2014039115A1 (en) * | 2012-09-07 | 2014-03-13 | Being Advanced Memory Corporation | Multilevel differential sensing in phase change memory |
US9076526B2 (en) | 2012-09-10 | 2015-07-07 | Shine C. Chung | OTP memories functioning as an MTP memory |
US9183897B2 (en) | 2012-09-30 | 2015-11-10 | Shine C. Chung | Circuits and methods of a self-timed high speed SRAM |
US9324447B2 (en) | 2012-11-20 | 2016-04-26 | Shine C. Chung | Circuit and system for concurrently programming multiple bits of OTP memory devices |
US8988926B2 (en) | 2013-01-11 | 2015-03-24 | Micron Technology, Inc. | Method, system and device for phase change memory with shunt |
KR102079370B1 (en) | 2013-02-05 | 2020-02-20 | 삼성전자주식회사 | Nonvolatile memory device and writing method thereof |
KR20140117893A (en) * | 2013-03-27 | 2014-10-08 | 인텔렉추얼디스커버리 주식회사 | Phase-change memory device and method for multi-level programing of phase-change memory device |
US9412473B2 (en) | 2014-06-16 | 2016-08-09 | Shine C. Chung | System and method of a novel redundancy scheme for OTP |
US10535413B2 (en) | 2017-04-14 | 2020-01-14 | Attopsemi Technology Co., Ltd | Low power read operation for programmable resistive memories |
US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
US11615859B2 (en) | 2017-04-14 | 2023-03-28 | Attopsemi Technology Co., Ltd | One-time programmable memories with ultra-low power read operation and novel sensing scheme |
US10726914B2 (en) | 2017-04-14 | 2020-07-28 | Attopsemi Technology Co. Ltd | Programmable resistive memories with low power read operation and novel sensing scheme |
US10770160B2 (en) | 2017-11-30 | 2020-09-08 | Attopsemi Technology Co., Ltd | Programmable resistive memory formed by bit slices from a standard cell library |
CN109991360B (en) * | 2017-12-14 | 2023-04-21 | 特利丹菲力尔探测公司 | Retaining deformable memory material in a flow path |
IT201900021606A1 (en) | 2019-11-19 | 2021-05-19 | St Microelectronics Srl | PHASE CHANGE MEMORY DEVICE AND METHOD OF PROGRAMMING A PHASE CHANGE MEMORY DEVICE |
US11283015B2 (en) | 2020-03-24 | 2022-03-22 | International Business Machines Corporation | Projected phase change memory devices |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3886577A (en) * | 1973-09-12 | 1975-05-27 | Energy Conversion Devices Inc | Filament-type memory semiconductor device and method of making the same |
US5825046A (en) | 1996-10-28 | 1998-10-20 | Energy Conversion Devices, Inc. | Composite memory material comprising a mixture of phase-change memory material and dielectric material |
US20030123277A1 (en) * | 2001-12-28 | 2003-07-03 | Tyler Lowrey | Method and apparatus to program a phase change memory |
EP1326254A1 (en) | 2001-12-27 | 2003-07-09 | STMicroelectronics S.r.l. | Architecture of a phase-change nonvolatile memory array |
EP1450373A1 (en) * | 2003-02-21 | 2004-08-25 | STMicroelectronics S.r.l. | Phase change memory device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3922648A (en) * | 1974-08-19 | 1975-11-25 | Energy Conversion Devices Inc | Method and means for preventing degradation of threshold voltage of filament-forming memory semiconductor device |
CA1322258C (en) | 1988-01-19 | 1993-09-14 | Thomas S. Buzak | Apparatus for and methods of addressing data storage elements |
JP3454821B2 (en) | 1991-08-19 | 2003-10-06 | エナージー・コンバーション・デバイセス・インコーポレーテッド | Electrically erasable, directly overwritable, multi-bit single-cell memory elements and arrays made therefrom |
US7365354B2 (en) * | 2001-06-26 | 2008-04-29 | Ovonyx, Inc. | Programmable resistance memory element and method for making same |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6813177B2 (en) * | 2002-12-13 | 2004-11-02 | Ovoynx, Inc. | Method and system to store information |
US7085154B2 (en) * | 2003-06-03 | 2006-08-01 | Samsung Electronics Co., Ltd. | Device and method for pulse width control in a phase change memory device |
KR100618855B1 (en) * | 2004-08-02 | 2006-09-01 | 삼성전자주식회사 | Method of forming metal contact structure and method of fabricating phase-change memory using the same |
-
2005
- 2005-06-03 DE DE602005025323T patent/DE602005025323D1/en active Active
- 2005-06-03 EP EP10171507A patent/EP2309516A1/en not_active Withdrawn
- 2005-06-03 EP EP10173621.3A patent/EP2249351B1/en active Active
- 2005-06-03 EP EP05104877A patent/EP1729303B1/en active Active
-
2006
- 2006-06-01 JP JP2008514105A patent/JP2008546124A/en active Pending
- 2006-06-01 KR KR1020077030076A patent/KR101263360B1/en active IP Right Grant
- 2006-06-01 WO PCT/EP2006/062812 patent/WO2006128896A1/en active Application Filing
- 2006-06-01 CN CN2006800286197A patent/CN101238523B/en active Active
-
2007
- 2007-12-03 US US11/949,598 patent/US7639526B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3886577A (en) * | 1973-09-12 | 1975-05-27 | Energy Conversion Devices Inc | Filament-type memory semiconductor device and method of making the same |
US5825046A (en) | 1996-10-28 | 1998-10-20 | Energy Conversion Devices, Inc. | Composite memory material comprising a mixture of phase-change memory material and dielectric material |
EP1326254A1 (en) | 2001-12-27 | 2003-07-09 | STMicroelectronics S.r.l. | Architecture of a phase-change nonvolatile memory array |
US20030185047A1 (en) | 2001-12-27 | 2003-10-02 | Stmicroelectronics S.R.L. | Architecture of a phase-change nonvolatile memory array |
US20030123277A1 (en) * | 2001-12-28 | 2003-07-03 | Tyler Lowrey | Method and apparatus to program a phase change memory |
EP1450373A1 (en) * | 2003-02-21 | 2004-08-25 | STMicroelectronics S.r.l. | Phase change memory device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11164628B2 (en) | 2020-02-21 | 2021-11-02 | International Business Machines Corporation | Compensating PCM drift for neuromorphic applications |
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US7639526B2 (en) | 2009-12-29 |
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EP1729303A1 (en) | 2006-12-06 |
KR20080021688A (en) | 2008-03-07 |
EP2309516A1 (en) | 2011-04-13 |
EP2249351B1 (en) | 2013-05-01 |
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