EP2058856A2 - Semiconductor package and mounting method thereof - Google Patents

Semiconductor package and mounting method thereof Download PDF

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Publication number
EP2058856A2
EP2058856A2 EP08168935A EP08168935A EP2058856A2 EP 2058856 A2 EP2058856 A2 EP 2058856A2 EP 08168935 A EP08168935 A EP 08168935A EP 08168935 A EP08168935 A EP 08168935A EP 2058856 A2 EP2058856 A2 EP 2058856A2
Authority
EP
European Patent Office
Prior art keywords
lead terminals
chip pad
grooves
semiconductor package
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08168935A
Other languages
German (de)
French (fr)
Other versions
EP2058856A3 (en
Inventor
Young-Cheol Jang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung SDI Co Ltd
Original Assignee
Samsung SDI Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung SDI Co Ltd filed Critical Samsung SDI Co Ltd
Publication of EP2058856A2 publication Critical patent/EP2058856A2/en
Publication of EP2058856A3 publication Critical patent/EP2058856A3/en
Withdrawn legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
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Definitions

  • the present invention relates to a semiconductor package and mounting method for improving reliability by strengthening adhesion strength between a printed circuit board and a surface mounting package.
  • Commonly used surface mounting packages include a small outline J-Iead (SOJ) type surface mounting package, and a special usage Zigzag Inline Package (ZIP) surface mounting package. Further, there is a Thin Small Outline Package (TSOP) type of surface mounting package that is suitable for a standardized memory card.
  • SOJ small outline J-Iead
  • ZIP Zigzag Inline Package
  • TSOP Thin Small Outline Package
  • a typical surface mounting package is formed with gold-plated nickel, and configured with a chip pad on which a semiconductor device will be adhered, and lead terminals for electrically connecting the package to an external device. Since the semiconductor device and the lead terminals include either an adhesive tape or an adhesive agent, they are electrically connected with wires. Further, the package is completed by forming an enveloping unit that is molded with epoxy molding compound (EMC) in order to protect the semiconductor device from any damage due to external thermal effects and external mechanical or chemical impacts.
  • EMC epoxy molding compound
  • a semiconductor package has a chip pad on which a semiconductor device is disposed, and has lead terminals, wherein at least one of the chip pad and the lead terminals comprise a plurality of grooves.
  • the semiconductor device may be connected to the lead terminals by wiring.
  • the chip pad may be made of nickel coated with gold.
  • the grooves may extend in one direction.
  • the grooves may have a mesh shape. According to an aspect of the present invention, the grooves have a matrix shape. According to an aspect of the present invention, the grooves are formed when the chip pad and the lead terminals are formed, or after the semiconductor package is completed.
  • a method includes providing a printed circuit board having terminals; coating cream solder on the terminals of the printed circuit board; disposing a semiconductor package having a chip pad and lead terminals on the printed circuit board, the chip pad and the lead terminals having a plurality of grooves; forcing the cream solder into the plurality of grooves by pressing together the semiconductor package and the printed circuit board; and adhering the semiconductor package onto the printed circuit board by hardening the cream solder.
  • a semiconductor package includes: a semiconductor device, a chip pad on which the semiconductor device is disposed; lead terminals electrically connected to the semiconductor device by respective wires; and an enveloping unit that is molded to envelop the semiconductor device, the chip pad, and the lead terminals, except for a surface of each of the chip pad and the lead terminals that are externally exposed, wherein the chip pad and the lead terminals comprise a plurality of grooves that are formed over the exposed surfaces of the chip pad and the lead terminals.
  • a mounting method of a semiconductor package includes: providing a printed circuit board having terminals; coating cream solder on the terminals of the printed circuit board; disposing a semiconductor package on the printed circuit board, the semiconductor package includes: a semiconductor device, a chip pad on which the semiconductor device is disposed, lead terminals electrically connected to the semiconductor device by respective wires, and an enveloping unit that is molded to envelop the semiconductor device, the chip pad, and the lead terminals, except for a surface of each of the chip pad and the lead terminals that are externally exposed, wherein the chip pad and the lead terminals comprise a plurality of grooves that are formed over the exposed surfaces of the chip pad and the lead terminals, and the chip pad and the lead terminals are aligned to the terminals of the printed circuit board; forcing the cream solder into the plurality of grooves by pressing together the semiconductor package and the printed circuit board; and adhering the semiconductor package onto the printed circuit board by hardening the cream solder.
  • FIG. 1A is a plan view illustrating a structure of a semiconductor package according to an aspect of the present invention
  • FIG. 1B is a side elevational view of the semiconductor package of FIG. 1A .
  • a package 100 may comprise a chip pad 110 on which a semiconductor device 120 is disposed, a plurality of lead terminals 130 to externally connect the semiconductor device 120, and wires 140 to electrically connect the semiconductor device 120 to the lead terminals 130.
  • the semiconductor device 120 and the lead terminals 130 are electrically connected to each other by fixing with either an adhesive tape or an adhesive agent. Further, the package is completed by forming an enveloping unit 150 that is molded with an epoxy molding compound (EMC) in order to protect the semiconductor device 120 from any damage due to thermal effects, or external mechanical or chemical impacts.
  • EMC epoxy molding compound
  • the enveloping unit 150 may be formed to entirely envelop the semiconductor device 120, and most of the chip pad 110 on which the semiconductor device 120 is disposed and most of the plurality of lead terminals 130, except for one surface on each of the chip pad 110 and the plurality of lead terminals 130.
  • the non-enveloped surfaces of the chip pad 110 and the plurality of lead terminals 130 are substantially coplanar, and are externally exposed.
  • a plurality of grooves 160 may be formed on a surface of both the chip pad 110 on which the semiconductor device is disposed, and the lead terminals 130, respectively, in order to improve shearing strength thereof by acquiring increased adhesive (or surface) areas available for adhesion.
  • the grooves 160 may be extendedly formed in one direction as illustrated in FIG. 1C , in a mesh shape as illustrated in FIG. 1D , or in a matrix shape as illustrated in FIG. 1E .
  • the surfaces on which the plurality of grooves 160 are formed are substantially coplanar.
  • shapes or cross sectional profiles of the grooves 160 may be formed as desired. That is, edges of the grooves 160 may be formed as one of right angles (as shown in FIG. 1B ) and curved surfaces. In aspects of the present invention, other shapes of the grooves 160 are also possible, such as triangular or pyramidal shapes.
  • cross sectional shapes of the grooves 160 may outline a square wave pattern as shown in FIG. 1B , or may outline a triangular wave, a sinusoidal wave, or other wave patterns.
  • the periodicity of the grooves 160 may be regular so that intervals between each groove 160 may be equal, though such is not required. Accordingly, the grooves 160 may also be formed at irregular intervals or at any desired intervals.
  • FIG. 1D illustrates a mesh shape arrangement of the grooves 160
  • FIG. 1E illustrates a matrix shape arrangement of the grooves 160. That is, FIG. 1D illustrates an arrangement of a set of the grooves 160 that extend perpendicularly to another set of the grooves 160
  • FIG. 1E illustrates an arrangement of grooves 160 that extend discontinuously.
  • square shaped land areas are formed in between the grooves 160 in FIG. 1D
  • square shaped indentations are formed by the grooves 160 in FIG. 1E , such is not required, and the shapes of the lands or indentations that may be formed by the grooves 160 may be circular, hexagonal, triangular, or other shapes.
  • the grooves 160 may be formed on at least one of the chip pad 110 and the lead terminals 130 (i.e., on the chip pad 110, the lead terminals 130, or both). Also, the grooves 160 may be formed when the chip pad 110 and the lead terminals 130 are formed, or after the package 100 is completed once an epoxy molding compound (EMC) is molded thereon, for example.
  • EMC epoxy molding compound
  • a cream solder is filled up in the grooves 160. Accordingly, areas of adhesion may be widened or increased so that shearing strength of the chip pad 110 and/or the lead terminals 130 relative to a printed circuit board may be improved, and greater solder joint reliability can be acquired therefore.
  • FIGS. 2A through 2D are drawings illustrating a mounting method of a semiconductor package according to aspects of the present invention.
  • FIG. 2A shows cream solder 200 that is coated on PCB terminals 310 formed on the printed circuit board (PCB) 300 before adhering the printed circuit board 300 to the package 100.
  • PCB printed circuit board
  • the package 100 may comprise the chip pad 110 and the lead terminals 130.
  • the chip pad 110 and the lead terminals 130 may have a plurality of the grooves 160 at surfaces to which the printed circuit board 300 is adhered.
  • the chip pad 110 and the lead terminals 130 are adhered to the printed circuit board 300 by way of the PCB terminals 310.
  • FIG. 2B shows disposing the package 100 on the printed circuit board 300 in order to adhere the package 100 to the printed circuit board 300.
  • the chip pad 110 and lead terminals 130 may be disposed on the PCB terminals 310 and cream solder 200, respectively, while being closely contacted.
  • FIG. 2C shows adhering the package 100 to the printed circuit board 300.
  • the cream solder 200 may flow into the grooves 160 formed on the chip pad 110 and the lead terminals 130 of the package 100 by melting the cream solder 200 by use of heat, and pressing the package 100 and the printed circuit board 300 together.
  • FIG. 2D shows incorporating the package 100 into the printed circuit board 300.
  • some of the melted cream solder 200 may flow into the grooves 160 of both the chip pad 110 and the lead terminals 130, and harden, thereby mounting the package 100 to the printed circuit board 300.
  • filling up or intrusion of the cream solder 200 into the grooves 160 enable interlocking of the land portions of the chip pad 110 and/or the lead terminals 130 with the cream solder 200 once the cream solder 200 is hardened, to increase shear strength of the package 100 relative to the printed circuit board 300.
  • the adhesive areas may be widened or increased so that the shearing strength may be improved and greater solder joint reliability can be acquired.
  • At least one of refers to alternatives chosen from available elements so as to include one or more of the elements.
  • the elements available include elements X, Y, and Z

Abstract

A semiconductor package and mounting method of improving reliability by strengthening adhesive strength of both a printed circuit board and a surface mounting package, includes a chip pad on which a semiconductor device is disposed, and lead terminals, wherein at least one of the chip pad and the lead terminals have a plurality of grooves. Accordingly, in comparison with a typical package, since a plurality of grooves are formed on both a chip pad and lead terminals of a package adhering to a printed circuit, an adhesive area of both the package and the cream solder is widened so that the shearing strength may be improved and greater solder joint reliability can be acquired.

Description

  • The present invention relates to a semiconductor package and mounting method for improving reliability by strengthening adhesion strength between a printed circuit board and a surface mounting package.
  • Commonly used surface mounting packages include a small outline J-Iead (SOJ) type surface mounting package, and a special usage Zigzag Inline Package (ZIP) surface mounting package. Further, there is a Thin Small Outline Package (TSOP) type of surface mounting package that is suitable for a standardized memory card.
  • A typical surface mounting package is formed with gold-plated nickel, and configured with a chip pad on which a semiconductor device will be adhered, and lead terminals for electrically connecting the package to an external device. Since the semiconductor device and the lead terminals include either an adhesive tape or an adhesive agent, they are electrically connected with wires. Further, the package is completed by forming an enveloping unit that is molded with epoxy molding compound (EMC) in order to protect the semiconductor device from any damage due to external thermal effects and external mechanical or chemical impacts.
  • In order to mount a typical Bottom Leaded Plastic Package (BLP) on a Printed Circuit Board (PCB), cream solder is coated on the PCB to contact a chip pad and terminals of the BLP, and heat is applied to the PCB and the BLP disposed thereon. Thereby, the cream solder is melted and hardened, so the package is finally mounted on the PCB.
  • According to aspects of the present invention, a semiconductor package has a chip pad on which a semiconductor device is disposed, and has lead terminals, wherein at least one of the chip pad and the lead terminals comprise a plurality of grooves.
  • According to an aspect of the present invention, the semiconductor device may be connected to the lead terminals by wiring. According to an aspect of the present invention, the chip pad may be made of nickel coated with gold. According to an aspect of the present invention, the grooves may extend in one direction.
  • According to an aspect of the present invention, the grooves may have a mesh shape. According to an aspect of the present invention, the grooves have a matrix shape. According to an aspect of the present invention, the grooves are formed when the chip pad and the lead terminals are formed, or after the semiconductor package is completed.
  • According to another aspect of the present invention, a method includes providing a printed circuit board having terminals; coating cream solder on the terminals of the printed circuit board; disposing a semiconductor package having a chip pad and lead terminals on the printed circuit board, the chip pad and the lead terminals having a plurality of grooves; forcing the cream solder into the plurality of grooves by pressing together the semiconductor package and the printed circuit board; and adhering the semiconductor package onto the printed circuit board by hardening the cream solder.
  • According to another aspect of the present invention, a semiconductor package includes: a semiconductor device, a chip pad on which the semiconductor device is disposed; lead terminals electrically connected to the semiconductor device by respective wires; and an enveloping unit that is molded to envelop the semiconductor device, the chip pad, and the lead terminals, except for a surface of each of the chip pad and the lead terminals that are externally exposed, wherein the chip pad and the lead terminals comprise a plurality of grooves that are formed over the exposed surfaces of the chip pad and the lead terminals.
  • According to another aspect of the present invention, a mounting method of a semiconductor package includes: providing a printed circuit board having terminals; coating cream solder on the terminals of the printed circuit board; disposing a semiconductor package on the printed circuit board, the semiconductor package includes: a semiconductor device, a chip pad on which the semiconductor device is disposed, lead terminals electrically connected to the semiconductor device by respective wires, and an enveloping unit that is molded to envelop the semiconductor device, the chip pad, and the lead terminals, except for a surface of each of the chip pad and the lead terminals that are externally exposed, wherein the chip pad and the lead terminals comprise a plurality of grooves that are formed over the exposed surfaces of the chip pad and the lead terminals, and the chip pad and the lead terminals are aligned to the terminals of the printed circuit board; forcing the cream solder into the plurality of grooves by pressing together the semiconductor package and the printed circuit board; and adhering the semiconductor package onto the printed circuit board by hardening the cream solder.
  • Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
  • These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the aspects, taken in conjunction with the accompanying drawings in which:
    • FIG. 1A is a plan view illustrating a structure of a semiconductor package according to an aspect of the present invention;
    • FIG. 1B is a side elevational view of the semiconductor package of FIG. 1A;
    • FIGS. 1C through 1E are aspects of the present invention in which grooves are formed in a chip pad and lead terminals of FIG. 1A;
    • FIGS. 2A through 2D are drawings illustrating a mounting method of a semiconductor package according to an aspect of the present invention.
  • Reference will now be made in detail to aspects of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The aspects are described below in order to explain the present invention by referring to the figures. FIG. 1A is a plan view illustrating a structure of a semiconductor package according to an aspect of the present invention, and FIG. 1B is a side elevational view of the semiconductor package of FIG. 1A.
  • Referring to FIG. 1A and 1B, a package 100 may comprise a chip pad 110 on which a semiconductor device 120 is disposed, a plurality of lead terminals 130 to externally connect the semiconductor device 120, and wires 140 to electrically connect the semiconductor device 120 to the lead terminals 130.
  • The semiconductor device 120 and the lead terminals 130 are electrically connected to each other by fixing with either an adhesive tape or an adhesive agent. Further, the package is completed by forming an enveloping unit 150 that is molded with an epoxy molding compound (EMC) in order to protect the semiconductor device 120 from any damage due to thermal effects, or external mechanical or chemical impacts.
  • As shown in FIG. 1B, the enveloping unit 150 may be formed to entirely envelop the semiconductor device 120, and most of the chip pad 110 on which the semiconductor device 120 is disposed and most of the plurality of lead terminals 130, except for one surface on each of the chip pad 110 and the plurality of lead terminals 130. In aspects of the present invention, the non-enveloped surfaces of the chip pad 110 and the plurality of lead terminals 130 are substantially coplanar, and are externally exposed.
  • As shown in FIG. 1B, a plurality of grooves 160 may be formed on a surface of both the chip pad 110 on which the semiconductor device is disposed, and the lead terminals 130, respectively, in order to improve shearing strength thereof by acquiring increased adhesive (or surface) areas available for adhesion. The grooves 160, may be extendedly formed in one direction as illustrated in FIG. 1C, in a mesh shape as illustrated in FIG. 1D, or in a matrix shape as illustrated in FIG. 1E. As shown in FIG. 1B, the surfaces on which the plurality of grooves 160 are formed are substantially coplanar.
  • Further, in aspects of the present invention, shapes or cross sectional profiles of the grooves 160 may be formed as desired. That is, edges of the grooves 160 may be formed as one of right angles (as shown in FIG. 1B) and curved surfaces. In aspects of the present invention, other shapes of the grooves 160 are also possible, such as triangular or pyramidal shapes.
  • In aspects of the present invention where the grooves 160 are extendedly formed in one direction as illustrated in FIG. 1C, cross sectional shapes of the grooves 160 may outline a square wave pattern as shown in FIG. 1B, or may outline a triangular wave, a sinusoidal wave, or other wave patterns. In such cases, the periodicity of the grooves 160 may be regular so that intervals between each groove 160 may be equal, though such is not required. Accordingly, the grooves 160 may also be formed at irregular intervals or at any desired intervals.
  • FIG. 1D illustrates a mesh shape arrangement of the grooves 160, and FIG. 1E illustrates a matrix shape arrangement of the grooves 160. That is, FIG. 1D illustrates an arrangement of a set of the grooves 160 that extend perpendicularly to another set of the grooves 160, and FIG. 1E illustrates an arrangement of grooves 160 that extend discontinuously. Although square shaped land areas are formed in between the grooves 160 in FIG. 1D, and square shaped indentations are formed by the grooves 160 in FIG. 1E, such is not required, and the shapes of the lands or indentations that may be formed by the grooves 160 may be circular, hexagonal, triangular, or other shapes.
  • Accordingly, it will be understood by those skilled in the art that a variety of modifications and variations of the grooves 160 may be made to the aspects herein without departing from the scope of the present invention.
  • In aspects of the present invention, the grooves 160 may be formed on at least one of the chip pad 110 and the lead terminals 130 (i.e., on the chip pad 110, the lead terminals 130, or both). Also, the grooves 160 may be formed when the chip pad 110 and the lead terminals 130 are formed, or after the package 100 is completed once an epoxy molding compound (EMC) is molded thereon, for example. Thus, it will be understood that, in order to form the grooves 160 more conveniently and easily in the manufacturing process of the package, the timing of forming the grooves can be selected accordingly.
  • Additionally, in aspects of the present invention, a cream solder is filled up in the grooves 160. Accordingly, areas of adhesion may be widened or increased so that shearing strength of the chip pad 110 and/or the lead terminals 130 relative to a printed circuit board may be improved, and greater solder joint reliability can be acquired therefore.
  • FIGS. 2A through 2D are drawings illustrating a mounting method of a semiconductor package according to aspects of the present invention. FIG. 2A shows cream solder 200 that is coated on PCB terminals 310 formed on the printed circuit board (PCB) 300 before adhering the printed circuit board 300 to the package 100.
  • As shown in FIG. 2A, for example, the package 100 may comprise the chip pad 110 and the lead terminals 130. The chip pad 110 and the lead terminals 130 may have a plurality of the grooves 160 at surfaces to which the printed circuit board 300 is adhered. For example, the chip pad 110 and the lead terminals 130 are adhered to the printed circuit board 300 by way of the PCB terminals 310.
  • FIG. 2B shows disposing the package 100 on the printed circuit board 300 in order to adhere the package 100 to the printed circuit board 300. Here, the chip pad 110 and lead terminals 130 may be disposed on the PCB terminals 310 and cream solder 200, respectively, while being closely contacted.
  • FIG. 2C shows adhering the package 100 to the printed circuit board 300. Here, the cream solder 200 may flow into the grooves 160 formed on the chip pad 110 and the lead terminals 130 of the package 100 by melting the cream solder 200 by use of heat, and pressing the package 100 and the printed circuit board 300 together.
  • FIG. 2D shows incorporating the package 100 into the printed circuit board 300. Here, some of the melted cream solder 200 may flow into the grooves 160 of both the chip pad 110 and the lead terminals 130, and harden, thereby mounting the package 100 to the printed circuit board 300.
  • Additionally, filling up or intrusion of the cream solder 200 into the grooves 160 according to aspects of the present invention enable interlocking of the land portions of the chip pad 110 and/or the lead terminals 130 with the cream solder 200 once the cream solder 200 is hardened, to increase shear strength of the package 100 relative to the printed circuit board 300.
  • Accordingly, in comparison with a typical package, since the cream solder 200 is filled up in the grooves 160, the adhesive areas may be widened or increased so that the shearing strength may be improved and greater solder joint reliability can be acquired.
  • In various aspects, at least one of refers to alternatives chosen from available elements so as to include one or more of the elements. For example, if the elements available include elements X, Y, and Z, at least one of refers to X, Y, Z, or any combination thereof.
  • Although a few aspects of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in the aspects without departing from the principles of the invention, the scope of which is defined in the claims.

Claims (11)

  1. A semiconductor package (100) comprising:
    a chip pad (110) on which a semiconductor device (120) is disposed; and
    lead terminals (130), wherein at least one of the chip pad and the lead terminals comprise a plurality of grooves.
  2. The semiconductor package of claim 1, wherein the semiconductor device is connected to the lead terminals by wiring (140).
  3. The semiconductor package of claim 1 or 2, wherein the chip pad comprises nickel coated with gold.
  4. The semiconductor package of any one of the preceding claims, wherein the grooves extend in one direction, have a mesh shape, or have a matrix shape.
  5. The semiconductor package of any one of the preceding claims, wherein the semiconductor package further comprises an enveloping unit (150) to cover the chip pad and the lead terminals.
  6. The semiconductor package of claim 5, wherein
    the enveloping unit (150) is molded to envelop the semiconductor device, the chip pad, and the lead terminals, except for a surface of each of the chip pad and the lead terminals that are externally exposed, wherein the plurality of grooves (160) are formed on the exposed surfaces of the chip pad and the lead terminals.
  7. The semiconductor package of claim 6, wherein the exposed surfaces of the chip pad and the lead terminals are coplanar.
  8. The semiconductor package of any one of the preceding claims, wherein the plurality of grooves comprise hardened cream solder (200).
  9. A method of mounting a semiconductor package comprising:
    providing a printed circuit board (300) having terminals (310);
    coating cream solder (200) on the terminals of the printed circuit board;
    disposing a semiconductor package (100) according to any one of the preceding claims on the printed circuit board;
    forcing the cream solder into the plurality of grooves by pressing together the semiconductor package and the printed circuit board; and
    adhering the semiconductor package onto the printed circuit board by hardening the cream solder.
  10. The method of claim 9, wherein the grooves are formed when the chip pad and the lead terminals are formed.
  11. The method of claim 9, wherein the grooves are formed after the semiconductor package is completed.
EP08168935.8A 2007-11-12 2008-11-12 Semiconductor package and mounting method thereof Withdrawn EP2058856A3 (en)

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KR1020070114898A KR100984132B1 (en) 2007-11-12 2007-11-12 Semiconductor package and mounting method thereof

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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8357998B2 (en) * 2009-02-09 2013-01-22 Advanced Semiconductor Engineering, Inc. Wirebonded semiconductor package
EP2337068A1 (en) * 2009-12-18 2011-06-22 Nxp B.V. Pre-soldered leadless package
US9418919B2 (en) * 2010-07-29 2016-08-16 Nxp B.V. Leadless chip carrier having improved mountability
US8766100B2 (en) 2011-03-02 2014-07-01 Samsung Electronics Co., Ltd. Printed circuit board and semiconductor package using the same
KR101237668B1 (en) * 2011-08-10 2013-02-26 삼성전기주식회사 Semiconductor package substrate
US9373609B2 (en) * 2012-10-18 2016-06-21 Infineon Technologies Ag Bump package and methods of formation thereof
KR101423136B1 (en) * 2012-12-28 2014-07-25 한국광기술원 Semiconductor bonding assembly and semiconductor bonding method
US20140239428A1 (en) * 2013-02-28 2014-08-28 Infineon Technologies Ag Chip arrangement and a method for manufacturing a chip arrangement
CN104659010B (en) * 2015-02-11 2018-03-16 江苏长电科技股份有限公司 A kind of lead frame structure and package body structure of square flat pinless encapsulation
KR20180044725A (en) * 2016-10-24 2018-05-03 주식회사 엘지화학 The shunt resistor for measuring current
CN106714451A (en) * 2016-12-19 2017-05-24 长沙牧泰莱电路技术有限公司 Composite printed circuit board and manufacturing method thereof
DE102018130936B4 (en) * 2018-12-05 2022-08-11 Infineon Technologies Ag Semiconductor package, sheet metal for use in a semiconductor package and method of manufacturing a semiconductor package
CN109904131B (en) * 2019-02-22 2020-11-17 西安航思半导体有限公司 High stability DFN packaged device
CN113451226B (en) * 2019-03-06 2022-07-19 西安航思半导体有限公司 Heat-resistant QFN (quad Flat No lead) packaging semiconductor device
CN109904125B (en) * 2019-03-06 2021-02-19 西安航思半导体有限公司 Preparation method of high-temperature-resistant QFN packaging structure
KR102512688B1 (en) * 2019-12-05 2023-03-23 한국전자기술연구원 Method for improving adhesion of Device
CN113015324B (en) * 2019-12-19 2023-05-09 华为技术有限公司 Circuit board assembly, electronic device and method for processing circuit board assembly

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145599A (en) * 1997-11-14 1999-05-28 Nec Shizuoka Ltd Structure for soldering surface-mounting part
US20030006055A1 (en) * 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
US6777788B1 (en) * 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad
WO2006109566A1 (en) * 2005-04-08 2006-10-19 Rohm Co., Ltd. Semiconductor device

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5069626A (en) 1987-07-01 1991-12-03 Western Digital Corporation Plated plastic castellated interconnect for electrical components
JPH0217854U (en) * 1988-07-18 1990-02-06
FR2636453B1 (en) * 1988-09-14 1992-01-17 Sgs Thomson Microelectronics METHOD FOR ENCAPSULATING INTEGRATED CIRCUITS IN PARTICULAR FOR CHIP CARDS
JPH05102381A (en) * 1991-10-09 1993-04-23 Mitsubishi Electric Corp Semiconductor device
JPH0577947U (en) * 1992-03-27 1993-10-22 安藤電気株式会社 Surface mount IC L-shaped terminal
JP3597913B2 (en) * 1995-07-20 2004-12-08 松下電器産業株式会社 Semiconductor device and its mounting method
KR19980048268A (en) 1996-12-17 1998-09-15 김광호 Semiconductor chip package having a grooved outer lead and structure in which it is mounted
US6365976B1 (en) * 1999-02-25 2002-04-02 Texas Instruments Incorporated Integrated circuit device with depressions for receiving solder balls and method of fabrication
KR100960739B1 (en) * 1999-02-26 2010-06-01 텍사스 인스트루먼츠 인코포레이티드 Thermally enhanced semiconductor ball grid array device and method of fabrication
JP2000294719A (en) * 1999-04-09 2000-10-20 Hitachi Ltd Lead frame, semiconductor device using the same, and manufacture thereof
KR20010004529A (en) 1999-06-29 2001-01-15 김영환 wafer level package and method of fabricating the same
JP4034073B2 (en) * 2001-05-11 2008-01-16 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP2003188335A (en) 2001-12-14 2003-07-04 Hitachi Ltd Semiconductor device and its manufacturing method
JP4243270B2 (en) 2001-12-14 2009-03-25 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
JP2004039882A (en) 2002-07-04 2004-02-05 Tateyama Kagaku Kogyo Kk Chip type thermistor and its manufacturing method
AU2002357592A1 (en) * 2002-12-18 2004-07-09 K-Tech Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
US8330258B2 (en) * 2003-12-24 2012-12-11 Stmicroelectronics, Inc. System and method for improving solder joint reliability in an integrated circuit package
JP2006100753A (en) 2004-09-30 2006-04-13 Sanyo Electric Co Ltd Semiconductor module and its manufacturing method
JP4111199B2 (en) * 2005-03-10 2008-07-02 ヤマハ株式会社 Semiconductor package and method for mounting the same on a circuit board
JP2006319030A (en) 2005-05-11 2006-11-24 Matsushita Electric Ind Co Ltd Circuit board, its manufacturing method, semiconductor device and its manufacturing method
US7405106B2 (en) * 2006-05-23 2008-07-29 International Business Machines Corporation Quad flat no-lead chip carrier with stand-off
JP2006237653A (en) 2006-06-12 2006-09-07 Kyocera Chemical Corp Adhesive for bonding semiconductor device, and method of bonding the semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145599A (en) * 1997-11-14 1999-05-28 Nec Shizuoka Ltd Structure for soldering surface-mounting part
US20030006055A1 (en) * 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
US6777788B1 (en) * 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad
WO2006109566A1 (en) * 2005-04-08 2006-10-19 Rohm Co., Ltd. Semiconductor device

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US8319319B2 (en) 2012-11-27
CN101436575A (en) 2009-05-20
CN101436575B (en) 2010-10-13
US20090121362A1 (en) 2009-05-14
JP2009124095A (en) 2009-06-04
KR100984132B1 (en) 2010-09-28
EP2058856A3 (en) 2014-08-27
KR20090048833A (en) 2009-05-15

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