EP1236090A4 - System and method to implement a cross-bar switch of a broadband processor - Google Patents

System and method to implement a cross-bar switch of a broadband processor

Info

Publication number
EP1236090A4
EP1236090A4 EP00910150A EP00910150A EP1236090A4 EP 1236090 A4 EP1236090 A4 EP 1236090A4 EP 00910150 A EP00910150 A EP 00910150A EP 00910150 A EP00910150 A EP 00910150A EP 1236090 A4 EP1236090 A4 EP 1236090A4
Authority
EP
European Patent Office
Prior art keywords
implement
cross
bar switch
broadband processor
broadband
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00910150A
Other languages
German (de)
French (fr)
Other versions
EP1236090A1 (en
Inventor
Craig Hansen
Bruce Bateman
John Moussouris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microunity Systems Engineering Inc
Original Assignee
Microunity Systems Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/382,402 external-priority patent/US6295599B1/en
Application filed by Microunity Systems Engineering Inc filed Critical Microunity Systems Engineering Inc
Publication of EP1236090A1 publication Critical patent/EP1236090A1/en
Publication of EP1236090A4 publication Critical patent/EP1236090A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
EP00910150A 1999-02-12 2000-02-11 System and method to implement a cross-bar switch of a broadband processor Withdrawn EP1236090A4 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11984199P 1999-02-12 1999-02-12
US119841P 1999-02-12
US382402 1999-08-24
US09/382,402 US6295599B1 (en) 1995-08-16 1999-08-24 System and method for providing a wide operand architecture
PCT/US2000/003566 WO2000048070A1 (en) 1999-02-12 2000-02-11 System and method to implement a cross-bar switch of a broadband processor

Publications (2)

Publication Number Publication Date
EP1236090A1 EP1236090A1 (en) 2002-09-04
EP1236090A4 true EP1236090A4 (en) 2002-09-04

Family

ID=26817762

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00910150A Withdrawn EP1236090A4 (en) 1999-02-12 2000-02-11 System and method to implement a cross-bar switch of a broadband processor

Country Status (2)

Country Link
EP (1) EP1236090A4 (en)
WO (1) WO2000048070A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367694A (en) * 1990-08-31 1994-11-22 Kabushiki Kaisha Toshiba RISC processor having a cross-bar switch
US5794061A (en) * 1995-08-16 1998-08-11 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0652509B1 (en) * 1993-11-05 2000-05-10 Intergraph Corporation Instruction cache associative cross-bar switch
US5931944A (en) * 1997-12-23 1999-08-03 Intel Corporation Branch instruction handling in a self-timed marking system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367694A (en) * 1990-08-31 1994-11-22 Kabushiki Kaisha Toshiba RISC processor having a cross-bar switch
US5794061A (en) * 1995-08-16 1998-08-11 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IYER R ET AL: "Switch cache: a framework for improving the remote memory access latency of CC-NUMA multiprocessors", HIGH-PERFORMANCE COMPUTER ARCHITECTURE, 1999. PROCEEDINGS. FIFTH INTERNATIONAL SYMPOSIUM ON ORLANDO, FL, USA 9-13 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 9 January 1999 (1999-01-09), pages 152 - 160, XP010321131, ISBN: 0-7695-0004-8 *
See also references of WO0048070A1 *

Also Published As

Publication number Publication date
EP1236090A1 (en) 2002-09-04
WO2000048070A1 (en) 2000-08-17

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