EP1050902A3 - Method for forming a copper layer over a semiconductor wafer - Google Patents

Method for forming a copper layer over a semiconductor wafer Download PDF

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Publication number
EP1050902A3
EP1050902A3 EP00109329A EP00109329A EP1050902A3 EP 1050902 A3 EP1050902 A3 EP 1050902A3 EP 00109329 A EP00109329 A EP 00109329A EP 00109329 A EP00109329 A EP 00109329A EP 1050902 A3 EP1050902 A3 EP 1050902A3
Authority
EP
European Patent Office
Prior art keywords
cycles
powered
positive
copper layer
pulsed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP00109329A
Other languages
German (de)
French (fr)
Other versions
EP1050902B1 (en
EP1050902A2 (en
Inventor
Cindy Reidsema Simpson
Robert Douglas Mikkola
Matthew T. Herrick
Brett Caroline Baker
David Moralez Pena
Edward Acousta
Rina Chowdhury
Marijean Azrak
Cindy Kay Goldberg
Mohammed Rabiul Islam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP1050902A2 publication Critical patent/EP1050902A2/en
Publication of EP1050902A3 publication Critical patent/EP1050902A3/en
Application granted granted Critical
Publication of EP1050902B1 publication Critical patent/EP1050902B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Abstract

A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect. <IMAGE>
EP00109329A 1999-05-03 2000-05-02 Method for forming a copper layer over a semiconductor wafer Expired - Lifetime EP1050902B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/305,093 US6297155B1 (en) 1999-05-03 1999-05-03 Method for forming a copper layer over a semiconductor wafer
US305093 1999-05-03

Publications (3)

Publication Number Publication Date
EP1050902A2 EP1050902A2 (en) 2000-11-08
EP1050902A3 true EP1050902A3 (en) 2001-04-11
EP1050902B1 EP1050902B1 (en) 2006-02-01

Family

ID=23179301

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00109329A Expired - Lifetime EP1050902B1 (en) 1999-05-03 2000-05-02 Method for forming a copper layer over a semiconductor wafer

Country Status (8)

Country Link
US (1) US6297155B1 (en)
EP (1) EP1050902B1 (en)
JP (4) JP4790894B2 (en)
KR (1) KR100707120B1 (en)
CN (1) CN1197128C (en)
AT (1) ATE317155T1 (en)
DE (1) DE60025773T2 (en)
SG (1) SG83793A1 (en)

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Also Published As

Publication number Publication date
JP2011091425A (en) 2011-05-06
SG83793A1 (en) 2001-10-16
US6297155B1 (en) 2001-10-02
EP1050902B1 (en) 2006-02-01
JP4791594B2 (en) 2011-10-12
CN1272685A (en) 2000-11-08
JP2000353675A (en) 2000-12-19
JP2011066447A (en) 2011-03-31
KR20010014857A (en) 2001-02-26
JP4791593B2 (en) 2011-10-12
JP2011063888A (en) 2011-03-31
JP5296043B2 (en) 2013-09-25
DE60025773T2 (en) 2006-07-20
JP4790894B2 (en) 2011-10-12
DE60025773D1 (en) 2006-04-13
ATE317155T1 (en) 2006-02-15
CN1197128C (en) 2005-04-13
KR100707120B1 (en) 2007-04-16
EP1050902A2 (en) 2000-11-08

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