EP0930604A1 - Apparatus and method for display synchronisation and display using such apparatus - Google Patents

Abstract

The synchronizing signal (I) causes the advance of a counter (22) at the speed of a rapid clock (Fr,20) and an enlarged synchronizing signal (IA) is sent to the display until a comparator (26) detects equality with a keyboard input (23) stored in a memory (25). The enlarged synchronizing signal alters the release timing of line signals received and stored in the display such that sampling of the signal levels is accurate

Description

The invention originates from the problem of displaying a map. geographic on the liquid crystal display, LCD, browser in a car.

An LCD screen has a matrix of controlled display elements each by an associated memory point. The memory points are cyclically refreshed by a video image signal line frame comprising a succession of steps each representing the intensity at restore by one of the elements. Screen management logic samples each step and stores successive samples in the various memory points.

In order to accurately memorize the amplitude of each level, you must sample it at a time when it has stabilized with respect to the bearing previous, while tolerating fluctuations on the clock that controls sampling, i.e. sampling it substantially at a time central of the period.

For this, the on-board navigator computer provides, in addition to the signal video image signal, a line synchronization signal, comprising a pulse relative to which the start of the video signal exhibits a delay of a fixed term. The screen management logic initializes then sampling with a local clock of period equal to the duration a step, clock with the above delay, increased by half a period in order to sample the bearings in the central area of their period.

However, the above delay is not precisely defined, as the calculator can only adjust it by jumps, or not, equal to the period of a landing. Therefore, if the sampling clock drifts up to one half phase phase shift phase, it will sample the flanks bearings instead of their stable central area, and the computer cannot perform the precise registration necessary.

However, the streets, in a map to be displayed, are represented by a line of a single row of pixels, given the limited size of the screen. Any line intersecting a line of the matrix is therefore represented by a only point which presents a strong contrast with those who frame it in the line, and which represent the background.

As these are the sides that are sampled, it is each time a intermediate value between two successive stages which is memorized and the point of the line is then displayed straddling two neighboring elements, with a reduced contrast. The vagueness due to this halving of the definition of the image is then clearly annoying, especially since the image is almost static.

EP-0 791 913A teaches to trigger, by a synchronization signal line, an oscillator sampling pixel signals through a delay circuit adjustable by a control circuit according to a setpoint value in memory.

Likewise, "Automatic Phase adjustment", IBM Technical Disclosure Bulletin, Vol. 37, No. 5, pages 203-204, teaches to measure delay between the pixel video signal and the sampling clock signal to choose a delay among several for an oscillator compared to the line synchronization signal.

This requires fairly complex circuits since it concerns relatively high frequency sampling of pixels.

To adjust the delay with the necessary finesse, it is also known to foresee in the screen a potentiometer integrated into an oscillator providing the sampling clock, to modify the constants at the factory physical determining the phase and therefore the delay compared to the signal synchronization, which makes it possible to deliver a functional screen.

However, the user of the screen cannot correct the drifts or the time dispersion of the control computer or that of the cables respectively providing image and synchronization.

The present invention aims to eliminate the display defect described above, in a manner other than explained above, in order to avoid drawbacks indicated.

To this end, the invention relates, first of all, to a device for synchronization of a display of image line signals associated with a line synchronization signal, device in which means adjustable time offset are arranged to receive the signal synchronization and to restore it to the display with an offset time determined by means for adjusting the shift means, comprising an input for receiving a setpoint offset value.

The device of the invention thus constitutes a fine adjustment element of the display, interposed between it and the microprocessor, or equivalent, who commands it. This device can in fact be mechanically autonomous or be incorporated, display side or microprocessor side, and processes a relatively low frequency signal, so with constraints of very limited achievement.

The offset setpoint can be applied by any user, for example by two impulse buttons, respectively increasing and decrease this value, possibly through the microprocessor. In particular, the setpoint can be transmitted at any speed desired, i.e. the speed of its transmission is independent of the fineness of the temporal adjustment which it controls, which does not impose thus to the microprocessor no speed constraint. It is the operator which plays the role of a correctly servo feedback loop the display, if the latter does not include a fault detector synchronization.

Advantageously, an oscillator is provided, with servo-control on the restored synchronization signal, arranged to provide the display with a line signal sampling clock, clock corresponding to a pixel frequency of these and locked in phase with respect to said signal synchronization restored.

The invention also relates to a display comprising a device for synchronization of a display screen for associated image line signals to a line synchronization signal, the device comprising means adjustable time offset arranged to receive signal synchronization and restore it to screen control means, with a time difference determined by means of adjusting the shift means, comprising an input for receiving a value of setpoint offset.

The invention finally relates to a method for controlling a display with line scan arranged to receive a line image signal and to sample it cyclically, and display it by a pixel phase clock slaved to a received line synchronization signal, method characterized by the fact that there is interposed between the display and a control circuit supplying said signals, a phase shift circuit of the signal synchronization and you adjust the clock phase, relative to the signal line image, by action on the phase shift circuit.

• la figure 1 est un schéma par blocs d'un afficheur et d'un ensemble à microprocesseur le commandant à travers un dispositif de synchronisation ligne, pour la mise en oeuvre du procédé de l'invention,
• la figure 2 représente, en fonction du temps t, les amplitudes d'un signal ligne d'image L et d'un signal de synchronisation ligne S associé reçus par l'afficheur, et d'un signal d'horloge Ha d'échantillonnage pixel, de l'afficheur,
• la figure 3 représente schématiquement l'ensemble de commande,
• la figure 4 est un schéma par blocs du dispositif de synchronisation ligne,
• la figure 5 illustre plus en détails, en fonction du temps t, le signal de synchronisation, et
• la figure 6 est un schéma par blocs de l'afficheur.

The invention will be better understood with the aid of the following description of a preferred embodiment of the method of the invention, with reference to the appended drawing, in which:

• FIG. 1 is a block diagram of a display and of a microprocessor assembly controlling it through a line synchronization device, for implementing the method of the invention,
• FIG. 2 represents, as a function of time t, the amplitudes of an image line signal L and of an associated line synchronization signal S received by the display, and of a sampling clock signal Ha pixel, of the display,
• FIG. 3 schematically represents the control assembly,
• FIG. 4 is a block diagram of the line synchronization device,
• FIG. 5 illustrates in more detail, as a function of time t, the synchronization signal, and
• Figure 6 is a block diagram of the display.

The control assembly 1 of FIG. 1 controls a display 3 at through a line 4 image signal transmission cable L and a cable line synchronization signal consisting of two sections 5 and 6 between which a phase shift device 2 is interposed. All these circuits are installed in a car, to display maps geographical and in particular detailed city maps, the streets being represented by a line the width of a pixel.

The line scan display 3 receiving the line image signal L, samples it cyclically, to display it, by a pixel clock Ha at phase controlled by the received line S synchronization signal. To this end, between the display 3 and the control circuit 1 supplying the signals L and S, is interposed the circuit 2 phase shifter of the synchronization signal S and the phase of the clock Ha is adjusted, relative to the image signal L, by action on the phase shift circuit 2.

As illustrated in figure 2, the image to be displayed is represented under the form of a succession of line L signals, transmitted cyclically by the set 1. Each line signal L comprises a plurality of steps elementary, here 320, corresponding to the number of elements per line of display 3, here of the liquid crystal display, LCD type. The amplitude of each level, of duration T, represents the intensity to be displayed on the display element of the same rank.

Synchronization signal S has negative pulses I (designated by "Ia" after crossing device 2), one per line period P and of adjustable duration D. By an oscillator circuit 31 controlled in phase at from the signal S (fig. 5), the display 3 generates the clock signal Ha of period T, used to sample the signal L to direct the various levels of steps towards memory points each commanding a particular pixel display element. The start of the first level of signal L has a guard time delay R relative to the edge backward, active and here rising, from pulse I (or Ia). For a correct operation of display 3, the clock signal Ha must present active edges, here amounts, of sampling of the signal L, located approximately in the middle of each landing period T, i.e. delayed by a duration R + T / 2 on the trailing edge of the pulse Ia.

As shown in Figure 3, circuit 1 includes, for the emission of signals L and S, an oscillator 11 at frequency F, or pixel period T, followed a divider by 400, referenced 12, of period line P. A circuit of formatting 13, such as monostable or decoder of several states of the divider 12, provides on the cable 5, at each period P, the signal S comprising the negative pulse I of duration D. A microprocessor, not shown, manages the sequencing of the functioning of the circuits shown.

A CCD shift register 14, previously filled with 320 values of pixel steps, is emptied on the cable 4 by the oscillator 11, under the control of circuit 13, with a delay determined relative to the edge back of pulse I. This delay is R, oscillator 31 producing the additional delay or phase shift of T / 2. It could have been expected, in variant, whether it is the display 3 which includes a delay circuit D in signal input L.

The phase shifting device 2 of FIG. 4 makes it possible to adjust, in advance or in delay, time position, or phase, of the active front, back, of the pulse I with respect to the line L signal.

The device 2 comprises at the input an activation circuit 21, such as monostable, sensitive to the front edge of pulses I and unlocking then, by a pulse I widened behind, Ie, (fig. 5), the input of reset of a counter 22. The unlocking time (Ie) is long enough, for example twenty periods T, to exceed clearly the duration of the pulse I received and thus allow adjustment, in a wide range (striped area), the position of the rear edge of the pulse Ia controlling the phase of the PLL circuit 31 of the display 3, at through a delay circuit 30 R. The leading edge of the pulse I, inactive vis-à-vis the display 3, is thus transformed into an activation front of the display 3. In FIG. 5, the rear edge of the pulse Ia restored is shifted forward with respect to its counterpart to the pulse I of origin.

The device 2 is therefore activated by a front, front, of the pulse I different from the front, rear, which synchronizes the display 3, which, in addition to the back shift, allows you to easily shift the front, back, following. In a case where it is the same fronts of the pulses I which activate device 2 and display 3, a delay of these edges cyclic, of a value adjustable around the period line P, would allow still to obtain, in addition to a backward shift, a forward shift for the restored pulse Ia, modulo P, leaves to increase the number of stages of counter 22.

An oscillator 20, with a high clock frequency, Fr, substantially more higher than that of oscillator 11, here ten times F, controls the advance of the counter 22, initially in the zero state, for determination, here digital, offset. The outputs of counter 22 are connected to first inputs of a comparator 26 controlling an input of a door 27 of which a second input receives the widened pulses from circuit 21.

An input 23 of the device 2 receives, here by a circuit 16 of the assembly 1, offset adjustment setpoints R, chosen by a user using a keyboard 15. It could have been expected that the device 2 is integrated into assembly 1 or else into display 3.

In this example, automatic compensation is provided by drift temperature of delay circuit 30 of display 3 and of circuit 13, so that the setpoint is changed according to the value of ambient temperature supplied by a thermal probe 24. A slight frequency drift of the PLL circuit 31 can likewise be masked by control of a compensating phase shift of the clock Ha, by adjusting the pulse Ie, so that the 320 samplings are each carried out on a stable part of the bearing concerned, for example the second half. A memory 25, containing a law or table of correction or compensation in temperature and addressed by the two values, setpoint and temperature, provides a corrected time offset numerical value to second comparator inputs 26.

In display 3, the 31 PLL frequency boost circuit by a factor 400, providing the clock Ha with the delay R of circuit 30, command the clock input of a CCD shift register 32 receiving the signal line L of cable 4 and thus copying the 320 bearings initially contained in the CCD circuit 14. A counter, not shown, limits each train of clock signals Ha at 320 pulses. Alternatively, it could be provided that circuits 30 and 31 are in device 2 and that the display 3 receives the Ha clock.

Once filled, the CCD 32 is emptied in parallel in a buffer register 33 whose parallel outputs respectively control the 320 elements of a specific line 34 of display 3. Of a line cycle in the next one, a sequencer, not shown, switches the line signals successive to as many registers as that referenced 33.

Alternatively, to avoid successive shifts of the analog values levels, likely to distort their values, provision could be made to use, in transmission and / or reception, a multiplexer addressed by a counter advancing at rhythm F. The analog values would then be directly transferred from a transmission memory, such as RAM or register with parallel outputs, and memorized according to the same principle in reception, through a demultiplexer.

To adjust display 3, to prevent the step values from being sampled during the level transitions between levels successive, the user enters a setpoint offset value, which he modifies until a correct functioning is obtained, i.e. a sampling by the Ha clock which occurs substantially at mid-term of each period T, operation visible by the fact that the display does not no blur.

When device 2 reaches the leading edge of pulse I, the circuit 21 authorizes the advance of the counter 22, at the rate of the fast clock Fr and the expanded pulse Ie begins to be transmitted to cable 6 through the door 27, the comparator 26 leaving it open. When the counter 22 reaches a value equal to that provided by memory 25, the comparator 26 then locks door 27, as well as a locking input clock 22 counter, which freezes the state thereof. So the duration of the pulse Ia retransmitted to the display 3 is adjusted as desired by the counter 22 and comparator 26, which together form a circuit delay, programmable by memory 25 controlled by input 23. The active front, rear, pulse Ia, servo-control of the PLL 31 circuit providing the sampling clock Ha, is thus out of phase as desired by relative to the levels of signal line L, unchanged. Here, the frequency Fr being ten times higher than frequency F, the adjustment step is therefore T / 10, or 36 degrees. A simple adjustment of 180 could have been expected degrees or less, i.e. a frequency Fr at least double the pixel frequency F of the elementary steps.

When circuit 21 again locks the reset input of the counter 22, already stopped, on the rear edge of the widened pulse Ie, this lock resets counter 22 to zero, freeing its input from clock lock, waiting for the next line cycle which will unlock the reset input.

Alternatively, a programmable counter could have been provided by the value of memory 25, with a decoder, replacing the comparator 26, to detect the arrival of the counter 22 at a predetermined state, by example the maximum counting state "15" for 4 bits, and therefore for detect the arrival just before the fallout rest state. State "15" could then, with a permanent hold at the input of the meter, authorize the propagation of this output, with the blocking effect exposed for the output of comparator 26.

According to another variant, the device 2 could comprise, in place of the counter 22 and comparator 26, analog delay circuits, do not therefore requiring no clock.

It could for example be a delay line comprising several intermediate outputs, i.e. consisting of a plurality of circuits cascading elementary delays. A multiplexer (functional equivalent comparator 26), whose signal inputs are connected to various outputs of the delay line, would then allow to select any desired output and therefore the corresponding time offset, depending on the address commands received from input 23. The setting step may thus be of great finesse, while overcoming the problems of radiation related to the presence of a high frequency clock in the digital delay.

We understand that instead of cascading delay circuits elementary, we could plan to set up several circuits, with different delays, to choose the one that suits the above multiplexer.

Claims (11)

Synchronization device for an image line signal display associated with a line synchronization signal, device in which adjustable time shift means (20, 21, 22, 26, 27) are arranged to receive the synchronization signal and to restore it to the display with a time offset determined by means (23, 25) of adjustment shifting means, comprising an input (23) for receiving a setpoint offset value. Device according to claim 1, in which the shifting means (20, 21, 22, 26, 27) are arranged to transform an inactive front of the synchronization signal received at an activation edge of the display. Device according to either of Claims 1 and 2, in which the shift means comprise a programmable delay circuit (22, 26) by the adjusting means (23, 25). Device according to claim 3, in which the delay circuit comprises a counter (22) with a circuit (26) for detecting a value predetermined counting device arranged to generate an active signal edge synchronization restored. Device according to claim 4, in which the counter is programmable in an initial state and the detection circuit is arranged for detect the arrival of a drop of the counter in a rest state. Device according to one of claims 4 and 5, in which it is provided an oscillator (20) for controlling the counter (22), arranged for advance it at a frequency at least double that of elementary steps, representing pixels, in the image signal. Device according to one of Claims 1 to 6, in which the means means comprise means (24, 25) for thermal compensation of the set value (23). Device according to claim 7, in which the means for thermal compensation include a compensation law memory (25) arranged to provide a compensated setpoint offset value as a function of a temperature value addressing the memory. Device according to one of claims 1 to 8, in which it is provided an oscillator (31), controlled by the synchronization signal rendered, arranged to provide the display with a sampling clock line signals, clock corresponding to a pixel frequency thereof and locked in phase with respect to said restored synchronization signal. Display comprising a device (2) for synchronizing a screen (34) for displaying image line signals associated with a signal line synchronization, the device (2) comprising adjustable means time offset (20, 21, 22, 26, 27) arranged to receive the signal synchronization and restore it to means (33) for controlling the screen (34), with a time offset determined by means (23, 25) for adjusting the shifting means, comprising an inlet (23) for reception of a setpoint offset value. Method for controlling a line scan display arranged for receive a line image signal (L) and to sample it cyclically, and display it, by a pixel clock (Ha) with phase controlled on a received line synchronization signal (S), process characterized by interposed between the display (3) and a control circuit (1) supplying said signals (L, S), a circuit (2) phase shifting of the signal synchronization (S) and the clock phase (Ha) is adjusted, relative to the line image signal (L), by action on the phase shifting circuit (2).

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