EP0851724A2 - Printed circuit board and electric components - Google Patents
Printed circuit board and electric components Download PDFInfo
- Publication number
- EP0851724A2 EP0851724A2 EP97122824A EP97122824A EP0851724A2 EP 0851724 A2 EP0851724 A2 EP 0851724A2 EP 97122824 A EP97122824 A EP 97122824A EP 97122824 A EP97122824 A EP 97122824A EP 0851724 A2 EP0851724 A2 EP 0851724A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- via hole
- printed circuit
- circuit board
- layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
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- H—ELECTRICITY
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
Description
Claims (25)
- A printed circuit board comprising: a base material layer having a first via hole; and an insulating layer having a second via hole, said insulating layer being provided on at least one surface of said base material layer, wherein a cross-sectional area of said second via hole is smaller than a cross-sectional area of said first via hole, and wherein said first and second via holes are filled with a conductive material.
- A printed circuit board according to claim 1, wherein said conductive material is a conductive paste.
- A printed circuit board according to claim 2, wherein said conductive material with which said first via hole is filled and said conductive material with which said second via hole is filled are the same.
- A printed circuit board according to claim 2, wherein said conductive material with which said first via hole is filled and said conductive material with which said second via hole is filled are different.
- A printed circuit board according to claim 1, wherein said insulating layer is provided on both surfaces of said base material layer.
- A printed circuit board according to claim 1, wherein a wiring portion is provided outside said insulating layer.
- A printed circuit board according to claim 1, wherein a wiring portion is provided inside said insulating layer.
- A printed circuit board according to claim 7, wherein said insulating layer comprises a plurality of layers.
- A multilayer printed circuit board wherein a plurality of said printed circuit boards according to any one of claims 1 to 8 are laminated.
- A circuit component mount unit wherein a circuit component is mounted being connected to said wiring portion on an outermost layer of said printed circuit board according to any one of claims 1 to 8 or to said wiring portion on an outermost layer of said multilayer printed circuit board according to claim 9.
- A circuit component mount unit according to claim 10, wherein said circuit component includes a bare integrated circuit.
- An electronic component package comprising: a base material layer having a first via hole, said base material having a copper foil pad attached to one surface; an insulating layer having a second via hole, said insulating layer being provided on another surface of said base material; and an electronic component having an electrode so as to correspond to a position of said second via hole, wherein a cross-sectional area of said second via hole is smaller than a cross-sectional area of said first via hole, and wherein said first and second via holes are filled with a conductive material.
- An electronic component package according to claim 12, wherein said conductive material is a copper paste.
- An electronic component package according to any one of claims 12 to 13, wherein said conductive paste includes an abrasive.
- An electronic component package according to any one of claims 12 to 14, wherein said copper foil pad does not exist, and wherein said conductive material with which the first and second via holes are filled is solderable.
- An electronic component package according to any one of claims 12 to 15, wherein said insulating layer and said conductive material have flexibility.
- An electronic component package according to any one of claims 12 to 16, wherein said electrode of said electronic component is an aluminum electrode.
- A printed circuit board manufacturing method comprising:a first step of forming a wiring layer on an insulating layer having a second via hole; anda second step of transferring said insulating layer and said wiring layer onto a base material layer having a first via hole filled with a conductive material, said first via hole having a larger cross-sectional area than said second via hole.
- A printed circuit board manufacturing method according to claim 18, wherein in said first step, said second via hole is filled with a conductive paste.
- A printed circuit board manufacturing method comprising a step of laminating an insulating layer on a base material layer and forming a wiring layer on said insulating layer, said base material layer having a first via hole filled with a conductive material, said insulating layer having a second via hole having a smaller cross-sectional area than said first via hole.
- An electronic component package manufacturing method comprising the steps of:forming an insulative resin layer on a surface of an electronic component having a predetermined electrode on said surface;forming a through hole in said insulative resin layer so as to correspond to a position of said electrode;embedding a conductive paste into said through hole; andheating and pressurizing said insulative resin layer filled with said conductive paste to thereby paste said insulative resin layer to said electronic component.
- An electronic package manufacturing method according to claim 21, wherein said conductive paste is a copper paste.
- An electronic component package manufacturing method according to claim 21, 22 or 23, wherein said conductive paste includes an abrasive.
- An electronic component package manufacturing method according to claim 21, 22 or 23, wherein said insulative resin layer has a compressibility.
- An electronic component package manufacturing method according to claim 24, wherein said insulative resin layer is a prepreg with aramid nonwoven cloth as a reinforcing material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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EP02013314A EP1250033B1 (en) | 1996-12-26 | 1997-12-23 | Printed circuit board and electronic component |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34728296 | 1996-12-26 | ||
JP347282/96 | 1996-12-26 | ||
JP34728296 | 1996-12-26 | ||
JP11317497 | 1997-04-30 | ||
JP11317497 | 1997-04-30 | ||
JP113174/97 | 1997-04-30 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02013314A Division EP1250033B1 (en) | 1996-12-26 | 1997-12-23 | Printed circuit board and electronic component |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0851724A2 true EP0851724A2 (en) | 1998-07-01 |
EP0851724A3 EP0851724A3 (en) | 2000-09-27 |
EP0851724B1 EP0851724B1 (en) | 2003-10-22 |
Family
ID=26452190
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97122824A Expired - Lifetime EP0851724B1 (en) | 1996-12-26 | 1997-12-23 | Printed circuit board and electric components |
EP02013314A Expired - Lifetime EP1250033B1 (en) | 1996-12-26 | 1997-12-23 | Printed circuit board and electronic component |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02013314A Expired - Lifetime EP1250033B1 (en) | 1996-12-26 | 1997-12-23 | Printed circuit board and electronic component |
Country Status (6)
Country | Link |
---|---|
US (2) | US6192581B1 (en) |
EP (2) | EP0851724B1 (en) |
JP (1) | JP3429734B2 (en) |
KR (1) | KR100338908B1 (en) |
CN (1) | CN1116790C (en) |
DE (2) | DE69730629T2 (en) |
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Cited By (16)
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EP1220588A1 (en) * | 1999-07-12 | 2002-07-03 | Ibiden Co., Ltd. | Method of manufacturing printed-circuit board |
EP1220588A4 (en) * | 1999-07-12 | 2004-09-22 | Ibiden Co Ltd | Method of manufacturing printed-circuit board |
US6889433B1 (en) | 1999-07-12 | 2005-05-10 | Ibiden Co., Ltd. | Method of manufacturing printed-circuit board |
EP1760778A3 (en) * | 1999-11-26 | 2008-05-28 | Ibiden Co., Ltd. | Multilayer circuit board |
EP1156525A1 (en) * | 1999-11-26 | 2001-11-21 | Ibiden Co., Ltd. | Multilayer circuit board and semiconductor device |
EP1156525A4 (en) * | 1999-11-26 | 2005-12-14 | Ibiden Co Ltd | Multilayer circuit board and semiconductor device |
US7927453B2 (en) | 2001-11-26 | 2011-04-19 | Mitsui Mining & Smelting Co., Ltd. | Method of manufacturing copper foil with insulating layer, copper foil with insulating layer obtained with the same method, and printed circuit board using the same copper foil with insulating layer |
US7163600B2 (en) | 2001-11-26 | 2007-01-16 | Mitsui Mining & Smelting Co., Ltd. | Method for preparing copper foil with insulating layer and copper foil with insulating layer prepared by the method, and printed wiring board using the copper foil with insulating layer |
WO2003047323A1 (en) * | 2001-11-26 | 2003-06-05 | Mitsui Mining & Smelting Co.,Ltd. | Method for preparing copper foil with insulating layer and copper foil with insulating layer prepared by the method, and printed wiring board using the copper foil with insulating layer |
WO2015095385A1 (en) * | 2013-12-20 | 2015-06-25 | Qualcomm Incorporated | Substrate comprising improved via pad placement in bump area |
CN105830213A (en) * | 2013-12-20 | 2016-08-03 | 高通股份有限公司 | Substrate Comprising Improved Via Pad Placement In Bump Area |
US9466578B2 (en) | 2013-12-20 | 2016-10-11 | Qualcomm Incorporated | Substrate comprising improved via pad placement in bump area |
CN105830213B (en) * | 2013-12-20 | 2019-09-10 | 高通股份有限公司 | The substrate placed including the improved-type via pad in bump region |
US9603247B2 (en) | 2014-08-11 | 2017-03-21 | Intel Corporation | Electronic package with narrow-factor via including finish layer |
EP3001784A1 (en) * | 2014-09-22 | 2016-03-30 | OCE-Technologies B.V. | Method of manufacturing a multi-layer printed circuit board |
US9357640B2 (en) | 2014-09-22 | 2016-05-31 | Oce'-Technologies B.V. | Method of manufacturing a multi-layer printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
EP1250033A2 (en) | 2002-10-16 |
DE69725689T2 (en) | 2004-04-29 |
US6192581B1 (en) | 2001-02-27 |
EP0851724B1 (en) | 2003-10-22 |
CN1189760A (en) | 1998-08-05 |
KR19980064661A (en) | 1998-10-07 |
CN1116790C (en) | 2003-07-30 |
DE69730629D1 (en) | 2004-10-14 |
EP1250033A3 (en) | 2003-01-02 |
JP2001028483A (en) | 2001-01-30 |
US6281448B1 (en) | 2001-08-28 |
DE69725689D1 (en) | 2003-11-27 |
DE69730629T2 (en) | 2005-02-03 |
EP0851724A3 (en) | 2000-09-27 |
EP1250033B1 (en) | 2004-09-08 |
JP3429734B2 (en) | 2003-07-22 |
KR100338908B1 (en) | 2002-11-30 |
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