EP0569512A4

EP0569512A4 - Packet transmission system and method utilizing both a data bus and dedicated control lines

Info

Publication number: EP0569512A4
Application number: EP92905769A
Authority: EP
Inventors: John M Kaczmarczyk; Dale R Buchholz; Thomas A Freeburg; Rita O'brien; Richard E White
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1991-01-28
Filing date: 1992-01-27
Publication date: 1997-11-05
Also published as: JP2678690B2; WO1992013395A1; JPH06503216A; JPH06505600A; WO1992013414A1; EP0569512A1; KR930703776A; KR970007257B1; BR9205487A

Abstract

A common communication controller (17) is linked to a plurality of peripheral devices (28) by a network interface bus (26). Packets containing information is communicated between the controller and the peripherals over the bus which consists of a parallel packet bus and a plurality of control lines utilized to implement a communication protocol which increases the efficiencies of packet communications by the utilization of additional direct command lines between the communications controller (17) and peripherals (28).

Description

PACKET TRANSMISSION SYSTEM AND METHOD UTILIZING BOTH A DATA BUS AND DEDICATED CONTROL LINES

Background of the Invention

This invention is directed to a packet transmission system and is especially suited for a packet system which must accommodate a variety of different peripheral devices. In packet networks, digital information is segregated into packets each containing a packet header, digitized data corresponding to the information to be transmitted and error checking information so that a receiving node in the system can verify that the packet has been correctly received. These packets are transmitted from node to node in the network to the destination address contained in the packet. At the destination address device, the packets are disassembled and the information provided to the receiving device. Packet protocols become increasingly inefficient as the amount of data to be transmitted per packet decreases^'" because of the required packet overhead required for each packet. Although short commands can be transmitted from one point to another using packets, a substantial delay exists before the receiving device can act upon the command due to the time requirements of packet transmission and packet disassembly before the command can be forwarded to the destination device. In a conventional direct control systems each function to be controlled is assigned a separate wire or communication channel which carries a predetermined command from a controller to the device implementing the function. Such systems exist for a variety of applications and are efficient where a limited number of commands are to be transmitted to specific devices. These systems become increasingly complex as the number of commands and devices to be controlled increase. No addressing is required in these systems since each dedicated path has a preassigned single function to control.

There exists a need for a system and method which can carry information utilizing packets while minimizing the inefficiencies related to the transmission of commands to associated devices.

Summary of the Invention

In accordance with the present invention, an embodiment includes a device connected to a network interface bus including a packet bus and control lines capable of transmitting packets to a communication controller. The device can be requested to transmit upon receipt of a command from the controller. The device determines if the network interface bus is available' to accept data by determining if a first and second control line have a predetermined binary state. If the network interface bus is available, the device causes the first control line to change to the other binary state. Data is then written on the packet bus for communication to the controller. The device causes a third control line that functions as a packet clock to change binary states and thereby provides the controller with a signal to read the written data. If additional data is to be transmitted from the device, it is written on the bus and the third control line toggled to cause it to be read by the controller. The device indicates the end of a packet by causing the first control line to change from the other state to the predetermined state.

Brief Description of the Drawings

FIG. 1 illustrates a wireless packet communication system suited for incorporating the present invention. FIG. 2 is a block diagram of a packet device in accordance with the present invention and suited for use in the system shown in FIG. 1. FIGS. 3A and 3B illustrate preferred packet formats utilized by the communication controller and a peripheral device, respectively, to communicate to the other.

FIG. 4 is a flow diagram illustrating the transmission of data from a communication controller to a peripheral device as shown in FIG. 2.

FIG. 5 is a timing diagram illustrating control signals utilized in accordance with the flow diagram of

FIG. 4. FIG. 6 is a flow diagram illustrating the transmission of data from a peripheral device to the communication controller shown in FIG. 2.

FIG. 7 is a timing diagram illustrating controls utilized to transmit information in accordance with the steps of FIG. 6. Description of a Preferred Embodiment

FIG. 1 illustrates a wireless packet communication system in which a control module 10 utilizes RF communications to communicate with user modules 12 that are each coupled to one or more user devices 14 consisting of a terminal, personal computer, telephone, or other information input/output device. In the illustrative system, the control module 10 is also coupled by a data channel 16 to a data network. The control module controls communications within the illustrated network and passes information from the data network via channel 16 to user devices 14 via the associated user module. The control module also controls local communications by receiving information from one user module and relaying the information to a different user module. The wireless information is conveyed in the form of packets. The data network to which control module 10 is connected may consist of an Ethernet network.

FIG. 2 illustrates a block diagram of an embodiment of a packet system in accordance with the present invention. The illustrative embodiment is for a user module of the system as shown in FIG. 1. A communications controller 17 includes a microprocessor 18, with associated read only memory 20, random access memory 22', and a network interface 24. The network interface consists of appropriate registers and line drivers for communication with peripheral devices connected by network interface (NI) bus 26. The physical structure of the NI bus is described below.

In the structure as shown in FIG. 2 a plurality of peripheral devices including two way RF radio 28, a Tl Gateway input/output device 30, an ISDN Gateway I/O device 32, and a telephone I/O device 34. The peripherals 28-34 each contain a NI bus interface 36, 38, 40, and 42, respectively. These interfaces provide the necessary registers and line drivers for communicating with NI bus 26 and will also include an PU, RAM, and ROM if these resources are not available in the peripheral device. The radio 28 includes one or more antennas 44 for RF communications with the control module 10 as shown in FIG. 1. The Tl Gateway I/O device 30 is coupled by wire 46 to a Tl line. Likewise ISDN Gateway I/O device 32 is coupled by wire 48 to an ISDN network. The telephone I/O device 32 is connected by wire 50 to a telephone instrument. The illustrative peripherals are merely representative that virtually any type of information can be coupled by means of an appropriate input/output device to the NI bus. The various peripherals reformat information communicated via the NI bus into the proper format for communication to other devices connected by paths 44-50. FIG. 3A illustrates a preferred embodiment of a packet format utilized for communications from the controller 17 to a peripheral device over the NI bus 26. It is generally segmented to contain a NI header and NI information. The NI address field contains the address of the destination peripheral. The NI length field contains the number of bytes in the NI command field. The command field is used to control a peripheral and contains a command for the peripheral device, for example, commands used to poll for status of the interface, poll for data received by an interface, or transmit/receive data. The information field may or may not be present depending on which command has been sent. For example, a poll-for-status command might not have an information field because a peripheral may return a well-defined status byte or bytes every time polled. On the other, the poll-for-status command could be further qualified with information that requests particular- status information from a set of status information kept by a peripheral device. An example would be a peripheral device that controls several interface ports such as multiple telephone lines. In such a case, the controller may wish to poll about the status of a particular line and the information field would be used to convey which line was of interest. The information field may also contain a well-formed data packet including header, data, and CRC field for transmission. For example, the command field may contain a radio transmit command addressed to radio 28 in which case the NI information field contains the data to be transmitted.

FIG. 3B illustrates a preferred embodiment of the NI bus packet format for Peripheral-to-Controller communication. The NI address field contains the address of the controller since all traffic in the preferred embodiment is routed through the controller. However, direct peripheral-to-peripheral communication is possible wherein the address field would contain the address of the destination peripheral, the NI data field contains the data requested by the controller, and the additional bytes field contains status information from the peripheral device. The additional bytes field is optional. Contrasting this format to that of FIG. 3A, the NI address constitutes the NI header and NI data, with or without the additional byte field, constitutes the NI information field.

The methods described below will most advantageously be integrated into a conventional software operating system that provides various operational capabilities dependent upon the specific operating environment.

FIG. 4 is a flow diagram illustrating the steps implemented by the communications controller 17 to transmit data or commands to a peripheral connected to the NI bus. The timing diagram illustrated in FIG. 5 also relates to the transmission of packets of data from the communications controller to the peripherals and should be read in conjunction with the steps described in FIG. 4. The timing diagram in FIG. 5 represents the physical NI bus which consists of a packet bus having a plurality of lines for conveying a byte of data during each bus clock cycle and separate control lines for packet clock, packet start, NI source, and bus clock. The NI source and bus clock lines are always controlled by the communications controller; the remaining lines and packet bus are bi-directional, i.e. the communications controller and the peripherals are capable of writing to and reading these lines. The transmission of data from the communications controller to a peripheral is accomplished as follows. Beginning with entry at START 52, the controller drives the NI source line from high to low as indicated in step 54. This gives the controller control of the NI bus and communicates to all peripherals that they are to receive data which will be transmitted from the controller. In step 56 the controller drives the packet start line from high to low which marks the beginning of the transmission of a packet to be transmitted by the controller to a peripheral. Next, the controller writes a byte of data on the packet bus as indicated by step 58. In step 60, the controller drives the packet clock line from high to low and back high. The peripherals read the data written on the packet bus during the high to low transition of the packet clock. In decision step 52 the controller determines if all data has been transmitted. If NO, the next byte of data is written on the packet bus by returning to step 58 and the cycle repeated. Upon completing the writing of all data (step 62 = YES) the controller drives the NI source line from low to high releasing control of the NI bus and packet start from low to high marking the end of the packet in step 64. This method terminates at END 66. In the illustrative example as shown in FIGS. 4 and 5, the communications controller sent a single packet as illustrated in FIG. 3A to one or a predetermined group of peripherals. The NI header contains the NI address, i.e. the peripheral device address of a particular peripheral or a group address for a predetermined group of peripherals. After receiving and decoding the peripheral address contained in the NI header, each peripheral can determine if the following information is intended for it. If the information is intended for a peripheral, then it will continue reading the data transmitted by the controller. If the packet is not intended for a peripheral, then it need not further process the information and can merely look for a low to high transition of the packet start line indicating the end of transmission of that packet. Although the illustrative example indicated the simultaneous transition of NI source and packet start in step 64, the controller may alternatively maintain the NI source line low, indicate the end of the packet transmission by driving the packet start line from low to high and then begin transmission of another packet by driving packet start from high to low thereby not relinquishing control of the NI bus between the transmission of successive packets. The packet clock line is controlled by the transmitting device with the high to low transition being a signal to the receiving device that data on the packet bus is stable and should be read.

FIG. 6 shows a flow diagram illustrating steps performed by a peripheral device in transmitting data to the communications controller. These steps should be read in conjunction with the timing diagram shown in FIG. 7. The timing diagram in FIG. 7 illustrates one additional control line, packet end, not shown in FIG. 5. In the preceding description relating to FIG. 5, the packet bus, packet clock, and packet start lines were sourced by the communications controller. With regard to FIG. 7, the packet bus, packet clock, and packet start lines are sourced by a peripheral. The packet end, NI source, and bus clock are sourced by the controller.

In START step 68, a flag (F) is set to zero. This flag generally relates to the ability of the controller to allow certain additional bytes or data to be transmitted after the end of the packet as marked by packet start. The operation of this flag is explained in detail below. In step 69 a determination is made by the peripheral if it has been instructed by a command from the controller on the packet bus to transmit data. A NO determination by step 69 results in a return to

START 68 since a peripheral is not able to transmit data except upon being instructed by a prior command send by the controller on the packet bus. The controller will normally poll each peripheral to determine its status and determine if data should be sent to it. On a YES determination by step 69, a determination is made by step 70, if packet start is high. A NO decision results in the termination of the method at END 72 since packet start must be high in order for a peripheral to initiate data transmission. Following a YES decision by step 70, step 74 determines if NI source is high. A NO decision by step 74 results in the termination of the method at END 72 since NI source must be high to allow transmission by a peripheral device. A YES decision by step 74 indicates that the NI bus is available for data transmission by the peripheral.

In step 78 the peripheral drives packet start line from high to low thereby advising the controller to receive data. The peripheral then proceeds to write data on the packet bus in step 80. The peripheral then drives the packet clock line from high to low which provides a timing signal to the controller to read the data on the packet bus. In step 84 a decision is made if packet end is low. The packet end line is controlled by the controller and can be utilized to^' terminate transmission by a peripheral at any time. A NO decision in step 84 leads to a determination in step 86 if flag F is high. A YES decision results in the peripheral initiating a stop sending data sequence 88 in which transmission of data is stopped. A NO determination by step 86, i.e. the flag is not set, results in a determination by the peripheral as to whether all data has been transmitted in step 90. A NO decision returns control to step 80 in which additional data is transmitted to the controller. A YES determination by step 90, indicating the end of desired data transmission by the peripheral, results in the peripheral driving the packet start from low to high as indicated in step 92. This tells the controller that the peripheral has finished transmitting the packet. Following step 92 the method terminates at END 94.

The following explanation indicates the ability of the controller to prematurely end the transmission of data by the peripheral. This sequence is initiated by the controller driving packet end line low, a YES decision by step 84. In step 96 the peripheral responds to this command by setting flag equal to 1. In step 98 a determination is made by the peripheral if more data remains to be sent to the controller. A NO decision results in terminating the transmission by return to steps 92 and 94. A YES determination by step 98, indicating that more data is to be sent, causes a return to step 80 in which the next byte of data is written to the packet bus and the packet clock is incremented in step 82. If the packet end line remains low as determined by step 84 the same sequence of steps will proceed until the peripheral has transmitted all of its data as determined by step 98. However, if the controller has caused the flag F to be reset by driving packet end from low to high, a NO determination will be made by step 84. In this case, step 86 will result in a YES determination since the flag has been set thereby implementing the immediate stop function by step 88.

Thus, the controller can terminate the transmission of data by a peripheral by driving packet end from high to low to high.

In the illustrative example as shown in FIG. 7, the packet start line is driven by the peripheral from low to high prior to a packet end line termination command, i.e. from high to low to high. Thus, this example illustrates that the peripheral completed the transmission of its data without an interruption by the controller. The heavy dashed line associated with the packet start line in FIG. 7 illustrates an alternative example in which the peripheral continued to have data to send but was interrupted by the packet end command, whereby the packet start line remains low until the beginning of the heavy dashed line and returns high concurrent with the packet end line being driven from low to high by the controller. This mechanism is advantageous in that it permits the possibility of additional bytes of data to be transmitted beyond a predefined packet as determined by the packet start line. Thus it is possible for a peripheral to immediately send a number of bytes of additional information following a packet. Such bytes of information can be utilized to monitor conditions of the peripheral or may correspond to general update information provided by the peripheral following the transmission of the packet. This permits such information to be communicated without requiring it being carried within a packet. This provides additional flexibility of communications which is especially advantageous when a plurality of peripherals each communicate with a common controller.

If one peripheral is transmitting a packet of information which is destined for another peripheral attached to the NI bus, the controller will process the packet and reformat a packet with a NI header addressed to the destination peripheral and transmit it over the NI bus. Thus, the communications controller acts as a traffic cop in routing packets and information between peripherals as well as providing a common point of coordination of communications.

It will be apparent to those skilled in the art that the method of this invention can be implemented in hardware or a state device as well as in software.

Although an embodiment of the present invention has been shown and described, the scope of the invention is defined by the claims which follow.

Claims

1. A method for a device connected to a network interface (NI) bus having a packet bus and control lines to transmit data packets to a communication controller connected to the NI bus comprising the steps of:

(a) determining if the device has been requested to transmit by receipt of a command from the controller; (b) determining if the NI bus is available to accept data from the device by determining if a first and second control line have a predetermined binary state;

(c) if the NI bus is available to accept data and said command is received, the device causing the first control line to change to the other binary state;

(d) writing a byte of data to be transmitted on the packet bus;

(e) causing a third control line that functions as a packet clock to change binary states thereby providing the communication controller with a signal to read the written data;

(f) if additional data is to be transmitted, repeating steps (d) and (e) ; (g) causing the first control line to change from the other state to the predetermined state thereby indicating the end of a packet.

2. The method according to claim 1 further comprising the steps of monitoring the binary state of a fourth control line under the control of the communication controller and terminating the sending of additional data upon said monitoring step sensing a transition of the fourth control line from one state to the other state and back to the one state.

3. The method according to claim 2 wherein said terminating step allows additional data to be transmitted until said fourth control line changes from said other state back to the one state.

4. A device connected to a network interface (NI) bus having a packet bus and control lines capable of transmitting data packets to a communication controller comprising: means for determining if the device has been requested to transmit by receipt of a command from the controller; means for determining if the NI bus is available to accept data from said device by determining if a first and second control line have a predetermined binary state; means for causing the first control line to change to the other binary state if the NI bus is available to accept data and said command is received; means for writing data to be transmitted on the packet bus; means for causing a third control line that functions as a packet clock to change binary states thereby providing the communication controller with a signal to read the written data; means for determining if additional data is to be transmitted and causing said writing means and third control line means to transmit the additional data; means for causing the first control line to change from the other state to the predetermined state thereby indicating the end of a packet. 5. The device according to claim 4 further comprising means for monitoring the binary state of a fourth control line that is under the control of the communication controller and terminating the sending of additional data upon said monitoring means sensing a transition of the fourth control line from one state to the other state and back to the one state.

6. The device according to claim 5 wherein said terminating means allows additional data to be transmitted until said fourth control line changes from said other state back to the one state.

7. A method for a communication controller connected to a network interface (NI) bus having a packet bus and control lines to transmit data packets to a device connected to the NI bus comprising the steps of:

(a) obtaining control of the NI bus by causing a first control line to change from a first binary state to the other binary state;

(b) marking the beginning of a packet by causing a second control line to change from a first binary state to the other binary state; (c) writing a byte of data to be transmitted on the packet bus;

(d) causing a third control line that functions as a packet clock to change binary states thereby providing said device with a signal to read the written data;

(e) if additional data is to be transmitted, repeating steps (c) and (d) ; (f) marking the end of the packet by causing the second control line to change from the other state to the first state and releasing control of the NI bus by causing the first control line to change from the other state to the first state.

8. A communication controller connected to a network interface (NI) bus having a packet bus and control lines capable of transmitting data packets to a device connected to the NI bus comprising: means for obtaining control of the NI bus by causing a first control line to change from a first binary state to the other binary state; means for marking the beginning of a packet by causing a second control line to change from a first binary state to the other binary state; means for writing a byte of data to be transmitted on the packet bus; means for causing a third control line that functions as a packet clock to change binary states thereby providing the device with a signal to read the written data; means for determining if additional data is to be transmitted and causing said writing means and third control line causing means to transmit the additional data; means for marking the end of the packet by causing the second control line to change from the other state to the first state; the end of a packet; means for releasing control of the NI bus by causing the first control line to change from the other state to the first state.